Flash memory cell, flash memory module, and flash memory chip

Abstract

The present invention provides a flash memory cell, a flash memory module, and a flash memory chip. The flash memory cell includes: a programmable semiconductor device for storing long-term data and an analog capacitor unit for storing temporary data. The programmable semiconductor device is connected in parallel with the analog capacitor unit. Wherein, by setting the analog capacitor unit to store temporary data, the number of erase / write operations of the programmable semiconductor device can be effectively reduced, and the aging of the programmable semiconductor device can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory, and in particular, to a flash memory cell, a flash memory module, and a flash memory chip. Background Art

[0002] Flash memory is a non-volatile memory that stores data by modulating the threshold voltage of flash transistors. According to the different flash transistors and array structures, flash memory is mainly divided into NOR-type flash memory and NAND-type flash memory. The read and write of NAND-type flash memory are in units of pages and blocks. It has a large capacity and low cost and is widely used in large-scale stand-alone memories; NOR-type flash memory supports random access of data. Compared with NAND-type flash memory, it has a lower density, smaller capacity, and higher cost, and is mainly used in embedded memories.

[0003] In recent years, in order to solve the bottleneck of the traditional von Neumann computing architecture, Computing-In-Memory (CIM) has been widely studied. Its basic idea is to directly use the memory for logical calculations, thereby reducing the amount and distance of data transmission between the memory and the processor, reducing power consumption while improving performance.

[0004] However, since the data in the flash memory is updated by erasing and writing the flash transistors, and the number of erasing and writing operations of the flash transistors is limited, frequent erasing and writing easily ages the flash transistors, and thus ages the in-memory computing chip. Summary of the Invention

[0005] In view of this, the present invention provides a flash memory cell, a flash memory module, and a flash memory chip to solve the problem of aging of the in-memory computing chip caused by frequent erasing and writing of flash transistors.

[0006] To solve the above technical problems, the present invention adopts the following technical solutions:

[0007] In a first aspect, a flash memory cell is provided, including: a programmable semiconductor device for storing long-term data and an analog capacitor unit for storing temporary data, and the programmable semiconductor device is connected in parallel with the analog capacitor unit.

[0008] Further, the analog capacitor unit includes: an output transistor, a charging transistor, a discharging transistor, and a capacitor;

[0009] The drain of the output transistor is connected to the drain of the programmable semiconductor device, the source is connected to the source of the programmable semiconductor device, and the gate is connected to one end of the capacitor;

[0010] The source of the charging transistor is connected to a high voltage, the gate is connected to a first control voltage, and the drain is connected to the other end of the capacitor;

[0011] The source of the discharge transistor is connected to a low voltage, the gate is connected to a second control voltage, and the drain is connected to the other end of the capacitor.

[0012] Further, the flash memory cell further includes: a programming circuit,

[0013] The programming circuit is connected to the gate of the charging transistor and / or the gate of the discharge transistor, and is configured to provide the first control voltage and / or the second control voltage to the charging transistor and the discharge transistor.

[0014] Further, the programming circuit is further connected to the programmable semiconductor device, and is configured to provide a programming voltage to the programmable semiconductor device.

[0015] Further, the programming circuit includes: a voltage generation circuit and a voltage control circuit. The voltage generation circuit is configured to generate the first control voltage and / or the second control voltage and / or the programming voltage, and the voltage control circuit is configured to load the voltage generated by the voltage generation circuit onto the corresponding charging transistor and / or discharge transistor and / or programmable semiconductor device.

[0016] Further, the flash memory cell further includes: a control circuit, connected to the programming circuit, for controlling the operation of the programming circuit.

[0017] In a second aspect, a flash memory module is provided, including a plurality of the above-mentioned flash memory cells arranged in an array, as well as a peripheral circuit and a control circuit. The peripheral circuit is connected to the flash memory cell and the control circuit.

[0018] Further, the peripheral circuit includes: a programming circuit, which is connected to the flash memory cell and the control circuit.

[0019] Further, the peripheral circuit further includes: a row-column decoder, which is connected to the flash memory cell and the control circuit.

[0020] In a third aspect, a flash memory chip is provided, including: an input interface circuit, a programming circuit, a row-column decoder, a control circuit, an output interface circuit, and a plurality of flash memory modules; each flash memory module includes a plurality of the above-mentioned flash memory cells arranged in an array;

[0021] A plurality of the flash memory modules are connected in series to form a series branch;

[0022] One end of the input interface circuit is connected to an external circuit, and the other end is connected to the input end of the series branch;

[0023] One end of the output interface circuit is connected to the output end of the series branch, and the other end is connected to an external circuit;

[0024] The control circuit is connected to the programming circuit and the row-column decoder;

[0025] The programming circuit and the row-column decoder are both connected to each flash memory module.

[0026] In a fourth aspect, a flash memory chip is provided, including: an input interface circuit, a programming circuit, a row-column decoder, a control circuit, an output interface circuit, an on-chip memory, and a plurality of flash memory modules; each flash memory module includes a plurality of the above-mentioned flash memory cells arranged in an array;

[0027] One end of the input interface circuit is connected to an external circuit, and the other end is connected to the input end of the on-chip memory;

[0028] One end of the output interface circuit is connected to the output end of the on-chip memory, and the other end is connected to an external circuit;

[0029] The plurality of flash memory modules are respectively connected to the on-chip memory;

[0030] The control circuit is connected to the programming circuit and the row-column decoder;

[0031] The programming circuit and the row-column decoder are both connected to each flash memory module.

[0032] The flash memory cell, the flash memory module, and the flash memory chip provided by the present invention include: a programmable semiconductor device for storing long-term data and an analog capacitor unit for storing temporary data. The programmable semiconductor device is connected in parallel with the analog capacitor unit. Among them, by setting the analog capacitor unit to store temporary data, the number of erase-write operations of the programmable semiconductor device can be effectively reduced, and the aging of the programmable semiconductor device can be avoided.

[0033] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0035] Figure 1 Circuit of the flash memory cell in the embodiment of the present invention Figure 1 ;

[0036] Figure 2 Circuit of the flash memory cell in the embodiment of the present invention Figure 2 ;

[0037] Figure 3 Structural frame of the flash memory cell in the embodiment of the present invention Figure 1 ;

[0038] Figure 4 is the structural frame of the flash memory cell according to the embodiment of the present invention Figure 2 ;

[0039] Figure 5 is the circuit diagram of the flash memory module according to the embodiment of the present invention;

[0040] Figure 6 is the circuit of the flash memory chip according to the embodiment of the present invention Figure 1 ;

[0041] Figure 7 is the circuit of the flash memory chip according to the embodiment of the present invention Figure 2 . Specific embodiments

[0042] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0043] For typical neural network or deep learning applications, it generally includes two aspects, namely training and inference. Training refers to obtaining the parameters of the neural network through known labeled samples, and inference refers to predicting unlabeled samples through the trained neural network. Training requires a large amount of calculations and samples to achieve high-accuracy inference. Currently, training is usually completed using servers with large computing power such as GPUs / TPUs, which is very inconvenient. Moreover, since training and inference do not use the same medium, parameter mismatch is inevitable, affecting the accuracy of inference. Therefore, in-situ training has been widely studied, that is, training and inference use the same medium. However, for traditional in-memory computing chips based on NOR-type flash memory, in-situ training is a huge challenge because the training process requires a large amount of calculations and samples, and frequently erases and writes to NOR-type flash memory transistors to continuously update the neural network parameters to obtain the final high-precision neural network parameters, while the number of erase and write cycles of NOR-type flash memory transistors is very limited and simply cannot meet the requirements of parameter update in in-situ training.

[0044] It should be noted that the parameter values that need to be updated at certain intervals are called short-term data. For example, when training a neural network, the weight parameters of the network need to be adjusted at certain intervals, and the adjustment value is short-term data. The data values accumulated over multiple intervals or the data values accumulated to a certain scale are called long-term data. For example, when training a neural network, the values obtained after multiple adjustments are accumulated to a certain number of times or a certain scale are long-term data.

[0045] To this end, embodiments of the present invention provide a flash memory cell, a flash memory module, and a flash memory chip. By setting an analog capacitance unit to store temporary data, the number of erase and write operations of the programmable semiconductor device can be effectively reduced, and the aging problem of the programmable semiconductor device can be avoided. Furthermore, the flash memory cell, the flash memory module, and the flash memory chip can be adapted to occasions with frequent erase and write operations, especially neural network or deep learning occasions, and support in-situ training of neural networks.

[0046] Figure 1 The circuit of the flash memory cell according to the embodiment of the present invention Figure 1 . As Figure 1 shown, the flash memory cell 1 includes: a programmable semiconductor device F for storing long-term data 0 and an analog capacitance unit 2 for storing temporary data. The programmable semiconductor device F 0 is connected in parallel with the analog capacitance unit 2.

[0047] Among them, the threshold voltage of the programmable semiconductor device is adjustable and can be implemented by a floating-gate transistor. For example: SONOS type floating-gate transistor, Split-gate floating-gate transistor, or Charge-trapping floating-gate transistor, including but not limited to this. All flash memory transistor devices used in flash memories belong to the protection scope of the embodiments of the present invention.

[0048] The floating-gate transistor includes a substrate, an insulating layer, a gate G, a source S, a drain D, and a floating gate F. The floating gate is disposed between the gate and the insulating layer, and the insulating layer is disposed between the floating gate and the substrate to protect the electrons in the floating gate from leakage. Electrons can be stored in the floating gate; by adjusting the number of electrons in the floating gate, the threshold voltage of the floating-gate transistor can be dynamically adjusted. Due to this structural characteristic of the floating-gate transistor, it can be regarded as a variable equivalent analog weight to store an analog data.

[0049] The gate of the programmable semiconductor device F 0 is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the source line SL.

[0050] Among them, by connecting an analog capacitance unit 2 in parallel with the programmable semiconductor device F 0 , when it is necessary to perform an erase and write operation on the programmable semiconductor device F 0 , the voltage value (equivalent to short-term data) that needs to be increased or decreased is applied to the analog capacitance unit, that is, the voltage of the analog capacitance unit is adjusted. The output current of the flash memory cell is the programmable semiconductor device F 0The sum of the output current and the output current of the analog capacitor unit 2. Therefore, by adjusting the voltage of the analog capacitor unit, the purpose of adjusting the output current (i.e., the weight) of the flash memory unit can be achieved. When the number of erase / write cycles of the analog capacitor unit reaches a preset number (such as 10 times, 50 times, 100 times, 300 times, etc., the embodiments of the present invention do not limit this) or a preset voltage (the voltage value is in the range of 0.01V to 2V, such as: 0.05V, 0.1V, 0.5V, 0.8V, 1V, the embodiments of the present invention do not limit this), then the voltage of the analog capacitor unit (equivalent to the data stored therein) is transferred to the programmable semiconductor device F 0 , so as to reduce the programmable semiconductor device F 0 's number of erase / write cycles and avoid the aging of the programmable semiconductor device F 0 .

[0051] Figure 2 is the circuit of the flash memory unit according to the embodiment of the present invention Figure 2 . As Figure 2 shown, the analog capacitor unit 2 of the flash memory unit 1 includes: an output transistor N 0 , a charging transistor P 0 , a discharging transistor Q 0 and a capacitor C 0 .

[0052] Among them, the drain of the output transistor N 0 is connected to the drain of the programmable semiconductor device F 0 , the source is connected to the source of the programmable semiconductor device F 0 , and the gate is connected to one end of the capacitor C 0 ;

[0053] The source of the charging transistor P 0 is connected to a high voltage, the gate is connected to the first control voltage Set, and the drain is connected to the other end of the capacitor C 0 ;

[0054] The source of the discharging transistor Q 0 is connected to a low voltage, the gate is connected to the second control voltage Reset, and the drain is connected to the other end of the capacitor C 0 .

[0055] Among them, the charging transistor P 0 is implemented by a PMOS transistor, and this PMOS transistor conducts when a negative voltage is applied; the discharging transistor Q 0 is implemented by an NMOS transistor, and this NMOS transistor conducts when a positive voltage is applied.

[0056] When it is necessary to increase the weight (i.e., the output current) of the flash memory unit, the first control voltage Set and the second control voltage Reset can be set low, and through the charging transistor P0 Charge the capacitor C 0 so that the voltage of the capacitor C 0 increases, thereby increasing the gate voltage of the output transistor N 0 . The output current of the output transistor N 0 is a function of its gate voltage, thus increasing the output current of the output transistor N 0 , thereby increasing the output current of the analog capacitor unit 2 and ultimately increasing the weight of the flash memory cell.

[0057] When it is necessary to reduce the weight (i.e., output current) of the flash memory cell, the first control voltage Set and the second control voltage Reset can be set high, and the capacitor C 0 is discharged through the discharge transistor Q 0 so that the voltage of the capacitor C 0 decreases, thereby reducing the gate voltage of the output transistor N 0 . The output current of the output transistor N 0 is a function of its gate voltage, thus reducing the output current of the output transistor N 0 , thereby reducing the output current of the analog capacitor unit 2 and ultimately reducing the weight of the flash memory cell.

[0058] Figure 3 is the structural block diagram of the flash memory cell according to the embodiment of the present invention Figure 1 . As Figure 3 shown, on the basis of including the flash memory cell 1 shown in Figure 2 , the flash memory cell further includes: a programming circuit 2 and a control circuit 3.

[0059] Among them, the programming circuit 2 is connected to the gate of the charging transistor P 0 in the flash memory cell 1 and the gate of the discharge transistor Q 0 , and is used to provide the first control voltage Set and / or the second control voltage Reset to the charging transistor P 0 and the discharge transistor Q 0 .

[0060] Moreover, the programming circuit 2 is also connected to the source, gate and / or substrate of the programmable semiconductor device F 0 , and is used to generate a programming voltage or an erasing voltage, load the programming voltage to the source of the programmable semiconductor device F 0 , or load the erasing voltage to the gate or substrate of the programmable semiconductor device F 0 to regulate the threshold voltage of the programmable semiconductor device F 0 .

[0061] When transferring the data in the analog capacitor unit 2 to the programmable semiconductor device F 0When, apply the programming voltage to the programmable semiconductor device F 0 , so that the programmable semiconductor device F 0 has an increase in threshold voltage equal to the voltage of the analog capacitor unit 2.

[0062] Specifically, the programming circuit utilizes the hot electron injection effect to apply a high voltage to the source of the programmable semiconductor device F 0 , accelerating the channel electrons to a high speed, so that a certain number of electrons cross the barrier and are injected into the floating gate, thereby increasing the number of electrons in the floating gate to increase the threshold voltage of the programmable semiconductor device F 0 ; alternatively, the programming circuit utilizes the tunneling effect to apply a high voltage to the gate or substrate of the programmable semiconductor device F 0 , attracting the electrons in the floating gate out of the floating gate, thereby reducing the number of electrons in the floating gate to reduce the threshold voltage of the programmable semiconductor device F 0 .

[0063] The control circuit 3 is connected to the programming circuit 2, and is used to control the voltage value and output direction generated by the programming circuit 2 (that is, to control whether the programming circuit 2 outputs voltage to any one or two or three of the charging transistor P 0 , the discharging transistor Q 0 , and the programmable semiconductor device F 0 , and the magnitude of the voltage output to the charging transistor P 0 , the discharging transistor Q 0 , and the programmable semiconductor device F 0 ).

[0064] Those skilled in the art can understand that the programming circuit 2 is an integrated circuit module, and the programming circuit 2 may include: a first programming circuit 2a and a second programming circuit 2b. As Figure 4 shown, the first programming circuit 2a is connected to the gates of the charging transistor P 0 in the flash memory cell 1 and the gate of the discharging transistor Q 0 , and is used to provide a first control voltage Set and / or a second control voltage Reset to the charging transistor P 0 and the discharging transistor Q 0 ; the second programming circuit 2b is connected to the source, gate, and / or substrate of the programmable semiconductor device F 0 , and is used to generate a programming voltage or an erasing voltage, load the programming voltage to the source of the programmable semiconductor device F 0 , or load the erasing voltage to the gate or substrate of the programmable semiconductor device F 0 , so as to regulate the threshold voltage of the programmable semiconductor device F 0 .

[0065] Specifically, the programming circuit 2 may include: a voltage generation circuit and a voltage control circuit. The voltage generation circuit is used to generate a first control voltage and / or a second control voltage and / or a programming voltage, and the voltage control circuit is used to load the voltage generated by the voltage generation circuit to the corresponding charging transistor and / or discharging transistor and / or programmable semiconductor device.

[0066] Those skilled in the art can understand that on the basis that the programming circuit 2 includes a voltage generation circuit and a voltage control circuit, the first programming circuit 2a also includes a voltage generation circuit and a voltage control circuit. The voltage generation circuit is used to generate a first control voltage and / or a second control voltage, and the voltage control circuit is used to load the voltage generated by the voltage generation circuit to the corresponding charging transistor and / or discharging transistor.

[0067] Similarly, the second programming circuit 2b also includes a voltage generation circuit and a voltage control circuit. The voltage generation circuit is used to generate a programming voltage, and the voltage control circuit is used to load the programming voltage to the source of the selected programmable semiconductor device, or to the gate or substrate of the selected programmable semiconductor device, so as to regulate the threshold voltage of the programmable semiconductor device.

[0068] In summary, the flash memory cell 1 provided by the embodiment of the present invention can achieve the purpose of adjusting the output current of the flash memory cell 1 by adjusting the voltage of the analog capacitor unit 2. When the number of erase / write cycles of the analog capacitor unit 2 reaches a preset number or a preset voltage, the voltage of the analog capacitor unit 2 (equivalent to the data stored therein) is transferred to the programmable semiconductor device F 0 , thereby reducing the number of erase / write cycles of the programmable semiconductor device F 0 and avoiding the aging of the programmable semiconductor device F 0 .

[0069] Figure 5 This is the circuit diagram of the flash memory module according to the embodiment of the present invention. As Figure 5 shown, the flash memory module includes: a plurality of flash memory cells arranged in an array as Figures 1 to 4 shown and a peripheral circuit (not shown in the figure), a control circuit (not shown in the figure). The peripheral circuit is connected to each flash memory cell and the control circuit.

[0070] In an optional embodiment, the peripheral circuit includes: a programming circuit and / or a row / column decoder.

[0071] The programming circuit is connected to each flash memory cell and the control circuit. The programming circuit is used to supply different voltages to each flash memory cell under the control of the control circuit. Different from the programming circuit as Figures 3 to 4 shown, this programming circuit is respectively connected to a plurality of flash memory cells to control the selected flash memory cells among the plurality of flash memory cells. For the principle, circuit connection and specific components, refer toFigures 3 to 4 The described programming circuit will not be elaborated here.

[0072] The row-column decoder is connected to each flash memory cell and the control circuit, and is used to select some or all of the flash memory cells under the control of the control circuit; perform arithmetic or storage operations using the selected flash memory cells, or program the selected flash memory cells using the programming circuit. Its programming principle is as described above, and reference can be made to each other, so it will not be elaborated here.

[0073] Among them, when the flash memory module works, by pre-controlling the output current of each flash memory cell, each flash memory cell is regarded as a variable equivalent analog weight, which is equivalent to storing an analog data, and the flash memory cell array stores an analog data array. If a column of analog voltage vectors or a column of analog voltage vectors converted from analog current vectors by a conversion device is applied to the corresponding flash memory cells, the current output by each flash memory cell is equal to the voltage applied to it multiplied by the weight. Since all the flash memory cells in each column are connected to the same output terminal, the current at this output terminal is the sum of the output currents of all the flash memory cells in this column, that is, the sum of the products of the gate voltages (voltages applied to them) of all the flash memory cells in this column and the weights. Multiple output terminals corresponding to multiple columns output the sum of the products of multiple gate voltages and weights, realizing the function of matrix multiplication operation.

[0074] When it is necessary to adjust the output current of each flash memory cell (i.e., the equivalent analog weight), it can be achieved by adjusting the voltage of the analog capacitor unit 2 of each flash memory cell. When the number of erase-write cycles of the analog capacitor unit 2 reaches the preset number of times or the preset voltage, the voltage of the analog capacitor unit 2 (equivalent to the data stored in it) is transferred to the corresponding programmable semiconductor device F 0 .

[0075] The flash memory module includes: a NOR-type flash memory processing array and a NAND-type flash memory processing array. Of course, the present invention is not limited thereto.

[0076] In an alternative embodiment, the flash memory module may further include supporting circuit modules such as an ADC, a DAC, and a shift register, which are used to assist the flash memory module in processing deep learning neural network tasks.

[0077] By adopting the above flash memory cells, the flash memory module, where the flash memory cells contain analog capacitor units for storing short-term data, can effectively reduce the number of erase-write cycles of the programmable semiconductor device, avoid the aging of the programmable semiconductor device, and thus improve the service life of the flash memory module.

[0078] Figure 6 is the circuit of the flash memory chip according to the embodiment of the present invention Figure 1 . Such as Figure 6As shown in the figure, the flash memory chip 100 includes: an input interface circuit 10, a programming circuit 30, a row and column decoder 50, a control circuit 40, an output interface circuit 60, and L flash memory modules 20 as shown in Figure 5 shown. The flash memory module 20 includes flash memory cells as shown in Figure 1 or Figure 2 shown, which are arranged in an array.

[0079] Multiple flash memory modules 20 are connected in series to form a series branch for implementing an arithmetic function or a storage function.

[0080] The flash memory module includes: a NOR-type flash memory processing array and a NAND-type flash memory processing array. Of course, the present invention is not limited thereto.

[0081] One end of the input interface circuit 10 is connected to an external circuit, and the other end is connected to the input end of the series branch for receiving an input signal from the external circuit and transmitting it to the series branch;

[0082] One end of the output interface circuit 60 is connected to the output end of the series branch, and the other end is connected to an external circuit for outputting the output signal of the series branch to the external circuit;

[0083] The control circuit 40 is connected to the programming circuit 30 and the row and column decoder 50 for controlling the voltage value and output direction generated by the programming circuit 30, and controlling the row and column decoder 50 to select some or all of the flash memory cells in the required flash memory module 20;

[0084] The programming circuit 30 and the row and column decoder 50 are both connected to each flash memory module 20. The programming circuit 30 is used to supply different voltages to the flash memory module 20. Different from the programming circuit shown in Figures 3 to 4 this programming circuit is respectively connected to multiple flash memory cells in multiple flash memory modules to control the selected flash memory cells among the multiple flash memory cells. For its principle, circuit connection and specific components, refer to the programming circuit described in Figures 3 to 4 which will not be elaborated here.

[0085] The row and column decoder 50 is used to select some or all of the flash memory cells under the control of the control circuit 40. The selected flash memory cells are used for arithmetic or storage operations, or the programming circuit is used to program the selected flash memory cells. The programming principle is as described above, and they can be referred to each other, which will not be elaborated here.

[0086] Next, taking neural network operation as an example, the working principle of the flash memory chip 100 will be described.

[0087] In application areas such as neural networks or deep learning, most calculations are vector-matrix multiplication and addition operations. The flash memory module contains multiple flash memory cells arranged in an array. Each flash memory cell is equivalent to storing a network weight. The flash memory module is equivalent to storing a network weight array. When the input signal is applied to the flash memory module, according to Kirchhoff's law, the flash memory module outputs multiple current sums to realize the matrix multiplication function.

[0088] The flash memory chip 100 utilizes a plurality of flash memory modules to implement operations of multiple layers of neurons in a neural network, and the plurality of flash memory modules are connected in series to implement data transmission between layers of the neural network.

[0089] The input interface circuit receives the signal input by the external circuit, which can be regarded as a vector, and applies the vector to the flash memory module 1. Through the multi-layer cascaded flash memory modules, each level of the flash memory module completes the operation of a layer of neurons in the neural network. The multi-level flash memory module is equivalent to completing the operation of multiple layers of neurons, thereby realizing the neural network operation and obtaining the processing result.

[0090] During the neural network training process, it is necessary to repeatedly adjust the parameters of the neural network (regarding the value that needs to be adjusted each time as short-term data), namely: the weight of the flash memory unit in the flash memory module. At this time, the flash memory unit weight adjustment can be achieved by adjusting the voltage of the analog capacitor unit in the flash memory unit. When the adjustment times reach the times threshold or the voltage of the analog capacitor unit reaches the threshold voltage, the control circuit controls the programming circuit to generate a programming voltage applied to the programmable semiconductor device, and adjusts the threshold voltage of the programmable semiconductor device so that the threshold voltage of the programmable semiconductor device is equal to the original threshold voltage plus the analog capacitor unit voltage (equivalent to long-term data), and the voltage in the analog capacitor unit is completely discharged, and then the short-term data is stored in the analog capacitor unit. This process is repeated to achieve the training process, and the erasure times of the programmable semiconductor device are effectively reduced to prevent the aging of the programmable semiconductor device, thereby increasing the service life of the flash memory chip.

[0091] The row and column decoders 50 are controlled by the control circuit 40 to select part or all of the flash memory cells in the required flash memory module 20 .

[0092] In an optional embodiment, the flash memory chip may also include supporting circuit modules such as ADC, DAC and shift register to assist the flash memory module in processing deep learning neural network tasks.

[0093] Figure 7 The circuit of the flash memory chip of the embodiment of the present invention Figure 2 .like Figure 7As shown, the flash memory chip 200 includes: an input interface circuit 201, a programming circuit (not shown in the figure), a row-column decoder (not shown in the figure), a control circuit (not shown in the figure), an output interface circuit 202, an on-chip memory 203, and t - 2 flash memory modules 204 as shown in Figure 5 ; each flash memory module 204 includes a plurality of flash memory cells as shown in Figure 1 or Figure 2 arranged in an array;

[0094] One end of the input interface circuit 201 is connected to an external circuit, and the other end is connected to the input terminal of the on-chip memory 203, for receiving the input signal of the external circuit and transmitting it to the on-chip memory 203;

[0095] One end of the output interface circuit 202 is connected to the output terminal of the on-chip memory 203, and the other end is connected to an external circuit, for outputting the data in the on-chip memory 203 to the external circuit;

[0096] A plurality of flash memory modules 204 are respectively connected to the on-chip memory 203. Each flash memory module 204 reads the data in the on-chip memory 203, performs arithmetic processing on the data to obtain an arithmetic result, and transmits the arithmetic result back to the on-chip memory 203.

[0097] The flash memory module includes: a NOR flash memory processing array and a NAND flash memory processing array. Of course, the present invention is not limited thereto.

[0098] The on-chip memory can be SRAM, DRAM, FLASH, etc., including but not limited to this.

[0099] The control circuit is connected to the programming circuit and the row-column decoder, for controlling the voltage value and output direction generated by the programming circuit, and controlling the row-column decoder to select some or all of the flash memory cells in the required flash memory module;

[0100] The programming circuit and the row-column decoder are both connected to each flash memory module 203. The programming circuit is used to supply different voltages to the flash memory module 203. Different from the programming circuit shown in Figures 3 to 4 , this programming circuit is respectively connected to a plurality of flash memory cells in a plurality of flash memory modules to control the selected flash memory cells among the plurality of flash memory cells. For its principle, circuit connection, and specific components, refer to the Figures 3 to 4 described programming circuit, which will not be elaborated here.

[0101] The row-column decoder is used to select some or all of the flash memory cells in the flash memory module 203 under the control of the control circuit. The selected flash memory cells are used for arithmetic or storage work, or the programming circuit is used to program the selected flash memory cells. Its programming principle is as described above, and they can be referred to each other, which will not be elaborated here.

[0102] Next, taking neural network operations as an example, the working principle of the flash memory chip 200 will be described.

[0103] Compared with the flash memory chip 100, in this flash memory chip 200, the on-chip memory is used to store input data and data to be processed (i.e., the operation results of each flash memory module). The flash memory module reads data from the on-chip memory for operation processing as needed. If a certain flash memory module needs to perform further operation processing on the processing results of other flash memory modules, it only needs to read the processing results stored in the on-chip memory, and there is no need to cascade this flash memory module with other flash memory modules. Therefore, the decoupling of each flash memory module is realized. Furthermore, when using the flash memory chip 200 in different application scenarios, some or all of the multiple flash memory modules can be selectively used according to different operation requirements to achieve different operation functions, thereby increasing the flexibility of use of the flash memory chip 200 and having good applicability.

[0104] During the neural network training process, it is necessary to repeatedly adjust the parameters of the neural network (regarding the value that needs to be adjusted each time as short-term data), that is: the weights of the flash memory cells in the flash memory module. At this time, by adjusting the voltage of the analog capacitor unit in the flash memory cell, the adjustment of the flash memory cell weight can be achieved. When the number of adjustment times reaches the number threshold or the voltage of the analog capacitor unit reaches the threshold voltage, the control circuit controls the programming circuit to generate a programming voltage and apply it to the programmable semiconductor device to adjust the threshold voltage of the programmable semiconductor device, so that the threshold voltage of the programmable semiconductor device is equal to the original threshold voltage plus the voltage of the analog capacitor unit (equivalent to long-term data), and all the voltage in the analog capacitor unit is discharged. Then, the short-term data is stored in the analog capacitor unit again. Repeating this process can achieve the training process and effectively reduce the number of erase / write operations of the programmable semiconductor device, prevent the programmable semiconductor device from aging, and thus increase the service life of this flash memory chip.

[0105] In an optional embodiment, the flash memory chip 200 may further include: a writing circuit, a reading circuit, and supporting circuit modules such as a DAC, an ADC, and a shift register, which are used to assist the flash memory module in processing deep learning neural network tasks.

[0106] The output end of the flash memory module is sequentially connected to the ADC, the writing circuit, and the on-chip memory. Since the operation result output by the flash memory module is analog information, an ADC is connected to the output end of the flash memory module to convert the analog operation result into a digital signal that can be stored in the on-chip memory. This digital signal is written into a predetermined address of the on-chip memory through the writing circuit, realizing the storage of analog information using a digital memory.

[0107] The output terminal of the on-chip memory is sequentially connected to a reading circuit, a DAC, and a flash memory module. The reading circuit is used to read the data required by the flash memory module from the on-chip memory. Since the on-chip memory is a digital memory, the signal read by the reading circuit is a digital signal, and the DAC is used to convert the digital signal into an analog input signal required by the flash memory module.

[0108] Among them, the control circuit can be used to control the working state of each flash memory module, the weights of the flash memory cells in the flash memory module, the writing address of the writing circuit, and the reading address of the reading circuit, etc.

[0109] Among them, the working state includes an operating state and a stop state. Specifically, when the flash memory chip works in a situation with a large amount of computation, all flash memory modules can be controlled to work. When the flash memory chip works in a situation with a small amount of computation, some flash memory modules can be controlled to work, realizing flexible adjustment of the chip architecture and effectively increasing the applicability of the flash memory chip.

[0110] The row-column decoder is used to select the flash memory cells to be programmed and control the reading circuit to read data according to the reading address and control the writing circuit to write data according to the writing address.

[0111] In the flash memory chip, each flash memory module is used to implement the operations of some neurons in the neural network and store the operation results in the on-chip memory.

[0112] The flash memory chip is suitable for being applied in electronic devices such as smart phones, tablet computers, smart wearable devices, vehicle navigators, smart TVs, smart cameras, smart bracelets, game devices, virtual reality devices, etc. to implement various computing functions, especially neural network operations.

[0113] Those skilled in the art can understand that in the above flash memory cells, flash memory modules, and flash memory circuits, conventional peripheral circuit structures such as reading circuits, writing circuits, and filtering circuits can also be included to make the functions of each flash memory cell, flash memory module, and flash memory circuit more perfect. Since these circuits are existing designs, those skilled in the art can all understand that in each embodiment, the core solutions of the present invention are mainly described, and other peripheral circuits will not be elaborated.

[0114] In summary, the flash memory cells, flash memory modules, and flash memory chips provided by the embodiments of the present invention can effectively reduce the number of erase and write operations of programmable semiconductor devices, avoid the aging of programmable semiconductor devices, support in-situ training of neural networks, and are widely used in systems that use neural networks for operations such as voice processing systems, image processing systems, video tracking systems, network fault handling systems, seismic data processing systems, navigation systems, reconnaissance systems, and intelligent monitoring systems.

[0115] The various embodiments in this specification are described in a progressive manner. For the same or similar parts among the various embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized.

[0116] Although the present application is depicted through embodiments, those of ordinary skill in the art know that the present application has many variations and changes without departing from the spirit of the present application. It is hoped that the appended claims will cover these variations and changes without departing from the spirit of the present application.

[0117] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device comprising a series of elements not only includes those elements but also other elements not explicitly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, commodity or device comprising the said element.

[0118] In the present invention, specific embodiments are used to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A flash memory cell, characterized in that, it comprises: a programmable semiconductor device for storing long-term data and an analog capacitor unit for storing short-term data, the programmable semiconductor device being connected in parallel with the analog capacitor unit; wherein, the output current of the flash memory cell is the sum of the output current of the programmable semiconductor device and the output current of the analog capacitor unit, and the output current of the flash memory cell is adjusted by adjusting the voltage of the analog capacitor unit; when the number of erase / write cycles of the analog capacitor unit reaches a preset number or the voltage of the analog capacitor unit reaches a preset voltage, the voltage of the analog capacitor unit is transferred to the programmable semiconductor device.

2. The flash memory cell according to claim 1, characterized in that, the analog capacitor unit comprises: an output transistor, a charging transistor, a discharging transistor and a capacitor; the drain of the output transistor is connected to the drain of the programmable semiconductor device, the source is connected to the source of the programmable semiconductor device, and the gate is connected to one end of the capacitor; the source of the charging transistor is connected to a high voltage, the gate is connected to a first control voltage, and the drain is connected to the other end of the capacitor; the source of the discharging transistor is connected to a low voltage, the gate is connected to a second control voltage, and the drain is connected to the other end of the capacitor.

3. The flash memory cell according to claim 2, characterized in that, it further comprises: a programming circuit, the programming circuit is connected to the gate of the charging transistor and / or the gate of the discharging transistor, and is used to provide the first control voltage and / or the second control voltage to the charging transistor and the discharging transistor.

4. The flash memory cell according to claim 3, characterized in that, the programming circuit is further connected to the programmable semiconductor device, and is used to provide a programming voltage to the programmable semiconductor device.

5. The flash memory cell according to claim 4, characterized in that, the programming circuit comprises: a voltage generating circuit and a voltage control circuit, the voltage generating circuit is used to generate the first control voltage and / or the second control voltage and / or the programming voltage, and the voltage control circuit is used to load the voltage generated by the voltage generating circuit to the corresponding charging transistor and / or discharging transistor and / or programmable semiconductor device.

6. The flash memory cell according to claim 5, characterized in that, it further comprises: a control circuit, connected to the programming circuit, for controlling the operation of the programming circuit.

7. A flash memory module, characterized in that, it comprises a plurality of flash memory cells as described in any one of claims 1 to 2 arranged in an array, and a peripheral circuit and a control circuit, the peripheral circuit being connected to the flash memory cells and the control circuit.

8. The flash memory module according to claim 7, characterized in that, the peripheral circuit comprises: a programming circuit, the programming circuit being connected to the flash memory cells and the control circuit.

9. The flash memory module according to claim 8, characterized in that, the peripheral circuit further comprises: a row-column decoder, the row-column decoder being connected to the flash memory cells and the control circuit.

10. A flash memory chip, characterized in that, it comprises: An input interface circuit, a programming circuit, a row-column decoder, a control circuit, an output interface circuit, and a plurality of flash memory modules; each flash memory module includes a plurality of flash memory cells as described in any one of claims 1 to 2 arranged in an array; A plurality of the flash memory modules are connected in series to form a series branch; One end of the input interface circuit is connected to an external circuit, and the other end is connected to the input end of the series branch; One end of the output interface circuit is connected to the output end of the series branch, and the other end is connected to an external circuit; The control circuit is connected to the programming circuit and the row-column decoder; The programming circuit and the row-column decoder are both connected to each flash memory module.

11. A flash memory chip, characterized in that, it includes: An input interface circuit, a programming circuit, a row-column decoder, a control circuit, an output interface circuit, an on-chip memory, and a plurality of flash memory modules; each flash memory module includes a plurality of flash memory cells as described in any one of claims 1 to 2 arranged in an array; One end of the input interface circuit is connected to an external circuit, and the other end is connected to the input end of the on-chip memory; One end of the output interface circuit is connected to the output end of the on-chip memory, and the other end is connected to an external circuit; A plurality of flash memory modules are respectively connected to the on-chip memory; The control circuit is connected to the programming circuit and the row-column decoder; The programming circuit and the row-column decoder are both connected to each flash memory module.

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