Semiconductor device and method for manufacturing the same, package and method for manufacturing the same

Abstract

The present invention relates to the field of semiconductor technology, and proposes a semiconductor device, which includes a stacking structure and an electrode; the stacking structure includes at least one chip; the electrode is located on the side surface of the stacking structure, and the length of the electrode in the chip thickness direction is greater than or equal to the thickness of the chip. The semiconductor device avoids the use of micro-bump connections, which reduces the thickness of the stacking structure and is conducive to thinning. The electrode is arranged on the side surface of the stacking structure, and there is no need to set a connection point on the wiring layer. When designing the circuit, there is no need to consider the reserved connection position, and there will be no restrictions on the circuit layout setting on the chip. The length of the electrode in the chip thickness direction is greater than or equal to the thickness of the chip, which is convenient for connecting circuits on multiple chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the semiconductor device, a package having the semiconductor device and a method for preparing the package. Background Art

[0002] High-capacity, thin-film storage devices are gaining more and more popularity in the market.

[0003] Reference Figure 1 The schematic diagram of the connection structure of the chips after stacking in the prior art is shown; the existing chips 1 are connected through silicon vias 2 and micro-bumps 3 after being stacked. In order to achieve better welding effect and conductivity, the size of the micro-bumps 3 needs to be increased, which limits the circuit layout setting and cannot better achieve high capacity and thinness. The existing memory cannot achieve higher capacity because the effective heat dissipation area cannot be increased. Moreover, the packaging structure cannot be better thinned because it is limited by the length and width of the chip 1.

[0004] Therefore, it is necessary to study a semiconductor device and a method for preparing the semiconductor device, a package having the semiconductor device and a method for preparing the package.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art that it is difficult to achieve high capacity and thinness, and to provide a semiconductor device and a method for preparing a semiconductor device that can easily achieve high capacity and thinness, a package having the semiconductor device, and a method for preparing the package.

[0007] Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

[0008] According to one aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0009] A stacked structure including at least one chip;

[0010] The electrode is located on the side surface of the stacked structure, and the length of the electrode in the thickness direction of the chip is greater than or equal to the thickness of the chip.

[0011] In an exemplary embodiment of the present disclosure, the semiconductor device further includes:

[0012] A wiring layer is provided on the chip, wherein the wiring layer is provided with a plurality of signal terminals, and the plurality of signal terminals are electrically connected to the electrodes through the wiring layer.

[0013] In an exemplary embodiment of the present disclosure, the stacking structure comprises:

[0014] First chip;

[0015] The second chip is arranged on the first chip.

[0016] In an exemplary embodiment of the present disclosure, a first wiring layer is disposed on the first chip, a second wiring layer is disposed on the second chip, and the first wiring layer and the second wiring layer are electrically connected through silicon vias.

[0017] In an exemplary embodiment of the present disclosure, the electrode is electrically connected to one or more of the first wiring layer and the second wiring layer.

[0018] In an exemplary embodiment of the present disclosure, a notch is provided on the chip, and the electrode is provided in the notch.

[0019] In an exemplary embodiment of the present disclosure, the semiconductor device further comprises: a bump, which is arranged on a side of the electrode away from the chip, and the bump protrudes from the notch.

[0020] In an exemplary embodiment of the present disclosure, the bump covers the electrode and a connection between the electrode and the wiring layer.

[0021] According to one aspect of the present disclosure, there is provided a package, comprising:

[0022] A semiconductor device as described in any one of the above;

[0023] The packaging substrate is arranged on the side surface of the stacking structure and is electrically connected to the electrode.

[0024] In an exemplary embodiment of the present disclosure, the package further includes:

[0025] The packaging film is disposed on a surface of the stacking structure where the packaging substrate is not disposed.

[0026] According to one aspect of the present disclosure, there is provided a method for preparing a semiconductor device, comprising:

[0027] forming a stacked structure, wherein the stacked structure comprises at least one chip;

[0028] An electrode is formed on a side surface of the stacked structure, and a length of the electrode in a thickness direction of the chip is greater than or equal to the thickness of the chip.

[0029] In an exemplary embodiment of the present disclosure, before forming the stacked structure, the method for preparing the semiconductor device further includes:

[0030] A wiring layer is formed on the chip, and the wiring layer is electrically connected to the electrodes to be formed subsequently.

[0031] In an exemplary embodiment of the present disclosure, a stacked structure is formed, including:

[0032] forming a first chip;

[0033] A second chip is formed over the first chip.

[0034] In an exemplary embodiment of the present disclosure, a first wiring layer is provided on the first chip, and a second wiring layer is provided on the second chip. Before forming the stacked chip structure, the preparation method further includes:

[0035] A first through silicon via is formed on the second chip, wherein the first through silicon via electrically connects the first wiring layer and the second wiring layer.

[0036] In an exemplary embodiment of the present disclosure, a second TSV is formed in the sealing area of ​​the second chip while the first TSV is formed.

[0037] In an exemplary embodiment of the present disclosure, forming an electrode on a side surface of the stack structure includes:

[0038] A portion of the sealing area is removed or a portion of the sealing area and a portion of the second TSV are removed to expose the second TSV to form the electrode, and the electrode is located on a side surface of the stacked structure.

[0039] In an exemplary embodiment of the present disclosure, after forming the electrode, the preparation method further includes:

[0040] A bump is formed on a side of the electrode away from the chip.

[0041] According to one aspect of the present disclosure, there is provided a method for preparing a package, comprising:

[0042] Forming any one of the semiconductor devices described above;

[0043] A packaging substrate is formed on a side surface of the stack structure, and the packaging substrate is electrically connected to the electrode.

[0044] In an exemplary embodiment of the present disclosure, a packaging film is formed on a surface of the stacked structure where the packaging substrate is not formed.

[0045] As can be seen from the above technical solutions, the present invention has at least one of the following advantages and positive effects:

[0046] The semiconductor device of the present invention includes a stacked structure formed by at least one chip, and electrodes are located on the side surface of the stacked structure. The length of the electrodes in the chip thickness direction is greater than or equal to the thickness of the chip. On the one hand, the use of microbumps for connection is avoided, thinning the thickness of the stacked structure, which is beneficial for achieving thinness. On the other hand, the electrodes are provided on the side surface of the stacked structure, eliminating the need to set connection points in the wiring layer. When designing the circuit, there is no need to consider reserving connection positions, and it will not cause restrictions on the circuit layout on the chip. On the still other hand, the length of the electrodes in the chip thickness direction is greater than or equal to the thickness of the chip, facilitating the connection of circuits on multiple chips.

[0047] The package of the present invention includes the above semiconductor device and a package substrate provided on the side surface of the stacked structure. The package substrate is electrically connected to the electrodes. On the one hand, the package substrate is arranged on the side surface of the stacked structure, enabling better thinness. On the other hand, the upper and lower surfaces of the stacked structure can serve as heat dissipation surfaces, increasing the effective heat dissipation area, which is beneficial for realizing higher capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] By referring to the accompanying drawings and describing its exemplary embodiments in detail, the above and other features and advantages of the present invention will become more apparent.

[0049] Figure 1 is a schematic diagram of the connection structure after chip stacking in the prior art;

[0050] Figure 2 is a schematic diagram of a structure of an exemplary embodiment of the semiconductor device of the present invention;

[0051] Figure 3 is Figure 2 a three-dimensional structure diagram of the semiconductor device shown in

[0052] Figure 4 is a schematic diagram of a structure of another exemplary embodiment of the semiconductor device of the present invention;

[0053] Figure 5 is a schematic flowchart of the manufacturing method of the semiconductor device of the present invention;

[0054] Figure 6 is a schematic diagram of the structure of the chip;

[0055] Figure 7 is a schematic diagram of the structure of forming silicon vias in the sealing area of the chip;

[0056] Figure 8 is a schematic diagram of the structure after the chips form a stacked structure;

[0057] Fig. 9 It is a schematic diagram of the structure after removing part of the sealing area of ​​the chip;

[0058] Fig.10 It is a schematic diagram of the structure after the stacked structure forms a bump;

[0059] Fig.11 yes Fig.10 A partial top view of a diagram;

[0060] Fig.12 is a schematic structural diagram of an exemplary embodiment of a package of the present invention;

[0061] Fig.13 yes Fig.12 A top view schematic diagram of

[0062] Fig.14 It is a schematic flow chart of the method for preparing the package of the present invention.

[0063] The main components in the figure are described as follows:

[0064] In the prior art: 1. Chip; 2. Silicon via; 3. Micro-bump;

[0065] In the present invention: 41, a first chip; 42, a first sub-chip; 43, a second sub-chip; 44, a third sub-chip;

[0066] 51, first wiring layer; 52, second wiring layer; 53, third wiring layer; 54, fourth wiring layer;

[0067] 6. Electrode; 61. First electrode; 62. Second electrode; 63. Third electrode; 64. Fourth electrode; 65. Fifth electrode;

[0068] 7. Bump;

[0069] 8. Chip; 81. Circuit area; 82. Sealing area; 83. Lead wire;

[0070] 91. a first through silicon via; 92. a second through silicon via;

[0071] 10. Packaging substrate; 11. Packaging film;

[0072] 121, a first signal terminal; 122, a second signal terminal; 123, a third signal terminal; 124, a fourth signal terminal; 125, a fifth signal terminal. DETAILED DESCRIPTION

[0073] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0074] The present invention provides a semiconductor device, which may include a stacking structure, a wiring layer and an electrode, wherein the stacking structure includes at least one chip; the electrode is located on the side surface of the stacking structure, and the length of the electrode in the thickness direction of the chip is greater than or equal to the thickness of the chip.

[0075] The semiconductor device of the present invention, on the one hand, avoids the use of micro-bump connections, reduces the thickness of the stacked structure, and is conducive to achieving thinness. On the other hand, the electrode is arranged on the side surface of the stacked structure, and there is no need to set a connection point on the wiring layer. When designing the circuit, there is no need to consider the reserved connection position, which will not cause restrictions on the circuit layout setting on the chip. On the other hand, the length of the electrode in the chip thickness direction is greater than or equal to the thickness of the chip, which is convenient for connecting circuits on multiple chips.

[0076] In this exemplary embodiment, the side of the chip provided with the wiring layer is referred to as "upper", the side opposite to "upper" is referred to as "lower", and the side surfaces are connected between the upper and lower parts.

[0077] The stacked structure may include only the first chip, or may include the first chip and the second chip, and the second chip may include one or more layers of chips.

[0078] In this example implementation, refer to Figure 2 A schematic diagram of the structure of an example implementation of a semiconductor device shown. The stacked structure may include four layers of chips. For the convenience of the following description, the four layers of chips may be referred to as the first chip 41, the first sub-chip 42, the second sub-chip 43 and the third sub-chip 44 from bottom to top, respectively. The first sub-chip 42, the second sub-chip 43 and the third sub-chip 44 form the second chip. A wiring layer is provided on each layer of chips. The wiring layer on the first chip 41 may be referred to as the first wiring layer 51, the wiring layer on the first sub-chip 42 may be referred to as the second wiring layer 52, the wiring layer on the second sub-chip 43 may be referred to as the third wiring layer 53, and the wiring layer on the third sub-chip 44 may be referred to as the fourth wiring layer 54. In addition, the specific structure of the stacked structure is not limited to the above description. For example, the stacked structure may include only one layer of chips, or may include two layers of chips, three layers of chips, five layers of chips or more layers of chips.

[0079] Reference Figure 2The schematic diagram of the structure of an exemplary embodiment of a semiconductor device is shown in FIG. The first wiring layer 51 , the second wiring layer 52 , the third wiring layer 53 and the fourth wiring layer 54 may be electrically connected through silicon vias, or may not be connected to each other.

[0080] In this example embodiment, a notch is provided on the side of the first sub-chip 42 and the third sub-chip 44, and the electrode 6 is formed in the notch. The electrode 6 provided on the first sub-chip 42 electrically connects the wiring layer on the first chip with the wiring layer on the first sub-chip, and the electrode 6 provided on the third sub-chip 44 electrically connects the wiring layer on the second sub-chip 43 with the wiring layer on the third sub-chip 44. The notch and the electrode 6 can be formed by removing part of the chip, that is, first forming a silicon via at the position where the electrode 6 needs to be formed, and then removing part of the chip to expose the silicon via to form the electrode 6. When the silicon via penetrates a layer of chip, the length of the electrode 6 in the chip thickness direction is greater than or equal to the thickness of the chip, and when the silicon via penetrates two layers of chips or multiple layers of chips, the length of the electrode 6 in the chip thickness direction is greater than the thickness of the chip. Of course, in other example embodiments of the present invention, the electrode 6 can be directly provided on the side of the chip, without having to be provided in the notch.

[0081] Reference Figure 3 In the three-dimensional structural diagram of the semiconductor device shown, five electrodes 6 are formed on the same side surface of the stacked structure, which can be respectively referred to as a first electrode 61, a second electrode 62, a third electrode 63, a fourth electrode 64 and a fifth electrode 65.

[0082] The first electrode 61 is electrically connected to the first signal terminal 121 through the first wiring layer 51. The second electrode 62 is electrically connected to the second signal terminal 122 through the second wiring layer 52. The third signal terminal 123 of the first wiring layer 51, the third signal terminal 123 of the second wiring layer 52, the third signal terminal 123 of the third wiring layer 53, and the third signal terminal 123 of the fourth wiring layer 54 are electrically connected through silicon vias and then connected to the third electrode 63, that is, the third electrode 63 is electrically connected to the third signal terminal 123 through the first wiring layer 51, the second wiring layer 52, the third wiring layer 53, and the fourth wiring layer 54. The fourth electrode 64 is electrically connected to the fourth signal terminal 124 through the fourth wiring layer 54. The fifth electrode 65 is electrically connected to the fifth signal terminal 125 through the third wiring layer 53. Such a setting can realize that individual signals on individual chips can be controlled by electrodes alone, and can also realize collective control of multiple signals on multiple chips, and whether to realize individual control or collective control according to the needs of the signal. Of course, the first electrode 61 can also be electrically connected to the first wiring layer 51 and the second wiring layer 52. The first wiring layer 51 and the second wiring layer 52 can be connected through silicon vias and then electrically connected to the first electrode 61. The first wiring layer 51 and the second wiring layer 52 can also be provided with leads and then directly electrically connected through the first electrode 61.

[0083] In this example implementation, refer to Figure 4 Schematic diagram of another exemplary embodiment of the semiconductor device shown. The semiconductor device may further include a bump 7, which is arranged on a side of the electrode 6 away from the chip, and the bump 7 protrudes from the notch, that is, the bump 7 covers the position of the chip where the electrode 6 is arranged. The bump 7 covers the electrode 6 and the connection between the electrode 6 and the wiring layer, that is, the length of the bump 7 is greater than or equal to the length of the electrode 6, and the width of the bump 7 is greater than or equal to the width of the electrode 6.

[0084] Furthermore, the present invention also provides a method for preparing a semiconductor device, referring to Figure 5 The schematic diagram of the process of manufacturing a semiconductor device shown in FIG. 1 is a schematic diagram of the process of manufacturing a semiconductor device, and the manufacturing method may include the following steps:

[0085] Step S10 , forming a stacking structure, wherein the stacking structure includes at least one chip 8 .

[0086] Step S20 , forming an electrode 6 on the side surface of the stacked structure, wherein the length of the electrode 6 in the thickness direction of the chip 8 is greater than or equal to the thickness of the chip 8 .

[0087] The following is a detailed description of each step of the method for preparing a semiconductor device.

[0088] Before forming the stacked structure, it is necessary to form a wiring layer on each chip 8. The method of forming the wiring layer can be a printing method, a vapor deposition method, etc., which will not be described in detail here. Figure 6 The schematic diagram of the chip structure shown in FIG. 8 shows that the chip 8 includes a circuit area 81 and a sealing area 82. The circuit area 81 is used to accommodate the wiring layer, and the sealing area 82 is used for packaging and sealing. The wiring layer on each chip 8 that needs to be connected to the outside can form a lead 83 to lead out to the sealing area 82.

[0089] Reference Figure 7 The schematic diagram of the structure of forming a through silicon via in the sealing area 82 of the chip 8 is shown. When the first through silicon via 91 is formed, a second through silicon via 92 can be formed in the sealing area 82 of the chip. The second through silicon via 92 is connected to the lead 83 formed in the sealing area 82. The second through silicon via 92 is formed at the same time as the first through silicon via 91, which saves the process flow.

[0090] Step S10: forming a stacking structure, wherein the stacking structure includes at least one chip.

[0091] In this exemplary embodiment, a four-layer chip is used as an example for description. Figure 8The schematic diagram of the structure after the stacking structure is formed is shown. For the convenience of the following description, the four-layer chip can be referred to as the first chip 41, the first sub-chip 42, the second sub-chip 43 and the third sub-chip 44 from bottom to top. The first silicon through-hole 91 can be formed on the first sub-chip 42, the second sub-chip 43 and the third sub-chip 44 respectively, and the first silicon through-hole 91 can connect the wiring layer on the first chip 41, the wiring layer on the first sub-chip 42, the wiring layer on the second sub-chip 43 and the wiring layer on the third sub-chip 44. The first sub-chip 42 is formed on the above-mentioned first chip 41, the second sub-chip 43 is formed on the first sub-chip 42, and the third sub-chip 44 is formed on the second sub-chip 43. Of course, the number of chips can also be one, two, three, five or more. In the case of one chip, since the chip does not need to be connected to the chip located below the chip, the first silicon through-hole 91 may not be formed; the second silicon through-hole 92 may be directly formed in the sealing area 82 of the first chip 41.

[0092] Step S20 , forming an electrode 6 on the side surface of the stacked structure, wherein the length of the electrode 6 in the thickness direction of the chip is greater than or equal to the thickness of the chip.

[0093] Reference Fig. 9 The schematic diagram of the structure after a part of the sealing area 82 of the chip 8 is removed is shown.

[0094] In this exemplary embodiment, after the stacking structure is formed, part of the sealing area 82 and part of the second silicon through hole 92 can be removed by grinding or other methods until the diameter of the second silicon through hole 92, so that the exposed second silicon through hole 92 forms a rectangular connection plane, and the area of ​​the connection plane is the largest at this time, which is convenient for the subsequent formation and connection of the bump 7. The exposed second silicon through hole 92 forms the electrode 6. Of course, in other exemplary embodiments of the present invention, only the material of the sealing area 82 can be removed without removing the material of the second silicon through hole 92, or the second silicon through hole 92 can be exposed to form the electrode 6. Since the electrode 6 is formed by the second silicon through hole 92, the length of the electrode 6 in the chip thickness direction is greater than the thickness of the chip. When the second silicon through hole 92 is formed at the same position of the two chips, the length of the electrode 6 in the chip thickness direction is greater than the thickness of the chip. The connection surface between the electrode 6 formed by the second silicon through hole 92 and the wiring layer is larger and the connection is more firm. In addition, the formation of the electrode 6 is not limited to the above description, and the electrode 6 can be directly formed on the side surface of the stacking structure by evaporation or printing.

[0095] Fig. 9 The electrode 6 shown in the figure is formed on one side surface of the stacked structure. Of course, the electrode 6 can also be arranged on two side surfaces or multiple side surfaces of the stacked structure, which all fall within the protection scope of the present invention.

[0096] In this exemplary embodiment, after forming the electrode 6, the preparation method may further include: forming a bump 7 on a side of the electrode 6 away from the chip. Fig.10 as well as Fig.11 The schematic diagram of the structure after the bump 7 is formed is shown. The bump 7 is arranged in a long strip shape, and the bump 7 is arranged on the side of the electrode 6 away from the chip 8, that is, the bump 7 covers the position where the electrode 6 is arranged on the chip 8. The bump 7 covers the electrode 6 and the connection between the electrode 6 and the wiring layer, that is, the length of the bump 7 is greater than or equal to the length of the electrode 6, and the width of the bump 7 is greater than or equal to the width of the electrode 6.

[0097] Furthermore, the present invention also provides a package, referring to Fig.12 as well as Fig.13 The package shown in the figure may include a semiconductor device, a package substrate 10 and a package film 11. The package substrate 10 is disposed on the side surface of the stack structure and is electrically connected to the electrode 6. The package film 11 is disposed on the surface of the stack structure where the package substrate 10 is not disposed.

[0098] The specific structure of the semiconductor device has been described in detail above, so it will not be repeated here.

[0099] In this example embodiment, one packaging substrate 10 is provided, which is provided on the side of the stacked structure where the electrode 6 is provided. Of course, in the case where electrodes 6 are provided on multiple side surfaces of the stacked structure, multiple packaging substrates 10 can be provided, all of which are provided on the side surfaces of the stacked structure, and the packaging film 11 is provided on the upper and lower surfaces with larger areas of the stacked structure, thereby increasing the heat dissipation area of ​​the package. The upper and lower surfaces of the stacked structure can be used as heat dissipation surfaces to increase the effective heat dissipation area, which is conducive to the realization of higher capacity. Moreover, the packaging substrate 10 is provided on the side surface of the stacked structure, which can better achieve thinness.

[0100] Furthermore, the present invention also provides a method for preparing a package, referring to Fig.14 The schematic diagram of the process of preparing the package shown in FIG. 1 is a schematic diagram of the process of preparing the package, and the process of preparing the package may include the following steps:

[0101] Step S60, forming the semiconductor device.

[0102] Step S70 , forming a packaging substrate 10 on the side surface of the stacked structure, wherein the packaging substrate 10 is electrically connected to the electrode 6 .

[0103] In the present exemplary embodiment, a packaging film 11 is formed on a surface of the stacked structure where the packaging substrate 10 is not formed.

[0104] The features, structures or characteristics described above may be combined in one or more embodiments in any suitable manner, and if possible, the features discussed in each embodiment are interchangeable. In the above description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0105] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned over so that it is upside down, the component described as being "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", etc., are also used to have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0106] In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising", "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0107] It should be understood that the present invention is not limited in its application to the detailed structure and arrangement of the components proposed in this specification. The present invention can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present invention. It should be understood that the present invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for implementing the present invention and will enable those skilled in the art to utilize the present invention.

Claims

1. A semiconductor device, It is characterized in that include: A stacked structure, wherein the stacked structure comprises a plurality of chips, wherein the chip comprises a circuit area and a sealing area, wherein the circuit area has a first through silicon via, and the sealing area has a second through silicon via; the chip comprises a first chip and a second chip, wherein a first sub-chip, a second sub-chip and a third sub-chip form the second chip, wherein a wiring layer is arranged on each layer of the chip, wherein the wiring layer on the first chip is a first wiring layer, the wiring layer on the first sub-chip is a second wiring layer, the wiring layer on the second sub-chip is a third wiring layer, and the wiring layer on the third sub-chip is a fourth wiring layer; and the first through silicon via connects the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer; An electrode is located on a side surface of the stacked structure, and a portion of the sealing area and a portion of the second TSV are removed until the diameter of the second TSV is reached, and the exposed second TSV forms the electrode; The electrodes include a first electrode, a second electrode, a third electrode, a fourth electrode and a fifth electrode, the first electrode is electrically connected to the first signal terminal through the first wiring layer, the second electrode is electrically connected to the second signal terminal through the second wiring layer, the third signal terminal of the first wiring layer, the third signal terminal of the second wiring layer, the third signal terminal of the third wiring layer and the third signal terminal of the fourth wiring layer are electrically connected through the first silicon via and then connected to the third electrode, the fourth electrode is electrically connected to the fourth signal terminal through the fourth wiring layer, and the fifth electrode is electrically connected to the fifth signal terminal through the third wiring layer.

2. The semiconductor device according to claim 1, It is characterized in that The chip is provided with a notch, and the electrode is arranged in the notch.

3. The semiconductor device according to claim 2, It is characterized in that The semiconductor device further comprises: a bump, which is arranged on a side of the electrode away from the chip, and the bump protrudes from the notch.

4. The semiconductor device according to claim 3, It is characterized in that The bump covers the electrode and a connection between the electrode and the wiring layer.

5. A package, It is characterized in that include: The semiconductor device according to any one of claims 1 to 4; The packaging substrate is arranged on the side surface of the stacking structure and is electrically connected to the electrode.

6. The package according to claim 5, It is characterized in that The package also includes: The packaging film is disposed on a surface of the stacking structure where the packaging substrate is not disposed.

7. A method for preparing a semiconductor device, It is characterized in that include: A stacked structure is formed, wherein the stacked structure comprises a plurality of chips, wherein the chip comprises a circuit area and a sealing area, wherein the circuit area has a first through silicon via, and the sealing area has a second through silicon via; wherein the chip comprises a first chip and a second chip, wherein a first sub-chip, a second sub-chip and a third sub-chip form the second chip, wherein a wiring layer is arranged on each layer of the chip, wherein the wiring layer on the first chip is a first wiring layer, the wiring layer on the first sub-chip is a second wiring layer, the wiring layer on the second sub-chip is a third wiring layer, and the wiring layer on the third sub-chip is a fourth wiring layer; wherein the first through silicon via connects the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer; forming an electrode on a side surface of the stacked structure, removing a portion of the sealing area and a portion of the second TSV until the diameter of the second TSV, and the exposed second TSV forms the electrode; The electrodes include a first electrode, a second electrode, a third electrode, a fourth electrode and a fifth electrode, the first electrode is electrically connected to the first signal terminal through the first wiring layer, the second electrode is electrically connected to the second signal terminal through the second wiring layer, the third signal terminal of the first wiring layer, the third signal terminal of the second wiring layer, the third signal terminal of the third wiring layer and the third signal terminal of the fourth wiring layer are electrically connected through the first silicon via and then connected to the third electrode, the fourth electrode is electrically connected to the fourth signal terminal through the fourth wiring layer, and the fifth electrode is electrically connected to the fifth signal terminal through the third wiring layer.

8. The method for preparing a semiconductor device according to claim 7, It is characterized in that After forming the electrode, the preparation method further comprises: A bump is formed on a side of the electrode away from the chip.

9. A method for preparing a package, It is characterized in that include: Forming the semiconductor device according to any one of claims 1 to 4; A packaging substrate is formed on a side surface of the stack structure, and the packaging substrate is electrically connected to the electrode.

10. The method for preparing a package according to claim 9, It is characterized in that A packaging film is formed on a surface of the stacked structure where the packaging substrate is not formed.

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