Electronic device comprising a supporting substrate and stacked electronic chips

Abstract

Embodiments of the present disclosure relate to an electronic device including a support substrate and stacked electronic chips. An electronic device includes a support substrate, a first electronic chip and a second electronic chip are mounted to the support substrate in a position one on top of the other. A first electrical connection element is inserted between the first electronic chip and the support substrate. A second electrical connection element is inserted between the second electronic chip and the support substrate and is located at a distance from the periphery of the first electronic chip. A third electrical connection element is inserted between the first electronic chip and the second electronic chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from French patent application number 1872005, filed on November 28, 2018, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Background

[0003] Embodiments relate to electronic devices including stacked electronic chips. Background Art

[0005] Known electronic devices include electronic chips that are adhesively bonded one on top of the other and further bonded on top of a supporting substrate. The chips are offset from each other and are electrically connected to the supporting substrate by electrical connection wires. Such a layout presents difficulties when the wires are mounted and presents drawbacks, in particular due to the length of the wires, such a layout is subject to electrical losses and is sensitive to mutual and surrounding electromagnetic effects. Summary of the invention

[0006] According to one embodiment, an electronic device is proposed, which includes: a supporting substrate having a front side; at least one first electronic chip located on top of the supporting substrate and having a back side, the back side at least partially facing the front side of the supporting substrate; at least one second electronic chip located on top of the first chip and having a back side, a portion of its back side extending facing the front side of the first chip, and a portion of its back side extending beyond at least one edge of the periphery of the first chip and at least partially facing the front side of the supporting substrate; a first electrical connection element inserted between the first chip and the supporting substrate; and a second electrical connection element inserted between the first chip and the supporting substrate and located at a certain distance from the periphery of the first chip.

[0007] Therefore, electrical links between the supporting substrate, the first chip, and the second chip can be short and mechanically stable, and the number of electrical links can be increased.

[0008] The electronic device may include a third electrical connection element interposed between the first chip and the second chip.

[0009] The back side of the second chip may include a recess, and the first chip may be at least partially held in the recess and facing a bottom of the recess.

[0010] The electronic device may include a third electrical connection element inserted between bottoms of the recesses of the first chip and the second chip.

[0011] The first chip may include a base layer, and a substrate layer on one side of the base layer, the substrate layer including an array of electrical connections.

[0012] The array of electrical connections of the first chip may be connected to the supporting substrate by means of first electrical connection elements.

[0013] The array of electrical connections of the first chip may be connected to a third electrical connection element interposed between the first chip and the second chip.

[0014] The base layer of the first chip may be provided with a plurality of electrically connecting through-vias.

[0015] The electrical connection through-via of the first chip may be connected to the supporting substrate through the first electrical connection element.

[0016] The electrical connection through-via of the first chip may be connected to the third electrical connection element inserted between the first chip and the second chip.

[0017] The support substrate may include an array of electrical connections connected to the first electrical connection element and the second electrical connection element.

[0018] The electrical connection elements may include balls, posts or solder joints. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The electronic device will now be described by way of non-limiting exemplary embodiments, which are illustrated by the accompanying drawings, in which:

[0020] Figure 1 showing a cross section of an electronic device;

[0021] Figure 2 Show Figure 1 an enlarged partial cross-section of an electronic device;

[0022] Figure 3 showing a cross section of another electronic device;

[0023] Figure 4 showing a cross section of another electronic device;

[0024] Figure 5 showing a cross section of another electronic device;

[0025] Figure 6 Show Figure 1 A cross-section of a variant embodiment of an electronic device;

[0026] Figure 7 Show Figure 6 an enlarged partial cross-section of an electronic device;

[0027] Figure 8 Show Figure 3 A cross-section of a variant embodiment of an electronic device;

[0028] Fig. 9 Show Figure 4 A cross-section of a variant embodiment of an electronic device; and

[0029] Fig.10 Show Figure 5 A cross section of a variant embodiment of an electronic device. DETAILED DESCRIPTION

[0030] Figure 1 and Figure 2 The electronic device 1 illustrated in the figure comprises a supporting substrate 2 in the form of a sheet, the supporting substrate 2 having a front face 3; a first electronic chip 4, located on the top of the supporting substrate 2, and the first electronic chip 4 having a rear face 5 facing the front face 3 of the supporting substrate 2, and a front face 6.

[0031] The electronic device 1 includes a second electronic chip 7, which is located on top of the first chip 4, and the second electronic chip 7 has a back side 8, a portion of which extends toward the front side 6 of the first chip 4, and another portion of which extends beyond at least part of the periphery of the first chip 4 and faces the front side 3 of the supporting substrate 2, thereby forming a specific stack.

[0032] The electronic device 1 also includes a first electrical connection element 9, which is inserted between the supporting substrate 2 and the first chip 4 (that is, located between the supporting substrate 2 and the first chip 4); and a second electrical connection element 10, which is inserted between the supporting substrate 2 and the second chip 7 (that is, located between the supporting substrate 2 and the second chip 7) and is located at a certain distance from the periphery of the first chip 4.

[0033] For example, the electrical connection element 9 may be formed by a ball, a solder column, and the electrical connection element 10 may be formed by a ball, a solder column, or a solder point, thereby forming a rigid direct electrical connection.

[0034] As in Figure 2 As more explicitly illustrated in FIG. 2 , the support substrate 2 is provided with an array 12 of electrical connections having positive pads to which the first electrical connection elements 9 and the second electrical connection elements 10 are electrically connected.

[0035] The first chip 4 comprises a base plate (substrate) 13 , for example made of silicon, having a face 14 on which electronic components (not shown) are formed, and an interconnect layer 15 comprising an array 16 of electrical connections, formed over the face 14 .

[0036] For example and advantageously, the interconnect layer 15 is located on one side of the support substrate 2 .

[0037] The array 16 of electrical connections of the first chip 4 has pads to which the first electrical connection elements 9 are electrically connected.

[0038] The second chip 7 comprises a base plate (substrate) 18, for example made of silicon, having a face 19 on which electronic components (not shown) are formed, and an interconnection layer 20 formed over the face 19 and comprising an array 21 of electrical connections. For example, the base plate 18 is located on the side opposite to the supporting substrate 2. For example, the layer 19 is located on a side having a portion thereof facing the substrate 2 and a portion thereof facing the first chip 4.

[0039] The array 21 of electrical connections has back pads to which the second electrical connection elements 10 are electrically connected.

[0040] The first electrical connection element 9 and the second electrical connection element 10 are dimensioned so that the front side 6 of the chip 4 and the back side 8 of the chip 7 are in contact or separated from each other by a small distance. A paste or adhesive made of a thermally conductive material may optionally be embedded between the front side 6 of the chip 4 and the back side 8 of the chip 7.

[0041] By means of the above described assembly, the chip 4 and the chip 7 are electrically connected to the array 12 of electrical connections of the support substrate 2 through the first electrical connection element 9 and the second electrical connection element 10 respectively, and can be connected to each other through the array 12 of electrical connections.

[0042] Figure 3 The electronic device 22 shown in FIG. Figure 1 and Figure 2 The described electronic device 1 differs in that, for example, the electronic device 22 comprises a plurality of first electronic chips 4 which are located between the support substrate 2 and the second chip 7 and at a distance from each other.

[0043] The first chip 4 is electrically connected to the support substrate 2 via the first electrical connection element 9 and the second electrical connection element 10 in a mounting manner equivalent to the first chip 4 of the electronic device 1 described above.

[0044] For example, in this case, some of the second electrical connection elements 10 connecting the support substrate 2 and the second chips 7 may advantageously be located in the space between the first chips 4 .

[0045] Figure 4 The electronic device 23 shown in the figure includes a reference Figure 1 and Figure 2The electronic device 1 described, and the electronic device 23 further includes a third electronic chip 24, which is located on top of the second chip 7 and has a back side 25, a portion of which extends toward the front side 26 of the second chip 7, and another portion of which extends beyond at least a portion of the periphery of the first chip 4 and the second chip 7, and faces the front side 3 of the supporting substrate 2, thereby forming another specific stack.

[0046] Furthermore, the electronic device 22 comprises an additional electrical connection element 27 which is inserted between the support substrate 2 and the third chip 7 (that is, is located between the support substrate 2 and the third chip 7) and which is located at a distance from the first chip 4 and the second chip 7. The electrical connection element 27 connects the electrical connection array of the support substrate 2 and the electrical connection array of the third chip 24.

[0047] Figure 5 The electronic device 29 shown in the figure is similar to the reference Figure 1 and Figure 2 The described electronic device 1 differs in that the rear side 8 of the second electronic chip 7 comprises a recess 30 in which the first chip 4 is at least partially held.

[0048] Advantageously, the recess 30 is formed in the layer 20 of the second chip 7 .

[0049] The front side 6 of the chip 4 may be in contact with the bottom 31 of the recess 30 or may be at a small distance therefrom. A layer made of a thermally conductive material may optionally be inserted between the front side 6 of the chip 4 and the bottom 31 of the recess 30.

[0050] Therefore, the thickness of the stack formed by the chip 4 and the chip 7 can be reduced.

[0051] Of course, a plurality of first chips may be mounted in the recess of the second chip, and a plurality of recesses of the second chip may be provided in order to accommodate at least one first chip.

[0052] Figure 6 to Figure 7 Electronic Devices 101 with Reference Figure 1 and Figure 2 The difference between the electronic device 1 and the electronic device 2 is that the electronic device 101 further comprises a third electrical connection element 11 which is inserted between the first chip 4 and the second chip 7 (that is, located between the first chip 4 and the second chip 7).

[0053] The third electrical connection element 11 may be formed by a ball, a column, or a solder joint.

[0054] As in Figure 7 As shown in the figure, chip 4 is relative to its Figure 2The layout in FIG. 1 is flipped so that the base plate 13 is located on one side of the support substrate 2 and the interconnect layer 15 including the electrical connection array 16 is located on one side of the second chip 7 .

[0055] Moreover, the base board 13 of the first chip 4 is provided with an electrical connection via 17 (TSV) in the form of a through hole, which, on the one hand, is connected to the electronic components of the first chip 4 and / or to the array 16 of electrical connections, and on the other hand, the electrical connection via 17 has a back pad to which the first electrical connection element 9 is electrically connected.

[0056] Furthermore, on the one hand the array 16 of electrical connections of the first chip 4 has a positive pad to which the third electrical connection element 11 is electrically connected and on the other hand the array 21 of electrical connections has a back pad to which the second electrical connection element 11 is electrically connected.

[0057] Therefore, in addition to the above-described electrical link by way of the first electrical connection element 9 and the second electrical connection element 10 , the chip 4 and the chip 7 are also directly connected to each other by way of the third electrical connection element 11 .

[0058] Figure 8 The electronic device 122 shown in FIG. Figure 3 The difference between the electronic device 22 described above is that the electronic device 122 further includes a third electrical connection element 11, and the third electrical connection element 11 is connected to the electronic device 122 described above. Figure 7 The equivalents described above are inserted between the first chip 4 and the second chip 7 and are electrically connected to the first chip 4 and to the second chip 7 .

[0059] Fig. 9 The electronic device 123 shown in the figure is the same as that described above with reference to Figure 4 The described electronic device 23 differs in that the electronic device 123 further comprises a third electrical connection element 11 inserted between the first chip 4 and the second chip 7 , and an additional electrical connection element 28 inserted between the second chip 7 and the third chip 24 .

[0060] The third electrical connection element 11 is connected to the Figure 7 The first chip 4 and the second chip 7 are electrically connected in the same manner as described above.

[0061] Furthermore, the second chip 7 is provided in the same way as the chip 4 with an array of electrical connections and an array of electrical connection vias, thereby forming a direct electrical connection between the second chip 7 and the third chip 24 .

[0062] Fig.10 The electronic device 129 shown in the figure is the same as that described above with reference to Figure 5The difference between the electronic device 29 described is that the electronic device 129 further comprises a third electrical connection element 11 inserted between the first chip 4 and the bottom 31 of the recess 30 .

[0063] The array 21 of electrical connections contained in the layer 20 of the second chip 7 has pads arranged at the bottom 31 of the recess 30 and to which the electrical connection elements 11 are electrically connected, forming a direct link between the first chip 4 and the second chip 7 .

Claims

1. An electronic device, comprising: a supporting substrate having a supporting surface; a first electronic chip located on top of the support substrate and having a first side and a second side, wherein the first side is mounted to the support side of the support substrate; a second electronic chip located on top of the first electronic chip, the second electronic chip comprising a semiconductor substrate and an interconnect layer, the semiconductor substrate having a first side and a second side, and the interconnect layer having a first side and a second side, wherein the second side of the interconnect layer is mounted to the first side of the semiconductor substrate, and wherein the first side of the interconnect layer is mounted to the support side of the support substrate; The first side of the interconnect layer further comprises a recess, and wherein the first electronic chip is at least partially disposed within the recess, the second side of the first electronic chip facing a bottom surface of the recess; a first electrical connection element, inserted between the first face of the first electronic chip and the support face of the support substrate; as well as A second electrical connection element is interposed between the first face of the interconnect layer for the second electronic chip and the supporting face of the supporting substrate. 2 . The device according to claim 1 , further comprising a third electrical connection element interposed between the second face of the first electronic chip and the bottom face of the recess. 3 . The device of claim 1 , wherein the support substrate comprises an array of electrical connections at the support surface, the array of electrical connections being connected to the first electrical connection element and the second electrical connection element.

4. The apparatus of claim 1, wherein the first and second electrical connection elements each comprise a structure selected from the group consisting of a ball, a post, and a pad.

5. The apparatus of claim 1, wherein the interconnect layer comprises an array of electrical connections.

6. The apparatus of claim 5, wherein the array of electrical connections is electrically connected to the support substrate through the second electrical connection elements.

7. The device of claim 5, wherein the array of electrical connections is electrically connected to the second side of the first electronic chip.

8. The device of claim 7, wherein the first electronic chip comprises a plurality of electrical connection through-vias in electrical contact with the array of electrical connections.

9. An electronic device, comprising: a supporting substrate having a front surface; a first electronic chip positioned over the front side of the support substrate, the first electronic chip comprising a first substrate having a first electronic circuit, and a first interconnect layer having a first interconnect network connected to the first electronic circuit; wherein the first interconnect layer faces the front side of the support substrate; a first electrical connection element, interposed between said first interconnection network of said first interconnection layer and said front side of said supporting substrate; a second electronic chip positioned over the front side of the support substrate, the second electronic chip comprising a second substrate having a second electronic circuit, and a second interconnect layer having a second interconnect network connected to the second electronic circuit; wherein the first portion of the second interconnect layer comprises a recess, a portion of the first electronic chip is positioned within the recess, and wherein the second portion of the second interconnect layer extends beyond a peripheral edge of the first electronic chip and faces the front side of the support substrate; as well as A second electrical connection element is interposed between the second interconnection network of the second interconnection layer and the front side of the supporting substrate, the second electrical connection element being located at a distance from the peripheral edge of the first electronic chip.

10. The device of claim 9, further comprising a third electrical connection element interposed between the first substrate of the first electronic chip and the second portion of the second interconnect layer. 11 . The device according to claim 10 , wherein the first substrate of the first electronic chip comprises a through-silicon via, the through-silicon via being electrically connected to the third electrical connection element.

12. An electronic device comprising: a supporting substrate having a front surface; a first electronic chip positioned above the front side of the support substrate, the first electronic chip comprising a first substrate having a first electronic circuit, and a first interconnect layer having a first interconnect network connected to the first electronic circuit; wherein the first substrate faces the front side of the supporting substrate; a first electrical connection element, interposed between said first substrate and said front side of said support substrate; a second electronic chip positioned above the front side of the support substrate, the second electronic chip comprising a second substrate having a second electronic circuit, and a second interconnect layer having a second interconnect network connected to the second electronic circuit; wherein the first portion of the second interconnect layer comprises a recess, a portion of the first electronic chip is positioned within the recess, and wherein the second portion of the second interconnect layer extends beyond a peripheral edge of the first electronic chip and faces the front side of the support substrate; as well as A second electrical connection element is interposed between the second interconnection network of the second interconnection layer and the front side of the supporting substrate, the second electrical connection element being located at a distance from the peripheral edge of the first electronic chip.

13. The device of claim 12, further comprising a third electrical connection element interposed between the first interconnect layer and the second portion of the second interconnect layer of the first electronic chip. 14 . The device of claim 13 , wherein the first substrate of the first electronic chip comprises a through-silicon via, the through-silicon via being electrically connected to the first electrical connection element.

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