Silicon carbide device, semiconductor device and method for forming the same

Abstract

A silicon carbide device, a semiconductor device and a method for forming the same are provided. The silicon carbide device comprises a silicon carbide substrate, the silicon carbide substrate comprises a body region and a source region of a transistor unit. In addition, the silicon carbide device comprises a titanium carbide gate electrode of the transistor unit.

Description

Technical Field

[0001] Examples of the present disclosure relate to silicon carbide devices and semiconductor devices. Additional examples relate to methods for forming silicon carbide devices and methods for forming semiconductor devices. Background Art

[0002] The size of trench power MOSFETs (metal oxide semiconductor field effect transistors) can be reduced to improve electrical performance and reduce costs between generations, both of which can be achieved by better lithography systems and more powerful tools with improved process control. The reduction in geometric size may not be accompanied by side effects. By reducing the geometry, the width (and therefore the extent of the electrode in the lateral direction) can be continuously reduced. For example, polycrystalline silicon (also called polysilicon) is used as an electrode material, which shows a drastically increased sheet resistance below a certain layer thickness due to the crystal structure of the material. In strip cells, this can be particularly applied to field plate electrodes, and the gate resistance may also not be at a value of <1 ohm, which may be desirable for some applications. Some concepts can use individual cells instead of strips, in which the field plate electrode can have a columnar shape (so-called needle-like) and is surrounded by a circumferential gate. Although the field plate resistance may not be so critical due to its direct connection to the source metal, the gate resistance may cause difficulties due to the arrangement of the gate trench between the columns of the field plate electrode. For devices with voltage levels as high as approximately 120V, very narrow gate widths can be achieved. In this example, the effective width of the gate electrode may be less than 100 nm, which may result in high distributed gate resistance values.

[0003] To improve electrical performance and reduce costs, similar to their silicon counterparts, silicon carbide (SiC) trench power MOSFETs can be further reduced in their geometric size. This can be achieved through improved lithography systems and more powerful tools with improved process control, and / or alternative cell structures can be used, which can minimize the structure size due to its cell design.

[0004] By reducing the cell geometry, the width of the gate electrode (and therefore the extent of the electrode in the lateral direction) can also be continuously reduced. As mentioned, polysilicon can have a drastically increased sheet resistance below a certain layer thickness due to the crystal structure of the material. The resulting gate resistance can cause increasing difficulties. Some cell concepts can have an average gate width of approximately 1 μm and may require the introduction of gate fingers at least in the case of large chip areas. In addition to the increase in gate resistance due to the smaller cross section, an additional increase due to the material properties can also be considered.

[0005] Therefore, it may be desirable to reduce the resistance of the gate electrode and / or the field electrode. Summary of the invention

[0006] The example relates to a silicon carbide device, comprising: a silicon carbide substrate, which comprises a body region and a source region of a transistor unit. In addition, the silicon carbide device comprises a titanium carbide gate electrode of the transistor unit.

[0007] Some examples relate to a semiconductor device, comprising: a semiconductor substrate including a body region and a source region of a transistor cell. In addition, the semiconductor device includes a titanium carbide field electrode of the transistor cell. The titanium carbide field electrode is connected or connectable to a reference voltage metallization structure so that a reference voltage independent of a gate voltage of the transistor cell can be provided to the titanium carbide field electrode.

[0008] An example relates to a method for forming a silicon carbide device. The method includes forming a body region of a transistor cell in a silicon carbide substrate, and forming a source region of the transistor cell in the silicon carbide substrate. In addition, the method includes forming a titanium carbide gate electrode of the transistor cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Some examples of apparatus and / or methods will be described below by way of example only and with reference to the accompanying drawings, in which:

[0010] Figure 1 shows a schematic cross-section of a portion of a silicon carbide device;

[0011] Figure 2 shows a schematic cross-section of a portion of a silicon carbide device having a channel at one side of each gate trench;

[0012] Figure 3 shows a schematic cross section of a portion of a silicon carbide device comprising a buried p-doped region connected to a source metallization;

[0013] Figure 4 shows a schematic cross-section of a portion of a silicon carbide device including an additional titanium carbide electrode within a gate trench;

[0014] Figure 5 shows a schematic cross-section of a portion of a semiconductor device;

[0015] Figure 6 shows a schematic cross-section of a portion of a semiconductor device including a field electrode within a gate trench;

[0016] Figure 7 shows a schematic cross-section of a portion of a semiconductor device comprising a field electrode within a field electrode trench;

[0017] Figure 8 A flow chart showing a method for forming a silicon carbide device; and

[0018] Fig. 9 A flow chart of a method for forming a semiconductor device is shown. DETAILED DESCRIPTION

[0019] Various examples will now be described more fully with reference to the accompanying drawings, in which some examples are illustrated.In the drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0020] Therefore, although other examples can have various modifications and alternative forms, some specific examples thereof are shown in each figure and will be described in detail later. However, this detailed description does not limit other examples to the described specific forms. Other examples can cover all modifications, equivalents and substitutes falling within the scope of the present disclosure. Throughout the description of each figure, the same or same numerals refer to the same or similar elements, which can be implemented in an equivalent or modified form when compared to each other, while providing the same or similar functionality.

[0021] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled, or via one or more intervening elements. If "or" is used to combine two elements A and B, this is to be understood as disclosing all possible combinations, i.e. only A, only B, and A and B, if not otherwise explicitly or implicitly defined. Alternative wording for the same combination is "at least one of A and B" or "A and / or B". This also applies, mutatis mutandis, to combinations of more than two elements.

[0022] The terms used herein for the purpose of describing a particular example do not limit the intention of other examples. Whenever a singular form such as "one", "an" and "the" is used and only a single element is neither explicitly nor implicitly defined as mandatory, other examples may also use plural elements to implement the same functionality. Similarly, when functionality is subsequently described as being implemented using multiple elements, other examples may use a single element or processing entity to implement the same functionality. It will also be understood that the terms "comprise", "comprises", "includes" and / or "includes" when used, specify the existence of the claimed features, integers, steps, operations, processes, actions, elements and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, processes, actions, elements, components and / or any groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) are used herein according to their ordinary meaning in the art to which the examples belong.

[0024] Some concepts may implement finger structures that provide a low-ohmic connection from the respective trench electrodes to the respective potentials. In this way, very low resistances may be achieved, which may be outweighed by the correspondingly increased active area losses. This negative effect may be higher the lower the on-resistance per unit area (Ron x A) of the technology, and this may be undesirable for wide bandgap technologies like SiC-MOSFETs.

[0025] Another concept could be to silicide the electrode surface. In this way, a reduction in gate resistance could be achieved. However, for SiC-MOSFET gate widths in the range of about 100 nm, silicideing the electrode surface may be difficult.

[0026] The polysilicon gate may also be replaced by a metal gate, which may result in a drastic reduction in the distributed resistance.In the logic domain metal is used as the gate electrode, but the requirements in the logic and power domains may be significantly different.

[0027] According to one concept, tungsten can be used to realize the gate electrode in the power region, which may require the use of a titanium nitride (TiN) barrier in addition to the gate insulating layer (e.g., gate oxide). Because the deposition of the TiN barrier may be performed using aggressive chemicals (e.g., chlorine), the oxide used may need to be of very good quality. Otherwise, damage to the oxide may occur, which may shorten the life and have a negative impact on the breakthrough field strength, which in the case of SiC-MOSFETs may require stronger shielding of the gate insulating layer and thus reduce the overall performance. For example, if an oxide is used as a gate insulating layer, it may be necessary to use an oxide grown at high temperature and in a dry atmosphere or alternatively to use a deposited oxide that is densified and / or post-oxidized at very high temperatures. For example, densification may be performed at 1150°C and post-oxidation at 1100°C to improve the quality of the gate insulating layer.

[0028] This can cause problems when used in SiC-MOSFETs. Densification of the deposited tetraethyl orthosilicate oxide can take place at high temperatures in the range between 1100°C-1250°C in a nitrogen monoxide (NO) atmosphere for saturation of the interface states. In addition to the saturation of the interface states (by "NO"), annealing can also cause densification of the deposited tetraethyl orthosilicate. Densification can improve the intrinsic properties of the oxide and fewer defects in the oxide can be achieved. Densification can also be used for silicon devices. Exact process parameters can be selected for good interface properties and for subsequent process steps in an aggressive atmosphere (like in TiN deposition), the process parameters may not be sufficient as a barrier for the tungsten gate. Subsequent densification at the indicated high temperatures may already lead to interface depassivation and thus to a deterioration of the component characteristics. Densification in oxygen at temperatures above 800°C may lead to interface depassivation. 100% inertia annealing (eg in N2) after interface passivation may result in a shift in threshold voltage, but may not significantly affect interface properties, at least for short annealing times and temperatures ≤ 1000°C.

[0029] The high temperature budget may cause difficulties for highly phosphorus doped substrates (e.g. for low voltage MOSFETs operating at voltages <= 40 V), and this may result in a pronounced diffusion tail for silicon devices. This may again lead to a deteriorated Ron x A and ultimately to a deteriorated figure of merit FOM all in all.

[0030] It may be desirable to provide low resistance concepts for gate electrodes for SiC devices and / or for field electrodes for semiconductor devices.

[0031] Figure 1 A schematic cross section of a portion of a silicon carbide device according to an embodiment is shown. The silicon carbide device 100 may include a silicon carbide (SiC) substrate including a body region 110 and a source region 120 of a transistor cell. Furthermore, the silicon carbide device 100 may include a titanium carbide (TiC) gate electrode 130 of the transistor cell.

[0032] By using titanium carbide as a material for the gate electrode, the resistance of the gate electrode can be significantly reduced compared to a polysilicon gate electrode. In this way, it may not be necessary to implement gate fingers to contact the gate more often, which can reduce the required die area. In addition, for example, for devices with high switching frequencies, the uniformity of switching of transistor cells can be improved and / or switching losses can be reduced. Furthermore, the use of titanium carbide can facilitate processing of wafers due to its high melting temperature.

[0033] The source region 120 may be a doped region having a first conductivity type, and the body region 110 may be a doped region having a second conductivity type. The body region 110 may be positioned adjacent to the source region 120 so that a pn junction occurs between the body region 110 and the source region 120. The doped region of the first conductivity type may be a p-doped region (e.g., caused by doping with aluminum ions or boron ions) or an n-doped region (e.g., caused by doping with nitrogen ions or phosphorus ions). Therefore, the second conductivity type indicates relative n-doping or p-doping. In other words, the first conductivity type may indicate n-doping, and the second conductivity type may indicate p-doping, or vice versa.

[0034] For example, the TiC gate electrode 130 or at least the TiC layer of the TiC gate electrode 130 includes TiC as a main material. The TiC gate electrode 130 or at least the TiC layer of the TiC gate electrode 130 may include at least 90% (or at least 95% or at least 99%) TiC. For example, the TiC gate electrode 130 or at least the TiC layer of the TiC gate electrode 130 may include only TiC except for impurities and / or contaminants that have no effect or only a negligible effect on the electrical functionality. For example, the TiC gate electrode 130 may include at least a TiC layer having a thickness of at least 50 nm (or at least 100 nm or at least 200 nm). The TiC gate electrode 130 or at least the TiC layer of the TiC gate electrode 130 may be positioned adjacent to and / or directly adjacent to a gate insulating layer of a transistor cell. The gate insulating layer of the transistor cell may be an oxide layer (e.g. a SiO2 layer) positioned between the body region 120 and the TiC gate electrode 130. In some embodiments, the gate insulating layer may include a so-called high Dielectric.

[0035] The TiC gate electrode 130 may be connected to a gate contact structure, a gate metallization structure, a gate wiring structure and / or a gate pad. During operation of the silicon carbide device 100 , a gate voltage may be applied to the TiC gate electrode 130 to control current flowing through the channel region of the body region 120 .

[0036] The TiC gate electrode 130 may be a planar gate electrode. The planar electrode may, for example, be located on the front side surface of the silicon carbide substrate. Alternatively, the TiC gate electrode 130 may be positioned in a gate trench. The TiC gate electrode 130 may then be part of a so-called trench gate.

[0037] For example, the transistor cell includes a trench gate including a gate trench and a TiC gate electrode 130 positioned in the gate trench. The gate trench may extend from a surface (e.g., a front side surface) of the silicon carbide substrate into the silicon carbide substrate. The width of the gate trench measured at the surface of the silicon carbide substrate may be at most 1.5 μm (or at most 1.2 μm or at most 0.8 μm or at most 0.5 μm). The width of the gate trench may be constant or may vary along the gate trench. If the width varies along the gate trench, the gate trench width at the narrowest portion of the gate trench may be at most 1.5 μm (or at most 1.2 μm or at most 0.8 μm or at most 0.5 μm). The gate trench may extend deeper into the silicon carbide substrate than the body region 120. The gate trench may be completely filled with TiC material except for the gate insulating layer of the trench gate. The gate insulating layer may line the gate trench. Alternatively, one or more voids may exist at or near the center of the gate trench.Alternatively, the TiC layer of the TiC gate electrode 130 may be positioned adjacent to the gate insulating layer, and the core region of the gate trench may be filled with another material (eg, polysilicon).

[0038] For example, the silicon carbide device 100 may include a plurality of gate trenches or a grid of gate trenches. The gate trenches in the plurality of gate trenches may be strip-shaped gate trenches. The titanium carbide gate electrode may be positioned in each of the plurality of gate trenches. In addition to the plurality of gate trenches, the silicon carbide device 100 may further include another trench (e.g., an edge trench).

[0039] The titanium carbide gate electrode may be connected to a gate contact structure (e.g., a gate runner or gate ring) at the cell field edge of the silicon carbide device 100 and / or the active area edge of the silicon carbide substrate. For example, the titanium carbide gate electrode may be connected to the gate metallization structure only at the end region of the titanium carbide gate electrode. The end region of the titanium carbide gate electrode may extend from the respective lateral end of the titanium carbide gate electrode over at most 10% of the length of the respective titanium carbide gate electrode. Due to the low resistance of the TiC gate electrode, it may be sufficient to contact the TiC gate electrode only at the end. The implementation of gate fingers may be avoided.

[0040] Additionally, the silicon carbide device 100 may include a gate trench (eg, Figure 4 ) or contact grooves (e.g., as shown in Figure 31 ). The TiC contact electrode may be electrically connected to the source region 120 of the transistor cell. If the TiC contact electrode is positioned in the gate trench, the TiC contact electrode may be positioned deeper in the gate trench than the TiC gate electrode 130 at least in some places. For example, the TiC contact electrode may be positioned below the TiC gate electrode 130 at least in some places. During operation of the silicon carbide device 100, a reference voltage (e.g., a source voltage) may be applied to the TiC contact electrode. The TiC contact electrode may affect the electric field near the bottom of the gate trench and / or may contact a buried doped region at the bottom of the gate trench (e.g., for example, Figure 4 The contact trench may be different from the gate trench and / or may be separated from the gate trench. The contact trench may be free of a gate electrode and / or have a material that is directly electrically connected to the gate electrode. For example, the contact trench may be a source contact trench (e.g., Figure 3 ).

[0041] For example, a transistor (eg a transistor cell) may be arranged only at one side of a trench gate (eg, Figure 2 ). In this case, the first sidewall of the gate trench may abut the transistor cell. The second opposing sidewall may be free of transistor cells. Alternatively, the transistor cells of the silicon carbide device 100 may be positioned on both sides of the gate trench, so that the body region may be positioned at opposite sides of the gate trench (e.g., as shown in FIG. Figure 1 , 3 or 4). For example, at least a portion of each body region may be in contact with a corresponding sidewall of the gate trench (eg, a gate insulating layer of the gate trench).

[0042] For example, the transistor cell is a vertical transistor cell configured to conduct current between the front side of the silicon carbide substrate and the back side of the silicon carbide substrate. The source region 120, the body region 110 and the drift region of the transistor cell can be arranged vertically in the silicon carbide substrate. The source region 120 can be positioned at the front side surface of the silicon carbide substrate.

[0043] For example, vertical directions and vertical dimensions or thicknesses of layers may be measured orthogonal to the frontside and / or backside surfaces of the silicon carbide substrate, and lateral directions and lateral dimensions may be measured parallel to the frontside and / or backside surfaces of the silicon carbide substrate.

[0044] The front side of the SiC substrate may be the side used to realize more sophisticated and complex structures (e.g., gates of transistors, wiring structures, and / or contact pads) than at the back side of the SiC substrate because, for example, if the structures have been formed at the front side of the SiC substrate, the process parameters (e.g., temperature) and handling for the back side may be limited.

[0045] The silicon carbide device 100 may also include a drain region of a transistor unit having a first conductivity type (e.g., for a MOSFET) or a collector region of a transistor unit having a second conductivity type (e.g., for an insulated gate bipolar transistor IGBT). The drain region or the collector region may have an average net doping concentration. The average net doping concentration of the drain region or the collector region may be, for example, at least 30 times or even at least 100 times the average net doping concentration of the drift region. The drain region or the collector region may be positioned at the back side of the silicon carbide substrate.

[0046] The transistor cell of the silicon carbide device 100 may be a transistor cell of a plurality of transistor cells of a transistor arrangement. Each transistor cell may, for example, include one or more source regions (e.g., distributed or positioned along a gate), at least one body region, and a gate electrode (e.g., a trench gate electrode positioned in a gate trench extending into a SiC substrate). In addition, the transistor cells of the plurality of transistor cells may share a common (common) drift region and / or a common drain region (e.g., if the transistor cell is a MOSFET cell) or a common collector region (e.g., if the transistor cell is an IGBT cell). For example, the transistor arrangement of the silicon carbide device 100 includes a plurality of source doped regions connected to a source wiring structure, a plurality of TiC gate electrodes or a TiC gate electrode grid connected to a gate wiring structure, and a back side drain or collector metallization.

[0047] The silicon carbide device 100 may be a power semiconductor device. The power semiconductor device or an electrical structure of the power semiconductor device (eg a transistor cell of the silicon carbide device 100 ) may have a breakdown voltage or a blocking voltage of more than 300V or more than 1000V or more than 2 kV.

[0048] The proposed concept may use TiC as a gate material for SiC power transistors. TiC may be a very temperature stable material with low sheet resistance. Instead of implementing polysilicon and / or consuming active regions of gate finger structures, it may be proposed to use titanium carbide as a temperature stable and highly conductive electrode material for the gate in SiC MOSFETs for achieving low distributed resistance. Additionally, TiC may be used as a material for contact electrodes or source electrodes (e.g. for contacting buried regions, such as e.g. Figure 4 ).

[0049] For example, titanium carbide is previously patterned (e.g., combined with Figure 8 The gate insulating layer is formed by heat treatment at a temperature of up to 1000° C. after carbon and titanium deposition (explained in more detail below). For example, depassivation of oxide interface states (of the gate insulating layer) can be avoided as much as possible due to the reduction in the required temperature budget as a result.

[0050] The proposed concept may enable lower manufacturing costs with improved performance (eg, preventing inactive areas without controlled current for finger structures with lower distributed resistance) and / or pitch reduction through smaller gate trench geometry.

[0051] Some embodiments relate to a semiconductor device having a transistor including a Figure 1 The TiC gate electrode described in the examples. In these examples, the semiconductor substrate used may be another wide bandgap semiconductor substrate or a silicon substrate instead of silicon carbide. For example, the wide bandgap semiconductor substrate may have a bandgap greater than 2 eV or greater than 3 eV. For example, the wide bandgap semiconductor substrate may be a silicon carbide substrate, a diamond (C) substrate, a gallium oxide (Ga2O3), a gallium arsenide (GaAs), or a gallium nitride (GaN) substrate.

[0052] The semiconductor substrate may be a semiconductor bulk substrate (e.g., obtained from a semiconductor blank) or an epitaxially grown semiconductor substrate, or may include an epitaxial semiconductor layer (e.g., used to implement a source region, a body region and / or a drift region of a vertical transistor cell) grown on a semiconductor bulk substrate (e.g., used to implement a drain region or a collector region of a transistor cell).

[0053] Figure 2 FIG. 2 shows a schematic cross-section of a portion of a silicon carbide device according to an embodiment, the silicon carbide device having a channel at one side of each gate trench. The silicon carbide device 200 may be similar to a device incorporating Figure 1 The silicon carbide device 200 includes a transistor cell including a body region 110 vertically positioned between a highly n-doped source region 120 and a lightly n-doped drift region 230. In addition, an n-doped current extension region 220 may be optionally positioned between the body region 110 and the drift region 230.

[0054] The silicon carbide device 200 includes a TiC gate electrode 130 in a gate trench. For example, a gate insulating layer of the trench gate is positioned between the body region and the TiC gate electrode 130. In the operation mode of the transistor, the current flowing through the transistor channel region can be controlled by a gate voltage applied to the TiC gate electrode 130.

[0055] The high p-doped region 240 of the silicon carbide device 200 can be positioned adjacent to the gate insulating layer at the second sidewall of the gate structure, which second sidewall is opposite to the first sidewall of the gate trench positioned adjacent to the body region of the transistor. The high p-doped region 240 extends from the bottom of the gate trench along the second sidewall of the trench gate to the high n-doped region 260 and / or to the front side surface. In addition, the high p-doped shielding region 250 can be positioned at the bottom of the trench gate. The high p-doped shielding region 250 can be in contact with the high p-doped region 240 or be part of the high p-doped region 240.

[0056] The high n-doped region 260 may extend from the high p-doped region 240 to the front surface of the silicon carbide substrate along the second sidewall of the trench gate. The high n-doped region 260 may be formed simultaneously with the source region 120. For example, the high n-doped region 260 may be electrically connected to the source region 120.

[0057] Furthermore, a source metallization 210 is positioned on the silicon carbide substrate. The source metallization 210 is electrically connected to the source region 120. Furthermore, the source metallization 210 may be connected to the body region 110, for example via a highly p-doped region 240.

[0058] Figure 2 The concept of an asymmetric MOSFET cell is shown.Although the average gate width (eg gate electrode width averaged along the gate trench) may be less than 1.5 μm (or less than 1.2 μm or less than 0.8 μm), due to the implementation of TiC gate electrodes, the introduction of gate fingers may not be necessary for large chip areas.

[0059] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 2 The silicon carbide device shown in may include one or more optional additional features, which correspond to one or more embodiments described above or below (for example, Figure 1 and / or one or more aspects of the concepts proposed in 3-9).

[0060] Figure 3 1 shows a schematic cross section of a portion of a silicon carbide device 300 according to an embodiment, the silicon carbide device 300 including a buried p-doped region 350 connected to a source metallization. Some aspects of the silicon carbide device 300 may be combined with Figure 1 and / or Figure 2 The silicon carbide device described is similarly or equivalently implemented. However, the source contact trench is positioned between the two gate trenches. The source contact trench may extend deeper into the silicon carbide substrate than the body region 110, or they may extend to an equal depth. The buried p-doped region 350 is positioned at the bottom of the source contact trench. For example, the buried p-doped region 350 may be contacted by the source contact trench. In addition, the high p-doped body contact region 340 is adjacent to the source contact trench and is positioned vertically between the source region 120 and the buried p-doped region 350. The source contact electrode 370 is positioned in the source contact trench to obtain an ohmic contact to the source region 120 and the body region 110. The source contact electrode 370 may be a TiC source contact electrode connected to a source metallization 210 (e.g., a power metallization).

[0061] The drift region 310 is realized by a lightly n-doped epitaxial layer. Additionally, an n-doped buffer layer 320 is realized between the drain region 330 (eg a highly n-doped substrate layer) and the drift region 310. Furthermore, an interlayer dielectric may be positioned vertically between the source metallization 210 and the silicon carbide substrate.

[0062] For example, Figure 3 The cell concept shown in can use a structure width (e.g. the width of the gate electrode) that is as small as possible, for example in the range of ≤350 nm (or less than 500 nm or less than 250 nm) for achieving good performance. Due to the use of TiC for the gate electrode, an increase in the gate resistance due to a smaller cross section and / or an additional increase due to material properties can be avoided.

[0063] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 3 The silicon carbide device shown in may include one or more optional additional features, which correspond to one or more embodiments described above or below (for example, Figure 1-2 and / or one or more aspects of the concepts proposed in 4-9).

[0064] Figure 4 FIG. 4 shows a schematic cross-section of a portion of a silicon carbide device 400 according to an embodiment, the silicon carbide device 400 including a contact electrode in a gate trench. The silicon carbide device 400 may be similar to a device incorporating a gate electrode. Figure 1 , 2 and / or the silicon carbide device described in 3.

[0065] In addition to the TiC gate electrode 130, an additional TiC electrode 430 may be positioned at the bottom of the gate trench. The additional TiC electrode 430 may be used to contact a buried shield region 440 (e.g., a deep p-junction field effect transistor JFET region) positioned adjacent to and / or below the bottom of the gate trench. The additional TiC electrode 430 may be connected or connectable to a voltage (e.g., a source voltage) that is different from the gate electrode (e.g., a gate voltage).

[0066] Figure 4 A cell concept with a buried electrode (additional TiC electrode 430) for contacting the buried shielding region 440 can be shown. The use of polysilicon, in particular for connecting the buried region 440, may lead to the necessity of finger structures, which may lead to a significant loss of active area. This can be avoided by the implementation of the additional electrode 430.

[0067] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 4The silicon carbide device shown in may include one or more optional additional features, which correspond to one or more embodiments described above or below (for example, Figure 1-3 and / or one or more aspects of the concepts proposed in 5-9).

[0068] Figure 5 A schematic cross section of a portion of a semiconductor device according to an embodiment is shown. The semiconductor device 500 may include a semiconductor substrate including a body region 110 and a source region 120 of a transistor cell. In addition, the semiconductor device 500 may include a titanium carbide field electrode 530 of the transistor cell. The titanium carbide field electrode 530 may be connected or connectable to a reference voltage metallization structure so that a reference voltage (e.g., a source voltage) independent of a gate voltage of the transistor cell may be provided to the titanium carbide field electrode 530.

[0069] By using titanium carbide as material for the field electrodes, the resistance of the field electrodes may be significantly reduced compared to polysilicon field electrodes. In this way, the implementation of contact finger structures to contact the field electrodes at several contact points may not be necessary, which may reduce the required die area.

[0070] By implementing a field electrode, such as a field plate or a columnar field electrode, a lower on-resistance can be achieved while providing the same breakdown voltage. For example, a field plate trench structure can utilize lateral charge compensation, thereby changing the electric field profile to obtain a higher breakdown, which can achieve an increased doping concentration in the drift region. In this way, the on-resistance can be significantly reduced.

[0071] The titanium carbide field electrode 530 may be connected or connectable to a reference voltage metallization structure (e.g., a reference voltage wiring structure and / or a reference voltage pad), such as a source metallization structure, a source wiring structure, and / or a source pad (e.g., via a control transistor). During operation, a reference voltage (e.g., a source voltage and / or a ground voltage) may be provided to the titanium carbide field electrode 530 via the reference voltage metallization structure.

[0072] The titanium carbide field electrode 530 may be positioned in a trench (eg, a field electrode trench and / or a gate trench).The trench may extend from a surface of the semiconductor substrate into the semiconductor substrate.

[0073] For example, the TiC field electrode 530 or at least the TiC layer of the TiC field electrode 530 includes TiC as a main material. The TiC field electrode 530 or at least the TiC layer of the TiC field electrode 530 may include at least 90% (or at least 95% or at least 99%) TiC. For example, the TiC field electrode 530 or at least the TiC layer of the TiC field electrode 530 may include only TiC, except for impurities and / or contaminants that have no effect or only a negligible effect on electrical functionality. For example, the TiC field electrode 530 may include at least a TiC layer having a thickness of at least 50 nm (or at least 100 nm or at least 200 nm). The TiC field electrode 530 or at least the TiC layer of the TiC field electrode 530 may be positioned directly adjacent to a field electrode insulating layer of a transistor cell. The field electrode insulating layer of a transistor cell may be an oxide layer (e.g., a SiO2 layer) positioned between the semiconductor substrate and the TiC field electrode 530. The thickness of the field electrode insulating layer may be greater than the thickness of the gate insulating layer of the transistor cell.

[0074] In addition to the TiC field electrode 530, the semiconductor device 500 may further include a gate electrode (eg, a TiC gate electrode). The gate electrode may be positioned in the same trench as the field electrode 530 (eg, Figure 6 ), or positioned in separate gate trenches (e.g. Figure 7 If the gate electrode and the TiC field electrode 530 are positioned in the same trench, the TiC field electrode 530 may be positioned deeper in the trench than the gate electrode at least in some places.

[0075] Instead of the frequently used polysilicon and in order to eliminate active areas of the consumed finger structures, it may be proposed to use titanium carbide as a temperature-stable and highly conductive electrode material for the field plate and / or (if applicable) the gate of the field plate trench MOSFET for achieving low distributed resistance.

[0076] For example, titanium carbide can be formed by heat treatment after carbon and titanium deposition after previous patterning (e.g., in combination with Fig. 9 explained in more detail).

[0077] Lower manufacturing costs may be achieved with improved performance (eg, preventing dead areas for finger structures while having lower distributed resistance).

[0078] The semiconductor substrate may be a silicon substrate.

[0079] The semiconductor device 500 may be a power semiconductor device. The power semiconductor device or the electrical structure of the power semiconductor device (eg, the transistor cell of the semiconductor device 500 ) may have a breakdown voltage or a blocking voltage of more than 10 V, more than 100 V, or more than 300 V.

[0080] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 5 The semiconductor device shown in may include one or more optional additional features, which correspond to one or more embodiments described above or below (for example, Figure 1-4 and / or one or more aspects of the concepts proposed in 6-9).

[0081] Figure 6 FIG. 4 shows a schematic cross-section of a portion of a semiconductor device 600 according to an embodiment, the semiconductor device 600 including a field electrode in a gate trench. The semiconductor device 600 may be similar to a semiconductor device incorporating a gate electrode. Figure 5 The semiconductor device described is implemented.

[0082] The semiconductor device 600 includes a plurality of strip-shaped gate trenches of a transistor cell. A TiC field electrode 530 and a gate electrode 620 (e.g., a TiC gate electrode) may be positioned in each gate trench. A source metallization structure 310 may be connected to the body region 110 and the source region 120. For example, the body region 110 is vertically positioned between the source region 120 and the drift region 630 of the transistor cell.

[0083] The length of the stripe-shaped gate trench may be at least 10 times (or at least 100 times) the width of the stripe-shaped gate trench.

[0084] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 6 The semiconductor device shown in may include one or more optional additional features, which correspond to one or more embodiments described above or below (for example, Figure 1-5 and / or one or more aspects of the concepts proposed in 7-9).

[0085] Figure 7 1 shows a schematic cross-section of a portion of a semiconductor device 700 according to an embodiment, the semiconductor device 700 including a field electrode in a field electrode trench. The semiconductor device 700 may be similar to a semiconductor device incorporating a semiconductor device 700 of the embodiment of the present invention. Figure 5 The semiconductor device described is implemented.

[0086] The semiconductor device 700 may include a plurality of pillar-shaped field electrode trenches (also referred to as “pin trenches”) surrounded by gate trenches of transistor cells. For example, a TiC field electrode 530 and a gate electrode 630 (eg a TiC gate electrode) are positioned in separate trenches.

[0087] The maximum depth of the pillar field electrode trench may be at least 5 times (or at least 10 times) the maximum lateral dimension of the pillar field electrode trench. The maximum depth of the pillar field electrode trench may be at least 2 times (or at least 5 times) the maximum depth of the gate trench.

[0088] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 7 The semiconductor device shown in may include one or more optional additional features, which correspond to one or more embodiments described above or below (for example, Figure 1-6 and / or one or more aspects of the concepts proposed in 8-9).

[0089] Figure 8 A flow chart of a method for forming a silicon carbide device according to an embodiment is shown. The method 800 may include forming 810 a body region of a transistor cell in a silicon carbide substrate, and forming 820 a source region of a transistor cell in a silicon carbide substrate. In addition, the method 800 may include forming 830 a titanium carbide gate electrode of the transistor cell.

[0090] The body region and the source region of the transistor cell may be formed by implanting dopants and / or by growth (eg epitaxial growth) of doped silicon carbide material. The body region and / or the source region of the transistor cell may be formed before the titanium carbide gate electrode.

[0091] The titanium carbide gate electrode may be a trench gate electrode positioned in a gate trench or a lateral gate electrode positioned on a surface of the silicon carbide substrate.For example, method 800 may additionally include forming a gate trench extending from a surface of the silicon carbide substrate into the silicon carbide substrate.

[0092] In order to generate a highly conductive gate electrode, the use of titanium carbide may be proposed. Titanium carbide has very good electrical conductivity (e.g. metallic properties and greatly improved electrical conductivity compared to doped polysilicon), for example, and has a melting point of 3140° C., but it is stable under the influence of air (e.g. an oxygen-rich atmosphere) only up to 800° C.

[0093] Due to the high melting point, if the TiC material is packaged, the subsequent processing may not be subject to any restrictions. For example, if the interlayer dielectric ILD deposition directly follows the gate deposition and patterning, then this point can be ensured. For example, for SiC devices, all or most of the doped regions may have been generated before the gate insulating layer, because the required high activation temperature of usually> 1600 ° C may otherwise cause damage to the gate insulating layer and / or interface passivation. For example, after TiC deposition, basically high temperature processes may not be necessary (for example, phosphosilicate glass PSG annealing at 800 ° C in N2 and / or contact annealing by rapid thermal processing RTP at 1000 ° C can be the highest temperature). In addition, compared with the deposition of TiN, chlorine precursors may not be necessary for forming TiC. Therefore, it is possible to avoid damage caused by the use of chlorine.

[0094] Compared to the metal system of TiN and W, the overall process temperature for forming a complete trench gate can be lower. Titanium carbide can be deposited by physical vapor deposition PVD (e.g., titanium and methane) and / or chemical vapor deposition CVD (e.g., titanium tetrachloride and methane). Alternatively, TiC can be formed by direct synthesis of two elements in the following manner: depositing both a carbon layer (e.g., graphite) and a titanium layer, and subsequently generating titanium carbide under the influence of high temperature (e.g., from approximately 900°C to approximately 1000°C). The required temperature budget can be relatively low, and thus the negative impact on the previously passivated gate insulating layer can be minimized. In order to avoid possible damage to the oxide by titanium deposition, the carbon layer can be deposited before the titanium layer. After the formation of titanium carbide, possible titanium residues can be chemically removed. For example, chemical removal can be performed using an etchant that does not attack titanium carbide compared to titanium. An example of such an etchant is sulfuric acid.

[0095] As mentioned, the manufacture of titanium carbide can be accomplished in a variety of possible ways. For example, TiC can be deposited (e.g., by PVD or CVD) on a gate insulating layer positioned on a silicon carbide substrate. Alternatively, the formation 830 of the titanium carbide gate electrode can include forming a carbon layer, forming a titanium layer and / or a titanium oxide layer on the carbon layer, and annealing after forming the titanium layer to obtain the titanium carbide gate electrode. The annealing can be performed at a temperature of at most 1100°C (or at most 1050°C or at most 1000°C) and / or at least 800°C (or at least 900°C or at least 950°C). Additionally, the formation 830 of the titanium carbide gate electrode can include oxidizing (e.g., by anodizing) the titanium layer before annealing.

[0096] For example, titanium can be deposited onto an existing carbon layer (e.g., previously formed on a gate insulating layer). To generate a thicker titanium carbide layer while keeping the temperature process time low, titanium and carbon can be deposited alternately. In other words, the formation of a carbon layer and the formation of at least one of a titanium layer and a titanium oxide layer can be repeated alternately to form a layer stack of alternating carbon and at least one of a titanium layer and a titanium oxide layer.

[0097] Stoichiometry (e.g., Ti:C ~ 1:1) may be considered for forming TiC. For example, if the TiC material is derived from a titanium layer and a carbon layer, then achieving a stoichiometric ratio of Ti:C ~ 1:1 may require that the layer thickness of the titanium layer is approximately twice the layer thickness of the carbon layer (i.e., the ratio of layer thicknesses is T:C ~ 2:1). This may be attributed to the fact that the density of titanium is approximately twice the density of carbon. In a subsequent furnace process (e.g., at a temperature of 900° C.-1200° C. in an inert atmosphere), titanium carbide may be formed. Excess titanium may be removed chemically, for example, by using sulfuric acid.

[0098] As an alternative to pure elemental reactions, titanium carbide may also be formed by the reaction of titanium dioxide and carbon, since pure titanium may not be formed.

[0099]

[0100] Titanium dioxide can be deposited, for example, by means of atomic layer deposition ALD, CVD, PVD or spin coating.

[0101] For example, a trench device (e.g., a device having a TiC gate electrode in a gate trench) may be formed by at least the following process steps in the following order (e.g., any additional intermediate steps may be possible):

[0102] A SiC substrate is provided which comprises a doped epitaxial layer (the so-called buffer layer) and a more lightly doped epitaxial layer

[0103] Formation of doped regions (e.g. body and source regions)

[0104] Gate trench etching, gate trench sidewall post-processing and gate trench bottom rounding

[0105] Optionally, a sacrificial oxide is formed

[0106] Formation of gate insulating layer

[0107] Post-annealing of gate insulation layer

[0108] Formation of TiC gate electrode

[0109] Encapsulation of the TiC gate electrode (e.g. via an oxide layer formed from tetraethyl orthosilicate or via a polysilicon layer)

[0110] Formation of ILD, formation of contacts and metallization (eg, deposition and structuring of one or more metal layers to form source and gate metallization).

[0111] In summary, the reaction Ti + C -> TiC may occur at a temperature greater than 1200° C. or greater than 1000° C. A carbon layer having a thickness between 100 nm and 300 nm may be formed on a semiconductor substrate (e.g., a silicon substrate or a SiC substrate), and a titanium layer having a thickness between 200 nm and 500 nm may be formed on the carbon layer. The layers may be annealed in an inert atmosphere (e.g., N2 at a temperature of at least 600° C., at least 800° C., and / or at least 1000° C.) to form a TiC layer.

[0112] Alternatively, titanium oxide (TiO2) can be formed as an intermediate product. For example, TiO2 can be formed via oxidation (i.e., ) is formed. Thereafter, TiC can be formed in an inert atmosphere (eg, at a temperature of at least 600° C., at least 800° C., and / or at least 1000° C., in a nitrogen N2 atmosphere) by reacting The oxidation may take place, for example, at a temperature of at least 500° C. and / or at least 700° C. in an environment containing oxygen (so-called oxidizing environment). The environment may contain oxygen. In particular, the amount of oxygen in the environment may be at least the amount required to form stoichiometric TiO2 (for example, the amount of oxygen atoms may be at least twice the amount of titanium atoms to be oxidized). In addition to oxygen, the environment may also include an inert gas (for example nitrogen or argon). For example, the environment may be air.

[0113] Alternatively, oxidation may be accomplished by anodic oxidation, for example in water (H2O) or a dilute mineral acid (eg phosphoric acid and / or sulfuric acid) as electrolyte.

[0114] For small structure sizes (e.g., pitch minimization), strip structures can be used, and the use of highly conductive gate electrodes can lead to a significant reduction in chip area due to the omission of the gate finger structure that would otherwise be required. In addition, the switching behavior can be homogenized across the chip (e.g., due to lower voltage drops along the field plates and strips in the gate), which can prevent the occurrence of undesirable critical states (e.g., local dynamic avalanche and / or parasitic restarts), and thus higher switching frequencies can be achieved.

[0115] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 8 The method shown in may include one or more optional additional features, which correspond to one or more embodiments described above or below (for example, Figure 1-7 or 9) one or more aspects of the proposed concept.

[0116] Fig. 9 A flow chart of a method for forming a semiconductor device according to an embodiment is shown. The method 900 may include forming 910 a body region of a transistor cell in a semiconductor substrate, and forming 920 a source region of a transistor cell in a semiconductor substrate. In addition, the method 900 may include forming 930 a titanium carbide field electrode of the transistor cell. The titanium carbide field electrode may be connected or connectable to a reference voltage metallization structure such that a reference voltage independent of a gate voltage of the transistor cell may be provided to the titanium carbide field electrode.

[0117] In order to generate highly conductive field plates and / or gate electrodes, the use of titanium carbide can be proposed. Titanium carbide has very good electrical conductivity (e.g. metallic properties and greatly improved conductivity compared to doped polysilicon) and has a melting point of 3140°C, and it is stable under the influence of air (e.g. oxygen-rich atmosphere) up to 800°C.

[0118] Due to the high melting point, if the TiC material is encapsulated, the subsequent processing can be free from any restrictions. When used as a field plate electrode, this can be ensured by the insulating oxide used for the gate electrode (for example, deposited tetraethyl orthosilicate or high-density plasma oxide can be used). In contrast to the material system titanium nitride and tungsten, for example for the gate insulating layer block, subsequent high-temperature processes can be achieved (for example, SACOX and actual GOX either as grown oxides or also as deposited oxides, each subsequently densified at a temperature of about 1100°C to ensure good oxide quality).

[0119] Titanium carbide can be deposited by PVD (e.g. titanium methane) and / or CVD (e.g. titanium tetrachloride and methane). Alternatively, a direct synthesis of the two elements can be used by depositing both a carbon layer (e.g. graphite) and a titanium layer and subsequently generating the titanium carbide under the influence of a temperature (e.g. approximately 900° C.). In order to avoid possible damage to the oxide by titanium deposition, the carbon layer can be deposited first and the titanium subsequently. After the formation of the titanium carbide, possible titanium residues can be removed chemically (e.g. by sulfuric acid).

[0120] As mentioned, the manufacture of titanium carbide can be done in various possible ways. For example, titanium can be deposited onto an existing carbon layer. In order to generate a thicker titanium carbide layer and at the same time keep the temperature process time low, titanium and carbon can be deposited alternately.

[0121] For the deposition of the carbon and titanium layers, a stoichiometry (e.g., Ti:C ~ 1:1) may be considered. For example, a layer thickness ratio of Ti:C ~ 2:1 may be desired. In a subsequent oven process (e.g., inert, 900°C-1200°C), titanium carbide may be formed. Excess titanium may be removed using sulfuric acid.

[0122] Alternatively to reacting the pure elements, titanium carbide can also be formed by reacting titanium dioxide and carbon.

[0123]

[0124] A field plate trench MOSFET may be formed by at least the following processes in the following basic order (eg, any additional intermediate steps may be possible):

[0125] Providing a silicon Si substrate having (one or more) epitaxial layers

[0126] Etch the field plate trench and, if applicable, round the trench (e.g. using rounded oxide)

[0127] Forming Field Oxide

[0128] Forming TiC field plate electrode

[0129] Etch back of field plate electrode

[0130] Encapsulation of field plate electrodes using oxides, etc.

[0131] Optionally forming a sacrificial oxide

[0132] Forming a gate insulating layer

[0133] Formation of TiC gate electrode

[0134] Encapsulation of the gate electrode (e.g. by a thin oxide)

[0135] Formation of necessary doped regions (e.g. source regions)

[0136] ILD formation

[0137] Contact formation and metallization

[0138] If the TiC field plate electrode and the TiC gate electrode are positioned in separate trenches, the gate trench may be formed prior to the sacrificial oxide formation. For example, etch-back of the field plate electrode may be optional.

[0139] Furthermore, the gate trenches may be formed before the field plate trenches, or vice versa.

[0140] Due to the low structural size of power devices in the field of low voltage power MOSFETs (e.g. ≤ 40V), strip structures can be used, and highly conductive field plates can provide the possibility of a suitable reduction in chip area due to avoiding the finger structures that would otherwise be required. In addition, the switching behavior can be homogenized across the chip (e.g., due to the lower voltage drop along the strips in the field plate and gate), which can prevent the occurrence of undesirable critical states (e.g., local dynamic avalanche, etc.), and thus higher switching frequencies can be achieved. For example, in the field of CPU voltage regulators, these devices can be used in integrated systems and higher power density can be achieved.

[0141] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Fig. 9 The method shown in may include one or more optional additional features, which correspond to one or more embodiments described above or below (for example, Figure 1-8 ) of the proposed concept and one or more aspects mentioned.

[0142] In at least some embodiments of the silicon carbide device, method and / or semiconductor device, the following features are applied alone or in combination (if applicable):

[0143] (i) the TiC gate electrode 130 or at least the TiC layer of the TiC gate electrode 130 includes TiC as a main material;

[0144] (ii) the TiC gate electrode 130 or at least the TiC layer of the TiC gate electrode 130 may include at least 90% (or at least 95% or at least 99%) TiC;

[0145] (iii) the transistor cell is an IGFET cell, a MOSFET cell or an IGBT cell;

[0146] (iv) The TiC layer of the TiC gate electrode 130 may be positioned adjacent to the gate insulating layer, and a core region of the gate trench may be filled with another material.

[0147] with one or more of the previously detailed examples and Figure 1 The aspects and features mentioned and described above may also be combined with one or more other examples in order to replace the same features of other examples or in order to additionally introduce features into other examples.

[0148] The description and drawings merely illustrate the principles of the present disclosure. In addition, all examples recorded herein are primarily intended to be used for illustrative purposes only, to help readers understand the principles of the present disclosure and the concepts contributed by (one or more) inventors to advance the art. All statements recording the principles, aspects and examples of the present disclosure and specific examples thereof are intended to include their equivalents.

[0149] Block diagrams may, for example, illustrate high-level circuit diagrams that implement the principles of the present disclosure. Similarly, flow charts, flow diagrams, state transition diagrams, pseudocodes, etc. may represent various processes, operations, or steps, which, for example, may be generally represented in a computer-readable medium and thus performed by a computer or processor, whether or not such a computer or processor is explicitly shown. The methods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the corresponding actions of these methods.

[0150] It is to be understood that, unless otherwise stated explicitly or implicitly, for example, for technical reasons, the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims may not be interpreted as being in a specific order. Therefore, the disclosure of multiple actions or functions will not limit these to a specific order, unless such actions or functions are not interchangeable for technical reasons. In addition, in some examples, a single action, function, process, operation or step may include or may be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations or sub-steps, respectively. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of the single action.

[0151] Furthermore, the appended claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. Although each claim may stand on its own as a separate example, it is noted that although a dependent claim may refer to a specific combination with one or more other claims in a claim, other examples may also include a combination of the dependent claim with the subject matter of each other's dependent or independent claims. Unless it is stated that no specific combination is intended, such a combination is explicitly proposed herein. Furthermore, it is intended that features of a claim also be included in any other independent claim, even if that claim is not directly dependent on the independent claim.

Claims

1. A silicon carbide device, comprising: A silicon carbide substrate, including a body region and a source region of a transistor unit; and Titanium carbide gate electrode of transistor cell, a gate metallization contacting a gate electrode, wherein the gate electrode of the transistor cell is contacted by the gate metallization at no more than two locations, wherein for each transistor cell, the titanium carbide gate electrode is connected to the gate metallization structure only at the terminal region of the titanium carbide gate electrode, and The end regions of the titanium carbide gate electrodes extend from respective lateral ends of the titanium carbide gate electrodes over at most 10% of the length of the respective titanium carbide gate electrodes. 2 . The silicon carbide device of claim 1 , wherein the titanium carbide gate electrode is positioned in the gate trench, and wherein the gate trench extends from a surface of the silicon carbide substrate into the silicon carbide substrate. 3 . The silicon carbide device according to claim 2 , wherein a width of the gate trench measured at the surface of the silicon carbide substrate is at most 1.5 μm.

4. The silicon carbide device according to claim 1, wherein: The transistor cell is a vertical transistor cell configured to conduct current between a front side of the silicon carbide substrate and a back side of the silicon carbide substrate.

5. The silicon carbide device of claim 1, wherein the gate insulating layer is positioned between the titanium carbide gate electrode and the silicon carbide substrate, wherein the titanium carbide gate electrode comprises at least a titanium carbide layer adjacent to the gate insulating layer, and wherein the titanium carbide layer has a thickness of at least 50 nm. The silicon carbide device according to claim 1 , wherein the transistor cell has a breakdown voltage of more than 300V.

7. A method for forming a silicon carbide device, the method comprising: forming a body region of a transistor cell in a silicon carbide substrate; forming a source region of a transistor cell in a silicon carbide substrate; as well as The titanium carbide gate electrode that forms the transistor cell, forming a gate metallization contacting the gate electrode such that the gate electrode of the transistor cell is contacted by the gate metallization at no more than two locations, wherein for each transistor cell, the titanium carbide gate electrode is connected to the gate metallization structure only at the terminal region of the titanium carbide gate electrode, and The end regions of the titanium carbide gate electrodes extend from respective lateral ends of the titanium carbide gate electrodes over at most 10% of the length of the respective titanium carbide gate electrodes. 8 . The method of claim 7 , further comprising forming a gate trench extending from a surface of the silicon carbide substrate into the silicon carbide substrate, wherein the titanium carbide gate electrode is formed in the gate trench. 9 . The silicon carbide device of claim 1 , wherein for each transistor cell, the position where the gate electrode contacts the gate electrode does not exceed 10% of the length of the gate electrode.

10. The silicon carbide device of claim 1, wherein the silicon carbide device comprises a plurality of transistor cells, wherein each transistor cell comprises a body region, a source region and a gate electrode, and wherein for each transistor cell in the plurality of transistor cells, the gate electrode is contacted by a gate metallization at no more than two locations. 11 . The silicon carbide device according to claim 7 , wherein for each transistor cell, the position where the gate electrode contacts the gate electrode does not exceed 10% of the length of the gate electrode.

12. The silicon carbide device of claim 7, wherein the silicon carbide device comprises a plurality of transistor cells, wherein each transistor cell comprises a body region, a source region and a gate electrode, and wherein for each transistor cell in the plurality of transistor cells, the gate electrode is contacted by a gate metallization at no more than two locations.

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