Interconnection method for semiconductor structure and semiconductor structure

Abstract

The present disclosure provides an interconnection method for a semiconductor structure and a semiconductor structure. The interconnection method includes: providing a stacking structure, the stacking structure includes multiple layers of bonded wafers or chips, each layer of wafers or chips includes a substrate and a wiring layer, and the wiring layer includes multiple metal wires; forming a silicon through hole in the stacking structure, the silicon through hole is connected to part of the metal wires; filling the silicon through hole with a conductive material. The interconnection method disclosed in the present disclosure can be made by a single mask etching process to electrically connect each layer of wafers or chips in the stacking structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to an interconnection method for a semiconductor structure and a semiconductor structure. Background Art

[0002] In the process of integrated circuit manufacturing, stacking multiple chips and establishing mechanical and electrical connections is an important method to reduce the size of integrated circuits. The current practice usually involves first making TSVs (Through Silicon Vias) for each chip to be stacked, then forming a bump (Micro-Bump) for each TSV, and finally using a chip-to-chip or chip-to-wafer method for positioning and bonding, and using each bump and TSV to achieve electrical connection between the upper chip and the lower chip.

[0003] First, the low efficiency in the chip-to-chip or chip-to-wafer bonding process leads to high costs. In addition, each chip needs to be pre-made with TSV and bumps. There is a high risk of positioning errors and connection errors during the bonding process, which can easily lead to disconnection of the electrical connection path between the upper and lower chips, resulting in a decrease in the yield rate.

[0004] Therefore, a solution for inter-chip electrical connection that can overcome the above problems is needed.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide an interconnection method and a semiconductor structure for a semiconductor structure, which are used to at least to a certain extent overcome the problems of complex semiconductor structure manufacturing procedures and low yield rate caused by the limitations and defects of related technologies.

[0007] According to a first aspect of the present disclosure, there is provided a method for interconnecting a semiconductor structure, comprising:

[0008] Providing a stacked structure, the stacked structure comprising multiple layers of bonded wafers or chips, each layer of the wafer or chip comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires;

[0009] Forming a through silicon via in the stacked structure, wherein the through silicon via is connected to a portion of the metal wire;

[0010] Filling the through silicon via with a conductive material.

[0011] In an exemplary embodiment of the present disclosure, forming a through silicon via in the stacked structure includes:

[0012] Vertically forming m first blind holes H1n with a diameter D1n and a length L1n on the stacked structure, wherein the penetration position of the first blind holes H1n in the wafer or chip is located between the metal wires, and D1n is smaller than the spacing DLn of the metal wires, and L1n is smaller than the height L0 of the stacked structure;

[0013] Applying a mask to the insides of the m first blind holes and the upper surface of the stacked structure;

[0014] Performing dry etching on the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind holes H1n;

[0015] A second blind hole H2n with a diameter of D2n and a length of L2n is formed at a portion of each of the first blind holes H1n where the mask is removed, so that the sidewall of the second blind hole exposes the end surface of the metal wire;

[0016] Remove all masks.

[0017] In an exemplary embodiment of the present disclosure, the step of dry etching the mask on the upper portion of the m first blind holes to remove the mask having a length L2n from top to bottom in the first blind hole H1n includes repeating the following steps:

[0018] A mask with a width of L3 is removed from the upper surface of the stacked structure directly opposite to the first blind hole H1n through a photolithography process;

[0019] The mask having a length of L1n is removed from top to bottom in the first blind hole H1n by a dry stripping process.

[0020] In an exemplary embodiment of the present disclosure, the step of removing the masked portion in each of the first blind holes H1n to form a second blind hole H2n having a diameter D2n and a length L2n includes:

[0021] Widening the portion of the first blind hole in the x-layer wafer or chip substrate to D2n by a first wet etching process, wherein the x-layer wafer or chip substrate is within the length range of the first blind hole removal mask;

[0022] The portion of the first blind hole in the wiring layer of the wafer or chip at the x layer is widened to D2n through a second wet etching process to expose the end surface of the metal wire, thereby forming the second blind hole H2n.

[0023] In an exemplary embodiment of the present disclosure, the filling of the conductive material in the through silicon via comprises:

[0024] Making a dielectric isolation layer on the inner surfaces of the first blind hole and the second blind hole;

[0025] Etching the dielectric isolation layer to expose the end surface of the metal wire and the bottom of the first blind hole;

[0026] Filling all the first blind holes and all the second blind holes with conductive material.

[0027] In an exemplary embodiment of the present disclosure, etching the dielectric isolation layer to expose the end surface of the metal wire and the bottom of the first blind hole includes:

[0028] The dielectric isolation layer at the location of the metal wire is etched by a plasma dry etching process to expose the end surface, a portion of the upper surface of the metal wire and the bottom of the first blind hole.

[0029] In an exemplary embodiment of the present disclosure, filling all the first blind holes and all the second blind holes with a conductive material comprises:

[0030] Sputtering a seed metal onto the inner wall and the bottom of the first blind hole and the second blind hole, wherein the seed metal comprises copper;

[0031] A metal is grown in the first blind hole and the second blind hole, wherein the metal includes copper.

[0032] In an exemplary embodiment of the present disclosure, it further includes:

[0033] Grinding the bottom layer of the stacked structure to expose the conductive material filled at the bottom of the through silicon via;

[0034] Producing bumps on the surface of the conductive material.

[0035] In an exemplary embodiment of the present disclosure, the cross-sectional shape of the through silicon via includes a circle, a polygon and an irregular shape.

[0036] According to a second aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0037] A stacked structure, the stacked structure comprising multiple layers of bonded wafers or chips, each layer of the wafers or chips comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires;

[0038] m through silicon vias, which are manufactured by any of the above interconnection methods, penetrate the stacked structure, and the center of the penetration position on each layer of the wafer or chip is located between the metal wires, and the through silicon vias include:

[0039] A first portion having a first diameter smaller than a pitch of the metal wires;

[0040] The second portion has a second diameter greater than the pitch of the metal wires, is coupled to the upper surface of the first portion and is aligned with the center of the first portion, and has a sidewall intersecting with the metal wires of a portion of the wafer or chip.

[0041] In an exemplary embodiment of the present disclosure, the cross-sectional shape of the through silicon via includes a circle, a polygon and an irregular shape.

[0042] The interconnection method for semiconductor structures provided by the embodiments of the present disclosure manufactures blind holes that penetrate the stacked structure for the bonded wafers or chips, and enlarges the blind holes by wet etching to expose the wire end faces of the preset wafers or chips in the stacked structure. Finally, the blind holes are filled with conductive materials to form TSVs that connect the preset wires. Multiple interconnection structures that connect wires of different wafers or chips can be manufactured through a single etching process, thus avoiding the problems of complex processes and low connection yield caused by the use of bumps to achieve electrical connection between chips in the related art.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0045] Figure 1A , Figure 1B and Figure 1C The flowchart and sub-flowcharts of the interconnection method in the exemplary embodiment of the present disclosure are shown.

[0046] Figure 2 is a schematic diagram of step S1.

[0047] Figure 3 is a schematic diagram of step S21.

[0048] Figure 4 is a schematic diagram of step S22.

[0049] Figure 5A to Figure 5E It is a schematic diagram of step S23.

[0050] Figure 6A to Figure 6D It is a schematic diagram of step S24.

[0051] Figure 7 It is a schematic diagram of step S25.

[0052] Figure 8A to Figure 8Gis a schematic diagram of step S3.

[0053] Figure 9A to Figure 9B is a schematic diagram of step S4.

[0054] Fig.10 It is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0056] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0057] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0058] Figure 1A , Figure 1B , Figure 1C The flowchart and sub-flowchart of the semiconductor interconnection method in the exemplary embodiment of the present disclosure are schematically shown. Figure 1A , the interconnection method 100 may include:

[0059] Step S1, providing a stacking structure, wherein the stacking structure comprises multiple layers of bonded wafers or chips, each layer of the wafer or chip comprises a substrate and a wiring layer, and the wiring layer comprises a plurality of metal wires;

[0060] Step S2, forming a through silicon via in the stacked structure, wherein the through silicon via is connected to a portion of the metal wire;

[0061] Step S3, filling the through silicon via with a conductive material.

[0062] The interconnection method for semiconductor structures provided by the embodiments of the present disclosure manufactures blind holes that penetrate the stacked structure for the bonded wafers or chips, and enlarges the blind holes by wet etching to expose the wire end faces of the preset wafers or chips in the stacked structure. Finally, the blind holes are filled with conductive materials to form TSVs that connect the preset wires. Multiple interconnection structures that connect wires of different wafers or chips can be manufactured through a single etching process, thus avoiding the problems of complex processes and low connection yield caused by the use of bumps to achieve electrical connection between chips in the related art.

[0063] Figure 1B is a sub-flowchart of step S2. Figure 1B In some embodiments, step S2 may include:

[0064] Step S21, vertically making m first blind holes with a diameter of D1n and a length of L1n for the stacked structure, wherein the penetration position of the first blind hole H1n in the wafer or chip is located between the metal wires, and D1n is smaller than the spacing between the metal wires, and L1n is smaller than the height L0 of the stacked structure;

[0065] Step S22, applying a mask to the inside of the m first blind holes and the upper surface of the stacked structure;

[0066] Step S23, dry etching the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind holes H1n;

[0067] Step S24, forming a second blind hole H2n with a diameter D2n and a length L2n at a portion of the first blind hole H1n where the mask is removed, so that the side wall of the second blind hole exposes the end surface of the metal wire;

[0068] Step S25, removing all masks.

[0069] Figure 1C This is a sub-flowchart of step S3. Figure 1C In some embodiments, step S3 may include:

[0070] Step 31, forming a dielectric isolation layer on the inner surfaces of the first blind hole and the second blind hole;

[0071] Step 32, etching the dielectric isolation layer to expose the end surface of the metal wire and the bottom of the first blind hole;

[0072] Step 33: Filling all the first blind holes and the second blind holes with conductive material.

[0073] Next, each step of the interconnection method 100 is described in detail.

[0074] Figure 2 is a schematic diagram of the stacking structure 200 provided in step S1. It can be understood that Figure 2 The process of manufacturing the stacked structure 200 (such as bonding the wafers or chips) may also be included before, which will not be described in detail in the present disclosure.

[0075] refer to Figure 2 The stacking structure may include a wafer stacking structure and a chip stacking structure, preferably a wafer stacking structure. Each layer of wafers or chips in the stacking structure 200 includes a substrate A and a wiring layer B, and the wiring layer B includes a plurality of metal wires 21. The purpose of the embodiment of the present disclosure is to connect the metal wires 21 corresponding to the positions of each layer by making a TSV to achieve electrical connection between the layers of wafers or chips. Figure 2 In the process, each wafer or chip is directly bonded, avoiding the cumbersome process of first making TSV and then making bumps in the related technology.

[0076] Figure 3 1 is a schematic diagram of step S21 of vertically forming m first blind holes H1n with a diameter D1n and a length L1n on the stacked structure 200, where n is a sequence number. Figure 3 , the penetration position of each first blind hole H1n in each layer of wafer or chip is located between metal wires 21, and D1n is smaller than the spacing DLn of the metal wires, and L1n is smaller than the height L0 of the stacked structure. The diameter D1n of each first blind hole can be determined according to the spacing DLn of the corresponding metal wires, as long as the difference between D1n and DLn is greater than the preset safety distance to avoid etching the metal wires.

[0077] The first blind hole can be manufactured by, for example, coating, photolithography, developing, etching and other related processes, and the present disclosure does not impose any special limitation on this.

[0078] Figure 4 Schematic diagram of step S22 of coating the inside of m first blind holes and the upper surface of the stacked structure with a mask 22. The mask material may be, for example, SiN, SiO2, etc. The coating mask may be, for example, deposited on the inside of each first blind hole and the upper surface of the stacked structure by a CVD (Chemical Vapor Deposition) process to form an inorganic thin film.

[0079] Figure 5A to Figure 5E 2 is a schematic diagram of performing dry etching on the masks at the upper portions of the m first blind holes in step S23 to remove the masks having a length L2n from top to bottom in the first blind hole H1n.

[0080] refer to Figure 5AFirst, a mask having a width Lw is removed from the upper surface of the stacked structure opposite to the first blind hole H1n by a photolithography process, for example, by coating a photoresist 23 to locate the position for removing the mask.

[0081] refer to Figure 5B ,exist Figure 5A After the process shown, a dry stripping process is used to remove the mask with a length of L2n from top to bottom in the first blind hole H1n. In this step, the mask removal length corresponding to each first blind hole can be determined according to the number of layers x of the wafer or chip to be connected.

[0082] refer to Figure 5C to Figure 5E Repeat the above process until the dry etching of m first blind holes is completed. Figure 5C , repeat the photolithography by applying the glue; Figure 5D , dry-etch the next first blind hole; Figure 5E After completing the dry etching of all the first blind holes, the photoresist is removed.

[0083] Figure 6A to Figure 6B The schematic diagram is that step S24 removes the mask in each first blind hole to make a second blind hole H2n with a diameter D2n and a length L2n, so that the sidewall of the second blind hole H2n exposes the end surface of the metal wire, wherein D2n is greater than the spacing DLn of the corresponding metal wire.

[0084] refer to Fig. 6A First, the portion of the nth first blind hole H1n located in the x-layer wafer or chip substrate A can be widened to a second diameter D2n by a first wet etching process. The first wet etching is, for example, to etch the substrate A with a width of D2n-D1n by injecting a first preset dose of a first etching solution into the first blind hole H1n. The type and dose of the first etching solution can be set according to the substrate type.

[0085] refer to Figure 6B ,exist Fig. 6A On the basis of the process shown, the portion of the first blind hole H1n located in the wiring layer B of the x-layer wafer or chip is widened to a second diameter D2n through a second wet etching process to expose the end surface of the metal wire 21, thereby forming a second blind hole H2n. The second wet etching process is, for example, to inject a second preset dose of a second etching solution into the first blind hole H1n to etch the dielectric portion of the wiring layer B with a width of D2n-D1n. The type and dose of the second etching solution can be set according to the type of the dielectric, and the dielectric is, for example, SiO2 or Si3N4.

[0086] exist Fig. 6A and Figure 6BIn the embodiment, the second diameter D2n can be determined according to the spacing DLn of the metal wires, as long as the difference between D2n and DLn is within a preset range so as to expose the end surface of the metal wire 21.

[0087] Figure 6C and Fig.6D They are Fig. 6A and Figure 6B Schematic diagram of the cross-sectional changes of the second blind hole H2n during the manufacturing process shown. Figure 6C ,exist Fig. 6A In the process shown, the diameter of the blind hole in substrate A changes from small to large. Fig.6D ,exist Figure 6B In the process shown, after the blind hole diameter is enlarged, the middle part of the wiring layer B is etched away, exposing the end surface of the metal wire 21. Figure 6C and Fig.6D Taking the cross-sectional shape of the first blind hole and the second blind hole as a circle as an example, in other embodiments of the present disclosure, the cross-sectional shape of the first blind hole and the second blind hole may also include a polygon, an irregular shape, a parallelogram (rhombus or square), a rounded quadrilateral, etc., and the present disclosure does not impose any special limitation on this.

[0088] Figure 7 It is a schematic diagram of removing all masks in step S25.

[0089] refer to Figure 7 Removing all masks may be performed by using a wet etching process to remove the mask material of each blind hole using different material selection ratios or other methods, and the present disclosure does not make any special limitation on this.

[0090] Figure 8A to Figure 8G is a schematic diagram of filling the through silicon via with a conductive material in step S3.

[0091] exist Fig. 8A In the embodiment, if a conductive material is to be filled into the first blind hole and the second blind hole, a dielectric isolation layer needs to be firstly formed on the inner surface of the second blind hole. The process of forming the dielectric isolation layer 24 can be, for example, depositing SiCN on the surface of the etched material by a chemical vapor deposition process, so that the dielectric isolation layer 24 covers the inner surface of the first blind hole H1n and the second blind hole H2n and the upper surface of the stacked structure.

[0092] exist Figure 8B In the process, the dielectric isolation layer is etched to expose the end surface of the metal wire 21 and the bottom of the first blind hole.

[0093] Figure 8C yes Figure 8B A magnified view of the process shown. Figure 8C, the dielectric isolation layer 24 at the metal wire position can be etched by a plasma dry etching process to expose the end surface, part of the upper surface and the bottom of the first blind hole H1n of the metal wire 21. At this time, the cross-sectional top view of the second blind hole at the metal lead position cannot see the lower surface of the metal lead and the dielectric isolation layer on the side wall of the second blind hole.

[0094] Fig.8D It is a schematic diagram of sputtering a seed metal 25 onto the inner wall and the bottom of the first blind hole and the second blind hole. The seed metal 25 includes, for example, tantalum and / or copper. Fig. 8E yes Fig.8D A magnified view of the process shown. Fig. 8E The sputtering position of the seed metal 25 may include the side walls of the first blind hole and the second blind hole, the upper surface and side surfaces of the metal wire end surface, and the bottom of the first blind hole, so that tantalum or copper can re-cover the metal wire so that the subsequently filled copper can be connected to the metal.

[0095] Fig.8F It is a schematic diagram of growing metal in the first blind hole and the second blind hole. In the process, the metal is, for example, copper or tungsten, and the process of growing the metal is, for example, electroplating.

[0096] Figure 8G yes Fig.8F A cross-sectional top view of the process is shown.

[0097] Figure 9A to Figure 9B is a schematic diagram of another step S4 of the interconnection method in an embodiment.

[0098] Step S4 may include Fig.9A The bottom layer of the stacked structure is grinded to expose the conductive material filled at the bottom of each through silicon via, and Fig. 9B The bumps 26 are shown formed on the surface of the conductive material. This process can prepare a structure that is interconnected with other stacked structures.

[0099] Through the above process, the different TSVs formed at the same time can realize electrical connection between metal wires in different layers of wafers or chips, overcoming the shortcomings of related technologies such as complex process, high cost and low yield when realizing electrical connection of stacked structures by making bumps, thereby improving the manufacturing efficiency of 3D integrated circuits.

[0100] Fig.10 It is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0101] refer to Fig.10 , the semiconductor structure 1000 may include:

[0102] A stacked structure 101, the stacked structure includes multiple layers of bonded wafers or chips, each layer of wafers or chips includes a substrate and a wiring layer, and the wiring layer includes multiple metal wires 102;

[0103] m through silicon vias (TSVs) can be manufactured by the above interconnection method, penetrating the stacked structure 101, and the center of the penetration position on each layer of wafer or chip is located between metal wires. The through silicon via n includes:

[0104] The first portion H1n has a first diameter D1n smaller than the pitch DLn of the metal wire 102;

[0105] The second part H2n has a second diameter D2n, which is greater than the spacing DLn of the metal wires 102, is coupled to the upper surface of the first part and is aligned with the center of the first part. The sidewall of the second part intersects with the metal wires 102 of the nth preset value wafer or chip, and the end surface of the metal wire 102 extends into the interior of the second part H2n. The main body of the through silicon via TSV includes metals such as copper and tungsten, and the outer insulating material includes tantalum, tantalum nitride and silicon carbonitride. The cross-section of the through silicon via TSV includes but is not limited to a circle, a quadrilateral (square, rectangle, parallelogram, rhombus), a polygon and other irregular shapes.

[0106] The semiconductor structure provided by the embodiment of the present disclosure does not have bumps between the chips, and can complete multiple metal interconnect structures connecting chips in different layers through a single TSV process, thereby avoiding problems such as misalignment and connection defects that are easily caused by electrical connection between chips through bumps in related technologies, thereby improving the efficiency and yield of manufacturing 3D integrated circuits.

[0107] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0108] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A method for interconnecting a semiconductor structure, characterized in that: include: Providing a stacked structure, the stacked structure comprising multiple layers of bonded wafers or chips, each layer of the wafer or chip comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires; Forming a through silicon via in the stacked structure, wherein the through silicon via is connected to a portion of the metal wire; Filling the through silicon via with a conductive material; The forming of a through silicon via in the stacked structure comprises: Vertically forming m first blind holes H1n with a diameter D1n and a length L1n on the stacked structure, wherein the penetration position of the first blind holes H1n in the wafer or chip is located between the metal wires, and D1n is smaller than the spacing DLn of the metal wires, and L1n is smaller than the height L0 of the stacked structure; Applying a mask to the insides of the m first blind holes and the upper surface of the stacked structure; Performing dry etching on the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind holes H1n; A second blind hole H2n with a diameter of D2n and a length of L2n is formed in the portion of the first blind hole H1n where the mask is removed, so that the side wall of the second blind hole exposes the end surface of the metal wire; Remove all masks.

2. The interconnection method according to claim 1, characterized in that: The dry etching of the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind holes H1n comprises repeating the following steps: A mask with a width of L3 is removed from the upper surface of the stacked structure directly opposite to the first blind hole H1n through a photolithography process; The mask having a length of L1n is removed from top to bottom in the first blind hole H1n by a dry stripping process.

3. The interconnection method according to claim 1, characterized in that: The method of removing the masked portion in each of the first blind holes H1n to form a second blind hole H2n with a diameter D2n and a length L2n comprises: Widening the portion of the first blind hole in the x-layer wafer or chip substrate to D2n by a first wet etching process, wherein the x-layer wafer or chip substrate is within the length range of the first blind hole removal mask; The portion of the first blind hole in the wiring layer of the wafer or chip at the x layer is widened to D2n through a second wet etching process to expose the end surface of the metal wire, thereby forming the second blind hole H2n.

4. The interconnection method according to claim 1, characterized in that: The filling of the conductive material in the through silicon via comprises: Making a dielectric isolation layer on the inner surfaces of the first blind hole and the second blind hole; Etching the dielectric isolation layer to expose the end surface of the metal wire and the bottom of the first blind hole; Filling conductive material in all the first blind holes and the second blind holes.

5. The interconnection method according to claim 4, characterized in that: The etching of the dielectric isolation layer to expose the end surface of the metal wire and the bottom of the first blind hole comprises: The dielectric isolation layer at the location of the metal wire is etched by a plasma dry etching process to expose the end surface, a portion of the upper surface of the metal wire and the bottom of the first blind hole.

6. The interconnection method according to claim 4, characterized in that: Filling all the first blind holes and all the second blind holes with a conductive material comprises: Sputtering a seed metal onto the inner wall and the bottom of the first blind hole and the second blind hole, wherein the seed metal comprises copper; A metal is grown in the first blind hole and the second blind hole, wherein the metal includes copper.

7. The interconnection method according to claim 1, characterized in that: Also includes: Grinding the bottom layer of the stacked structure to expose the conductive material filled at the bottom of the through silicon via; Producing bumps on the surface of the conductive material.

8. The interconnection method according to claim 1, characterized in that: The cross-sectional shapes of the through silicon via include circular, polygonal and irregular shapes.

9. A semiconductor structure, characterized in that: include: A stacked structure, the stacked structure comprising multiple layers of bonded wafers or chips, each layer of the wafers or chips comprising a substrate and a wiring layer, the wiring layer comprising a plurality of metal wires; m through silicon vias, penetrating the stacked structure and located between the metal wires, the through silicon vias comprising: A first portion having a first diameter smaller than a pitch of the metal wires; The second portion has a second diameter greater than the pitch of the metal wires, is coupled to the upper surface of the first portion and is aligned with the center of the first portion, and has a sidewall intersecting with the metal wires of a portion of the wafer or chip; the length of the second portion of each of the through silicon vias is different; Forming a through silicon via in the stacked structure includes: Vertically forming m first blind holes H1n with a diameter D1n and a length L1n on the stacked structure, wherein the penetration position of the first blind holes H1n in the wafer or chip is located between the metal wires, and D1n is smaller than the spacing DLn of the metal wires, and L1n is smaller than the height L0 of the stacked structure; Applying a mask to the insides of the m first blind holes and the upper surface of the stacked structure; Performing dry etching on the masks on the upper portions of the m first blind holes to remove the masks having a length of L2n from top to bottom in the first blind holes H1n; A second blind hole H2n with a diameter of D2n and a length of L2n is formed in the portion of the first blind hole H1n where the mask is removed, so that the side wall of the second blind hole exposes the end surface of the metal wire; Remove all masks.

10. The semiconductor structure according to claim 9, wherein: The cross-sectional shapes of the through silicon via include circular, polygonal and irregular shapes.

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