Display Panel

Abstract

A display panel may include the following elements: a substrate including an opening area, a display area surrounding the opening area, and a first non-display area between the opening area and the display area; a data line located on a first side relative to the opening area; a first scan line; a second scan line; a first pixel connected to the data line and the first scan line; a second pixel connected to the data line and the second scan line; a first emission control line connected to the first pixel; a connecting portion located on the first non-display area; a second emission control line connected to the second pixel and connected to the first emission control line through the connecting portion; and an emission control driver configured to simultaneously provide an emission control signal to the first emission control line and the second emission control line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0153022 filed in the Korean Intellectual Property Office on November 30, 2018, the disclosure of which is incorporated herein by reference in its entirety.

[0003] The technical field relates to a display panel. Background Art

[0004] A display panel may be included in an electronic device for displaying images. In addition to displaying images, the display panel may facilitate other functions of the electronic device. For example, the display panel may enable a user interface of the electronic device. Summary of the invention

[0005] One or more embodiments may relate to a display panel including an opening area for accommodating at least one of a camera, a sensor, etc., and may relate to a device and / or an electronic device including the display panel.

[0006] According to one or more embodiments, a display panel includes: a substrate including an opening area, a display area surrounding the opening area, a first non-display area between the opening area and the display area, and a second non-display area outside the display area; a plurality of data lines extending in a first direction and arranged around the opening area; a plurality of scan lines arranged in a second direction intersecting the first direction, the plurality of scan lines being arranged at two opposite sides of the opening area; a plurality of emission control lines arranged in the second direction and including a first emission control line and a second emission control line, the first emission control lines being connected to each other on a basis of two adjacent lines on a first side of the opening area, and the second emission control lines being connected to each other on a basis of two adjacent lines on a second side of the opening area facing the first side; and an emission control driver arranged in the second non-display area and configured to simultaneously provide emission control signals to the emission control lines connected to each other on a basis of two adjacent lines.

[0007] The first emission control line and the second emission control line may be connected to one emission control bypass line that is routed around the opening area.

[0008] The emission control bypass line may be disposed between adjacent data lines bypassing the opening area in the first non-display area.

[0009] The emission control detour line may be formed on a layer different from those of the first emission control line and the second emission control line.

[0010] An insulating layer may be further disposed between the emission control detour line and the first and second emission control lines, and the emission control detour line and the first and second emission control lines may contact each other through contact holes formed in the insulating layer.

[0011] Emission control detour lines adjacent to each other among the emission control detour lines may be provided on different layers, respectively.

[0012] The emission control detour line may be provided on the same layer on which the first emission control line and the second emission control line are disposed.

[0013] The emission control detour line, the first emission control line, and the second emission control line may include the same material.

[0014] The first emission control line may include a (1-1)th emission control line and a (1-2)th emission control line adjacent to the (1-1)th emission control line, the second emission control line may include a (2-1)th emission control line and a (2-2)th emission control line adjacent to the (2-1)th emission control line, the first emission control driver may simultaneously supply an emission control signal to the two emission control lines connected to the (1-1)th emission control line, and the second emission control driver may simultaneously supply an emission control signal to the two emission control lines connected to the (2-2)th emission control line.

[0015] The first emission control driver may be disposed for every four adjacent emission control lines at a first side of the second non-display area, and the second emission control driver may be disposed for every four adjacent emission control lines at a second side of the second non-display area facing the first side.

[0016] The first emission control line and the second emission control line may be separated from each other with an open area therebetween.

[0017] The first emission control line and the second emission control line may be provided on the same layer.

[0018] The first emission control line and the second emission control line may include the same material.

[0019] The first emission control line may include a (1-1)th emission control line and a (1-2)th emission control line adjacent to the (1-1)th emission control line, the second emission control line may include a (2-1)th emission control line and a (2-2)th emission control line adjacent to the (2-1)th emission control line, the first emission control driver may simultaneously supply an emission control signal to the two emission control lines connected to the (1-1)th emission control line, and the second emission control driver may simultaneously supply an emission control signal to the two emission control lines connected to the (2-2)th emission control line.

[0020] The first emission control driver may be disposed one for every two adjacent emission control lines at a first side of the second non-display area, and the second emission control driver may be disposed one for every two adjacent emission control lines at a second side of the second non-display area facing the first side.

[0021] The display panel may further include: a previous scan line disposed in the second direction and disposed at two opposite sides of the opening area; and a scan driver disposed in the second non-display area and configured to transmit a scan signal to the scan line and the previous scan line.

[0022] The scan line may extend by circling around an edge of the opening area, and the previous scan line may be spaced apart from the scan line and extend by circling around the edge of the opening area.

[0023] The scan line and the previous scan line may include different materials, respectively.

[0024] The display area may include a plurality of pixels, a scan line and a previous scan line may be arranged together in one pixel, and the scan line and the previous scan line arranged together in one pixel may be connected to each other at two opposite sides of an opening area and connected by a scan bypass line that is arranged around the opening area.

[0025] The scan detour lines adjacent to each other among the scan detour lines may be arranged on different layers.

[0026] The scan detour line may be disposed on a layer different from a layer on which the scan line and the previous scan line are disposed.

[0027] The scan line and the previous scan line disposed at two opposite sides of the opening region can be separated from each other using the opening region therebetween.

[0028] The scan line and a portion of the previous scan line close to the opening area may be connected to each other.

[0029] The scanning line and the portion of the previous scanning line close to the opening area may not be connected to each other.

[0030] The display area may include a plurality of pixels, a scan line and a previous scan line may be arranged together in one pixel, and the scan line and the previous scan line arranged together in one pixel may be connected to each other at two opposite sides of the opening area, and the scan driver may include a first scan driver and a second scan driver, the first scan driver may be arranged on a first side of the second non-display area according to the scan line and the previous scan line included in one pixel, and the second scan driver may be arranged on a second side of the second non-display area facing the first side according to the scan line and the previous scan line included in one pixel.

[0031] The display panel may include the following elements: a substrate including an opening area, a display area surrounding the opening area, a first non-display area between the opening area and the display area, and a second non-display area located outside the display area; a first data line located on a first side relative to the opening area in a plan view of the display panel; a first scan line; a second scan line; a first pixel electrically connected to each of the first data line and the first scan line; a second pixel electrically connected to each of the first data line and the second scan line; a first emission control line electrically connected to the first pixel; a first connection portion located on the first non-display area; a second emission control line electrically connected to the second pixel and electrically connected to the first emission control line through the first connection portion; and a first emission control driver located on the second non-display area and configured to simultaneously provide an emission control signal to the first emission control line and the second emission control line.

[0032] The display panel may include the following elements: a second data line located at a second side relative to the opening area in a plan view of the display panel, wherein the opening area may be located between the first data line and the second data line; a third pixel electrically connected to each of the second data line and the first scan line; and a fourth pixel electrically connected to each of the second data line and the second scan line. The second emission control line may be electrically connected to the fourth pixel and may include a first emission control bypass portion. The first emission control bypass portion may bypass the opening area.

[0033] The display panel may include the following elements: a third data line including a first data bypass portion, the first data bypass portion bypassing the opening area and being located on the first non-display area; and a fourth data line including a second data bypass portion, the second data bypass portion bypassing the opening area and being located on the first non-display area. The first emission control bypass portion may be disposed between the first data bypass portion and the second data bypass portion.

[0034] The display panel may include a first insulating layer having a first contact hole. The second emission control line may include a first pixel connection portion. The first emission control detour portion may be connected to the first pixel connection portion through the first contact hole and may be electrically connected to the second pixel through the first pixel connection portion.

[0035] The display panel may include a second insulating layer having a second contact hole. The first emission control bypass portion may be connected to the first pixel connection portion through the second contact hole.

[0036] The display panel may include: a second emission control detour portion immediately adjacent to the first emission control detour portion, with no intermediate emission control detour portion located between the first emission control detour portion and the second emission control detour portion. The first emission control detour portion and the second emission control detour portion may directly contact different insulating layers, respectively.

[0037] The display panel may include a first insulating layer. The second emission control line may include a first pixel connection portion. The first emission control detour portion may be electrically connected to the second pixel through the first pixel connection portion. The first emission control detour portion and the first pixel connection portion may directly contact the same surface of the first insulating layer.

[0038] The material of the first emission control bypass portion may be the same as that of the first pixel connection portion.

[0039] The display panel may include the following elements: a first opposing emission control line positioned opposite to the first emission control line and electrically connected to the third pixel; and a second emission control driver located on the second non-display area and configured to simultaneously provide an emission control signal to the first opposing emission control line and the second emission control line.

[0040] The first emission control driver may be electrically connected to four adjacent emission control lines located at a first side relative to the opening area. The second emission control driver may be electrically connected to four adjacent emission control lines located at a second side relative to the opening area.

[0041] The display panel may include the following elements: a second data line located on a second side relative to the opening area in a plan view of the display panel, wherein the opening area may be located between the first data line and the second data line; a third pixel electrically connected to the second data line and each of the first scan lines; and a first opposing emission control line positioned opposite to the first emission control line and electrically connected to the third pixel, wherein the opening area may be located between the first emission control line and the first opposing emission control line.

[0042] The display panel may include an insulating layer. The first emission control line and the first opposing emission control line may directly contact the same surface of the insulating layer.

[0043] The material of the first emission control line may be the same as that of the first opposing emission control line.

[0044] The display panel may include the following elements: a fourth pixel electrically connected to each of the second data line and the second scan line; a first opposing connection portion disposed opposite to the first connection portion and located on the first non-display area;

[0045] a second opposing emission control line electrically connected to the fourth pixel and electrically connected to the first opposing emission control line through the first opposing connection portion; and a second emission control driver located on the second non-display area and configured to simultaneously supply an emission control signal to the first opposing emission control line and the second opposing emission control line.

[0046] Each of the first connection portion and the first opposing connection portion may conform to an arc of a geometric circle. In a plan view of the display panel, the geometric circle may be concentric with a perimeter of the opening area.

[0047] The display panel may include the following elements: a second data line located at a second side relative to the opening area in a plan view of the display panel, wherein the opening area may be located between the first data line and the second data line; a third pixel electrically connected to each of the second data line and the first scan line; a first previous scan line electrically connected to each of the first pixel and the third pixel; and a first scan driver disposed on the second non-display area and configured to provide a scan signal to both the first scan line and the first previous scan line. The first scan line may be electrically connected to a gate electrode of a first transistor of the first pixel. The first previous scan line may be electrically connected to a gate electrode of a second transistor of the first pixel.

[0048] The first scan line may include a first scan detour portion. The first scan detour portion may detour the opening area. The first previous scan line may include a first previous scan detour portion. The first previous scan detour portion may be spaced apart from the first scan detour portion and may detour the opening area.

[0049] The material of the first scan line may be different from the material of the first previous scan line.

[0050] The display panel may include a first scanning detour portion. The first scanning detour portion may detour the opening area. Each of the first scanning line and the first previous scanning line may be electrically connected to the first scanning detour portion.

[0051] The display panel may include the following elements: a second previous scan line electrically connected to the second pixel; and a second scan bypass portion. The second scan bypass portion may bypass the opening area, may be electrically connected to each of the second scan line and the second previous scan line, and is adjacent to the first scan bypass portion, with no intermediate scan bypass portion located between the first scan bypass portion and the second scan bypass portion. The first scan bypass portion and the second scan bypass portion are respectively in direct contact with different insulating layers.

[0052] The first scan detour portion may directly contact the first insulating layer. The first scan line and the first previous scan line may directly contact a second insulating layer different from the first insulating layer.

[0053] The display panel may include the following elements: a second data line located on a second side relative to the opening area in a plan view of the display panel, wherein the opening area may be located between the first data line and the second data line; a first opposing scan line positioned opposite to the first scan line, wherein the opening area may be located between the first scan line and the first opposing scan line; a third pixel electrically connected to each of the second data line and the first opposing scan line; a first previous scan line electrically connected to the first pixel; and a first opposite previous scan line positioned opposite to the first previous scan line and electrically connected to the third pixel, wherein the opening area may be located between the first previous scan line and the first opposite previous scan line.

[0054] The display panel may include the following elements: a first scan connection portion located on a first non-display area, wherein a first scan line can be electrically connected to a first previous scan line through the first scan connection portion; and a first opposing scan connection portion placed opposite to the first scan connection portion and located on the first non-display area, wherein the first opposing scan line can be electrically connected to a first opposing previous scan line through the first opposing scan connection portion.

[0055] An end portion of the first scan line and an end portion of the first previous scan line may be spaced apart from each other and may not be electrically connected to each other. At least one of the end portion of the first scan line and the end portion of the first previous scan line may be located at a boundary of the first non-display area.

[0056] The display panel may include: a second scan driver located on the second non-display area and configured to provide a scan signal to both the first scan line and the first previous scan line. Each of the opening area, the first non-display area, and the display area may be located between the first scan driver and the second scan driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a perspective view of a display device according to an embodiment.

[0058] Figure 2 is a cross-sectional view of a display device according to an embodiment.

[0059] Figure 3A is a cross-sectional view of a display panel according to an embodiment.

[0060] Figure 3B is a cross-sectional view of a display panel according to an embodiment.

[0061] Figure 3C is a cross-sectional view of a display panel according to an embodiment.

[0062] Figure 4A is a cross-sectional view of a display panel according to an embodiment.

[0063] Figure 4Bis a cross-sectional view of a display panel according to an embodiment.

[0064] Figure 4C is a cross-sectional view of a display panel according to an embodiment.

[0065] Figure 5 is a plan view of a display panel according to an embodiment.

[0066] Figure 6 is an equivalent circuit diagram of one of the pixels of the display panel according to the embodiment.

[0067] Fig. 7A is a plan view of one of the pixels of the display panel according to the embodiment.

[0068] Figure 7B is along Fig. 7A A cross-sectional view taken along line AA' and line BB'.

[0069] Figure 8 is a plan view of lines around an opening area of ​​a display panel according to an embodiment.

[0070] Fig.9A According to the embodiment Figure 8 A cross-sectional view of the emission control line taken along line IX-IX'.

[0071] Fig. 9B According to the embodiment Figure 8 A cross-sectional view of the emission control line taken along line IX-IX'.

[0072] Fig.10 is a plan view of at least an emission control line and an emission control driver of a display panel according to an embodiment.

[0073] Fig.11 is a plan view of at least an emission control line and an emission control driver of a display panel according to another embodiment.

[0074] Fig.12 is a plan view of at least an emission control line and an emission control driver of a display panel according to another embodiment.

[0075] Fig.13 is a plan view of at least an emission control line and an emission control driver of a display panel according to another embodiment.

[0076] Fig.14 is a plan view of at least a scan line, a previous scan line, and a scan driver of a display panel according to another embodiment.

[0077] Fig.15 is a plan view of at least a scan line, a previous scan line, and a scan driver of a display panel according to another embodiment.

[0078] Fig.16 is a plan view of at least a scan line, a previous scan line, and a scan driver of a display panel according to another embodiment.

[0079] Fig.17 is a plan view of at least a scan line, a previous scan line, and a scan driver of a display panel according to another embodiment. DETAILED DESCRIPTION

[0080] The exemplary embodiments are described with reference to the accompanying drawings. The implementable embodiments may be embodied in many different forms and should not be construed as being limited to these exemplary embodiments.

[0081] The same reference numerals in the drawings may denote the same or corresponding elements, and descriptions related to these elements may not be repeated.

[0082] Expressions such as “at least one of,” when preceding a list of elements, may modify the entire list of elements but may not modify the individual elements in the list.

[0083] Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another element. The first element can be referred to as the second element without departing from the teaching of one or more embodiments. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. Terms "first", "second", etc. can also be used herein to distinguish between elements of different categories or sets. For simplicity, the terms "first", "second", etc. can represent "first type (or first set)", "second type (or second set)", etc., respectively.

[0084] The singular forms "a", "an", "the" may also include plural forms, unless the context clearly indicates otherwise.

[0085] The term “includes / comprising” may specify the presence of stated features or components, but does not exclude the presence or addition of one or more other features or components.

[0086] When a first element is referred to as being “on” or “connected to” a second element, the first element may be directly on or directly connected to the second element, and one or more intervening elements may be present between the first and second elements.

[0087] For convenience of explanation, the size of each element in the drawings may be exaggerated.

[0088] When a certain embodiment can be implemented differently, a specific process can be performed in a different order than described. For example, two processes described in succession can be performed substantially at the same time, or in a reverse order to the described order.

[0089] The term “bypass” may mean “get around”. The term “connect” may mean “electrically connected”. The term “conductive” may mean “electrically conductive”. The term “insulating” may mean “electrically insulating”. The term “line” may mean “portion” or “a collection of portions”. The term “opening area” may mean “opening” or “an area corresponding to an opening”. The term “around the opening area” may mean “at / on / in the first non-display area”. The term “portion” may mean “portion”. The term “row” may mean “pixel row”. The term “column” may mean “pixel column”. The term “on different layers” may mean “directly contacting different insulating layers respectively”. The term “on the same layer” may mean “directly contacting the same face / surface of the same insulating layer”.

[0090] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0091] refer to Figure 1 The display device 1 includes a display area DA that emits light and a non-display area NDA that does not emit light. The non-display area NDA is adjacent to the display area DA. The display device 1 may provide an image using light emitted from a plurality of pixels disposed in the display area DA.

[0092] The display device 1 includes an opening area OA at least partially surrounded by a display area DA. In an embodiment, Figure 1 , the opening area OA is shown to be completely surrounded by the display area DA. The non-display area NDA may include a first non-display area NDA1 surrounding the opening area OA and a second non-display area NDA2 surrounding the periphery of the display area DA. The first non-display area NDA1 may completely surround the opening area OA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0093] In an embodiment, the display device 1 may be an organic light emitting display device, an inorganic light emitting display device, or a quantum dot light emitting display device.

[0094] The number and positions of the opening areas OA may be configured according to the embodiment.

[0095] Figure 2 is according to the embodiment and along Figure 1 The cross-sectional view corresponds to the cross-sectional view taken along the line II-II'.

[0096] refer to Figure 2, the display device 1 may include a display panel 10, and may include an input sensing layer 40 and an optical functional layer 50 disposed on the display panel 10. These layers may be covered by a window 60. The display device 1 may be or may be included in an electronic device such as a mobile phone, a laptop computer, or a smart watch.

[0097] The display panel 10 may display an image. The display panel 10 includes pixels arranged in a display area DA. Each of the pixels may include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode.

[0098] The input sensing layer 40 obtains coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a trace connected to the sensing electrode. The input sensing layer 40 may be disposed on the display panel 10. The input sensing layer 40 may sense an external input using a mutual capacitance method and / or a self-capacitance method.

[0099] The input sensing layer 40 may be directly formed on the display panel 10, or may be separately formed and then coupled using an adhesive layer such as an optically clear adhesive (OCA). The input sensing layer 40 may be continuously formed after the process of forming the display panel 10. An adhesive layer may not be provided between the input sensing layer 40 and the display panel 10. In an embodiment, the optical functional layer 50 may be located between the display panel 10 and the input sensing layer 40.

[0100] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce light reflected from the display panel 10 and transmitted through the window 60. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal retarder. The retarder may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may include a film-type polarizer or a liquid crystal polarizer. The film-type polarizer may include a retractable synthetic resin film, and the liquid crystal polarizer may include liquid crystals arranged in a predetermined arrangement. Each of the retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or their protective films may be the base layer of the anti-reflection layer.

[0101] In an embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be set by considering the color of the light emitted from the pixel of the display panel 10. In an embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer respectively arranged in different layers. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may generate destructive interference, and thus undesired reflected light may be reduced.

[0102] The optical function layer 50 may include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display panel 10 or reduce the color deviation of the light. The lens layer may include a layer having a concave lens or a convex lens structure and / or include a plurality of layers having different refractive indices, respectively. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or may include one of the anti-reflection layer and the lens layer.

[0103] The display panel 10 , the input sensing layer 40 , and / or the optical function layer 50 may include an opening. Figure 2 It is shown that the display panel 10, the input sensing layer 40 and the optical function layer 50 include openings 10H, 40H and 50H corresponding to each other, respectively. The openings 10H, 40H and 50H correspond to the opening area OA. In an embodiment, at least one of the display panel 10, the input sensing layer 40 and the optical function layer 50 may not include an opening. For example, one or two of the display panel 10, the input sensing layer 40 and the optical function layer 50 may not include an opening. The opening area OA may be at least one of the openings 10H, 40H and 50H, or may correspond to at least one of the openings 10H, 40H and 50H. For example, the opening area OA may be the first opening 10H of the display panel 10, or may correspond to the first opening 10H of the display panel 10.

[0104] The component 20 may be located at the opening area OA. Figure 2 As shown by the solid line, the component 20 may be located inside the openings 10H, 40H, and 50H. As shown by the dotted line, the component 20 may correspond to at least one of the openings 10H, 40H, and 50H, and may be located outside the display panel 10.

[0105] Component 20 may include electronic components. For example, component 20 may include electronic components that use light or sound. For example, the electronic component may be a sensor such as an infrared sensor that emits and / or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small lamp that outputs light, or a speaker that outputs sound. The electronic component using light may use light in one or more bands of various bands such as at least one of visible light, infrared light, and ultraviolet light. In an embodiment, the opening area OA may be a transmission area, wherein the light and / or sound provided and / or received by component 20 may pass through the transmission area.

[0106] In an embodiment, the display device 1 can be used in a smart watch or an instrument panel of a car, and the component 20 can be a member including a clock needle or a needle for indicating information (e.g., the speed of the vehicle). The component 20 can be exposed through the window 60, and the window 60 can include an opening corresponding to the opening area OA.

[0107] Component 20 may include one or more elements related to the functionality of display panel 10 and / or related to the aesthetic design of display panel 10. Figure 2 Although not shown in the drawings, an adhesive layer (eg, an OCA layer) may be located between the window 60 and the optical function layer 50 .

[0108] FIG. 3A to FIG. 3C Each of them shows a cross-sectional view of the display panel 10 according to the embodiment.

[0109] refer to FIG. 3A to FIG. 3C The display panel 10 includes a display element layer 200 disposed on a substrate 100. The substrate 100 may include a glass material or a polymer resin. For example, the substrate 100 may include SiO 2 , or may include reinforced plastics.

[0110] The display element layer 200 may correspond to the display area DA and include a plurality of pixels. The display element layer 200 includes a pixel circuit corresponding to each pixel and a display element electrically connected to the pixel circuit. The pixel circuit may include a thin film transistor and a storage capacitor, and the display element may include an organic light emitting diode.

[0111] As a part of the packaging member 300, the packaging substrate 340 overlaps with the substrate 100. The sealing material 350 is disposed between the substrate 100 and the packaging substrate 340. The sealing material 350 surrounds the display element layer 200 between the substrate 100 and the packaging substrate 340. The sealing material 350 may be surrounded by a first edge (also referred to as an inner edge) of the display element layer 200 in the first non-display area NDA1, and may surround a second edge (also referred to as an outer edge) of the display element layer 200 in the second non-display area NDA2. When viewed in a direction perpendicular to the main surface, the opening area OA may be completely surrounded by the sealing material 350, and the second edge of the display element layer 200 may also be completely surrounded by the sealing material 350.

[0112] The display panel 10 may include a first opening 10H corresponding to the opening area OA. Figure 3A It is shown that the substrate 100 and the packaging substrate 340 include through holes 100H and 340H corresponding to the opening area OA, respectively. The display element layer 200 may also include a through hole corresponding to the opening area OA.

[0113] In another embodiment, if Figure 3B As shown in , the package substrate 340 may include a through hole 340H corresponding to the opening area OA, but the substrate 100 may not include a through hole. Figure 3CAs shown, the substrate 100 and the encapsulation substrate 340 may not include a through hole corresponding to the opening area OA, respectively. The display element layer 200 may include a through hole corresponding to the opening area OA. In another embodiment, the sealing material 350 provided in the first non-display area NDA1 of the display panel 10 may be unnecessary. The display element layer 200 may not include a through hole corresponding to the opening area OA. The component 20 with relatively high light transmittance is not required (see Figure 2 ) may be disposed in the opening area OA. Even if the display element layer 200 does not include a through hole corresponding to the opening area OA, a portion of the display element layer 200 corresponding to the opening area OA may provide sufficient light transmittance.

[0114] FIG. 4A to FIG. 4C Each of them shows a cross-sectional view of a display panel 10 ′ according to an embodiment.

[0115] refer to Figure 4A , the display element layer 200 is disposed on the substrate 100. The display element layer 200 may be covered by a thin film encapsulation member 300'. The thin film encapsulation member 300' may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 4A A first inorganic encapsulating layer 310 ′, a second inorganic encapsulating layer 330 ′, and an organic encapsulating layer 320 ′ between the inorganic encapsulating layers 310 ′ and 330 ′ are shown.

[0116] The inorganic encapsulation layers 310' and 330' may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320' may include a polymer material. The polymer material may include at least one of acrylic resin, epoxy resin, polyimide, and polyethylene.

[0117] The substrate 100 may include a polymer resin and may include a multi-layer structure. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 sequentially stacked in the z direction.

[0118] Each of the base layers 101 and 103 may include a polymer resin. For example, the base layers 101 and 103 may include a polymer resin such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), and cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0119] Each of the barrier layers 102 and 104 may include a barrier layer configured to prevent penetration of external foreign matter, and may include a material including SiN x and / or SiO x A single or multilayer structure of inorganic materials.

[0120] The substrate 100 and the thin film encapsulation member 300 ′ may optimize flexibility of the display panel 10 ′.

[0121] refer to Figure 4A The through holes 100H and 300H' pass through the substrate 100 and the thin film encapsulation member 300', respectively, and both correspond to the first opening 10H and the opening area OA of the display panel 10'. The display element layer 200 may also include a through hole corresponding to the opening area OA.

[0122] In another embodiment, if Figure 4B As shown in FIG. 1 , the organic encapsulation layer 320 ′ of the thin film encapsulation member 300 ′ includes a through hole 320H ′ corresponding to the opening area OA, but the substrate 100 and the inorganic encapsulation layers 310 ′ and 330 ′ may not include a through hole, respectively. Figure 4C As shown in FIG. 1 , the layers constituting the thin film encapsulation member 300 ′ may not include a through hole corresponding to the opening area OA. That is, the inorganic encapsulation layers 310 ′ and 330 ′ and the organic encapsulation layer 320 ′ may cover the opening area OA. In another embodiment, a component 20 with high light transmittance is not required (see FIG. 1 ). Figure 2 ) is disposed in the opening area OA. Even if the display element layer 200 does not include a through hole corresponding to the opening area OA, a portion of the display element layer 200 corresponding to the opening area OA may provide sufficient light transmittance.

[0123] Figure 5 is a plan view of a display panel 10 according to an embodiment.

[0124] refer to Figure 5 The display panel 10 includes a display area DA and non-display areas NDA1 and NDA2. The substrate 100 may have areas OA, NDA1, and NDA2 corresponding to the opening area OA and the non-display areas NDA1 and NDA2 of the display panel 10, respectively.

[0125] The display panel 10 includes a plurality of pixels P disposed in a display area DA. Each of the pixels P may include a display element such as an organic light emitting diode. Each pixel P may emit, for example, red light, green light, blue light, or white light through an organic light emitting diode. An opening area OA is disposed inside the display area DA, and a first non-display area NDA1 is located between the opening area OA and the display area DA.

[0126] The first non-display area NDA1 may surround the opening area OA. No display element, for example, no organic light emitting diode is provided in the first non-display area NDA1. Traces and / or power lines providing signals to the pixels P provided around the opening area OA may pass through the first non-display area NDA1.

[0127] Each pixel P is electrically connected to an external circuit disposed in the second non-display area NDA2. A first external driving circuit 110, a second external driving circuit 120, a terminal 140, a data driving circuit 150, a first power line 160, and a second power line 170 may be disposed in the second non-display area NDA2.

[0128] The first external driving circuit 110 may be a scanning and control driving circuit, and may provide a scanning signal and an emission control signal to the pixel P through the scanning line SWL and the emission control line EL. The second external driving circuit 120 may also be a scanning and control driving circuit, and may be disposed opposite to the first external driving circuit 110. Like the first external driving circuit 110, the second external driving circuit 120 may provide a scanning signal and an emission control signal to the pixel P through the scanning line SWL and the emission control line EL.

[0129] The terminal 140 may be disposed at one side of the second non-display area NDA2. The terminal 140 may not be covered by the insulating layer and may be electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits a control signal or power to the display panel 10. The control signal generated by the controller may be transmitted to the external driving circuits 110 and 120 through the printed circuit board PCB. The controller may transmit the driving voltage ELVDD and the common voltage ELVSS (see below) through the connection wirings 161 and 171, respectively. Figure 6 ) are supplied to the power lines 160 and 170. The driving voltage ELVDD may be supplied to each pixel P through the driving voltage line PL connected to the first power line 160, and the common voltage ELVSS may be supplied to the counter electrode of the pixel P connected to the second power line 170.

[0130] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to the pixel P through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151. Figure 5 It is shown that the data driving circuit 150 is disposed on the printed circuit board PCB. In another embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power line 160.

[0131] The first power line 160 may include a first line 162 and a second line 163 extending in the x-direction at opposite sides of the display area DA. The second power line 170 may partially surround the display area DA and may have one open side.

[0132] Figure 6 is an equivalent circuit diagram of one pixel among the pixels P of the display panel 10 according to the embodiment.

[0133] refer to Figure 6 , the pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor Cst. The thin film transistors and the storage capacitor Cst may be connected to the traces SWL, SIL, EL and DL, the initialization voltage line VL and the driving voltage line PL.

[0134] Although Figure 6 , each pixel P is shown to be connected to the traces SWL, SIL, EL and DL, the initialization voltage line VL and the driving voltage line PL, but the present disclosure is not limited thereto. In another embodiment, at least one of the traces SWL, SIL, EL and DL, the initialization voltage line VL and the driving voltage line PL can be shared by adjacent pixels.

[0135] The plurality of thin film transistors may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 , and a second initialization thin film transistor T7 .

[0136] The trace may include a scan line SWL configured to transmit a scan signal GW, a previous scan line SIL configured to transmit a previous scan signal GI to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL configured to transmit an emission control signal EM to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SWL and configured to transmit a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transmits an initialization voltage Vint for initializing the driving thin film transistor T1 and the pixel electrode of the organic light emitting diode OLED.

[0137] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin film transistor T2 and drives the driving current I OLED Supplied to the organic light emitting diode OLED.

[0138] A switching gate electrode G2 of the switching thin film transistor T2 is connected to the scanning line SWL, a switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is connected to the driving voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scanning signal GW transmitted through the scanning line SWL, and performs a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0139] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SWL, the compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and is connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal GW transmitted through the scan line SWL, and diode-connects the driving thin film transistor T1 by electrically connecting the driving gate electrode G1 of the driving thin film transistor T1 to the driving drain electrode D1.

[0140] A first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SIL, a first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and a first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal GI transmitted through the previous scan line SIL, and performs an initialization operation of initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0141] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0142] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0143] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal EM transmitted through the emission control line EL to allow the driving voltage ELVDD to be transmitted to the organic light emitting diode OLED and the driving current I OLED Flow through the organic light emitting diode OLED.

[0144] The second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SIL, the second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on in response to the previous scan signal GI transmitted through the previous scan line SIL to initialize the pixel electrode of the organic light emitting diode OLED.

[0145] Although Figure 6 , the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are shown to be connected to the previous scan line SIL, but the present disclosure is not limited thereto. In another embodiment, the first initialization thin film transistor T4 may be connected to the previous scan line SIL and driven in response to the previous scan signal GI, and the second initialization thin film transistor T7 may be connected to a separate trace (e.g., the next scan line) and driven in response to a signal transmitted through the trace.

[0146] The second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED can receive the driving current I from the driving thin film transistor T1. OLED and emits light to display images.

[0147] Although in Figure 6 2 shows that each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 includes a double gate electrode, but each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 may include one gate electrode.

[0148] Figure 6 It is shown that the pixel circuit PC includes seven thin film transistors and one storage capacitor. The number of thin film transistors and the number of storage capacitors may be six or less, or eight or more, and may be configured according to the embodiment.

[0149] Fig. 7A is a plan view of one pixel among the pixels P of the display panel 10 according to the embodiment, and Figure 7B is along Fig. 7A A cross-sectional view taken along line AA' and line BB'.

[0150] refer to Fig. 7A and Figure 7BThe driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6 and the second initialization thin film transistor T7 are arranged along the semiconductor layer 1130. Figure 7B As shown in , a semiconductor layer 1130 is located above a substrate 100 , and a buffer layer 2111 including an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride is formed below the semiconductor layer 1130 .

[0151] Some areas of the semiconductor layer 1130 correspond to the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. In other words, it can be understood that the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 are connected to each other and bent into various shapes. Figure 7B A driving semiconductor layer 1130 a of the driving thin film transistor T1 , a compensation semiconductor layer 1130 c of the compensation thin film transistor T3 , and an emission control semiconductor layer 1130 f of the emission control thin film transistor T6 , which respectively correspond to some regions of the semiconductor layer 1130 , are shown.

[0152] The semiconductor layer 1130 includes a channel region and a source region and a drain region at two opposite sides of the channel region. The source region and the drain region can be understood as the source electrode and the drain electrode of the related thin film transistor. In the following, for the convenience of description, the source region and the drain region are respectively referred to as the source electrode and the drain electrode.

[0153] The driving thin film transistor T1 includes a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 respectively at two opposite sides of the driving channel region C1. The driving channel region C1 overlapping the driving gate electrode G1 can form a long channel length in a narrow space by having a curved shape such as an Ω shape. In the case where the length of the driving channel region C1 is long, the driving range of the gate voltage becomes wide, and thus the grayscale of the light emitted from the organic light emitting diode OLED can be more delicately controlled, and thus the display quality can be improved.

[0154] The switching thin film transistor T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 at two opposite sides of the switching channel region, respectively. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0155] The compensation thin film transistor T3 is a double thin film transistor and may include a compensation gate electrode G3 overlapping two compensation channel regions C3 and may include a compensation source electrode S3 and a compensation drain electrode D3 respectively at two opposite sides of the compensation channel region C3. The compensation thin film transistor T3 may be connected to the driving gate electrode G1 of the driving thin film transistor T1 through a node connection line 1174 to be described below.

[0156] The first initialization thin film transistor T4 is a double thin film transistor and may include a first initialization gate electrode G4 overlapping two first initialization channel regions and may include a first initialization source electrode S4 and a first initialization drain electrode D4 at two opposite sides of the first initialization channel regions, respectively.

[0157] The operation control thin film transistor T5 may include an operation control gate electrode G5 overlapping the operation control channel region and an operation control source electrode S5 and an operation control drain electrode D5 at two opposite sides of the operation control channel region, respectively. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0158] The emission control thin film transistor T6 may include an emission control gate electrode G6 overlapping the emission control channel region and an emission control source electrode S6 and an emission control drain electrode D6 at two opposite sides of the emission control channel region, respectively. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0159] The second initialization thin film transistor T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 at two opposite sides of the second initialization channel region, respectively.

[0160] The above-mentioned thin film transistors may be connected to the track lines SWL, SIL, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0161] Gate insulating layer 2141 (see Figure 7B ) may be disposed on the semiconductor layer 1130. The scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL may be disposed on the gate insulating layer 2141. The gate insulating layer 2141 may include an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride. The scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VL may include a metal such as Mo, Al, Cu, Ti, and an alloy.

[0162] The scan line SWL may extend in the x direction. Some regions of the scan line SWL may correspond to the switch gate electrode G2 and the compensation gate electrode G3, respectively. For example, regions of the scan line SWL that overlap with the channel regions of the switch thin film transistor T2 and the compensation thin film transistor T3 may be the switch gate electrode G2 and the compensation gate electrode G3, respectively.

[0163] The previous scan line SIL may extend in the x direction. Some regions of the previous scan line SIL may correspond to the initialization gate electrodes G4 and G7, respectively. For example, regions of the previous scan line SIL that overlap the channel regions of the initialization thin film transistors T4 and T7 may be the initialization gate electrodes G4 and G7, respectively.

[0164] The emission control line EL may extend in the x direction. Some regions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively. For example, regions of the emission control line EL that overlap the channel regions of the operation control thin film transistor T5 and the emission control thin film transistor T6, respectively, may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0165] The driving gate electrode G1 is a floating electrode and may be connected to the compensation thin film transistor T3 through a node connection line 1174 .

[0166] The initialization voltage line VL may extend in the x direction. The initialization voltage line VL may be connected to the initialization thin film transistors T4 and T7 through an initialization connection line 1173 to be described below.

[0167] Although in Fig. 7A The initialization voltage line VL is described as being disposed on the gate insulating layer 2141, but in another embodiment, the initialization voltage line VL may be disposed on the planarization insulating layer 2180 (see Figure 7B ) and may include the same material as that of the pixel electrode 210.

[0168] The electrode voltage line HL may be provided with a first interlayer insulating layer 2143 (see Figure 7B ), which is disposed above the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1 and the initialization voltage line VL.

[0169] like Fig. 7AAs shown in , the electrode voltage line HL may extend in the x direction and may cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1 and may constitute a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may serve as a first storage capacitor plate Cst1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may serve as a second storage capacitor plate Cst2 of the storage capacitor Cst.

[0170] The electrode voltage line HL and the second storage capacitor plate Cst2 are electrically connected to the driving voltage line PL. Fig. 7A 1150 shows that the electrode voltage line HL is connected to the driving voltage line PL disposed on the electrode voltage line HL through the contact hole 1158. The electrode voltage line HL may have the same voltage level (constant voltage, for example, +5V) as the driving voltage line PL. The electrode voltage line HL may be understood as a lateral driving voltage line.

[0171] Since the driving voltage line PL extends in the y direction and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the x direction different from the y direction, the plurality of driving voltage lines PL and the plurality of electrode voltage lines HL may constitute a mesh structure in the display area DA.

[0172] The data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174 may be formed with a second interlayer insulating layer 2150 (see Figure 7B ) is disposed on the second storage capacitor plate Cst2 and the electrode voltage line HL. The data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174 may include at least one of Al, Cu, Ti, Mo, and TiN, and may include a single layer or multiple layers. In an embodiment, the driving voltage line PL and the data line DL may have a multilayer structure including Ti / Al / Ti.

[0173] The data line DL may extend in the y direction, and may be connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode S2.

[0174] The driving voltage line PL may extend in the y direction and may be connected to the electrode voltage line HL through the contact hole 1158. In addition, the driving voltage line PL may be connected to the operation control thin film transistor T5 through the contact hole 1155. The driving voltage line PL may be connected to the operation control source electrode S5 through the contact hole 1155.

[0175] One end of the initialization connection line 1173 may be connected to the initialization thin film transistors T4 and T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to the initialization voltage line VL through the contact hole 1151 .

[0176] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157 .

[0177] A planarization insulating layer 2180 including an organic insulating material is positioned on the data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174. The pixel electrode 210 is disposed on the planarization insulating layer 2180.

[0178] refer to Figure 7B , the edge of the pixel electrode 210 is covered by the pixel defining layer 2190 on the planarization insulating layer 2180. The central area of ​​the pixel electrode 210 can be exposed through the opening of the pixel defining layer 2190. The pixel electrode 210 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound. In another embodiment, the pixel electrode 210 may further include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and / or indium oxide (In 2 O 3 The intermediate layer 220 is disposed on a portion of the pixel electrode 210 exposed through the opening.

[0179] The intermediate layer 220 includes an emission layer 222 on a portion of the pixel electrode 210 exposed by the opening of the pixel defining layer 2190. The emission layer 222 may include a polymer or a low molecular weight organic material that emits light of a predetermined color. Figure 7B As shown in , the intermediate layer 220 may include a first functional layer 221 below the emission layer 222 and / or a second functional layer 223 on the emission layer 222 .

[0180] The first functional layer 221 may include a single layer or multiple layers. For example, in the case where the first functional layer 221 includes a polymer material, the first functional layer 221 may include a hole transport layer (HTL) having a single layer structure, and may include poly-(3,4)-ethylene-dihydroxythiophene (PEDOT) or polyaniline (PANI). In the case where the first functional layer 221 includes a low molecular weight material, the first functional layer 221 may include a hole injection layer (HIL) and the HTL.

[0181] The second functional layer 223 may be omitted. For example, in the case where the first functional layer 221 and the emission layer 222 include a polymer material, the second functional layer 223 is preferably provided so that the characteristics of the organic light emitting diode OLED are excellent. The second functional layer 223 may be a single layer or a multilayer. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0182] The counter electrode 230 may overlap the pixel electrode 210 with the intermediate layer 220 in between. The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a semi-transparent or transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy. The counter electrode 230 may further include a conductive layer including ITO, IZO, ZnO, or In 2 O 3 layer.

[0183] Although in Figure 7B 2. The display element layer 200 may be shown in FIG. FIG. 3A to FIG. 4C A package member described in one of the covers.

[0184] Figure 8 is a plan view of lines around the opening area OA in the display panel 10 according to the embodiment, Fig.9A and Fig. 9B According to the embodiment Figure 8 A cross-sectional view of the emission control line EL6 taken along the line IX-IX', and Fig.10 is a plan view of at least an emission control line and an emission control driver of a display panel 10 according to an embodiment.

[0185] Although Figure 8 and Fig.10 It is shown that eight pixels are disposed at each of four sides with respect to the opening area OA for convenience of description, but more pixels and more lines may be disposed.

[0186] refer to Figure 8 , the data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8 and DL9 and the driving voltage lines PL0, PL1, PL2, PL3, PL4, PL5, PL6, PL7, PL8 and PL9 may extend substantially in the y direction. Figure 8Portions of the driving voltage lines PL1, PL2, PL3, PL4, PL5, PL6, PL7, and PL8 located above and below the opening area OA among the driving voltage lines PL0, PL1, PL2, PL3, PL4, PL5, PL6, PL7, and PL8 in the circuit may be disconnected around the opening area OA. Portions of the driving voltage lines PL1, PL2, PL3, PL4, PL5, PL6, PL7, and PL8 located above the opening area OA may be connected to the reference Figure 5 The second line 163 is described, and portions of the driving voltage lines PL1 , PL2 , PL3 , PL4 , PL5 , PL6 , PL7 , and PL8 located under the opening area OA may be connected to the first line 162 .

[0187] Each initialization voltage line VL may transmit an initialization voltage to the pixel P and may extend in the x-direction in the display area DA. Portions of the initialization voltage line VL disposed at the left and right sides relative to the opening area OA may be disconnected around the opening area OA. The initialization voltage line VL disconnected around the opening area OA may be connected to the electrode layer VL-R disposed in the first non-display area NDA1 through the second contact hole CNT2. The electrode layer VL-R may have a ring shape surrounding the opening area OA.

[0188] refer to Fig. 7A and Figure 7B , the initialization voltage line VL may be disposed on the first interlayer insulating layer 2143, and the electrode layer VL-R may be disposed on the planarization insulating layer 2180. The electrode layer VL-R may be connected to the initialization voltage line VL through the second contact hole CNT2.

[0189] In the first non-display area NDA1, some of the data lines (e.g., data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, and DL8) may surround the edge of the opening area OA. Each of the data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, and DL8 may be electrically connected to the pixels P disposed above and below the opening area OA, may include a portion extending in the y direction in the display area DA, and may include a portion surrounding the edge of the opening area OA in the first non-display area NDA1. Although Figure 8 The detour portion of the data line DL is shown as an arc curve, but the detour portion may be a line bent in a zigzag shape. Figure 8 The detour portion of each of the remaining lines is shown as an arc curve, but the detour portion may be a line bent in a zigzag shape. In an embodiment, Figure 8At least one of the arc-shaped curves shown in FIG. 1 conforms to an arc of a geometric circle, and in a plan view of the display panel 10 , the geometric circle is concentric with the perimeter of the opening area OA.

[0190] exist Figure 8 In the embodiment, the pixels P located above and below the opening area OA are electrically connected to the data lines DL1, DL2, DL3, DL4, DL5, DL6, DL7, and DL8 arranged around the opening area OA, and can receive data signals through the connected data lines. The data lines DL1, DL2, DL3, and DL4 can be arranged around the opening area OA at a first side (e.g., the left side) of the opening area OA, and the data lines DL5, DL6, DL7, and DL8 can be arranged around the opening area OA at a second side (e.g., the right side) of the opening area OA.

[0191] The scan lines SWL0, SWL1, SWL2, SWL3, SWL4, SWL5, SWL6, SWL7, SWL8, and SWL9 and the previous scan lines SIL0, SIL1, SIL2, SIL3, SIL4, SIL5, SIL6, SIL7, SIL8, and SIL9 may extend substantially in the x direction different from the y direction. Some of the scan lines (e.g., the scan lines SWL1, SWL2, SWL3, SWL4, SWL5, SWL6, SWL7, and SWL8) may be arranged around the opening area OA. In addition, some of the previous scan lines SIL0, SIL1, SIL2, SIL3, SIL4, SIL5, SIL6, SIL7, SIL8, and SIL9 (e.g., the previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5, SIL6, SIL7, and SIL8) may be arranged around the opening area OA. For example, the scan lines SWL1, SWL2, SWL3 and SWL4 and the previous scan lines SIL1, SIL2, SIL3 and SIL4 can be arranged around the opening area OA on a third side (e.g., an upper side) of the opening area OA, and the scan lines SWL5, SWL6, SWL7 and SWL8 and the previous scan lines SIL5, SIL6, SIL7 and SIL8 can be arranged around the opening area OA on a fourth side (e.g., a lower side) of the opening area OA.

[0192] In the display area DA, the scan lines SWL1, SWL2, SWL3, SWL4, SWL5, SWL6, SWL7, and SWL8 and the previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5, SIL6, SIL7, and SIL8 may be located on the gate insulating layer 2141 (refer to Fig. 7A and Figure 7BAs described above, and in the first non-display area NDA1, a line may be formed around the opening area OA on the gate insulating layer 2141.

[0193] The emission control lines EL0, EL1, EL2, EL3, EL4, EL5, EL6, EL7, EL8, and EL9 may extend substantially in the x-direction. Some of the emission control lines (e.g., the emission control lines EL1, EL2, EL3, EL4, EL5, EL6, EL7, and EL8) may be arranged around the opening area OA. For example, the emission control lines EL1, EL2, EL3, and EL4 may be arranged around the opening area OA at the upper side of the opening area OA, and the emission control lines EL5, EL6, EL7, and EL8 may be arranged around the opening area OA at the lower side of the opening area OA.

[0194] In the first non-display area NDA1, the emission control line of one of the two adjacent pixels may be connected to the emission control line of the other pixel. For example, the first emission control line EL1 on the first pixel row that transmits the emission control signal to the pixels P disposed on the left and right sides of the opening area OA of the first pixel row may be connected to the second emission control line EL2 on the second pixel row in the first non-display area NDA1. For example, in the first non-display area NDA1, the first emission control line EL1 may be connected to the detour line EL-C of the second emission control line EL2. If the emission control lines EL1 and EL2 are not connected to each other and have detour lines EL-C respectively, the number of emission control lines passing through the first non-display area NDA1 may be undesirably large. In an embodiment, since the first emission control line EL1 is connected to the detour line EL-C of the second emission control line EL2 in the first non-display area NDA1, in other words, since the first emission control line EL1 and the second emission control line EL2 share the detour line EL-C, the number of detour lines of the emission control lines passing through the first non-display area NDA1 may be advantageously minimized.

[0195] Similarly, the third emission control line EL3 on the third row can be connected to the fourth emission control line EL4 on the fourth row in the first non-display area NDA1, the fifth emission control line EL5 on the fifth row can be connected to the sixth emission control line EL6 on the sixth row in the first non-display area NDA1, and the seventh emission control line EL7 on the seventh row can be connected to the eighth emission control line EL8 on the eighth row in the first non-display area NDA1. In an embodiment, adjacent detour lines can be located on different insulating layers (i.e., directly contact different insulating layers, respectively). For example, the detour line EL-C of the second emission control line EL2 and the detour line EL-C of the fourth emission control line EL4 can be located on different insulating layers.

[0196] The extending portions EL-E and the detour wire EL-C of the emission control lines EL1, EL2, EL3, EL4, EL5, EL6, EL7, and EL8 may be located on different layers. Fig.9A and Fig. 9B Each of shows a cross section of the emission control line taken along line IX-IX' according to an embodiment.

[0197] refer to Fig.9A , the extension portion EL-E of the sixth emission control line EL6 may be located on the gate insulating layer 2141, and the detour line EL-C of the sixth emission control line EL6 may be located on the first interlayer insulating layer 2143. The extension portion EL-E of the sixth emission control line EL6 and the detour line EL-C may be electrically connected to each other through the first contact hole CNT1.

[0198] refer to Fig. 9B , the extension portion EL-E of the sixth emission control line EL6 may be located on the gate insulating layer 2141, and the detour line EL-C of the sixth emission control line EL6 may be located on the planarization insulating layer 2180. The extension portion EL-E of the sixth emission control line EL6 and the detour line EL-C may be electrically connected to each other through the first contact hole CNT1, and the intermediary metal ML may be located between the elements EL-E and EL-C.

[0199] The intermediary metal ML may be located on the second interlayer insulating layer 2150. The intermediary metal ML may be connected to the extension portion EL-E through the contact holes CNT1-1 of the interlayer insulating layers 2143 and 2150, respectively, and the detour line EL-C may be connected to the intermediary metal ML through the contact hole CNT1-2. The intermediary metal ML may include a metal member disposed only in a region corresponding to the first contact hole CNT1, and may include the same material as that of the data line. The detour line EL-C on the planarizing insulating layer 2180 may include a contact hole CNT1-2 that is the same as that of the reference line. Figure 7B The material of the pixel electrode 210 is the same material as described.

[0200] refer to Fig.10 , the emission control drivers ED1 , ED2 , ED3 , and ED4 may be disposed in the second non-display area NDA2 , and may be disposed at two opposite sides of the display area DA.

[0201] The first emission control driver ED1 disposed on the left side of the second non-display area NDA2 simultaneously provides emission control signals to the emission control lines EL1 and EL2, and the emission control signals can be provided to the pixels P disposed on the left and right sides of the opening area OA through the extension portions EL-E and the bypass lines EL-C of the emission control lines EL1 and EL2.

[0202] The emission control signal provided by the first emission control driver ED1 is transmitted as a carry signal to the second emission control driver ED2 disposed on the right side of the second non-display area NDA2. The second emission control driver ED2 simultaneously provides the emission control signal to the emission control lines EL3 and EL4, and the emission control signal can be provided to the pixels P disposed on the left and right sides of the opening area OA through the extension portions EL-E and the bypass lines EL-C of the emission control lines EL3 and EL4.

[0203] The emission control signal transmitted by the second emission control driver ED2 is transmitted as a carry signal to the third emission control driver ED3 disposed on the left side of the second non-display area NDA2. The third emission control driver ED3 simultaneously provides the emission control signal to the emission control lines EL5 and EL6, and the emission control signal can be provided to the pixels P disposed on the left and right sides of the opening area OA through the extension portions EL-E and the bypass lines EL-C of the emission control lines EL5 and EL6.

[0204] The emission control signal transmitted by the third emission control driver ED3 is transmitted as a carry signal to the fourth emission control driver ED4 disposed on the right side of the second non-display area NDA2. The fourth emission control driver ED4 simultaneously provides the emission control signal to the emission control lines EL7 and EL8, and the emission control signal can be provided to the pixels P disposed on the left and right sides of the opening area OA through the extension portions EL-E and the bypass lines EL-C of the emission control lines EL7 and EL8.

[0205] The areas 1A and 3A of the second non-display area NDA2 may be Figure 5 The first external driving circuit 110 corresponds to the first non-display area NDA2, and the areas 2A and 4A of the second non-display area NDA2 may correspond to the first external driving circuit 110 of the second non-display area NDA2. Figure 5 Corresponding to the second external driving circuit 120.

[0206] One emission control line is set on one pixel row. In the embodiment, the first emission control driver ED1 and the second emission control driver ED2 are respectively set in the areas 1A and 2A corresponding to the four pixel rows on the left and right sides of the second non-display area NDA2. The third emission control driver ED3 and the fourth emission control driver ED4 are respectively set in the areas 3A and 4A corresponding to the next four pixel rows on the left and right sides of the second non-display area NDA2.

[0207] This embodiment can minimize the number of emission control drivers. Since the number of emission control drivers is minimized, the space occupied by the emission control drivers can be advantageously minimized. Additional drivers can be further arranged in areas 1A, 2A, 3A, and 4A. Advantageously, the utilization of the non-display area can be optimized.

[0208] Figures 11 to 13 is a plan view of at least an emission control line and an emission control driver of a display panel according to an embodiment. Features different from the above-described features are mainly described.

[0209] refer to Fig.11 , when Fig.10 When compared with the display panel 10 of FIG. 1 , the structures of the emission control lines EL3 and EL4 and the emission control lines EL7 and EL8 are different. Fig.10 In the structure, the extension portion (also referred to as the connection portion) EL-E and the detour line EL-C are not provided on the same layer, and are connected to each other through the first contact hole CNT1 of the insulating layer in between. Fig.11 The emission control lines EL3 and EL4 of this embodiment and the connection portion EL-E and the detour line EL-C of the emission control lines EL7 and EL8 are provided on the same layer. That is, Fig.11 Embodiments may include emission control lines provided on different layers and connected through contact holes, and may include emission control lines provided on the same layer.

[0210] refer to Fig.12 , the connection parts EL-E and the detour lines EL-C of all the emission control lines EL1, EL2, EL3, EL4, EL5, EL6, EL7 and EL8 are formed on the same layer. Since all the emission control lines include the same material and can be formed using the same mask process, the process can be simplified.

[0211] refer to Fig.13 , not formed Fig.10 The detour line EL-C shown in FIG.

[0212] The emission control lines EL1 and EL2 on the left side of the opening area OA are connected to each other, and the emission control lines EL1 and EL2 on the right side of the opening area OA are connected to each other. Since there is no detour line EL-C, the emission control lines EL1 and EL2 on the left side of the opening area OA are electrically isolated from the emission control lines EL1 and EL2 on the right side of the opening area OA. Similarly, the emission control lines EL3 and EL4, the emission control lines EL5 and EL6, and the emission control lines EL7 and EL8 do not include the detour line EL-C connecting the left and right sides of the opening area OA.

[0213] In the present embodiment, since the detour line EL-C is not formed, the display panel may include emission control drivers ED1, ED2, ED3, ED4, ED5, ED6, ED7, and ED8.

[0214] The first emission control driver ED1 disposed on the left side of the second non-display area NDA2 may simultaneously provide a first emission control signal to the emission control lines EL1 and EL2, and the first emission control signal may be provided to the pixel P disposed on the left side of the opening area OA through the extension portion EL-E of the emission control lines EL1 and EL2.

[0215] The first emission control signal output from the first emission control driver ED1 may be transmitted as a carry signal to the third emission control driver ED3 disposed on the left side of the second non-display area NDA2. The third emission control driver ED3 may provide a second emission control signal to the emission control lines EL3 and EL4 at the same time, and the second emission control signal may be provided to the pixel P disposed on the left side of the opening area OA through the extension portion EL-E of the emission control lines EL3 and EL4.

[0216] Likewise, the second emission control signal output from the third emission control driver ED3 may be transmitted as a carry signal to the fifth emission control driver ED5 disposed on the left side of the second non-display area NDA2. The fifth emission control driver ED5 may provide the third emission control signal to the emission control lines EL5 and EL6 at the same time, and the third emission control signal may be provided to the pixel P disposed on the left side of the opening area OA through the extension portion EL-E of the emission control lines EL5 and EL6.

[0217] The third emission control signal output from the fifth emission control driver ED5 may be transmitted as a carry signal to the seventh emission control driver ED7 disposed on the left side of the second non-display area NDA2. The seventh emission control driver ED7 may provide a fourth emission control signal to the emission control lines EL7 and EL8 at the same time, and the fourth emission control signal may be provided to the pixel P disposed on the left side of the opening area OA through the extension portion EL-E of the emission control lines EL7 and EL8.

[0218] The second emission control driver ED2 disposed on the right side of the second non-display area NDA2 may provide the first emission control signal to the emission control lines EL1 and EL2 at the same time, and the first emission control signal may be provided to the pixel P disposed on the right side of the opening area OA through the extension portion EL-E of the emission control lines EL1 and EL2.

[0219] The first emission control signal output from the second emission control driver ED2 may be transmitted as a carry signal to the fourth emission control driver ED4 disposed on the right side of the second non-display area NDA2. The fourth emission control driver ED4 may provide the second emission control signal to the emission control lines EL3 and EL4 at the same time, and the second emission control signal may be provided to the pixel P disposed on the right side of the opening area OA through the extension portion EL-E of the emission control lines EL3 and EL4.

[0220] Likewise, the second emission control signal output from the fourth emission control driver ED4 may be transmitted as a carry signal to the sixth emission control driver ED6 disposed on the right side of the second non-display area NDA2. The sixth emission control driver ED6 may provide the third emission control signal to the emission control lines EL5 and EL6 at the same time, and the third emission control signal may be provided to the pixel P disposed on the right side of the opening area OA through the extension portion EL-E of the emission control lines EL5 and EL6.

[0221] The third emission control signal output from the sixth emission control driver ED6 may be transmitted as a carry signal to the eighth emission control driver ED8 disposed on the right side of the second non-display area NDA2. The eighth emission control driver ED8 may provide the fourth emission control signal to the emission control lines EL7 and EL8 at the same time, and the fourth emission control signal may be provided to the pixel P disposed on the right side of the opening area OA through the extension portion EL-E of the emission control lines EL7 and EL8.

[0222] According to the above-described embodiment, the first non-display area NDA1 may be minimized by minimizing the number of detour lines EL-C around the opening area OA.

[0223] Figures 14 to 17 1 is a plan view of at least a scan line, a previous scan line, and a scan driver of the display panel 10 according to the embodiment. Features different from the above-described features are mainly described.

[0224] refer to Fig.14 , scan drivers SD1, SD2, SD3, SD4, SD5, SD6, SD7, SD8, SD9, SD10, SD11, SD12, SD13, SD14, SD15 and SD16 are disposed in the second non-display area NDA2. The structures of emission control lines EL1, EL2, EL3, EL4, EL5, EL6, EL7 and EL8 are similar to those of Fig.10 The structure of the embodiment is the same. Fig.14 , but an emission control driver configured to provide an emission control signal to the emission control lines EL1, EL2, EL3, EL4, EL5, EL6, EL7, and EL8 may be connected to Fig.10 The emission control drivers ED1, ED2, ED3 and ED4 shown in FIG. 1 are identical.

[0225] exist Fig.10 In an embodiment, each of the scan lines SWL1, SWL2, SWL3, SWL4, SWL5, SWL6, SWL7, and SWL8 and the previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5, SIL6, SIL7, and SIL8 may extend substantially in the x-direction and surround the opening area OA. In an embodiment, the material of the scan line SWL1 may be different from that of the previous scan line SIL1. Fig.14 In the present embodiment, a scanning line and a previous scanning line included in a pixel row are connected to each other, and a bypass line SWL-C connecting the scanning line and the previous scanning line is provided.

[0226] For example, in the first non-display area NDA1, the first previous scan line SIL1 is connected to the bypass line SWL-C of the first scan line SWL1. In other words, the first previous scan line SIL1 and the first scan line SWL1 share the bypass line SWL-C. Similarly, each group in the group ranging from the group including the second previous scan line SIL2 and the second scan line SWL2 to the group including the eighth previous scan line SIL8 and the eighth scan line SWL8 includes only one bypass line SWL-C. In an embodiment, adjacent bypass lines may be located on different insulating layers (i.e., directly contacting different insulating layers, respectively). For example, the bypass line SWL-C of the first scan line SWL1 and the bypass line SWL-C of the second scan line SWL2 may be located on different insulating layers. Advantageously, the first non-display area NDA1 around the opening area OA may be minimized.

[0227] Scan drivers SD1, SD2, SD3, SD4, SD5, SD6, SD7, SD8, SD9, SD10, SD11, SD12, SD13, SD14, SD15 and SD16 are arranged at two opposite sides of the second non-display area NDA2 and in the second non-display area NDA2, and two scan drivers can be connected to a pixel row having pixels located at two opposite sides of the opening area OA.

[0228] For example, the first scan driver SD1 disposed on the left side of the second non-display area NDA2 and the second scan driver SD2 disposed on the right side of the second non-display area NDA2 provide scan signals to the first previous scan line SIL1 and the first scan line SWL1 at the same time. The third scan driver SD3 disposed on the left side of the second non-display area NDA2 and the fourth scan driver SD4 disposed on the right side of the second non-display area NDA2 provide scan signals to the second previous scan line SIL2 and the second scan line SWL2 at the same time. Similarly, the fifteenth scan driver SD15 disposed on the left side of the second non-display area NDA2 and the sixteenth scan driver SD16 disposed on the right side of the second non-display area NDA2 provide scan signals to the eighth previous scan line SIL8 and the eighth scan line SWL8 at the same time. Since the scan signals are provided from the left and right sides of the display area DA at the same time, the scan signal delay can be prevented, and thus the display quality can be improved.

[0229] Four scan drivers are provided in each of the regions 1A, 2A, 3A, and 4A. Since the emission control drivers ED1, ED2, ED3, and ED4 (see FIG. 1 ) provided in each of the regions 1A, 2A, 3A, and 4A Fig.10 ) is small, so a sufficient number of scan drivers can be set in each of the areas 1A, 2A, 3A and 4A.

[0230] The material of a scan line connected in a pair and a previous scan line may be different from the material of an immediately adjacent scan line connected in a pair and a previous scan line.

[0231] refer to Fig.15 , when Fig.14 When compared with the display panel 10 of FIG. 1 , the structure of the scan line is different from that of the previous scan line. Fig.14 In the display panel 10, all of the scanning lines and the previous scanning lines are formed on the same layer. Fig.15 In the display panel 10 of the present embodiment, the first scan line SWL1 and the first previous scan line SIL1 are connected to each other through the detour line SWL-C. The detour line SWL-C of the first scan line SWL1, the connection portion SWL-E, and the connection portion SIL-E of the first previous scan line SIL1 are arranged on different layers with at least an intermediate insulating layer, and are connected through contact holes CNT3 and CNT4.

[0232] refer to Fig.16 , not formed Fig.14 The first non-display area NDA1 may be advantageously minimized by minimizing the number of the detour lines SWL-C around the opening area OA.

[0233] refer to Fig.17, the scan line and the paired previous scan line may be disconnected at the periphery of the first non-display area NDA1 relatively close to the opening area OA. The scan lines SWL1, SWL2, SWL3, SWL4, SWL5, SWL6, SWL7 and SWL8 and the previous scan lines SIL1, SIL2, SIL3, SIL4, SIL5, SIL6, SIL7 and SIL8 that have extended from the left and right parts of the second non-display area NDA2 to the display area DA may not extend into the first non-display area NDA1. By minimizing the number of wirings provided in the first non-display area NDA1, the first non-display area NDA1 may be advantageously minimized.

[0234] According to an embodiment, the area of ​​the non-display area NDA may be minimized by minimizing the number of detour lines for connecting lines in the first non-display area NDA1 around the opening area OA in the display device 1 .

[0235] Although exemplary embodiments have been described with reference to the accompanying drawings, various changes may be made in form and details without departing from the scope defined by the appended claims and equivalents.

Claims

1. A display panel, comprising: A substrate, comprising an opening area, a display area surrounding the opening area, a first non-display area between the opening area and the display area, and a second non-display area outside the display area; a first data line located at a first side relative to the opening area in a plan view of the display panel; The first scan line; The second scan line; a first pixel electrically connected to each of the first data line and the first scan line; a second pixel electrically connected to each of the first data line and the second scan line; a first emission control line electrically connected to the first pixel; a first connecting portion located on the first non-display area; a second emission control line electrically connected to the second pixel and electrically connected to the first emission control line through the first connection portion; as well as The first emission control driver is located on the second non-display area, and only the first emission control driver provides an emission control signal to the first emission control line and the second emission control line at the same time.

2. The display panel according to claim 1, further comprising: a second data line located at a second side relative to the opening area in the plan view of the display panel, wherein the opening area is located between the first data line and the second data line; a third pixel electrically connected to each of the second data line and the first scan line; as well as a fourth pixel electrically connected to each of the second data line and the second scan line, The second emission control line is electrically connected to the fourth pixel and includes a first emission control detour portion, and the first emission control detour portion detours the opening area.

3. The display panel according to claim 2, further comprising: a third data line including a first data bypassing portion, the first data bypassing portion bypassing the opening area and being located on the first non-display area; as well as a fourth data line including a second data bypassing portion, the second data bypassing portion bypassing the opening area and being located on the first non-display area, The first emission control bypass section is arranged between the first data bypass section and the second data bypass section.

4. The display panel according to claim 2, further comprising: A first insulating layer having a first contact hole, wherein the second emission control line further includes a first pixel connection portion, and wherein the first emission control detour portion is connected to the first pixel connection portion through the first contact hole and is electrically connected to the second pixel through the first pixel connection portion.

5. The display panel according to claim 4, further comprising: A second insulating layer having a second contact hole, and wherein the first emission control detour portion is connected to the first pixel connection portion through the second contact hole.

6. The display panel according to claim 2, further comprising: A second emission control bypass portion is immediately adjacent to the first emission control bypass portion, with no intermediate emission control bypass portion located between the first emission control bypass portion and the second emission control bypass portion, wherein the first emission control bypass portion and the second emission control bypass portion directly contact different insulating layers, respectively.

7. The display panel according to claim 2, further comprising: a first insulating layer, wherein the second emission control line further includes a first pixel connection portion, and wherein the first emission control bypass portion is electrically connected to the second pixel through the first pixel connection portion, and wherein the first emission control bypass portion and the first pixel connection portion directly contact the same surface of the first insulating layer.

8. The display panel according to claim 7, wherein: A material of the first emission control bypass portion is the same as a material of the first pixel connection portion.

9. The display panel according to claim 2, further comprising: a first opposing emission control line disposed opposite to the first emission control line and electrically connected to the third pixel; as well as A second emission control driver is located on the second non-display area and is configured to simultaneously provide an emission control signal to the first opposing emission control line and the second emission control line.

10. The display panel according to claim 9, wherein: The first emission control driver is electrically connected to four adjacent emission control lines located at the first side relative to the opening area, and wherein the second emission control driver is electrically connected to four adjacent emission control lines located at the second side relative to the opening area.

11. The display panel according to claim 1, further comprising: a second data line located at a second side relative to the opening area in the plan view of the display panel, wherein the opening area is located between the first data line and the second data line; a third pixel electrically connected to each of the second data line and the first scan line; and A first opposing emission control line is disposed opposite to the first emission control line and is electrically connected to the third pixel, wherein the opening area is located between the first emission control line and the first opposing emission control line.

12. The display panel according to claim 11, further comprising: An insulating layer, wherein the first emission control line and the first opposing emission control line directly contact a same surface of the insulating layer.

13. The display panel according to claim 11, wherein: The material of the first emission control line is the same as that of the first opposing emission control line.

14. The display panel according to claim 11, further comprising: a fourth pixel electrically connected to each of the second data line and the second scan line; a first opposing connection portion disposed opposite to the first connection portion and located on the first non-display area; a second opposing emission control line electrically connected to the fourth pixel and electrically connected to the first opposing emission control line through the first opposing connection portion; as well as A second emission control driver is located on the second non-display area and is configured to simultaneously supply an emission control signal to the first opposing emission control line and the second opposing emission control line.

15. The display panel according to claim 14, wherein: Each of the first connection portion and the first opposing connection portion conforms to an arc of a geometric circle, and wherein in the plan view of the display panel, the geometric circle is concentric with a perimeter of the opening area.

16. The display panel according to claim 1, further comprising: a second data line located at a second side relative to the opening area in the plan view of the display panel, wherein the opening area is located between the first data line and the second data line; a third pixel electrically connected to each of the second data line and the first scan line; a first previous scan line electrically connected to each of the first pixel and the third pixel; and A first scan driver is disposed on the second non-display area and is configured to provide a scan signal to both the first scan line and the first previous scan line, wherein the first scan line is electrically connected to the gate electrode of the first transistor of the first pixel, and wherein the first previous scan line is electrically connected to the gate electrode of the second transistor of the first pixel.

17. The display panel according to claim 16, wherein: The first scan line includes a first scan detour portion, wherein the first scan detour portion detours the opening area, wherein the first previous scan line includes a first previous scan detour portion, and wherein the first previous scan detour portion is spaced apart from the first scan detour portion and detours the opening area.

18. The display panel according to claim 17, wherein: A material of the first scan line is different from a material of the first previous scan line.

19. The display panel according to claim 16, further comprising: A first scan detour portion, wherein the first scan detour portion detours the opening area, and wherein each of the first scan line and the first previous scan line is electrically connected to the first scan detour portion.

20. The display panel according to claim 19, further comprising: a second previous scan line electrically connected to the second pixel; as well as A second scanning bypass portion, wherein the second scanning bypass portion bypasses the opening area, is electrically connected to each of the second scanning line and the second previous scanning line, and is adjacent to the first scanning bypass portion, with no intermediate scanning bypass portion located between the first scanning bypass portion and the second scanning bypass portion, and wherein the first scanning bypass portion and the second scanning bypass portion directly contact different insulating layers, respectively.

21. The display panel according to claim 19, wherein: The first scanning detour portion directly contacts a first insulating layer, and wherein the first scanning line and the first previous scanning line directly contact a second insulating layer different from the first insulating layer.

22. The display panel according to claim 1, further comprising: a second data line located at a second side relative to the opening area in the plan view of the display panel, wherein the opening area is located between the first data line and the second data line; a first opposing scan line disposed opposite to the first scan line, wherein the opening area is located between the first scan line and the first opposing scan line; a third pixel electrically connected to each of the second data line and the first opposing scan line; A first previous scan line electrically connected to the first pixel; and A first opposing previous scan line is disposed opposite to the first previous scan line and is electrically connected to the third pixel, wherein the opening area is located between the first previous scan line and the first opposing previous scan line.

23. The display panel according to claim 22, further comprising: a first scan connection portion located on the first non-display area, wherein the first scan line is electrically connected to the first previous scan line through the first scan connection portion; as well as A first opposing scan connection portion is disposed opposite to the first scan connection portion and located on the first non-display area, wherein the first opposing scan line is electrically connected to the first opposing previous scan line through the first opposing scan connection portion.

24. The display panel according to claim 22, wherein: An end portion of the first scan line and an end portion of the first previous scan line are spaced apart from each other and are not electrically connected to each other, and wherein at least one of the end portion of the first scan line and the end portion of the first previous scan line is located at a boundary of the first non-display area.

25. The display panel according to claim 16, further comprising: A second scan driver located on the second non-display area and configured to provide a scan signal to both the first scan line and the first previous scan line, wherein each of the opening area, the first non-display area and the display area is located between the first scan driver and the second scan driver.

Images