PMOS transistor including a low thermal budget gate stack

Abstract

A p-channel metal oxide semiconductor (pMOS) transistor includes a gate stack, the gate stack including: a dielectric interlayer containing silicon oxide on a substrate, wherein the thickness of the dielectric interlayer is less than 1 nm; a high-k dielectric layer having a higher dielectric constant than the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting the high-k bandgap of the high-k dielectric layer downward relative to the valence band of the substrate, wherein the thickness of the first dipole-forming capping layer is less than 2 nm; and at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and high reliability without the use of reliability annealing, which makes the pMOS transistor suitable for use as a back-end-of-line (BEOL) device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims foreign priority from European application number EP 18209442.5 filed on November 30, 2018, the entire contents of which are incorporated herein by reference. Background Art Technical Field

[0003] The disclosed technology generally relates to metal oxide field effect transistors, and more particularly to low thermal budget gate stack designs with negative bias temperature instabilities small enough for reliable device operation at ultra-thin effective oxide thicknesses.

[0004] Related technical notes

[0005] There are many different architectures for metal oxide semiconductor field effect (MOSFET) transistors. The gate first integration initially includes the deposition of high-k material and metal gate to form a gate stack. The integration also includes depositing source and drain after forming the high-k material and metal gate. In this process, the gate stack including the high-k material and metal gate is subjected to a source / drain (S / D) activation anneal. The source / drain (S / D) activation anneal can be performed at about 1100°C and for metal work function (i.e., threshold voltage (V 阈 (V th ))Control) may be harmful.

[0006] SUMMARY OF CERTAIN INVENTIVE ASPECTS

[0007] One object of the disclosed embodiments is to provide a reliable pMOS gate stack and a method for producing the same. Another object of the disclosed embodiments is to provide a reliable CMOS device and a method for producing the same.

[0008] The above objects are achieved by the method and device according to the present disclosure. As described herein, a gate stack refers to a gate dielectric formed above a channel (stacked) and a gate electrode formed above the gate dielectric (stacked) for influencing the channel.

[0009] In a first aspect, embodiments of the present disclosure relate to a p-channel metal oxide semiconductor transistor including a gate stack. The gate stack includes: a dielectric interlayer containing silicon oxide on a substrate, wherein the thickness of the dielectric interlayer is less than 1 nm; a high-k dielectric layer having a higher dielectric constant than the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting the high-k bandgap of the high-k dielectric layer downward relative to the valence band of the substrate, wherein the thickness of the first dipole-forming capping layer is less than 2 nm; and at least one work function metal above the high-k dielectric layer.

[0010] Direct contact includes direct physical contact so no other layers exist between the first dipole-forming capping layer and the dielectric layer.

[0011] Advantageously, reliability is improved by introducing a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer for shifting the high-k bandgap of the high-k dielectric layer downwards relative to the valence band of the substrate. This improves reliability as the dielectric interlayer thickness is less than 1 nm, thus traps in the (thicker) high-k dielectric layer affect device reliability compared to traps in the (thinner) dielectric interlayer. The thickness of the high-k dielectric layer may be, for example, greater than 1 nm, or even greater than 1.5 nm, or even up to 3 nm, for example 2 nm.

[0012] Further advantageously, negative BTI (NBTI) reliability of p-channel metal oxide semiconductor (pMOS) transistors can be achieved in a lower thermal budget process flow without the need for high temperature "reliability anneals" that are incompatible with certain CMOS integrations (e.g., sequential three-dimensional (3D) stacking of transistor tiers). The improvement can be attributed to the formation of interface dipoles that shift the energy level of high-k traps relative to the silicon (Si) valence band.

[0013] In some embodiments, the thickness of the dipole-forming capping layer (DIP) is less than 1 nm. Above this thickness, the dipole effect may not increase even if the thickness continues to increase.

[0014] In some embodiments, the substrate can be a silicon substrate, a silicon germanium (SiGe) substrate, a germanium (Ge) substrate, or a III-V compound substrate (e.g., indium gallium arsenide (InGaAs), indium arsenide (InAs), gallium arsenide (GaAs), gallium antimonide (GaSb), indium phosphide (InP), gallium nitride (GaN)).

[0015] In some embodiments, the dielectric layer is a silicon dioxide (SiO 2 ) layer or a silicon oxynitride (SiON) layer.

[0016] The dielectric layer may be a silicon oxide (SiOx) layer that is substantially stoichiometric (ie, x is approximately equal to 2), and not necessarily completely stoichiometric (ie, some unit cells may not have an exact ratio of 2 oxygen atoms per Si atom).

[0017] In some embodiments, the SiO 2 interlayer can be doped with nitrogen (eg, to make it a better diffusion barrier to prevent dopant atoms from diffusing away from the substrate).

[0018] In some embodiments, the first dipole-forming capping layer is an Al2O3 layer.

[0019] In some embodiments, the high-k dielectric layer is a HfO 2 layer.

[0020] In some embodiments, a device may include a complementary metal oxide semiconductor device including a pMOS transistor and an n-channel metal oxide semiconductor (nMOS) transistor according to embodiments of the present disclosure.

[0021] According to some embodiments of the present disclosure, a metal oxide semiconductor device may include an nMOS transistor gate stack, wherein the nMOS transistor includes a gate stack on an active region in a substrate, wherein the gate stack of the nMOS transistor includes a second dipole-forming capping layer between an interface dielectric layer and a high-k dielectric layer having a high-k bandgap, wherein the second dipole-forming capping layer is suitable for shifting the high-k bandgap upward relative to a conduction band of the substrate.

[0022] Advantageously, by shifting the high-k bandgap upward relative to the conduction band of the substrate, the energy barrier for capturing electrons from the semiconductor channel can be increased.

[0023] In some embodiments, the second dipole-forming capping layer is a transition metal oxide layer or a transition metal silicate layer.

[0024] The second dipole-forming capping layer may include lanthanum oxide (La x O z ), wherein x and z are each greater than 0, or it may contain lanthanum silicon oxide (La x Si y O z ), where x, y, and z are each greater than 0.

[0025] In some embodiments, the second dipole-forming capping layer of the nMOS transistor is La x Si y O z(and x and z are greater than 0, and y is greater than or equal to 0, for example La2O3), and the interface dielectric layer of the nMOS transistor is SiO2, and the high-k dielectric layer of the nMOS transistor is HfO2, and the dielectric intermediate layer of the pMOS transistor is SiO2, and the high-k dielectric layer of the pMOS transistor is HfO2, and the first dipole-forming capping layer of the pMOS transistor is Al2O3.

[0026] Embodiments of the present disclosure may relate to a semiconductor device comprising a three-dimensional stack of transistors, the stack comprising a pMOS transistor according to some embodiments of the present invention in a first layer, or a CMOS device according to some embodiments of the present invention, stacked on one or more transistors in a second layer.

[0027] In some implementations, the pMOS transistor or CMOS device can be implemented in a back-end-of-line (BEOL) process.

[0028] Semiconductor devices according to some embodiments of the present invention may include a memory array and a pMOS transistor or a CMOS device according to embodiments of the present invention, wherein the pMOS transistor and / or the CMOS device is deposited on top of the memory array.

[0029] In another aspect of the present disclosure, a method for forming a gate stack of a p-channel metal oxide semiconductor transistor is provided. The method comprises: forming a dielectric interlayer containing silicon oxide with a thickness of less than 1 nm on a substrate; depositing a first dipole-forming capping layer directly in contact with the dielectric interlayer and with a thickness of less than 2 nm; depositing a high-k dielectric layer having a high-k band gap on the first dipole-forming capping layer, wherein the first dipole-forming capping layer is adapted to shift the high-k band gap downward relative to the valence band of the substrate; and depositing one or more work function metals above the high-k dielectric layer.

[0030] Advantageously, a functionally reliable pMOS gate stack can be obtained according to a number of embodiments without the need for a high temperature reliability anneal after the gate stack is deposited. Because reliability is improved by forming a capping layer with a first dipole having a thickness of less than 2 nm and between the dielectric interlayer and the high-k dielectric layer, a post-deposition high temperature reliability annealing step can be omitted. Therefore, the method according to some embodiments of the present disclosure is compatible with certain CMOS integrations. Therefore, according to some embodiments, a method of manufacturing a semiconductor device includes completing the manufacturing without subjecting the pMOS gate stack to a temperature greater than 800°C.

[0031] In some embodiments, the method can be implemented as part of a high-k dielectric post-replacement metal gate process, wherein after completely removing the dummy gate stack, a method (i.e., forming a dielectric layer, depositing a first dipole to form a capping layer, and depositing a high-k dielectric layer) can be used to replace the dummy gate with a pMOS gate stack according to some embodiments of the present disclosure. After the pMOS gate stack is used, one or more workfunction setting metals can be deposited. Advantageously, neither the gate dielectric nor the workfunction setting metal is exposed to a high temperature reliability annealing step.

[0032] Some embodiments of the present disclosure provide a method for forming a complementary metal oxide semiconductor device, the method comprising: providing an nMOS gate stack, and forming a pMOS gate stack using the method steps of the disclosed method.

[0033] In some embodiments, a method for forming a CMOS device includes: providing an nMOS gate stack and a pMOS gate stack using similar steps for forming a pMOS stack to also form an nMOS stack. These steps may include: forming a dielectric interlayer for the nMOS gate stack having a thickness of less than 1 nm on a semiconductor substrate, while also forming a dielectric interlayer for the pMOS gate stack, depositing a second dipole-forming capping layer on the dielectric interlayer for the nMOS gate stack and on the first dipole-forming capping layer for the pMOS gate stack, and at the same time, depositing a high-k dielectric layer for the pMOS transistor gate stack, wherein the second dipole-forming capping layer is suitable for shifting the high-k band gap upward relative to the conduction band of the semiconductor substrate, and depositing one or more work function metals.

[0034] In some embodiments, the first dipole-forming capping layer may be prevented from forming on the dielectric interlayer of the nMOS transistor gate stack. Advantageously, in a pMOS transistor gate stack, a second dipole-forming capping layer may be provided on the first dipole-forming capping layer without significantly reducing the reliability of the pMOS transistor gate stack.

[0035] Some embodiments of the present disclosure may be directed to a method for providing a three-dimensional transistor stack, the method comprising: forming a pMOS transistor gate stack in a plurality of layers to form a three-dimensional transistor stack. The pMOS transistor gate stack may be formed using the method steps according to some embodiments of the present invention.

[0036] The method according to some embodiments of the present disclosure may be used to form a pMOS transistor gate stack to be integrated in the BEOL. The method according to some embodiments of the present disclosure may also be used to form a pMOS transistor gate stack on top of a memory layer.

[0037] Specific aspects of the present disclosure are set out in the accompanying independent claims and dependent claims. Features in dependent claims can be appropriately combined with features in independent claims and features in other dependent claims, and are not limited to the situations explicitly described in the claims.

[0038] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 shows the threshold voltage instability of the gate stack before and after reliability annealing.

[0040] FIG. 2 shows two graphs showing the threshold voltage variation of nMOS and pMOS gate stacks with and without reliability annealing compared to an exemplary threshold voltage of a typical device.

[0041] FIG. 3 shows the energy levels of an exemplary nMOS transistor gate stack before and after insertion of a dipole layer.

[0042] FIG. 4 shows the energy levels of an exemplary pMOS transistor gate stack.

[0043] FIG. 5 is a graph in which a curve shows the dipole construction result of nMOS PBTI.

[0044] FIG. 6 is a graph in which a curve shows the dipole construction result of a pMOS NBTI with a 1 nm dielectric interlayer thickness.

[0045] Figure 7 is a graph in which a graph shows pMOS transistor NBTI results for an exemplary pMOS transistor gate stack according to some embodiments of the present disclosure.

[0046] Figure 8 A schematic diagram of an exemplary pMOS transistor gate stack according to some embodiments of the present disclosure is shown.

[0047] Fig. 9 Energy levels of an exemplary pMOS transistor gate stack according to some embodiments of the present disclosure are shown compared to energy levels of another exemplary pMOS transistor gate stack.

[0048] Fig.10 is a graph showing the effect of the first dipole-forming layer on the reliability of an exemplary pMOS gate stack with respect to different thicknesses of the dielectric interlayer.

[0049] Fig.11 and Fig.12Shown is the effect of hole traps in Al2O3 capping on pMOS N BTI compared to the effect of hole traps in HfO2 capping.

[0050] Fig.13 The gate leakage current density when the thickness of the dielectric interlayer in the pMOS transistor gate stack is increased according to some embodiments of the present disclosure is shown compared to the gate leakage current density of an exemplary pMOS transistor gate stack after reliability annealing.

[0051] Fig.14 A graph illustrating the reliability of a pMOS transistor gate stack according to some embodiments of the present disclosure after reliability annealing is shown.

[0052] Fig.15 A graph showing the flat band voltage of a pMOS transistor gate stack according to some embodiments of the present disclosure before and after reliability annealing.

[0053] Fig.16 A schematic diagram of a CMOS device is shown, which includes a pMOS transistor gate stack and an nMOS transistor gate stack according to some embodiments of the present disclosure.

[0054] Fig.17 A graph illustrating the reliability of a pMOS transistor gate stack according to some embodiments of the present disclosure after introducing a second dipole-forming capping layer is shown.

[0055] Fig.18 is a graph showing the effect of inserting a second dipole-forming capping layer into a gate stack of a pMOS transistor according to some embodiments of the present disclosure on its flat-band voltage.

[0056] Fig.19 The dipole offset in a pMOS transistor gate stack is shown as a function of the nominal Al2O3 thickness according to some embodiments of the present disclosure.

[0057] Fig. 20 A schematic diagram of a CMOS device is shown, which includes a pMOS transistor gate stack and an nMOS transistor gate stack according to some embodiments of the present disclosure, but shows that the reliability of the nMOS transistor gate stack is reduced compared to the nMOS transistor gate stack with a second dipole-forming capping layer.

[0058] Fig.21 is a graph showing the reliability of an nMOS transistor gate stack after introducing a first dipole-forming capping layer on a second dipole-forming capping layer.

[0059] Fig. 22is a graph showing the effect of inserting a first dipole-forming capping layer on top of a second dipole-forming capping layer in an nMOS transistor gate stack on its flat-band voltage.

[0060] Fig.23 Showing the D of HfO2 at low and high temperatures ot And the D of Al2O3 at low temperature ot .

[0061] Fig.24 A schematic diagram showing a three-dimensional stack of transistors, wherein the three-dimensional stack of transistors includes a pMOS transistor according to some embodiments of the present disclosure.

[0062] Fig.25 A flow chart showing a method according to some embodiments of the present disclosure.

[0063] Any reference signs in the claims should not be construed as limiting the scope of the present invention.

[0064] In different drawings, the same reference signs identify the same or similar elements.

[0065] DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

[0066] Replacement metal gate (RMG) integration, also known as gate-last integration, is a MOSFET process architecture in which the gate stack is formed after the source and drain are formed, thereby forming a high-k material and a metal gate after an S / D activation anneal. In RMG, negative bias temperature instability (NBTI) has been observed in p-channel metal oxide semiconductor (pMOS) transistors, which can be attributed to the presence of hole traps in native silicon dioxide. An additional anneal can be performed after the gate stack is deposited to mitigate the effects of NBTI. This anneal is called a reliability anneal (also known as a post-deposition anneal or a post-metal anneal). The reliability anneal can be performed at the temperature of the first S / D activation anneal, but is typically performed at a temperature above 800°C. In RMG, a reliability anneal can be performed to improve the functionality and reliability of the gate stack by curing dielectric defects. Figure 1 shows exemplary threshold voltage instabilities (ΔV 阈 ). As can be seen from the reduction in threshold voltage instability, reliability can be improved by performing a reliability anneal. In the example shown in Figure 1, the reliability anneal is a rapid anneal step performed at 900°C for about 1 second. Using a rapid anneal step can mitigate NBTI, which can improve pMOS reliability. However, a rapid anneal step may make the RGB architecture unsuitable for top devices in stacked CMOS technology because the high temperature may be detrimental to the back end of line (BEOL) or bottom devices.

[0067] It has been found that MOSFETs used in CMOS technology may exhibit undesirable bias temperature instability (BTI) of their electrical characteristics based on defects present in the gate dielectric stack, which can trap / release channel carriers and affect device electrostatics, which may lead to performance degradation.

[0068] During device construction / manufacturing, BTI mitigation schemes can be employed since excessive device instability may lead to circuit failure at the product level. Similar to pMOS transistors, n-channel MOS (nMOS) transistors exhibit positive BTI (PBTI), which can be attributed to electron traps in high-k dielectrics (e.g., HfO2). As oxide thickness scales, the oxide electric field (E ox ) increases, BTI may increase. BTI mitigation can include:

[0069] 1) Limit the scaling of the SiO2 interfacial layer (IL) to slow down E ox ; and especially

[0070] 2) After dielectric deposition (even in replacement gate process flows), a rapid thermal anneal (called a “reliability anneal” at temperatures above 800°C for 1-2 seconds) is employed to minimize oxide defect density. Thermal budget limitations in certain technologies (e.g., sequential 3D integration where multiple semiconductor device layers are stacked on top of each other; Ge / III-V channel MOS technologies, etc.) may prevent the use of high temperature reliability anneals.

[0071] For nMOS PBTI, depositing the intermediate layer using atomic layer deposition (ALD) that forms a dipole between SiO2 and HfO2 can make the defect levels in HfO2 energetically unfavorable for trapping channel electrons (e.g., see U.S. Patent Application Publication 2017 / 0162686, entitled “Field Effect Transistor Containing Germanium and Method of Fabrication Thereof”). pMOS transistors with gate stacks having a high thermal budget may be advantageous.

[0072] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the invention is not limited thereto, only by the claims. The drawings described are illustrative only and non-limiting. In the drawings, the size of some elements may be exaggerated and not drawn to scale for illustrative purposes. The sizes and relative sizes do not necessarily correspond to actual reductions in practicing the disclosed technology.

[0073] The terms first, second, etc. in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a sequence in time, space, hierarchy, or any other manner. It should be understood that the terms used in this manner are interchangeable where appropriate, and the embodiments of the present invention are capable of operating in other sequences than those described or illustrated herein.

[0074] Furthermore, in the specification and claims, the terms top, bottom, etc. are used for descriptive purposes and not necessarily for describing relative positions. It is understood that the terms so used are interchangeable where appropriate, and that the embodiments of the technology described herein are capable of operating in other orientations than those described or illustrated herein.

[0075] The term "comprising" as used in the claims should not be understood as being limited to the means listed hereinafter, and it does not exclude other elements or steps. Therefore, it should be understood as indicating the presence of the features, integers, steps or components, but this does not exclude the presence or addition of one or more other features, integers, steps or components or combinations thereof. Therefore, the scope of the expression "a device comprising components A and B" should not be limited to the device consisting only of components A and B. It means that for the present invention, the relevant components of the device are only A and B.

[0076] References to "one embodiment" or "an embodiment" in the specification mean that the specific features, structures, or characteristics described in relation to the embodiment are included in at least one embodiment of the technology disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in the specification do not necessarily all refer to the same embodiment, but may all refer to the same embodiment. In addition, it will be apparent to one of ordinary skill in the art that specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0077] Similarly, it should be understood that in the description of exemplary embodiments of the disclosed technology, different features of the disclosed technology are sometimes combined into a single embodiment, feature, or description thereof, in order to simplify the disclosure and aid in understanding one or more different aspects of the invention. However, this method of disclosure should not be understood to reflect an intention that the claimed technology requires more features than are expressly cited in the claims. And, as reflected in the appended claims, the disclosed aspects may include fewer features than all of the features of a single embodiment of the preceding disclosure. Therefore, the claims that follow the detailed description will be expressly incorporated into the detailed description, and each claim is itself a separate embodiment of the disclosure.

[0078] In addition, when some embodiments described herein include some but not other features included in other embodiments, the combination of features of different embodiments should be intended to be included in the scope of this disclosure and form different embodiments, which should be understood by those skilled in the art. For example, in the claims below, any embodiment claimed for protection can be used in any combination.

[0079] Numerous specific details are set forth in the description herein. However, it should be understood that the embodiments of the disclosed technology may be implemented without these specific details. In other cases, well-known methods, procedures, and techniques are not described in detail in order not to obscure the understanding of this specification.

[0080] High-k dielectrics are understood to refer to dielectrics with a higher dielectric constant than SiO 2. The dielectric constant of a high-k dielectric may be, for example, 10 to 50. An exemplary high-k dielectric material that may be used as a gate dielectric is a Hf-based material, such as HfO 2, which has a k value of about 25.

[0081] The graphs in FIG. 2 show, for example, improvements in reliability of pMOS and nMOS transistors including gate stacks. In these graphs, the improvement in BTI can be attributed to high temperature annealing. The graph on the left shows the nMOS transistor threshold voltage V 阈 The right graph shows the stability of the pMOS transistor threshold voltage V 阈 Ideally, the threshold voltage should be stable when a given operating voltage is applied.

[0082] Curve A (whose measurement points are marked with “+” signs) shows the threshold voltage instability (V 阈 Curve B (marked with a circle) shows the V of the nMOS transistor and the pMOS transistor when no high temperature reliability annealing is performed. 阈 Curve C (indicated by an “x” symbol) shows the threshold voltage instability (V 阈 ). The large asterisk shows the available V that can provide sufficient stability and reliability. 阈 As can be seen from these graphs, the reliability of both the pMOS transistor and the nMOS transistor including the gate stack can be improved by performing a high temperature reliability anneal. However, it has been found that the gap between curves B and C for the pMOS transistor can be closed without performing a high temperature reliability anneal.

[0083] In addition, in nMOS transistors, BTI can be mitigated by providing a gate stack, where the schematic diagram in FIG3 shows the energy levels. This scheme is also proposed in US20170162686. The left figure shows a gate stack including a Si substrate, a SiO2 layer, and a HfO2 layer. The right figure shows a gate stack including a Si substrate, a SiO2 layer, a LaSiO x The schematic diagram in Figure 3 shows how the gate stack of the dipole layer and HfO2 layer is formed by introducing LaSiO x The dipole-forming layer deflects the traps in the high-k dielectric material.

[0084] Without being bound by any theory, for nMOS transistors, PBTI may be mainly attributed to electron traps in high-k dielectric materials, and for pMOS transistors, NBTI may be mainly attributed to traps in SiO2 near the semiconductor interface. For pMOS transistors, hole traps in high-k dielectric materials still lead to NBTI, but NBTI is controlled by traps in SiO2 near the semiconductor interface. The energy bands of a pMOS transistor are schematically shown in FIG4, which shows hole traps in SiO2 of a gate stack including a Si substrate, a SiO2 layer, and a HfO2 layer. When comparing the energy bands of FIG3 and FIG4, it can be seen that the dipole at the SiO2 / HfO2 interface is mainly related to improving PBTI reliability by "shifting" the electron trap energy levels in the high-k dielectric material upward, and this strategy is in principle irrelevant to pMOS transistor NBTI. In pMOS transistors, the main problem comes from hole traps in the SiO2 dielectric interlayer (IL), and the dipole is expected to have less impact on NBTI. A person of ordinary skill in the art will not realize that the scheme used for nMOS transistors may not be effective for pMOS. Even though the energy levels are offset in the high-k dielectric material, traps will still exist in the native SiO2 layer.

[0085] This is confirmed by the simulations shown in the graphs of Figures 5 and 6. These figures show simulations of the effect of SiO2 IL thickness on reliability improvement by dipole construction for nMOS transistor PBTI and pMOS transistor NBTI, respectively. In both simulations, the SiO2 IL thickness is 1 nm and the thickness of the high-k dielectric layer (HfO2) is 2 nm. In both figures, the solid line shows the reliability of a gate stack containing traps in both the dielectric interlayer (SiO2) and the high-k dielectric layer (HfO2). The dashed line shows a gate stack containing traps only in the high-k dielectric layer (HfO2). The dot-dash line shows a gate stack containing traps only in the dielectric interlayer (SiO2).

[0086] In FIG5 , a graph is shown showing the results of the dipole construction of the PBTI of an nMOS transistor. Curve A (solid and dashed lines) is a reference curve for a low thermal budget stack (in this example, the temperature is kept below 500° C.). Curve B (solid and dashed lines) simulates the curve for a gate stack containing a 0.2 eV dipole offset. Curve C (solid and dashed lines) simulates the curve for a gate stack containing a 0.4 eV dipole offset. As can be seen from the solid lines in this figure, the threshold voltage instability (V) can be reduced by introducing a dipole layer without using a high thermal budget. 阈 ). For the solid line (stack with traps in the dielectric layer SiO2) and for the dashed line (stack without traps in SiO2), there is an effect on the threshold voltage shift. Thus, for nMOS transistor PBTI, the improvement seems to be insensitive to IL thickness. Since the electron traps are mainly located in the high-k dielectric material, the interface dipoles have a direct benefit.

[0087] The curves in FIG6 show the dipole construction results of the pMOS transistor NBTI of a stack with a dielectric interlayer (SiO2) thickness of 1 nm. In FIG6 , curve (A) (including solid and dashed lines) is a reference curve for a low thermal budget stack. Curve (B) (including solid and dashed lines) is a simulation curve for a gate stack including a 0.1 eV dipole offset; curve (C) (including solid and dashed lines) is a curve for a gate stack including a 0.2 eV dipole offset; curve (D) (including solid and dashed lines) is a curve for a gate stack including a 0.4 eV dipole offset. As can be seen from FIG6 , when a dipole layer is introduced into the pMOS gate stack, the improvement in reliability is minimal. It has been found that for a SiO2 IL with a thickness of 1 nm or more, hole capture in SiO2 is the main contributor to the NBTI of the pMOS transistor. Therefore, for a dielectric IL with a thickness of about 1 nm or more, the improvement of introducing a dipole layer is minimal.

[0088] It has been found that by scaling the SiO2 IL to a few monolayers (<1nm), the total number of traps in the SiO2 can be reduced to a level that does not affect reliability. When the number of traps in the SiO2 is reduced by reducing the thickness of the IL, the traps in the high-k dielectric dominate. As discussed earlier, a dipole layer can be used to mitigate the effects of traps in the high-k dielectric. Therefore, when the thickness of the dielectric IL is less than 1nm, a significant improvement in reliability can be achieved by introducing a dipole-forming capping layer.

[0089] Compared with the graph in Figure 6, Figure 7 The graph in shows the effect of SiO2 IL thickness on reliability improvement through dipole construction. Figure 7In the figure, curve A (including solid and dashed lines) is a reference curve for a low thermal budget stack. Curve B (including solid and dashed lines) is a simulation curve for a gate stack including a 0.1 eV dipole offset; curve C (including solid and dashed lines) is a simulation curve for a gate stack including a 0.2 eV dipole offset; and curve D (including solid and dashed lines) is a simulation curve for a gate stack including a 0.4 eV dipole offset. Figure 7 The graphs in show the results from a pMOS transistor gate stack with a SiO2 IL layer thickness of 0.6nm. From these graphs, it can be seen that if the SiO2 IL is scaled sufficiently (i.e., below 1nm), the pMOS NBTI can be improved by dipole construction, unlike when the SiO2 IL thickness is 1nm or greater as shown in Figure 6.

[0090] Figure 8 An embodiment of the first aspect of the present disclosure is shown, including: a p-channel metal oxide semiconductor transistor having a gate stack 100. The gate stack includes a dielectric interlayer 120 containing silicon oxide on a substrate 110. The thickness of the dielectric interlayer 120 may be less than 1 nm. The gate stack also includes a high-k dielectric layer 140 having a higher dielectric constant than the dielectric interlayer 120. The gate stack also includes: a first dipole-forming capping layer 130 between the dielectric interlayer 120 and the high-k dielectric layer 140 and in direct contact with the dielectric interlayer 120, for shifting the band gap of the high-k dielectric layer downward relative to the valence band of the substrate 110, wherein the first dipole-forming capping layer 130 is in physical contact with the dielectric interlayer and has a thickness of less than 1 nm. The gate stack also includes: at least one work function metal 150 above the high-k dielectric layer.

[0091] The dipole is formed by depositing a dipole-forming capping layer (e.g., Al2O3) on a dielectric interlayer (e.g., SiO2) and in direct contact with the dielectric interlayer. It has been found that in some cases, a pMOS transistor gate stack including a high-k dielectric layer on top of the dipole-forming capping layer and on top of the dielectric interlayer improves the pMOS transistor NBTI reliability compared to a stack without the dipole-forming capping layer. For example, a thinner dielectric interlayer (e.g., SiO2 IL) can cause the NBTI reliability to be primarily affected by traps in the high-k dielectric layer, which has been found to occur when the thickness of the SiO2 IL is below 1 nm.

[0092] In some embodiments, the substrate 110 may be a silicon substrate, the dielectric layer may be a SiO2 layer, the first dipole-forming capping layer 130 may be an Al2O3 layer, and the high-k dielectric layer may be a HfO2 layer. In some embodiments, the substrate 110 may be a germanium substrate, a silicon germanium substrate, or a III-V compound substrate, and the precursor is to deposit a SiO2 IL on the substrate. The SiO2 IL may be deposited, for example, using ALD. For all of these embodiments, the Al2O3 layer may be in direct contact with the SiO2 IL, which may be a dipole-forming capping layer.

[0093] Advantageously, the pMOS gate stack can be manufactured without relying on high temperature reliability annealing (i.e., at low process thermal budgets, compatible with novel technologies) and still have adequate pMOS transistor NBTI reliability. Furthermore, the pMOS transistor gate stack can enable further scaling of SiO2 and EOT with standard Si technology, which is currently limited by reliability issues, thereby enabling further improvements in CMOS performance. Therefore, the size of the SiO2 IL (currently limited by reliability issues) can be further scaled, thereby enabling further performance improvements in CMOS technology.

[0094] In some embodiments, the dielectric interlayer has a thickness of less than 1 nm. In some embodiments, the dielectric interlayer has a thickness of less than 0.8 nm. In some embodiments, the dielectric interlayer has a thickness of about 0.6 nm. For example, the dielectric interlayer can be SiO2 IL.

[0095] The thickness of the dipole-forming capping layer may be less than 1.2 nm, less than 1 nm, or less than 0.5 nm. In some embodiments, the thickness is greater than 0.2 nm. In some embodiments, the thickness may be 0.2 nm to 0.5 nm. When the thickness of the dipole-forming capping layer is about 0.2 nm, a strong dipole effect may be obtained so that the reliability of the obtained pMOS transistor gate stack may be improved.

[0096] In some embodiments, an Al2O3 interlayer can be added to the standard SiO2 / HfO2 dielectric stack. This can improve the EOT. However, the reliability improvement significantly outweighs the EOT increase, i.e., the maximum operating oxide electric field can be greatly improved. Therefore, the EOT increase can be mitigated by scaling the SiO2 thickness. Assuming that the dielectric constant of Al2O3 is higher than that of SiO2, a reduction in SiO2 thickness of ~0.2nm can compensate for the EOT increase including the Al2O3 layer.

[0097] Still see Figure 8In some embodiments, the dielectric interlayer 120 containing silicon, the first dipole forming capping layer 130 and the high-k dielectric layer 140 can be part of the gate dielectric stack. At least one work function metal 150 can be part of the gate electrode stack. It should be understood that in some RMG processes, a sacrificial gate electrode can be first formed above the high-k dielectric layer, and then the sacrificial gate electrode can be replaced by at least one work function metal. For example, the sacrificial gate electrode can be a polysilicon layer. However, in some RMG processes, the sacrificial gate electrode can be completely removed. Thus, in some embodiments, the gate stack 100 can be formed using an RMG process, whereby, in the final device, at least the pMOS gate stack may not include a silicon layer, such as a polysilicon layer. For example, the pMOS gate stack may include a gate electrode stack and a gate dielectric stack deposited on a substrate. In some embodiments, the gate electrode stack may consist only of the work function metal 150 and may not contain polysilicon. It will be appreciated that a gate electrode that does not include polysilicon may be advantageous for various reasons, including, for example, threshold voltage adjustment using work function adjustment, threshold voltage reduction, and / or enabling the omission of high temperature dopant activation in polysilicon. For example, when a pMOS is formed as part of a back-end process of a semiconductor device (e.g., see Fig.24 and related text), it is advantageous that a gate stack that does not include polysilicon can be formed without activating dopants in the polysilicon. Fig. 9 Energy levels of a pMOS gate stack according to some embodiments of the present disclosure (right diagram) and a comparative example pMOS transistor gate stack (left diagram) are shown.

[0098] In both cases, the pMOS transistor gate stack includes: a dielectric interlayer 120 containing silicon oxide on a substrate; a first dipole-forming (p-dipole) capping layer 130 having a thickness of less than 1 nm, which is used to shift the energy levels of high-k traps in a high-k dielectric layer 140 on top of the first dipole-forming capping layer 130. The thickness of the dielectric interlayer of the device in the left figure is less than 1 nm, while the thickness of the dielectric interlayer of the device in the right figure is greater than 1 nm.

[0099] By introducing the first dipole forming layer 130 between the dielectric interlayer 120 and the high-k dielectric layer 140, and by scaling the dielectric interlayer 120 to a thickness below 1 nm, the NBTI reliability of a standard high thermal budget process can be matched with minimal EOT increase. Reliability is maintained when scaling the dielectric interlayer 120 to compensate for the EOT increase. This is shown in Fig.10 middle.

[0100] As discussed previously, the reduced scaling of the dielectric interlayer 120 allows high-k traps within the high-k dielectric layer to dominate over traps within the dielectric interlayer, thereby improving pMOS transistor NBTI.

[0101] like Fig.10 As shown in the graph in , the high-k bandgap downward shift is less effective when the SiO2 IL has a thickness of 1 nm or more. The figure shows experimental data for a pMOS transistor gate stack according to an embodiment of the present disclosure and an exemplary pMOS transistor gate stack having SiO2 with a thickness greater than 1 nm. As shown in the schematic stack diagram above the graph, the thickness of the silicon oxide including the dielectric interlayer 120 disposed on top of the substrate 110 varies linearly from about 0.5 nm to up to about 1.2 nm.

[0102] Instead of Figure 7 The threshold voltage instability plotted as shown can be plotted on the vertical axis for the maximum operating overdrive voltage applied to a given gate stack within the operating life of the device without causing the threshold voltage instability to be greater than a predetermined value (i.e., the failure criterion). The voltage is preferably as large as possible because a higher voltage corresponds to an increased stability of the gate stack. For example, a failure criterion of 4 mV within 1000 seconds at 25°C corresponds approximately to a failure criterion of ~30 and ~50 mV within 10 years at 25°C and 125°C, respectively. In the chart, the "x" symbol represents the results obtained from the deposited stack (without a dipole-forming layer), the "◇" symbol corresponds to the results of the same stack after reliability annealing, and the "○" symbol corresponds to a stack including an Al2O3 first dipole-forming capping layer with a thickness of 0.2 nm according to an embodiment of the present disclosure. The dotted line represents the electric field (E) corresponding to 5 MV / cm applied to the dielectric interlayer. ox ) trend line.

[0103] The maximum operating voltage on the horizontal axis is represented as a function of the equivalent capacitance thickness (CET) of the gate stack on the vertical axis.

[0104] The stack includes a first dipole-forming capping layer Al2O3 having a thickness of 0.2 nm. It has been confirmed that a first dipole-forming capping layer Al2O3 having a thickness of 0.2 nm can produce sufficient NBTI reliability. However, the thickness of the dipole-forming layer is not limited to this thickness. For example, the thickness may be 0.2 nm to 1 nm.

[0105] Fig.10The top schematic diagram shows an obliquely etched SiO2 IL deposited on top of a silicon substrate with a thickness decreasing from right to left. Curve (A) shows the reference voltage for the gate stack without an annealing step. As can be seen from this curve, the gate stack can only withstand low operating voltages. Curve (B) shows the improvement after applying a high temperature annealing step. The device operates at or preferably even above the dotted line (corresponding to an electric field of 5 MV / cm on the dielectric interlayer). To bridge this gap, the standard approach is to perform a temperature anneal at temperatures above 800°C. Curve (C) shows the voltage of a pMOS gate stack according to an embodiment of the present invention. Al2O3 is introduced and a positive dipole is formed, which can shift the high-k band gap "downward" relative to the silicon valence band (and therefore reduce the defect level therein). By Fig.10 It can be seen that if thick SiO2 (thickness ≥ 1 nm) is introduced into Al2O3, the reliability of NBTI will not be improved. If the thickness of SiO2 is reduced to below 1 nm, the introduction of Al2O3 will have a positive impact on the maximum operating voltage. When the thickness of SiO2 IL is about 0.6 nm, the reliability of the gate stack according to the embodiment of the present invention matches the high thermal budget gate stack. From these experiments, it can be concluded that as long as the size of the dielectric interlayer is reduced to below 1 nm, the introduction of the first dipole forming capping layer will effectively improve the reliability.

[0106] Scaling the thickness of such dielectric interlayers (e.g. SiO2) to below 1 nm is counterintuitive to those skilled in the art. When trying to solve the pMOS NBTI reliability problem, those skilled in the art will instead increase the thickness of the dielectric interlayer to increase the capacitance equivalent thickness, thereby reducing the electric field on the oxide at a given gate voltage, thereby improving reliability. This is why IL scaling in current technology stops at ~1 nm after decades of continuous scaling from one technology generation to another. Another reason why technicians do not reduce the dielectric interlayer is to avoid increased gate leakage due to thinner interlayers.

[0107] Other approaches that those skilled in the art will take when trying to solve the pMOS NBTI reliability problem are:

[0108] A post-deposition anneal of >800°C is performed as is customary in replacement gate (RMG) High-K-last integration schemes. Note that this anneal would be a "build-up" step in alternative integration schemes such as Gate-First Metal-Inserted Poly-Silicon (MIPS) or RMG High-k-First (HKF) integration schemes. However, this is not compatible with new low thermal budget integration concepts.

[0109] A cap is deposited on top of the high-k layer, followed by a drive-in anneal to passivate / modify the defects in the high-k layer. Such a step is good for nMOS PBTI, but ineffective for pMOS NBTI (as most of the relevant defects are in the SiO2 interlayer close to the channel). Furthermore, the drive-in step is not compatible with new low thermal budget integration concepts.

[0110] In an embodiment of the second aspect of the present disclosure, a method 200 for forming a p-channel metal oxide semiconductor transistor gate stack is provided. An exemplary flow chart of the method is shown in FIG. Fig.25 The method comprises:

[0111] - forming 210 a dielectric intermediate layer 120 having a thickness of less than 1 nm and containing silicon oxide on the substrate 110;

[0112] - depositing 220 a first dipole-forming capping layer 130 in physical contact with the dielectric interlayer and having a thickness of less than 1 nm;

[0113] - depositing 240 a high-k dielectric layer 140 having a high-k bandgap on the first dipole-forming capping layer 130, wherein the first dipole-forming capping layer 130 is adapted to shift the high-k bandgap downward relative to the valence band of the substrate 110;

[0114] - Depositing one or more work function metals 150 over the high-k dielectric layer.

[0115] In the method according to the disclosed embodiments, the high temperature post deposition reliability anneal is eliminated to make the manufacturing compatible with low thermal budget applications. This is possible because the reliability is improved by the first dipole forming capping layer between the dielectric interlayer and the high-k interlayer having a thickness of less than 1 nm.

[0116] The deposition of the dipole-forming capping layer and the high-k dielectric layer may be accomplished by techniques such as physical vapor deposition or atomic layer deposition.

[0117] Fig.25 The step 230 shown for depositing the second dipole layer is merely an optional step and will be discussed later.

[0118] Furthermore, the size of the dielectric interlayer is scaled to a thickness of less than 1 nm, or even less than 0.9 nm, or even less than 0.7 nm, such as 0.6 nm, or less than 0.6 nm. Through simulations using proprietary software, the inventors found that when the thickness of the dielectric interlayer is scaled to less than 1 nm, similar to nMOS PBTI, pMOS NBTI reliability is dominated by the high-k defect level (which can be offset).

[0119] In the method of the present embodiment, a first dipole-forming capping layer (e.g., Al2O3) having a thickness of less than 1 nm is on top of a dielectric layer (e.g., SiO2), and a high-k dielectric layer is disposed on top of the dipole-forming capping layer. The dipole-forming capping layer is introduced to shift the energy level of the high-k traps of the high-k dielectric layer relative to the band edge of the semiconductor channel substrate. In some embodiments of the present invention, the dipole formation causes the high-k defect level to shift relative to the silicon valence band.

[0120] Without high temperature annealing, the defect density in the IL and high-k increases, but the defect levels are energetically shifted by the dipole-forming layer so that they are not feasible at operating voltages.

[0121] As discussed above, reducing the thickness of the dielectric interlayer generally results in reduced reliability, so it is not obvious to those skilled in the art to reduce the thickness. However, an advantage of the pMOS gate stack according to an embodiment of the present invention is that the pMOS gate stack can withstand higher oxide fields while the defect level of the energy offset remains infeasible.

[0122] Furthermore, inserting a relatively low-k layer (the dipole-forming capping layer has a lower dielectric constant compared to the HfO2 high-k layer) is counterintuitive to one skilled in the art because it results in an effective oxide thickness (EOT) penalty, and therefore a performance penalty. However, an advantage of embodiments of the present invention is that this penalty can be compensated by scaling the dielectric interlayer to a thickness of less than 1 nm.

[0123] Moreover, inserting an additional layer that may be defective (the dipole-forming capping layer may be a non-native oxide deposited using a low-temperature ALD process) is counterintuitive to those skilled in the art. However, the inventors have found that the defect level of the dipole-forming capping layer does not interact with the Si valence band, which is beneficial for pMOS reliability.

[0124] By calibrating simulations with experimental data on charge trapping in low thermal budget HfO2 and Al2O3 layers, the inventors have derived the energy distribution of defect levels in these layers, such as Fig.11 (for deposited HfO2) and Fig.12 (for deposited Al2O3), the conclusion is that Al2O3 has a negligible defect level density near the Si valence band, making it suitable for pMOS device gate stacks and does not contribute a significant additional amount of traps compared to HfO2. For pMOS NBTI, the most relevant energy level is the one close to Et-Ec=1.12eV=Ev. Low thermal budget HfO2 shows a defect density of ~2e21 / cm at this energy. 3 / eV, while at the same energy level, low thermal budget Al2O3 shows a defect density of “only” ~4e18 / cm 3 / eV.

[0125] When trying to improve pMOS NBTI reliability, the inventors performed multiple simulations using in-house developed BTI simulation software. To the inventors’ surprise, these simulations showed that for thin SiO2 ILs (<0.8nm), traps in the high-k dielectric layer account for the majority of the overall pMOS NBTI degradation, especially due to the high defect density associated with low temperature process flows. Calculations showed that a dipole offset of about 0.4eV at the interface between SiO2 and HfO2 would be sufficient to suppress charge trapping, sufficient to demonstrate pMOS NBTI reliability.

[0126] Therefore, the inventors searched for a dipole capping layer for shifting the energy levels of the high-k traps of the high-k dielectric layer. Therefore, a suitable layer is a thin Al2O3 oxide layer deposited on a dielectric interlayer (e.g., SiO2). This layer can produce a dipole shift of up to 0.35 eV. Based on the data analysis, the inventors concluded that other oxide traps in the Al2O3 dipole forming layer will not have an impact on pMOS NBTI because their energy levels are far away from the Si valence band.

[0127] When adding an Al2O3 interlayer to a standard SiO2 / HfO2 dielectric stack, an EOT penalty is intrinsic. However, the reliability improvement is significantly greater than the corresponding EOT increase, i.e., the maximum operating oxide electric field is greatly improved. Therefore, the intrinsic EOT penalty can be restored by scaling the SiO2 thickness. Assuming that the dielectric constant of Al2O3 is higher than that of SiO2, a reduction in SiO2 thickness of ~0.2nm will be sufficient to compensate for the EOT penalty caused by the necessary Al2O3 layer.

[0128] According to an exemplary embodiment of the present invention, the inventors designed a pMOS gate stack that can produce sufficient reliability according to calculations, which includes a thin SiO2 IL with a thickness of less than 1nm (e.g., 0.6nm), a thin Al2O3 dipole-forming layer (0.2-1nm), and a standard HfO2 high-k dielectric layer (1-1.9nm).

[0129] In experiments, MOS capacitors were fabricated by depositing the designed stack. NBTI measurements confirmed significantly improved reliability. The gate stack design can produce reliability comparable to high thermal budget processes without requiring any "reliability anneal" or high temperature (e.g. >500°C) steps after dielectric deposition.

[0130] Fig.13 It is shown that as the thickness of SiO2 IL 120 increases, the gate leakage current density decreases (see point A). The 0.6 nm thick SiO2 layer in the pMOS stack according to the embodiment of the present invention achieves the same reliability as the prior art pMOS stack with a SiO2 layer thickness of 0.7 nm after reliability annealing (see point B). It can be seen in this graph that due to the thinner SiO2, the additional current leakage is small and the total leakage is still below 1 A / cm 2 Point C is the result of a deposited prior art pMOS stack.

[0131] Fig.14 It was evaluated whether Al2O3 can be combined with reliability annealing to further improve the bottom layer reliability. The failure criterion is a function of the capacitance equivalent thickness. For example, a failure criterion of 4 mV within 1000 seconds at 25°C therefore corresponds approximately to a failure criterion of ~30 or ~50 mV within 10 years at 25°C and 125°C, respectively. In the graph, the "x" symbol represents the result obtained from the deposited stack (without dipole-forming layer), the "◇" symbol corresponds to the result of the same stack after reliability annealing, the "○" symbol corresponds to a stack including an Al2O3 first dipole-forming capping layer having a thickness of 0.5 nm according to an embodiment of the present disclosure, and the "Δ" symbol corresponds to a stack including an Al2O3 first dipole-forming capping layer having a thickness of 0.5 nm after annealing. The dotted line represents an E of 5 MV / cm ox The graph shows that for thin SiO2, reliability is lost when exposed to high temperature (850°C for 1.5s, a typical "reliability anneal" condition). From the graph, it can be seen that the reliability improvement achieved by introducing Al2O3 is lost due to heating the stack. This is especially true for dipole-forming capping layers with a thickness of less than 1nm.

[0132] For dielectric interlayers thicker than 1 nm, NBTI is dominated by SiO2 hole traps, the SiO2 hole trap density is reduced by reliability annealing (rel.anneal), thus improving reliability.

[0133] The dipole shift is usually measured by observing the flat-band voltage of a MOS capacitor without and with a dipole-forming layer. Fig.15 The graph in shows the flat band of the gate stack before (A) and after (B) a reliability anneal at 850°C (1.5s duration) as a function of the SiO2 interlayer thickness. In fact, the horizontal axis represents the Y position on the wafer (in mm), which is linearly related to the SiO2 interlayer thickness. From this graph, it can be seen that the layer mixing caused by heating leads to dipole losses. Therefore, the reliability improvement caused by the dipole forming layer cannot be maintained after adopting a high thermal budget.

[0134] In some embodiments of the present disclosure, method 200 may include providing an nMOS gate stack and a pMOS gate stack by using the steps of forming a pMOS stack and forming an nMOS stack. Examples of these stacks are Fig.16 Available in.

[0135] The combined method includes the following steps:

[0136] - For the nMOS gate stack 300 , a dielectric interlayer 320 having a thickness of less than 1 nm is formed 210 on the semiconductor substrate, and a dielectric interlayer 120 is also formed 210 for the pMOS gate stack 100 ;

[0137] - depositing 230 a second dipole-forming capping layer 332 , 132 over the dielectric interlayer 320 of the nMOS gate stack 300 and over the first dipole-forming capping layer 130 of the pMOS gate stack 100 to simplify CMOS dual gate stack integration;

[0138] - depositing 240 a high-k dielectric layer 340 over the second dipole-forming capping layer 332 of the nMOS gate stack 300 and simultaneously depositing 240 the high-k dielectric layer 140 of the pMOS gate stack 100,

[0139] The second dipole-forming capping layer (322) is adapted to shift the high-k band gap upward relative to the valence band of the semiconductor substrate.

[0140] - Depositing 250 one or more work function metals 150 , 350 .

[0141] The stack of two dipole layers on pMOS allows for simplified dual gate stack integration. However, the present disclosure is not limited thereto. In fact, the pMOS gate stack according to some embodiments of the present disclosure will also work (even better) if the pMOS only has its own (first) dipole-forming layer.

[0142] In the exemplary embodiment of the present disclosure, the second dipole-forming capping layer 32 of the nMOS transistor is La x Si y O z (and x and z must be >0, while y can be equal to 0, such as La2O3), and the interface dielectric layer 320 of the nMOS transistor is SiO2, and the high-k dielectric layer 340 of the nMOS transistor is HfO2, and the dielectric interlayer 120 of the pMOS transistor is SiO2, and the high-k dielectric layer 140 of the pMOS transistor is HfO2, and the first dipole-forming capping layer 130 of the pMOS transistor is Al2O3. In this example, the second dipole-forming layer is present in the pMOS stack. In this exemplary embodiment of the present invention, the thickness of the dielectric interlayer 120 of the pMOS transistor is less than 1nm and greater than 0.2nm, and the thickness of the first dipole-forming capping layer 130 of the pMOS transistor is less than 2nm and greater than 0.1nm. The thickness of the high-k dielectric layer 340 of the nMOS transistor can range from 1nm to 3nm, or even 1nm to 2.5nm, for example. The second dipole-forming capping layer 332 of the nMOS transistor is La x Si y O z For example, its thickness may range from 0.1 nm to 2 nm, or even 0.1 nm to 1 nm. For example, the interface dielectric layer of an nMOS transistor may be SiO2. For example, its thickness may range from 0.2 nm to 1 nm (or even up to 2 nm for nMOS). For example, the high-k dielectric layer of an nMOS transistor may be HfO2. For example, its thickness may range from 1 nm to 3 nm.

[0143] In some embodiments of the present disclosure, the method for depositing a dual gate stack can be simplified by depositing a second dipole-forming capping layer on top of the first dipole-forming capping layer. Fig.17 and Fig.18 Among them, LaSiO x Can it be deposited on top without a pMOS reliability penalty? From these graphs, it can be seen that although there is LaSiO on the top x (residue from nMOS gate stack fabrication), but for a 0.5nm thick Al2O3 layer the residual net dipole shift is still sufficient to meet NBTI reliability targets. Fig.17The failure criteria are shown as a function of the capacitance equivalent thickness. For example, a failure criterion of 4 mV within 1000 seconds at 25°C thus corresponds approximately to failure criteria of ~30 and ~50 mV within 10 years at 25°C and 125°C, respectively. In the graph, the "x" symbol represents the results obtained from the deposited stack (without the dipole-forming layer), the "◇" symbol corresponds to the results of the same stack after reliability annealing, the "○" symbol corresponds to a stack including an Al2O3 first dipole-forming capping layer having a thickness of 0.5 nm according to an embodiment of the present disclosure, and the "□" symbol corresponds to a stack including an Al2O3 first dipole-forming capping layer having a thickness of 0.5 nm and a 0.2 nm LaSiO3 on top. x The dotted line indicates the E of 5 MV / cm ox .

[0144] Fig.19 The dipole offset is shown as a function of the nominal Al2O3 thickness (in nm) of a pMOS gate stack according to some embodiments of the present disclosure. Reference points with thin HfO2 (A) and without HfO2 (B) are shown.

[0145] It was also evaluated whether depositing a first dipole-forming capping layer on a second dipole-forming capping layer is an option for nMOS gate stacks without degrading nMOS reliability. Fig. 20 An example of a gate stack that would be obtained using this method is shown in FIG.

[0146] Al2O3 as the first dipole capping layer and LaSiO x As a second dipole-forming capping layer, it was evaluated. Fig.21 The failure criterion is shown as a function of the capacitance equivalent thickness. For example, a failure criterion of 4 mV within 1000 seconds at 25°C thus corresponds approximately to a failure criterion of ~30 and ~50 mV within 10 years at 25°C and 125°C, respectively. In this graph, the "x" symbol represents the result obtained with the deposited stack (without the dipole-forming layer), the "◇" symbol corresponds to the result of the same stack after reliability annealing, and the "○" symbol corresponds to a LaSiO2 stack comprising a thickness of 0.2 nm. x The second dipole forms a stack of capping layers, and the "□" symbol corresponds to a stack of LaSiO x The second dipole forms a stack of capping layers and is topped by a 0.5 nm Al2O3 layer. The dashed line represents the E at 5 MV / cm ox .

[0147] The nMOS gate stack has Al2O3 Fig.21 and Fig. 22It can be seen that the nMOS PBTI reliability is lower than the as-deposited reference stack. Although the net dipole shift ( Fig. 22 DS in , but there is still PBTI reliability loss. This may be due to Al2O3, which introduces a non-negligible electron trap density (i.e. >1e19 / cm 3 / eV) and is not beneficial to nMOS gate stacks. Fig.23 The defect distribution in HfO2 is shown as deposited (A) and after reliability annealing (i.e., the gate stack of the prior art) (B). As can be seen from the figure, the reliability annealing slightly reduces the defect density and, most importantly, changes the distribution in a way that significantly reduces the defect density near the Si conduction band (and valence band). The dipole layer achieves the same effect in a completely different way: it changes the defect distribution of energy, thereby minimizing the defects near the Si conduction band (and valence band). The figure also shows the distribution C of "natural" defects in Al2O3. The Si valence band of this density is less than the HfO2 defect density remaining after the offset. Therefore, the introduction of Al2O3 does not increase the harmful defect density associated with pMOS. The difference is that at the conduction band, Al2O3 increases the defect density to be much greater than the HfO2 defect density remaining after the offset. Therefore, inserting Al2O3 is not good for nMOS.

[0148] One advantage of embodiments of the present invention is that reliability can be achieved without high temperature annealing (more specifically, without reliability annealing). For example, a pMOS gate stack according to embodiments of the present invention can be used in a sequential 3D stack of CMOS logic layers (an exemplary 3D stack of Seq3D on CMOS is shown in FIG. Fig.24), in CMOS in a memory array, or in CMOS integrated in the BEOL (e.g., access transistor / selector memory cell). The solid rectangles represent portions of the stacked device where high temperature (e.g., >800°C) steps are allowed, and the dashed lines highlight portions of the stacked device where low thermal budget solutions need to be used. Therefore, according to an embodiment, a pMOS transistor according to the embodiments described herein is formed on a metallization level including metal lines, vias, and dielectric layers (e.g., an interlayer dielectric (ILD) layer). The metallization level may then be formed on a substrate. The substrate may include additional front-end-of-line (FEOL) structures or devices manufactured thereon, such as nMOS transistors. In the illustrated embodiment, the metal lines of the metallization level include metal lines that will electrically connect the pMOS transistor to the substrate, which may include FEOL structures or devices, such as nMOS transistors. Thus, in the illustrated embodiment, a channel of a pMOS, e.g., a p-channel semiconductor layer, may be formed after and above the formation of the metallization levels, followed by the formation of a first transistor, e.g., an nMOS transistor, including a first channel semiconductor layer that may be formed in a substrate, and then a metallization levels are formed after and above the formation of the first transistor.

[0149] In addition, the illustrated embodiment includes a metallization level including a metal line, a via, and a first dielectric layer between a pMOS transistor and an nMOS transistor. The metal line can be a metal interconnect that electrically connects the nMOS transistor and the pMOS transistor, wherein the metal interconnect is located between the pMOS transistor and the nMOS transistor. A second dielectric layer is located between the nMOS transistor and the metal interconnect. A vertical cross-section of the three-dimensional stack of transistors includes from bottom to top: a second dielectric layer, a metal interconnect, a first dielectric layer, a p-channel semiconductor layer, a dielectric interlayer, a first dipole-forming capping layer, a high-k dielectric layer, and at least one work function metal.

[0150] Thus, sequential 3D stacking of CMOS logic layers is possible because reliability can be achieved without resorting to a high temperature “reliability anneal.” A typical reliability anneal of about 850°C in about 1 second is not feasible with an underlying BEOL in place.

[0151] The stack may include pMOS on nMOS or CMOS on CMOS. As mentioned above, the gate stack for nMOS may be LaSiO x Gate stack.

[0152] The pMOS gate stack according to some embodiments of the present disclosure may also be integrated as a part of an access transistor or a selector of an emerging memory (eg, a crossbar switch).

[0153] The pMOS gate stack according to some embodiments of the present disclosure may also be used as a gate stack of a thin film transistor, for example, in a display.

[0154] The gate stack according to some embodiments of the present disclosure can also be used to reset the process steps of forming metal contacts on the source / drain. Today, the source / drain is formed on a finFET obtained by epitaxial growth (improved S / D). After growing the source / drain, it may be useful to form a contact between the metal and the semiconductor. However, this is not possible in the prior art because a high thermal budget still needs to be applied to fix the reliability of the gate stack. In this way, the contact will degrade under the influence of the high thermal budget. Since the high temperature reliability annealing step can be avoided in an embodiment of the present invention, the resetting of the standard RMG HKL integration process can be easily achieved. Therefore, the formation of the contact can be completed immediately after the S / D manufacturing. Therefore, "Epi-through-contact" integration can be achieved.

Claims

1. A semiconductor device comprising a p-channel metal oxide semiconductor (pMOS) transistor, the p-channel metal oxide semiconductor (pMOS) transistor comprising a gate stack, the gate stack comprising: A silicon oxide dielectric interlayer having a thickness of less than 0.6 nm formed on the substrate, the dielectric interlayer comprising a SiO2 or SiON layer; a high-k dielectric layer having a higher dielectric constant than the silicon oxide dielectric interlayer, the high-k dielectric layer comprising a HfO2 layer; a first dipole-forming capping layer between the silicon oxide dielectric interlayer and the high-k dielectric layer and in direct contact with the silicon oxide dielectric interlayer, wherein the first dipole-forming capping layer shifts the high-k bandgap of the high-k dielectric layer downward relative to the valence band of the substrate and compared to the high-k bandgap in a gate stack identical to the gate stack but without the first dipole-forming capping layer, and the first dipole-forming capping layer has a thickness of less than 2 nm, and the first dipole-forming capping layer comprises an Al2O3 layer; at least one work function metal over the high-k dielectric layer; The pMOS transistor is formed on a metallization level such that a metal line electrically connecting the pMOS transistor to the substrate is inserted between the pMOS transistor and the substrate in a vertical direction perpendicular to a major surface of the substrate.

2. The semiconductor device according to claim 1, wherein: The substrate includes a silicon substrate, a SiGe substrate, a Ge substrate, or a III-V compound substrate.

3. The semiconductor device of claim 1, comprising a complementary metal oxide semiconductor (CMOS) device comprising the pMOS transistor of claim 1 and an n-channel metal oxide semiconductor (nMOS) transistor.

4. The semiconductor device of claim 3, wherein the nMOS transistor comprises an nMOS transistor gate stack on an active region of a substrate, wherein: The nMOS transistor gate stack of the nMOS transistor includes a second dipole-forming capping layer between the interface dielectric layer and the second high-k dielectric layer including a second high-k band gap, wherein the second dipole-forming capping layer shifts the second high-k band gap of the nMOS transistor upward relative to the conduction band of the substrate and compared to the second high-k band gap in the nMOS transistor gate stack that is the same as the nMOS transistor gate stack but does not contain the second dipole-forming capping layer.

5. The semiconductor device according to claim 4, wherein: The second dipole-forming capping layer includes a transition metal oxide layer or a transition metal silicate layer.

6. The semiconductor device according to claim 5, wherein: The second dipole-forming capping layer of the nMOS transistor includes La x Si y O z , where x and z are greater than 0, y is greater than or equal to 0, the interface dielectric layer of the nMOS transistor is SiO2, and the high-k dielectric layer of the nMOS transistor is HfO2, and The silicon oxide dielectric interlayer of the pMOS transistor includes SiO2, the high-k dielectric layer of the pMOS transistor includes HfO2, and the first dipole-forming capping layer of the pMOS transistor includes Al2O3.

7. A semiconductor device as described in claim 1, wherein the device also includes a three-dimensional stack of transistors, wherein the three-dimensional stack of transistors includes the pMOS transistor as described in claim 1 in a first layer, and the first layer is vertically stacked on one or more transistors in a second layer in a direction substantially perpendicular to the main surface of the substrate.

8. The semiconductor device according to claim 7, wherein: The gate stack of the pMOS transistor further includes a semiconductor layer below the silicon oxide dielectric interlayer, and the three-dimensional stack of transistors further includes: a first dielectric layer between the one or more transistors and the pMOS transistor in the second layer; a metal interconnect electrically connecting the one or more transistors in the second layer to the pMOS transistor, wherein the metal interconnect is located between the one or more transistors in the second layer and the first dielectric layer; and a second dielectric layer between the one or more transistors and the metal interconnect in the second layer; Among them, the vertical cross-section of the three-dimensional stack of transistors also includes from bottom to top: a second dielectric layer, a metal interconnect, a first dielectric layer, a semiconductor layer, a silicon oxide dielectric intermediate layer, a first dipole-forming capping layer, a high-k dielectric layer and at least one work function metal.

9. The semiconductor device according to claim 1, wherein: The pMOS transistor is formed in the back-end process of a semiconductor device.

10. The semiconductor device according to claim 1, wherein The pMOS transistors are formed on the memory array.

11. The semiconductor device according to claim 1, wherein: The gate stack does not include a silicon layer.

12. The semiconductor device according to claim 1, wherein: The metal line electrically connects the pMOS transistor to the nMOS transistor formed on the substrate.

13. A method for manufacturing a semiconductor device, the method comprising: Forming a p-channel metal oxide semiconductor (pMOS) gate stack, the method comprising: A dielectric intermediate layer containing silicon oxide having a thickness of less than 0.6 nm is formed on the substrate, wherein the dielectric intermediate layer comprises a SiO2 or SiON layer; Depositing a first dipole-forming capping layer in direct contact with the dielectric intermediate layer and having a thickness of less than 2 nm, wherein the first dipole-forming capping layer comprises an Al2O3 layer; depositing a high-k dielectric layer having a high-k bandgap on the first dipole-forming capping layer, wherein the first dipole-forming capping layer shifts the high-k bandgap downward relative to a valence band of the substrate and compared to a high-k bandgap in a gate stack identical to the pMOS gate stack but without the first dipole-forming capping layer, the high-k dielectric layer comprising a HfO2 layer; and depositing one or more work function metals over the high-k dielectric layer; The pMOS transistor is formed on a metallization level such that a metal line electrically connecting the pMOS transistor to the substrate is inserted between the pMOS transistor and the substrate in a vertical direction perpendicular to a major surface of the substrate.

14. The method of claim 13, wherein: The semiconductor device is a complementary metal oxide semiconductor (CMOS) device, and the method further includes providing an nMOS transistor gate stack and forming the pMOS gate stack of claim 13 .

15. The method of claim 14, further comprising: Forming a dielectric interlayer having a thickness of less than 1 nm on the substrate for the nMOS gate stack and simultaneously forming a dielectric interlayer for the pMOS gate stack; depositing a second dipole-forming capping layer over the dielectric interlayer for the nMOS gate stack and over the first dipole-forming capping layer for the pMOS gate stack; depositing a high-k dielectric layer of the nMOS transistor gate stack over a second dipole-forming capping layer of the nMOS transistor gate stack while depositing a high-k dielectric layer of the pMOS gate stack, wherein the second dipole-forming capping layer shifts the high-k bandgap upward relative to a conduction band of the substrate; as well as One or more work function metals are deposited for the nMOS transistor gate stack.

16. The method of claim 13, wherein: The semiconductor device comprises a three-dimensional stack of transistors, the method comprising repeating the method of claim 13 to form a plurality of pMOS transistor gate stacks in a plurality of layers of the three-dimensional stack of transistors.

17. The method of claim 13, wherein: Fabricating the semiconductor device includes completing the fabrication without subjecting the pMOS gate stack to a temperature greater than 800° C. after forming the pMOS gate stack.

18. A semiconductor device, comprising a three-dimensional stack of transistors, wherein the three-dimensional stack of transistors comprises: A pMOS transistor comprising: A silicon oxide dielectric interlayer having a thickness of less than 0.6 nm formed on the semiconductor layer, wherein the dielectric interlayer comprises a SiO2 or SiON layer; a high-k dielectric layer having a higher dielectric constant than the dielectric interlayer, the high-k dielectric layer comprising a HfO2 layer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting the high-k bandgap of the high-k dielectric layer downward relative to the valence band of the semiconductor layer, wherein the first dipole-forming capping layer has a thickness of less than 2 nm and comprises an Al2O3 layer; and at least one work function metal over the high-k dielectric layer; an nMOS transistor above the substrate and below the pMOS transistor; a first dielectric layer between the nMOS transistor and the pMOS transistor; A metal interconnection electrically connecting the nMOS transistor and the pMOS transistor, wherein the metal interconnection is located between the pMOS transistor and the nMOS transistor; a second dielectric layer between the nMOS transistor and the metal interconnect; Wherein, the vertical cross section of the three-dimensional stack of transistors further comprises, from bottom to top: a second dielectric layer, a metal interconnect, a first dielectric layer, a semiconductor layer, a dielectric intermediate layer, a first dipole-forming capping layer, a high-k dielectric layer, and at least one work function metal; The pMOS transistor is formed on a metallization level such that a metal line electrically connecting the pMOS transistor to the substrate is inserted between the pMOS transistor and the substrate in a vertical direction perpendicular to a major surface of the substrate.

19. The three-dimensional transistor stack of claim 18, wherein the metal interconnect electrically connects at least one work function metal of the pMOS transistor to the gate electrode of the nMOS transistor.

20. The three-dimensional transistor stack according to claim 18, wherein: The semiconductor layer includes silicon, SiGe, Ge, or a III-V compound semiconductor.

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