Integrated circuit and its manufacturing method and design method

Abstract

An integrated circuit and a manufacturing method and a design method thereof are provided. The integrated circuit includes a semiconductor substrate, a plurality of gate lines and a plurality of metal lines. The plurality of gate lines are formed in a gate layer above the semiconductor substrate, wherein the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the first direction. The plurality of metal lines are formed in a conductive layer above the gate layer, wherein the plurality of metal lines are arranged in a first direction and extend in a second direction. 6N metal lines and 4N gate lines form a unit line structure, wherein N is a positive integer, and the plurality of unit line structures are arranged in the first direction. The design efficiency and performance of the integrated circuit are enhanced by the unit line structure.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2018-0155192 filed on December 5, 2018, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to an integrated circuit having a cell line structure and methods of manufacturing and designing the integrated circuit. Background Art

[0003] Standard cells with fixed functions can be used in the design of integrated circuits. Standard cells have a predetermined architecture and are stored in a cell library. When designing an integrated circuit, standard cells are retrieved from the cell library and placed in the desired location on the integrated circuit layout. Then wiring is performed to connect the standard cells to each other and to other cells. Standard cells have a predetermined (or set) architecture, such as cell width, cell height, cell length, etc. The design efficiency of the integrated circuit can be determined based on the configuration and layout of the standard cells. Summary of the invention

[0004] Some example embodiments may provide an integrated circuit having a circuit structure suitable for design, and a method of manufacturing and designing the integrated circuit.

[0005] An integrated circuit is also provided, comprising: a semiconductor substrate; a plurality of gate lines formed in a gate layer above the semiconductor substrate, the plurality of gate lines being arranged in a first direction and extending in a second direction perpendicular to the first direction; and a plurality of metal lines formed in a conductive layer above the gate layer, the plurality of metal lines being arranged in the first direction and extending in the second direction, wherein the plurality of metal lines comprise 6N metal lines, the plurality of gate lines comprise 4N gate lines, the 6N metal lines and the 4N gate lines form a unit line structure, N is a positive integer, and the plurality of unit line structures are arranged in the first direction.

[0006] In some embodiments of the integrated circuit, N=1, the multiple unit line structures include a first unit line structure and a second unit line structure, the second unit line structure is adjacent to the first unit line structure in a first direction, and the morphology of the second unit line structure is the same as that of the first unit line structure.

[0007] In some embodiments of the integrated circuit, two metal pitches between every three metal lines sequentially adjacent in the first direction among the plurality of metal lines are different from each other.

[0008] In some embodiments of the integrated circuit, the plurality of metal lines are formed by self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP).

[0009] In some embodiments of the integrated circuit, the plurality of gate lines are formed by single patterning, SADP, or SAQP.

[0010] In some embodiments of the integrated circuit, the unit line structure is a minimum unit structure that is not divided into at least two equal sub-line structures. In addition, in some embodiments, each unit line structure includes six metal lines and four gate lines. In addition, in some embodiments, the six metal lines of each unit line structure are formed by self-aligned double patterning (SADP), and the six metal lines of each unit line structure are arranged in a first direction to alternately have a first metal pitch and a second metal pitch. In addition, in some embodiments, the four gate lines of each unit line structure are formed by single patterning, and the four gate lines of each unit line structure are arranged in the first direction to have equal gate pitches.

[0011] Generally, in some embodiments, four gate lines of each unit line structure are formed by, for example, SADP, and are arranged in a first direction to alternately have a first gate pitch and a second gate pitch.

[0012] Typically, in some embodiments, as another example, the four gate lines of each unit line structure are formed by, for example, self-aligned quadruple patterning (SAQP), and the four gate lines of each unit line structure are arranged in a first direction to sequentially have a first gate pitch, a second gate pitch, a first gate pitch, and a third gate pitch.

[0013] In some embodiments, each unit line structure includes twelve metal lines and eight gate lines. In addition, in some embodiments, the twelve metal lines of each unit line structure are formed by self-aligned quadruple patterning (SAQP), and the twelve metal lines of each unit line structure are arranged in the first direction to sequentially and repeatedly have a first metal pitch, a second metal pitch, a first metal pitch, and a third metal pitch. In addition, in some embodiments, the eight gate lines of each unit line structure are formed by single patterning, and the eight gate lines of each unit line structure are arranged in the first direction to have an equal gate pitch.

[0014] In some embodiments, each unit wiring structure includes twelve metal lines and eight gate lines, the twelve metal lines of each unit wiring structure are formed by self-aligned quadruple patterning (SAQP), and the twelve metal lines of each unit wiring structure are arranged in a first direction to sequentially and repeatedly have a first metal pitch, a second metal pitch, a first metal pitch, and a third metal pitch. In addition, for example, the eight gate lines of each unit wiring structure are formed by self-aligned double patterning (SADP), and the eight gate lines of each unit wiring structure are arranged in the first direction to alternately have a first gate pitch and a second gate pitch.

[0015] In yet another embodiment, each unit wiring structure includes twelve metal lines and eight gate lines, the twelve metal lines of each unit wiring structure are formed by self-aligned quadruple patterning (SAQP), and the twelve metal lines of each unit wiring structure are arranged in the first direction to sequentially and repeatedly have a first metal pitch, a second metal pitch, a first metal pitch, and a third metal pitch. In this embodiment, eight gate lines of each unit wiring structure are formed by SAQP, and the eight gate lines of each unit wiring structure are arranged in the first direction to sequentially and repeatedly have a first gate pitch, a second gate pitch, a first gate pitch, and a third gate pitch.

[0016] A method for manufacturing an integrated circuit is also provided. The method includes: forming a plurality of gate lines in a gate layer above a semiconductor substrate, the plurality of gate lines being arranged in a first direction and extending in a second direction perpendicular to the first direction; and forming a plurality of metal lines in a conductive layer above the gate layer, the plurality of metal lines being arranged in the first direction and extending in the second direction, so that 6N metal lines included in the plurality of metal lines and 4N gate lines included in the plurality of gate lines form a unit line structure, wherein N is a positive integer, and the plurality of unit line structures are arranged in the first direction.

[0017] In some embodiments of the method, two metal pitches between every three metal lines that are sequentially adjacent in the first direction among the plurality of metal lines are different from each other.

[0018] In some embodiments of the method, the plurality of metal lines are formed by self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP).

[0019] Also in some embodiments of the method, the unit line structure is a smallest unit structure that is not divided into at least two equal sub-line structures.

[0020] In addition, a method for designing an integrated circuit is provided, the method comprising: receiving input data defining the integrated circuit; setting a standard cell library including a plurality of standard cells; performing layout and routing based on the input data and the standard cell library; and generating output data defining the integrated circuit based on the results of the layout and routing, wherein the integrated circuit comprises: a semiconductor substrate, a plurality of gate lines formed in a gate layer above the semiconductor substrate, the plurality of gate lines arranged in a first direction and extending in a second direction perpendicular to the first direction, and a plurality of metal lines formed in a conductive layer above the gate layer, the plurality of metal lines arranged in the first direction and extending in the second direction. In some embodiments of the method, 6N metal lines of the plurality of metal lines and 4N gate lines of the plurality of gate lines form a unit line structure, N is a positive integer, and the plurality of unit line structures are arranged in the first direction.

[0021] According to an example embodiment, an integrated circuit includes: a semiconductor substrate, a plurality of gate lines, and a plurality of metal lines. The plurality of gate lines are formed in a gate layer above the semiconductor substrate, wherein the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the first direction. The plurality of metal lines are formed in a conductive layer above the gate layer, wherein the plurality of metal lines are arranged in the first direction and extend in the second direction. 6N metal lines and 4N gate lines form a unit line structure, wherein N is a positive integer, and the plurality of unit line structures are arranged in the first direction.

[0022] According to an example embodiment, a method for manufacturing an integrated circuit, the method comprising: forming a plurality of gate lines in a gate layer above a semiconductor substrate, the plurality of gate lines being arranged in a first direction and extending in a second direction perpendicular to the first direction; and forming a plurality of metal lines in a conductive layer above the gate layer, the plurality of metal lines being arranged in the first direction and extending in the second direction, so that 6N metal lines and 4N gate lines form a unit line structure, wherein N is a positive integer, and the plurality of unit line structures are arranged in the first direction.

[0023] According to an example embodiment, a method for designing an integrated circuit includes: receiving input data defining the integrated circuit; setting a standard cell library including a plurality of standard cells; performing layout and routing based on the input data and the standard cell library; and generating output data defining the integrated circuit based on the results of the layout and routing. The integrated circuit includes: a semiconductor substrate, a plurality of gate lines formed in a gate layer above the semiconductor substrate, the plurality of gate lines arranged in a first direction and extending in a second direction perpendicular to the first direction, and a plurality of metal lines formed in a conductive layer above the gate layer, the plurality of metal lines arranged in the first direction and extending in the second direction, wherein 6N metal lines and 4N gate lines form a unit line structure, wherein N is a positive integer, and the plurality of unit line structures are arranged in the first direction.

[0024] Integrated circuits and methods of manufacturing and designing the same according to example embodiments may improve design efficiency and performance of the integrated circuit through a cell line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0026] Figure 1 is a flow chart illustrating a method of manufacturing an integrated circuit.

[0027] Figure 2 is a cross-sectional view of an integrated circuit according to example embodiments.

[0028] Figure 3 is a perspective view of an integrated circuit according to an example embodiment.

[0029] FIG. 4A to FIG. 4I is a diagram for describing a patterning process for manufacturing an integrated circuit according to example embodiments.

[0030] Figures 5 to 10 is a diagram of an example embodiment of a cell line structure applied to an integrated circuit according to an example embodiment.

[0031] Fig.11 is a diagram showing a layout of an example standard cell.

[0032] Fig. 12A , Fig. 12B and Fig. 12C yes Fig.11 Cross-sectional view of a standard cell.

[0033] Fig.13 is a diagram illustrating a method of designing an integrated circuit according to example embodiments.

[0034] Fig.14is a block diagram illustrating a design system for an integrated circuit according to example embodiments.

[0035] Fig.15 It is shown Fig.14 A flowchart of an example operation of the design system.

[0036] Fig.16 is a diagram illustrating a layout of an integrated circuit according to example embodiments.

[0037] Fig.17 is a block diagram illustrating a mobile device according to example embodiments. DETAILED DESCRIPTION

[0038] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings showing some example embodiments. In the accompanying drawings, the same reference numerals always represent the same elements. Repeated descriptions may be omitted.

[0039] Hereinafter, the structure of the integrated circuit according to the example embodiment is described in a three-dimensional space using a first direction X, a second direction Y, and a third direction Z. The first direction X may be a row direction, the second direction Y may be a column direction, and the third direction Z may be a vertical direction. The first direction X, the second direction Y, and the third direction Z may cross, for example, may be orthogonal or perpendicular to each other.

[0040] Figure 1 is a flow chart illustrating a method of manufacturing an integrated circuit.

[0041] Reference Figure 1 , forming a plurality of gate lines in a gate layer above a semiconductor substrate, wherein the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the first direction (S100). Forming a plurality of metal lines in a conductive layer above the gate layer, wherein the plurality of metal lines are arranged in a first direction and extend in a second direction, so that 6N metal lines and 4N gate lines form a unit line structure, wherein N is a positive integer, and the plurality of unit line structures are arranged in the first direction (S200).

[0042] According to an example embodiment, a plurality of metal lines may be formed by self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP). SADP and SAQP are manufacturing techniques. In addition, according to an example embodiment, a plurality of gate lines may be formed by single patterning (i.e., direct patterning), SADP, or SAQP. Single patterning is also a manufacturing technique. FIG. 4A to FIG. 4I Describe single patterning, SADP, and SAQP.

[0043] In some embodiments, the unit line structure corresponds to a minimum unit structure that is not divided into at least two equal sub-line structures. In some example embodiments, each unit line structure may include six metal lines and four gate lines. In this case, the unit line structure is not divided into two sub-line structures, so that each sub-line structure includes three metal lines and two gate lines. In some example embodiments, each unit line structure may include twelve metal lines and eight gate lines. In this case, the unit line structure is not divided into four sub-line structures, so that each sub-line structure includes three metal lines and two gate lines, and the unit line structure is not divided into two sub-line structures, so that each sub-line structure includes six metal lines and four gate lines.

[0044] As semiconductor processes are scaled down, the number of transistors integrated into an integrated circuit grows exponentially. Due to the large number of transistors, integrated circuits are designed using standard cell libraries, which include multiple standard cells that standardize logic gates rather than custom designs. Complex integrated circuits that implement desired functions can be automatically designed using standard cell libraries, logic synthesis tools, and automatic placement and routing tools.

[0045] The standard cells are arranged to form multiple rows for automatic design, and the rows of the manufactured integrated circuit have a regular pitch except for optical deviations. The gate lines of the integrated circuit extend in the column direction and are repeatedly arranged in the row direction. The metal lines above the gate lines transmit signals and / or voltages bidirectionally or unidirectionally. Typically, the metal lines in the upper layer are implemented as unidirectional.

[0046] The gate lines and metal lines are very dense, and the pitch of the gate lines and metal lines is used as a pattern restriction in the photolithography process. If the pitch of the metal lines arranged in the same direction as the gate lines is different from the pitch of the gate lines, some metal tracks are unusable due to aliasing caused by different pitches, and the design is limited.

[0047] To solve these problems, the exemplary embodiment provides an effective line structure of gate lines and metal lines extending in the same direction so as to maximize the resources of the gate lines and metal lines set in the manufacturing process. The integrated circuit and the method of manufacturing and designing the integrated circuit according to the exemplary embodiment can improve the design efficiency and performance of the integrated circuit through the unit line structure.

[0048] The conductive layer may be referred to as a column conductive layer, and the metal line may be referred to as a column metal line. The column metal line may be a metal line extending in a certain direction (eg, in the second direction), and the "column" is not limited to a specific direction.

[0049] Figure 2 is a cross-sectional view of an integrated circuit according to an example embodiment, Figure 3 is a perspective view of an integrated circuit according to an example embodiment.

[0050] Reference Figure 2 and Figure 3 , the integrated circuit includes a semiconductor substrate (not shown), a plurality of gate lines GL1 to GL4N and a plurality of metal lines ML1 to ML6N.

[0051] A plurality of gate lines GL1 to GL4N are formed in a gate layer GTL above a semiconductor substrate. The plurality of gate lines GL1 to GL4N are arranged in a first direction X and extend in a second direction Y perpendicular to the first direction X. A plurality of metal lines ML1 to ML6N are formed in a column conductive layer CCL above the gate layer GTL. The plurality of metal lines ML1 to ML6N are arranged in the first direction X and extend in a second direction Y. At least one of the gate lines GL1 to GL4N may be cut into gate segments, and / or at least one of the metal lines ML1 to ML6N may be cut into metal segments.

[0052] like Figure 2 and Figure 3 As shown in FIG. 1 , 6N metal lines ML1 to ML6N and 4N gate lines GL1 to GL4N may form a unit line structure UWS, and a plurality of unit line structures UWS may be arranged in a first direction X.

[0053] Two metal pitches between every three metal lines sequentially adjacent in the first direction X among the plurality of metal lines ML1 to ML6N may be different from each other. For example, the first metal pitch PMa and the second metal pitch PMb between the first metal line ML1, the second metal line ML2, and the third metal line ML3 adjacent in the first direction X may be different from each other. In the same manner, the second metal pitch PMb and the third metal pitch PMc between the second metal line ML2, the third metal line ML3, and the fourth metal line ML4 adjacent in the first direction X may be different from each other. The first metal pitch PMa and the third metal pitch PMc may be the same as or different from each other.

[0054] In some example embodiments, each unit line structure UWS may include six metal lines and four gate lines. In this case, the six metal lines of each unit line structure UWS may be formed by SADP. Figure 5 , Figure 6 and Figure 7 Example embodiments of SADP are described.

[0055] In some example embodiments, each unit line structure UWS may include twelve metal lines and eight gate lines. In this case, the twelve metal lines of each unit line structure UWS may be formed by SAQP. Figure 8, Fig. 9 and Fig.10 Example embodiments of the SAQP are described.

[0056] Typically, a plurality of conductive layers may be arranged above the gate layer GTL. At least one conductive layer forming a line pattern may be inserted between the gate layer GTL and the column conductive layer CCL, and / or at least one conductive layer may be arranged above the column conductive layer CCL. In some example embodiments, the integrated circuit may further include a plurality of row metal lines formed in a row conductive layer between the gate layer GTL and the column conductive layer CCL, such that the row metal lines are arranged in the second direction Y and extend in the first direction X. The conductive layers sequentially arranged above the gate layer GTL may be referred to as an M1 layer, an M2 layer, an M3 layer, an M4 layer, and the like. The row conductive layer may correspond to the M1 layer or the M2 layer, and the column conductive layer CCL may correspond to the M2 layer or the M3 layer.

[0057] FIG. 4A to FIG. 4I is a diagram for describing a patterning process for manufacturing an integrated circuit according to example embodiments.

[0058] You can refer to FIG. 4A to FIG. 4I Describes the pitch of the cell line structure associated with single patterning, SADP, and SAQP. FIG. 4A to FIG. 4I The mandrel spacer patterning is described as an example, but example embodiments are not limited to a specific patterning process.

[0059] In the present disclosure, single patterning, SADP, and SAQP are defined as follows. Single patterning or direct patterning means forming a target pattern having the same average pitch as an exposure pattern in a photolithography process. Here, the target pattern includes a gate line and a column metal line included in a cell line structure according to an example embodiment. SADP means forming a target pattern having an average pitch corresponding to 1 / 2 of the average pitch of the exposure pattern. SAQP means forming a target pattern having an average pitch corresponding to 1 / 4 of the average pitch of the exposure pattern.

[0060] Reference Figure 4A , intermediate layers 210, 220, and 230 are formed over the semiconductor substrate 200. The semiconductor substrate 200 includes silicon as a semiconductor wafer. In various embodiments, the semiconductor substrate 200 may include another element semiconductor (such as germanium), a compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or a combination thereof.

[0061] The semiconductor substrate 200 may include active regions, epitaxial features, isolation structures, fin-shaped semiconductor regions, and / or other suitable features. In some example embodiments, the semiconductor substrate 200 includes a polysilicon layer, which may be used to form a polysilicon gate electrode or to form a dummy gate electrode in a gate replacement process.

[0062] The intermediate layers 210, 220 and 230 may be dielectric layers, which may be formed by one or more deposition techniques such as thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD) and atomic layer deposition (ALD).

[0063] Reference Figure 4B , photoresists (or resist patterns) PR1, PR2, and PR3 are patterned over layers 240 and 250 disposed over dielectric layer 230. For example, layer 250 may be a silicon-containing hard mask layer, and layer 240 may be an anti-reflective coating. Layers 240 and 250 may be formed using CVD, PVD, or other suitable methods. In some example embodiments, resist patterns PR1, PR2, and PR3 may be formed directly over dielectric layer 230 without layers 240 and 250.

[0064] The resist patterns PR1, PR2, and PR3 may be formed using a photolithography process. For example, a resist layer is formed on the layer 250 using a spin coating process and a soft bake process. Figure 4C The mask defined by the first mandrel patterns 231, 232 and 233 exposes the resist layer to radiation. The first mandrel patterns 231, 232 and 233 will provide a mask based on the first mandrel patterns 231, 232 and 233 to create Figure 4E 2. The first sidewall spacers 261 to 266 shown in FIG. The first mandrel patterns 231, 232 and 233 will eventually be etched away. The exposed resist layer is developed using post-exposure baking, development and hard baking to form resist patterns PR1, PR2 and PR3 over layer 250. The resist patterns PR1, PR2 and PR3 have a pitch P1 and a width W1 in the first direction X.

[0065] Reference Figure 4C , the layers 250, 240, and 230 are etched through the openings of the resist patterns PR1, PR2, and PR3 to form first mandrel patterns 231, 232, and 233. The etching process may include dry (or plasma) etching, wet etching, or other suitable etching methods. The resist patterns PR1, PR2, and PR3 are then removed using a suitable process (such as wet stripping or plasma ashing). One or more etching processes are also used to remove the layers 250 and 240, thereby generating a first mandrel pattern 231, 232, and 233 above the intermediate layer 220. Figure 4CThe first mandrel patterns 231, 232 and 233 are shown in FIG. Considering the feature variation through the above-mentioned patterning process, the first mandrel patterns 231, 232 and 233 have a pitch P2 and a width W2 in the first direction X that substantially match the pitch P1 and the width W1, respectively.

[0066] Reference Figure 4D , a first spacer 260 is formed over the dielectric layer 220, over the first mandrel patterns 231, 232, and 233, and on the sidewalls of the first mandrel patterns 231, 232, and 233. The first spacer 260 is disposed over the dielectric layer 220 and the first mandrel patterns 231, 232, and 233. The first spacer 260 includes one or more materials different from the dielectric layer 220 and the first mandrel patterns 231, 232, and 233, so that the first spacer 260 has different etching selectivities for the etching process. The first spacer 260 may be formed by a CVD process, a PVD process, an atomic layer deposition (ALD) process, or other suitable deposition techniques.

[0067] Reference Figure 4E , an etching process is performed on the first spacer layer 260, thereby defining first sidewall spacers 261 to 266. The first sidewall spacers 261 (similarly, 262 to 266) may be referred to herein as a second mandrel pattern. Figure 4E As shown in FIG. 2 , the first mandrel pattern 231 exists before etching. Figure 4F 2 shows the result after etching away the first mandrel pattern 231 (e.g., the first sidewall spacers 261 and 262 remain). In some embodiments, the pitch (also referred to as distance, spacing, resolution, feature resolution, or feature separation distance in some embodiments) obtained between 261 and 262 is greater than that obtained using the method provided by Figure 4B The pitch obtainable by photolithography of the resist patterns PR1, PR2, and PR3 is small or precise.

[0068] Reference Figure 4F, an etching process with a suitable etching selectivity is performed to remove the first mandrel patterns 231, 232 and 233, and the first sidewall spacers 261 to 266 are retained. 261 is formed as a sidewall, and in some embodiments, will be etched away in a later process step, so it is a spacer. In summary, 261 can be referred to as a sidewall spacer. The first sidewall spacers 261 to 266 have pitches P3 and P4 and a width W3 in the first direction X. The pitch P3 of two sidewall spacers (e.g., sidewall spacers 261 and 262) corresponding to one mandrel pattern may be equal to or different from the pitch P4 of two opposite sidewall spacers (e.g., sidewall spacers 262 and 263) of the mandrel pattern adjacent to the mandrel pattern. In some embodiments, the average pitch of the first sidewall spacers 261 to 266 is reduced to 1 / 2 the average pitch of the resist patterns PR1, PR2 and PR3.

[0069] In some embodiments, Figure 4F The structure is used as a starting point to sequentially apply the applied spacer layer and repeat the etching steps. Figure 4G , a second spacer 270 may be formed over the dielectric layer 220, over the first sidewall spacers 261 to 266, and on the sidewalls of the first sidewall spacers 261 to 266. In other words, the first sidewall spacers 261 to 266 may be used as a second mandrel pattern. In some embodiments, 261 to 266 have been fabricated to receive material deposition, and then 261 to 266 will be etched away, leaving the deposited material in place. A second spacer 270 is disposed over the dielectric layer 220 and the first sidewall spacers 261 to 266. The second spacer 270 includes one or more materials different from the dielectric layer 220 and the first sidewall spacers 261 to 266, so that the second spacer 270 has different etching selectivities for the etching process. The second spacer 270 may be formed by a CVD process, a PVD process, an ALD process, or other suitable deposition techniques.

[0070] Reference Figure 4H , an etching process is performed with respect to the second spacer layer 270 , thereby defining second sidewall spacers 271 to 282 .

[0071] Reference Fig. 4I, an etching process with a suitable etching selectivity is performed to remove the first sidewall spacers 261 to 266, and the second sidewall spacers 271 to 282 are retained. The second sidewall spacers 271 to 282 have pitches P5, P6, and P7 and a width W4 in the first direction X. The pitches P5, P6, and P7 are determined according to the width W3 of the first sidewall spacers 261 to 266 and the width W4 of the second sidewall spacers 271 to 282. In some embodiments, the average pitch of the second sidewall spacers 271 to 282 is reduced to 1 / 4 of the average pitch of the resist patterns PR1, PR2, and PR3.

[0072] In some example embodiments, as shown in FIG. Figure 4G , Figure 4H and Fig. 4I As described above, the second sidewall spacers 271 to 282 may be formed in the same layer as the first sidewall spacers 261 to 266 using the first sidewall spacers 261 to 266 as a mandrel pattern.

[0073] In some example embodiments, even if not shown in the drawings, the first sidewall spacers 261 to 266 may be printed in a lower layer, and the second sidewall spacers 271 to 282 may be formed in a layer lower than the first sidewall spacers 261 to 266 using the printed pattern as a mandrel pattern.

[0074] Different pitch values ​​(feature resolution or feature separation distance) are obtained depending on the number of process steps used. In the case of single patterning or direct patterning, a target pattern having the same average pitch as the resist patterns PR1, PR2 and PR3 can be formed using the resist patterns PR1, PR2 and PR3. In the case of SADP, a target pattern having 1 / 2 the average pitch of the resist patterns PR1, PR2 and PR3 can be formed in a layer lower than the resist patterns PR1, PR2 and PR3 using the first mandrel patterns 231, 232 and 233. In the case of SAQP, a target pattern having 1 / 4 the average pitch of the resist patterns PR1, PR2 and PR3 can be formed in a layer lower than the resist patterns PR1, PR2 and PR3 using the first sidewall spacers 261 to 266 as the second mandrel patterns.

[0075] Figures 5 to 10 is a diagram illustrating an example embodiment of a unit line structure applied to an integrated circuit.

[0076] For the convenience of description, the patterns DPM, QPM, DPG, and QPG formed in the sacrificial layer are additionally shown in FIG. Figures 5 to 10 The patterns DPM, QPM, DPG and QPG can be compared with the reference FIG. 4A to FIG. 4I The mandrel patterns described correspond to and may be removed during an intermediate process to be excluded from the final integrated circuit.

[0077] In the following, reference will be made to Figure 5 , Figure 6 and Figure 7 An example embodiment of forming a plurality of column metal lines by SADP is described.

[0078] Reference Figure 5 , Figure 6 and Figure 7 , each of the unit line structures UWS1 , UWS2 , and UWS3 may include six column metal lines ML1 to ML6 and four gate lines GL1 to GL4 arranged in the first direction X, respectively.

[0079] As reference FIG. 4A to FIG. 4I As described above, double mandrel patterns DPM1, DPM2, and DPM3 may be formed over the column conductive layer CCL. The label "DPM" may be understood as follows: "D" means double, "P" means pattern, and "M" means metal. For example, the double mandrel patterns DPM1, DPM2, and DPM3 may be arranged to have the same double mandrel pitch PDM in the first direction X, and the double mandrel pitch PDM may be the same as the pitch of the resist pattern.

[0080] For each of the unit line structures UWS1 , UWS2 , and UWS3 , six column metal lines ML1 to ML6 may be formed in the column conductive layer CCL using three double mandrel patterns DPM1 , DPM2 , and DPM3 .

[0081] The six column metal lines ML1 to ML6 of each unit line structure may be arranged to alternately have a first metal pitch PM11 and a second metal pitch PM12 in the first direction X. The first metal pitch PM11 and the second metal pitch PM12 may be represented by Expression 1.

[0082] Expression 1

[0083] PM11=WDM+WML

[0084] PM12=PDM-(WDM+WML)

[0085] In Expression 1, WDM represents the width of the double mandrel patterns DPM1, DPM2, and DPM3, and WML represents the width of the column metal lines ML1 to ML6.

[0086] Before forming the column metal lines ML1 to ML6, four gate lines GL1 to GL4 for each unit line structure may be formed in the gate layer GTL under the column conductive layer CCL. Figure 5, the four gate lines GL1 to GL4 of each unit line structure UWS1 may be formed by single patterning. In this case, the four gate lines GL1 to GL4 of each unit line structure UWS1 may be arranged to have an equal gate pitch PG1 in the first direction X. The gate pitch PG1 may be equal to the pitch of the resist pattern formed by the exposure process. Figure 5 Two unit line structures are shown, both having the same layout or the same topography: the one on the left is labeled UWS1 and the one shifted to the right on the x-axis is also labeled UWS1. Figure 5 The spatial relationships within the UWS1 on the left are the same as those within the UWS1 on the right. The spatial relationships include the pitches between GL1, GL2, GL3, GL4 in the GTL and the pitches between ML1, ML2, ML3, ML4, ML5, ML6 in the CCL, as well as the relative pitches between features in the CCL and GTL. Figure 5 represents a common example in which there are 6N metal lines and 4N gate lines. Figure 5 In the unit line structure with N=1, there are six metal lines and four gate lines. Figure 5 Includes multiple unit line structures, multiple unit line structures include Figure 5 The first unit line structure on the left side and Figure 5 The second unit line structure on the right side of the second unit line structure is adjacent to the first unit line structure in the x direction (also referred to as the first direction X herein), and the morphology of the second unit line structure is the same as that of the first unit line structure.

[0087] Reference Figure 6 , the four gate lines GL1 to GL4 of each unit line structure UWS2 can be formed by SADP. FIG. 4A to FIG. 4I As described, double mandrel patterns DPG1 and DPG2 can be formed above the gate layer GTL. The label "DPG" can be understood as follows: "D" means double, "P" means pattern, and "G" means gate. For example, the double mandrel patterns DPG1 and DPG2 can be arranged in the first direction X to have the same double mandrel pitch PDG that can be equal to the pitch of the resist pattern. In this case, the four gate lines GL1 to GL4 of each unit line structure UWS2 can be arranged in the first direction X to alternately have a first gate pitch PG11 and a second gate pitch PG12. The first gate pitch PG11 and the second gate pitch PG12 can be expressed by Expression 2.

[0088] Expression 2

[0089] PG11=WDG+WGL

[0090] PG12=PDG-(WDG+WGL)

[0091] In Expression 2, WDG represents the width of the double mandrel patterns DPG1 and DPG2, and WGL represents the width of the gate lines GL1 to GL4.

[0092] Reference Figure 7 , the four gate lines GL1 to GL4 of each unit line structure UWS3 may be formed by SAQP. FIG. 4A to FIG. 4I As described, a quadruple mandrel pattern QPG and double mandrel patterns DPG1 and DPG2 may be sequentially formed above the gate layer GTL. For example, the quadruple mandrel pattern QPG may be arranged in the first direction X to have the same quadruple mandrel pitch PQG which may be equal to the pitch of the resist pattern. In this case, the four gate lines GL1 to GL4 of each unit line structure UWS3 may be arranged in the first direction X to sequentially have a first gate pitch PG21, a second gate pitch PG22, a first gate pitch PG21, and a third gate pitch PG23. In some embodiments, the third gate pitch PG23 is the distance from the next unit line structure. The first gate pitch PG21, the second gate pitch PG22, and the third gate pitch PG23 may be different from each other. The first gate pitch PG21, the second gate pitch PG22, and the third gate pitch PG23 may be represented by Expression 3.

[0093] Expression 3

[0094] PG21=WDG+WGL

[0095] PG22=WQG-WGL

[0096] PG23=PQG-(WQG+2WDG+WGL)

[0097] In Expression 3, WDG represents the width of the double mandrel patterns DPG1 and DPG2, WQG represents the width of the quadruple mandrel pattern QPG, and WGL represents the width of the gate lines GL1 to GL4.

[0098] In the following, reference will be made to Figure 8 , Fig. 9 and Fig.10 Example embodiments of forming multiple column metal lines by SAQP are described.

[0099] Reference Figure 8 , Fig. 9 and Fig.10 , each of the unit line structures UWS4 , UWS5 , and UWS6 may include twelve column metal lines ML1 to ML12 and eight gate lines GL1 to GL8 arranged in the first direction X, respectively.

[0100] As reference FIG. 4A to FIG. 4I As described above, quadruple mandrel patterns QPM1, QPM2, and QPM3 and dual mandrel patterns DPM1 to DMP6 may be sequentially formed over the column conductive layer CCL. For example, the quadruple mandrel patterns QPM1, QPM2, and QMP3 may be arranged to have the same quadruple mandrel pitch PQM in the first direction X, and the quadruple mandrel pitch PQM may be the same as the pitch of the resist pattern.

[0101] For each of the unit line structures UWS4 , UWS5 , and UWS6 , twelve column metal lines ML1 to ML12 may be formed in the column conductive layer CCL using three quadruple mandrel patterns QPM1 , QPM2 , and QPM3 .

[0102] The twelve column metal lines ML1 to ML12 of each unit line structure may be arranged to sequentially and repeatedly have a first metal pitch PM21, a second metal pitch PM22, a first metal pitch PM21, and a third metal pitch PM23 in the first direction X. The first metal pitch PM21, the second metal pitch PM22, and the third metal pitch PM23 may be represented by Expression 4.

[0103] Expression 4

[0104] PM21=WDM+WML

[0105] PM22=WQM-WML

[0106] PM23=PQM-(WQM+2WDM+WML)

[0107] In Expression 4, WDM represents the width of the double mandrel patterns DPM1 to DPM6 , WQM represents the width of the quadruple mandrel patterns QPM1 , QPM2 , and QPM3 , and WML represents the width of the column metal lines ML1 to ML12 .

[0108] Before forming the column metal lines ML1 to ML12 , eight gate lines GL1 to GL8 for each unit line structure may be formed in the gate layer GTL under the column conductive layer CCL.

[0109] Reference Figure 8 , the eight gate lines GL1 to GL8 of each unit line structure UWS4 may be formed by single patterning. In this case, the eight gate lines GL1 to GL8 of each unit line structure UWS4 may be arranged to have an equal gate pitch PG2 in the first direction X. The gate pitch PG2 may be equal to the pitch of the resist pattern formed by the exposure process.

[0110] Reference Fig. 9, the eight gate lines GL1 to GL8 of each unit line structure UWS5 can be formed by SADP. FIG. 4A to FIG. 4I As described, double mandrel patterns DPG1 to DPG4 may be formed above the gate layer GTL. For example, the double mandrel patterns DPG1 to DPG4 may be arranged in the first direction X to have the same double mandrel pitch PDG which may be equal to the pitch of the resist pattern. In this case, the eight gate lines GL1 to GL8 of each unit line structure UWS5 may be arranged in the first direction X to alternately have a first gate pitch PG11 and a second gate pitch PG12. The first gate pitch PG11 and the second gate pitch PG12 may be different from each other. The first gate pitch PG11 and the second gate pitch PG12 may be represented by Expression 2.

[0111] Reference Fig.10 , the eight gate lines GL1 to GL8 of each unit line structure UWS6 may be formed by SAQP. FIG. 4A to FIG. 4I As described, quadruple mandrel patterns QPG1 and QPG2 and double mandrel patterns DPG1 to DPG4 may be sequentially formed above the gate layer GTL. For example, the quadruple mandrel patterns QPG1 and QPG2 may be arranged in the first direction X to have the same quadruple mandrel pitch PQG which may be equal to the pitch of the resist pattern. In this case, the eight gate lines GL1 to GL8 of each unit line structure UWS6 may be arranged in the first direction X to sequentially and repeatedly have a first gate pitch PG21, a second gate pitch PG22, a first gate pitch PG21, and a third gate pitch PG23. The first gate pitch PG21, the second gate pitch PG22, and the third gate pitch PG23 may be different from each other. The first gate pitch PG21, the second gate pitch PG22, and the third gate pitch PG23 may be represented by Expression 3.

[0112] Integrated circuits and methods of manufacturing and designing the same according to example embodiments may improve design efficiency and performance of the integrated circuit through the unit line structures UWS1 to UWS6 .

[0113] Hereinafter, reference is made to a layout diagram that may support an understanding of an integrated circuit according to example embodiments. Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C Describes an example structure of a standard cell.

[0114] Fig.11 It is indicative in nature. Fig.11 Not all features of the above-described embodiments are shown. Figure 2 It is shown that in some embodiments metal lines "ML" appear at a ratio of 6 to 4 relative to gate lines "GL". Figure 5 and Figure 7 An embodiment is shown in which six metal lines and four gate lines exist in a single unit wire structure (UWS). Figure 8 An embodiment is shown in which twelve metal lines ("ML") are present in a single unit wiring structure (UWS) having eight gate lines ("GL").

[0115] Fig.11 is a diagram showing a layout of an example standard cell, Fig. 12A , 12B and 12C is Fig.11 Cross-sectional view of a standard cell.

[0116] Fig. 12A , 12B 12C shows a portion of a standard cell SCL including a fin field effect transistor (FinFET). Fig. 12A yes Fig.11 A cross-sectional view of a standard cell SCL along line AA'. Fig. 12B yes Fig.11 A cross-sectional view of a standard cell SCL along line BB'. Fig. 12C yes Fig.11 A cross-sectional view of a standard cell SCL along line CC'.

[0117] Reference Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C , the standard cell may be formed on a substrate 110 having an upper surface 110A extending in a horizontal direction (eg, a first direction X and a second direction Y).

[0118] In some example embodiments, the substrate 110 may include a semiconductor such as silicon (Si), germanium (Ge), etc., or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InP, etc. In some example embodiments, the substrate 110 may have a silicon-on-insulator (SOI) structure. The substrate 110 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities.

[0119] The standard cell may include a first device region RX1, a second device region RX2, and an active cutout region ACR separating the first device region RX1 and the second device region RX2 along a second direction Y. Each of the first device region RX1 and the second device region RX2 may include a plurality of fin-type active regions AC protruding from the substrate 110 along a third direction Z (see FIG. Fig. 12C ).

[0120] The plurality of active regions AC may extend parallel to each other in the first direction X. The device isolation layer 112 may be located between the plurality of active regions AC on the substrate 110 along the second direction Y. The plurality of active regions AC protrude from the device isolation layer 112 along the third direction Z in the form of fins.

[0121] A plurality of gate insulating layers 118 and a plurality of gate lines PC 11, 12, 13, 14, 15, and 16 may be formed on the substrate 110. The gate lines PC 11, 12, 13, 14, 15, and 16 may extend in a second direction Y intersecting the plurality of active regions AC. The plurality of gate insulating layers 118 and the plurality of gate lines PC 11, 12, 13, 14, 15, and 16 may cover an upper surface and sidewalls of each active region AC and an upper surface of the device isolation layer 112. A plurality of metal oxide semiconductor (MOS) transistors may be formed along the plurality of gate lines PC 11, 12, 13, 14, 15, and 16. The MOS transistor may have a three-dimensional structure in which a channel is formed in an upper surface and both sidewalls of the active region AC. Fig.11 A legend is provided: "PC" represents gate line, "CA" represents contact, "CB" represents contact, "VO" represents through-hole contact, and "M1" represents line.

[0122] The gate insulating layer 118 may be formed of a silicon oxide layer, a high-k dielectric layer, or a combination thereof. A plurality of gate lines PC11, 12, 13, 14, 15, and 16 may extend on the gate insulating layer 118 across a plurality of active regions AC while covering an upper surface and both sidewalls of each active region AC.

[0123] The mask 122 may be formed on each of the gate lines PC 11, 12, 13, 14, 15, and 16. The sidewalls of the gate insulating layer 118, the gate lines PC, and the mask 122 may be covered by the spacer 124. Specifically, the spacer 124 may extend along the gate insulating layer 118, the gate lines PC, and the mask 122 along the third direction Z. Fig. 12C In the cross section shown in , the gate insulating layer 118 may extend along the third direction Z between the gate line PC and the spacer 124 .

[0124] The gate lines PC 11, 12, 13, 14, 15 and 16 may have a structure in which a metal nitride layer, a metal layer, a conductive cover layer and a gap filling metal layer are stacked in sequence. The metal nitride layer and the metal layer may include titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), etc. For example, the metal layer and the metal nitride layer may be formed by using an atomic layer deposition (ALD) method, a metal organic ALD method and / or a metal organic chemical vapor deposition (MOCVD) method. The conductive cover layer may be used as a protective layer to prevent surface oxidation of the metal layer. In addition, the conductive cover layer may be used as an adhesive layer (e.g., a wetting layer) that facilitates the deposition of another conductive layer on the metal layer. The conductive cover layer may be formed by a metal nitride (e.g., TiN, TaN, a combination thereof, etc.). The gap filling metal layer may fill the space between the active regions AC and extend on the conductive cover layer. The gap filling metal layer may be formed by a W (e.g., tungsten) layer. The gap-fill metal layer may be formed, for example, by using an ALD method, a CVD method, or a physical vapor deposition (PVD) method.

[0125] A plurality of conductive contacts CA and CB may be located on the first layer LY1 on the active region AC. The plurality of conductive contacts CA and CB include a plurality of first contacts CA 21, 22, 23, 24, 25, 31, 32, 33, 34, and 35 connected to the source / drain regions 116 of the active region AC (see Fig. 12B ) and a plurality of second contacts CB 41, 42 and 43 connected to the gate lines PC 11, 12, 13, 14, 15 and 16 (see Fig. 12A and 12C ).

[0126] The plurality of conductive contacts CA and CB may be insulated from each other by the first interlayer insulating layer 132 covering the active region AC and the gate line PC. The plurality of conductive contacts CA and CB may have upper surfaces substantially at the same level as an upper surface of the first interlayer insulating layer 132. The first interlayer insulating layer 132 may be a silicon oxide layer.

[0127] A second interlayer insulating layer 134 and a plurality of lower via contacts V051, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, and 62 passing through the second interlayer insulating layer 134 are located on the first interlayer insulating layer 132. The second interlayer insulating layer 134 may be a silicon oxide layer.

[0128] A plurality of lines M1 71, 72, 73, 74, 75, 76, 77, and 78 extending along the first direction X on a second layer LY2 that is higher than the first layer LY1 (e.g., farther from the substrate 110 along the third direction Z) may be located on the second interlayer insulating layer 134. Each line M1 may be connected to one of the plurality of conductive contacts CA and CB through one of the plurality of lower via contacts V0 formed between the first layer LY1 and the second layer LY2. Each of the plurality of lower via contacts V0 may be connected to one of the plurality of conductive contacts CA and CB, for example, by passing through the second interlayer insulating layer 134. The plurality of lower via contacts V0 may be insulated from each other by the second interlayer insulating layer 134.

[0129] The lines M1 71 to 78 may include internal connection lines that electrically connect multiple regions in the standard cell SCL. For example, the internal connection line M1 78 may electrically connect the active area AC in the first device region RX1 and the active area AC in the second device region RX2 through the lower via contacts V0 55 and 58 and the first contacts 24 and 33.

[0130] Lines M1 71 and 72 may correspond to a first power rail and a second power rail, respectively. The first power rail 71 may be connected to an active region AC in the first device region RX1. The second power rail 72 may be connected to an active region AC in the second device region RX2. One of the first power rail 71 and the second power rail 72 may be a line for supplying a power supply voltage (e.g., a first power supply voltage VDD), and the other of the first power rail 71 and the second power rail 72 may be a line for supplying a ground voltage (e.g., a second power supply voltage VSS).

[0131] The first power rail 71 and the second power rail 72 may extend parallel to each other on the second layer LY2 in the first direction X. In some example embodiments, the power rails 71 and 72 may be formed substantially simultaneously with other lines M1 73 to 78. The lines M1 may pass through the third interlayer insulating layer 136. The third interlayer insulating layer 136 may insulate the lines M1 from each other.

[0132] A cell height CH of the standard cell SCL may be defined by a distance between the first power rail 71 and the second power rail 72 along the second direction Y. A cell width CW of the standard cell SCL may be defined along a first direction X parallel to the power rails 71 and 72 .

[0133] The pitch of the line M1 may need to satisfy constraints due to the minimum pitch rule. For example, the line M1 may need to satisfy constraints according to the "tip to side" constraint and the "rounded corner" constraint. The size, arrangement, and spacing of the line M1 may be limited by these constraints.

[0134] The lower via contact V0 and the line M1 may have a stacked structure of a barrier layer and a line conductive layer. The barrier layer may be formed of, for example, TiN, TaN, a combination thereof, etc. The line conductive layer may be formed of, for example, W, Cu, an alloy thereof, a combination thereof, etc. The line M1 and the lower via contact V0 may be formed using a CVD method, an ALD method, and / or an electroplating method.

[0135] Integrated circuits according to some example embodiments may correspond to a combination of various standard cells.Although not shown in the drawings, column metal lines for forming a cell line structure according to example embodiments may be formed in an M2 layer or an M3 layer above the second layer LY2.

[0136] Fig.13 is a diagram illustrating a method of designing an integrated circuit according to example embodiments.

[0137] Fig.13 The method may include a method of designing a layout of an integrated circuit performed by a design tool. In some example embodiments, the design tool may include programming software containing a plurality of instructions executable by a processor, i.e., software implemented in some form of hardware (e.g., processor, ASIC, etc.).

[0138] Reference Fig.13 , input data defining an integrated circuit may be received (S10). For example, the integrated circuit may be defined by a plurality of cells, and the integrated circuit may be designed using a cell library including information of the plurality of cells. Hereinafter, the cell may be a standard cell, and the cell library may be a standard cell library.

[0139] In some example embodiments, the input data may be data generated from an abstract form for the behavior of the integrated circuit. For example, the input data may be defined by synthesis in a register transfer level (RTL) using a standard cell library. For example, the input data may be a bitstream and / or netlist generated by synthesizing an integrated circuit defined by a hardware description language (HDL), such as VHSIC hardware description language (VHDL) or Verilog.

[0140] In some example embodiments, the input data may be data for defining a layout of an integrated circuit. For example, the input data may include geometric information for defining structures implemented as semiconductor materials, metals, and insulators. For example, the layout of the integrated circuit indicated by the input data may have a layout of cells and wires for connecting one cell to other cells.

[0141] A standard cell library including a plurality of standard cells is set (S20). The term "standard cell" may refer to a cell of an integrated circuit, wherein the size of the layout in the cell of the integrated circuit satisfies a preset or specified rule. The standard cell may include an input pin and an output pin, and may process a signal received through the input pin to output a signal through the output pin. For example, the standard cell may be a basic cell such as an AND logic gate, an OR logic gate, a NOR logic gate, or an inverter, a composite cell such as an OR / AND / Inverter (OAI) or an AND / OR / Inverter (AOI), or a storage cell such as a master-slave flip-flop or a latch.

[0142] The standard cell library may include information about a plurality of standard cells. For example, the standard cell library may include the name and function of the standard cell, as well as timing information, power information, and layout information of the standard cell. The standard cell library may be stored in a storage device, and the standard cell library may be set by accessing the storage device.

[0143] Placement and routing are performed based on input data and the standard cell library (S30), and output data defining the integrated circuit is set based on a result of the placement and routing (S40).

[0144] In some example embodiments, when the received input data is data such as a bitstream or a netlist generated by synthesizing an integrated circuit, the output data may be a bitstream or a netlist. In other example embodiments, when the received input data is data defining a layout of an integrated circuit (e.g., data in a Graphic Data System II (GDSII) format), the format of the output data may also be data defining a layout of an integrated circuit.

[0145] pass Fig.13 The integrated circuit designed and manufactured by the method may include a semiconductor substrate, a plurality of gate lines and a plurality of column metal lines. Figures 1 to 10 As described above, 6N metal lines and 4N gate lines form a unit line structure, wherein N is a positive integer and a plurality of unit line structures are arranged in a first direction.

[0146] Fig.14 is a block diagram illustrating a design system for an integrated circuit according to example embodiments.

[0147] Reference Fig.14 , the design system 1000 may include a storage medium 1100 , a design module 1400 , and a processor 1500 .

[0148] The storage medium 1100 (e.g., a storage device) may store the standard cell library SCLB 1110. The standard cell library 1110 may be provided to the design module 1400 from the storage medium 1100. The standard cell library 1110 may include a plurality of standard cells, and the standard cell may be a small (e.g., smallest) unit for designing a block, a device, and / or a chip.

[0149] Storage medium 1100 may include any computer-readable storage medium for providing commands and / or data to a computer as a computer-readable storage medium. For example, a computer-readable storage medium may include volatile memory such as random access memory (RAM), read-only memory (ROM), etc., and non-volatile memory such as flash memory, magnetoresistive RAM (MRAM), phase change RAM (PRAM), resistive RAM (RRAM), etc. The computer-readable storage medium may be inserted into a computer, may be integrated into a computer, or may be connected to a computer via a communication medium such as a network and / or a wireless link.

[0150] The design module 1400 may include a layout module PLMD 1200 and a routing module RTMD 1300 .

[0151] Herein, the term "module" may indicate, but is not limited to, software and / or hardware components (such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs)) that perform specific tasks. A module may reside in a tangible, addressable storage medium and may be executed on one or more processors. For example, a module may include a software component, a class component, a task component, a process, a function, a property, a step, a subroutine, a program code segment, a driver, firmware, microcode, a circuit, data, a database, a data structure, a table, an array, a parameter, etc. A module may be divided into multiple modules that perform detailed functions.

[0152] The layout module 1200 may use the processor 1500 to arrange the standard cells based on the input data DI defining the integrated circuit and the standard cell library 1110. The routing module 1300 may perform signal routing for the cell layout provided from the layout module 1200. If the routing is unsuccessful, the layout module 1200 may modify the previous cell layout, and the routing module 1300 may perform signal routing using the modified cell layout. When the routing is successfully completed, the routing module 1300 may provide output data DO defining the integrated circuit.

[0153] The layout module 1200 and the routing module 1300 may be implemented by a single integrated design module 1400, or may be implemented by separate and distinct modules. The design module 1400 including the layout module 1200 and the routing module 1300 may perform layout and routing such that delay matching and / or duty cycle adjustment may be implemented in an integrated circuit using a plurality of load standard cells.

[0154] The layout module 1200 and / or the routing module 1300 may be implemented in software, but example embodiments are not limited thereto. If the layout module 1200 and the routing module 1300 are implemented in software, they may be stored as program codes in the storage medium 1100 or in other storage media.

[0155] When the design module 1400 performs calculations, the processor 1500 may be used. Fig.14 , only one processor 1500 is shown. Optionally, multiple processors may be included in the design system 1000. In addition, the processor 1500 may include a cache memory to increase computing capacity.

[0156] As such, the integrated circuit and the method of designing the integrated circuit according to example embodiments may improve the design efficiency and performance of the integrated circuit through the unit line structure.

[0157] Fig.15 It is shown Fig.14 A flowchart of an example operation of the design system.

[0158] Reference Fig.14 and Fig.15 , the design module 1400 may receive input data DI defining an integrated circuit (S11). The layout module 1200 may refer to the standard cell library 1110 including a plurality of standard cells as described above, so as to extract a standard cell corresponding to the input data DI, and may perform cell layout using the extracted standard cell (S12). The wiring module 1300 may perform signal wiring for the laid out cells (S13).

[0159] When signal routing is unsuccessful (S14: No), the layout module 1200 may replace at least one standard cell, for example, with another standard cell, to modify the layout of the cells (S15). The routing module 1300 may perform signal routing again for the modified layout (S13).

[0160] In this way, placement and routing may be repeated until signal routing is successfully completed. When signal routing is successfully completed (S14: Yes), the design module 1400 may generate output data DO defining the integrated circuit (S16).

[0161] Fig.16is a diagram illustrating a layout of an integrated circuit according to example embodiments.

[0162] Fig.16 The integrated circuit 300 may be an application specific integrated circuit (ASIC). The layout of the integrated circuit 300 may be determined by performing the above-described placement and routing of the standard cells SC1 to SC12. Power may be provided to the standard cells SC1 to SC12 through power rails 311 to 316. The power rails 311 to 316 may include high power rails 311, 313, and 315 for providing a first power supply voltage VDD, and low power rails 312, 314, and 316 for providing a second power supply voltage VSS lower than the first power supply voltage VDD. For example, the first power supply voltage VDD may have a positive voltage level, and the second power supply voltage VSS may have a ground level (e.g., 0V) or a negative voltage level.

[0163] The high power rails 311, 313 and 315 and the low power rails 312, 314 and 316 extend in the first direction X and are alternately arranged one by one in the second direction Y to form boundaries of a plurality of circuit rows CR1 to CR5 corresponding to areas defined by the power rails 311 to 316 arranged in the second direction Y.

[0164] According to some example embodiments, power may be distributed to the power rails 311 to 316 through power grid lines 321 to 324 extending in the second direction Y. Some of the power grid lines 322 and 324 may provide a first power supply voltage VDD, and other power grid lines 321 and 323 may provide a second power supply voltage VSS. The power grid lines 321 to 324 may be connected to the power rails 311 to 316 through vertical contacts VC, such as through-hole contacts.

[0165] Typically, each of the circuit rows CR1 to CR5 may be connected to two adjacent power rails located at its boundaries to be powered. For example, standard cells SC1 and SC2 in the first circuit row CR1 may be connected to adjacent and corresponding power rail pairs including a high power rail 311 and a low power rail 312 .

[0166] According to an example embodiment, Fig.16 As shown in , the integrated circuit 300 may include a plurality of unit line structures UWS repeatedly arranged in a first direction X. Each unit line structure UWS includes 6N column metal lines and 4N gate lines as described above.

[0167] Fig.17 is a block diagram illustrating a mobile device according to example embodiments.

[0168] Reference Fig.17, the mobile device 4000 may include at least one application processor 4100 , a communication module 4200 , a display / touch module 4300 , a storage device 4400 , and a buffer RAM 4500 .

[0169] The application processor 4100 may control the operation of the mobile device 4000. The communication module 4200 is implemented to perform wireless or wired communication with an external device. The display / touch module 4300 is implemented to display data processed by the application processor 4100 and / or receive data through a touch panel. The storage device 4400 is implemented to store user data. The storage device 4400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc. As described above, the storage device 4400 may perform a cache of mapping data and user data.

[0170] The buffer RAM 4500 may temporarily store data for processing operations of the mobile device 4000. For example, the buffer RAM 4500 may be a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0171] According to the example embodiments described above, at least one component in the mobile device 4000 may include an integrated circuit having a cell line structure.

[0172] As such, the integrated circuit and the method of manufacturing and designing the integrated circuit according to example embodiments may improve the design efficiency and performance of the integrated circuit through a cell line structure.

[0173] Embodiments can be applied to any electronic device and system. For example, embodiments can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0174] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without substantially departing from the inventive concept.

Claims

1. An integrated circuit, comprising: Semiconductor substrate; A plurality of gate lines formed in a gate layer above the semiconductor substrate, the plurality of gate lines being arranged in a first direction and extending in a second direction perpendicular to the first direction; as well as A plurality of metal lines are formed in a conductive layer above the gate layer, the plurality of metal lines are arranged in a first direction and extend in a second direction, wherein the plurality of metal lines include 6N metal lines, the plurality of gate lines include 4N gate lines, the 6N metal lines and the 4N gate lines form a unit line structure, N is a positive integer, and the plurality of unit line structures are arranged in the first direction, wherein two metal pitches between every three metal lines that are sequentially adjacent in the first direction among the plurality of metal lines are different from each other, and The unit line structure is a minimum unit structure that is not divided into at least two equal sub-line structures.

2. The integrated circuit according to claim 1, wherein: The plurality of metal lines are formed by self-aligned double patterning or self-aligned quadruple patterning.

3. The integrated circuit according to claim 2, wherein: The plurality of gate lines are formed by single patterning, self-aligned double patterning, or self-aligned quadruple patterning.

4. The integrated circuit according to claim 1, wherein: Each unit line structure includes six metal lines and four gate lines.

5. The integrated circuit according to claim 4, wherein: The six metal lines of each unit circuit structure are formed by self-aligned double patterning, and The six metal lines of each unit line structure are arranged in a first direction to alternately have a first metal pitch and a second metal pitch.

6. The integrated circuit according to claim 5, wherein: Four gate lines of each unit line structure are formed by single patterning, and The four gate lines of each unit line structure are arranged in a first direction to have an equal gate pitch.

7. The integrated circuit according to claim 5, wherein: Four gate lines of each unit line structure are formed by self-aligned double patterning, and The four gate lines of each unit line structure are arranged in a first direction to alternately have a first gate pitch and a second gate pitch.

8. The integrated circuit according to claim 5, wherein: The four gate lines of each unit line structure are formed by self-aligned quadruple patterning, and The four gate lines of each unit line structure are arranged in a first direction to sequentially have a first gate pitch, a second gate pitch, a first gate pitch, and a third gate pitch.

9. The integrated circuit of claim 1, wherein: Each unit line structure includes twelve metal lines and eight gate lines.

10. The integrated circuit of claim 9, wherein: The twelve metal lines of each unit circuit structure are formed by self-aligned quadruple patterning, and The twelve metal lines of each unit line structure are arranged in a first direction to sequentially and repeatedly have a first metal pitch, a second metal pitch, a first metal pitch, and a third metal pitch.

11. The integrated circuit of claim 10, wherein: Eight gate lines of each unit line structure are formed by single patterning, and The eight gate lines of each unit line structure are arranged in a first direction to have an equal gate pitch.

12. The integrated circuit of claim 10, wherein: Eight gate lines of each unit line structure are formed by self-aligned double patterning, and The eight gate lines of each unit line structure are arranged in a first direction to alternately have a first gate pitch and a second gate pitch.

13. The integrated circuit of claim 10, wherein: The eight gate lines of each unit line structure are formed by self-aligned quadruple patterning, and The eight gate lines of each unit line structure are arranged in a first direction to sequentially and repeatedly have a first gate pitch, a second gate pitch, a first gate pitch, and a third gate pitch.

14. The integrated circuit of claim 1, wherein: N=1， The plurality of unit line structures include a first unit line structure and a second unit line structure, The second unit line structure is adjacent to the first unit line structure in the first direction, and The morphology of the second unit wiring structure is the same as that of the first unit wiring structure.

15. A method of manufacturing an integrated circuit, the method comprising: forming a plurality of gate lines in a gate layer over a semiconductor substrate, the plurality of gate lines being arranged in a first direction and extending in a second direction perpendicular to the first direction; as well as A plurality of metal lines are formed in a conductive layer above the gate layer, the plurality of metal lines are arranged in a first direction and extend in a second direction, so that 6N metal lines included in the plurality of metal lines and 4N gate lines included in the plurality of gate lines form a unit line structure, wherein N is a positive integer, and the plurality of unit line structures are arranged in the first direction, wherein two metal pitches between every three metal lines that are sequentially adjacent in the first direction among the plurality of metal lines are different from each other, and The unit line structure is a minimum unit structure that is not divided into at least two equal sub-line structures.

16. The method according to claim 15, wherein: The plurality of metal lines are formed by self-aligned double patterning or self-aligned quadruple patterning.

17. A method for designing an integrated circuit, the method comprising: receiving input data defining the integrated circuit; providing a standard cell library including a plurality of standard cells; Performing placement and routing based on input data and standard cell libraries; as well as Generates output data that defines the integrated circuit based on the results of placement and routing, Wherein, the integrated circuit comprises: Semiconductor substrate; a plurality of gate lines formed in a gate layer above a semiconductor substrate, the plurality of gate lines being arranged in a first direction and extending in a second direction perpendicular to the first direction; and A plurality of metal lines are formed in a conductive layer above the gate layer, the plurality of metal lines are arranged in a first direction and extend in a second direction, wherein: 6N metal lines among the plurality of metal lines and 4N gate lines among the plurality of gate lines form a unit line structure, N is a positive integer, and A plurality of unit line structures are arranged in a first direction, wherein two metal pitches between every three metal lines that are sequentially adjacent in the first direction among the plurality of metal lines are different from each other, and The unit line structure is a minimum unit structure that is not divided into at least two equal sub-line structures.

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