Semiconductor Devices

Abstract

The present invention provides a semiconductor device. The semiconductor device may include an active pattern on a substrate. The active pattern may include a first source / drain region and a second source / drain region. The semiconductor device may also include a bit line electrically connected to the first source / drain region, a first connection electrode electrically connected to the second source / drain region, and a capacitor on the first connection electrode. The capacitor may include a first electrode, a second electrode, and a dielectric pattern between the first electrode and the second electrode. The lower portion of the dielectric pattern may overlap with the top surface of the first connection electrode, and the first electrode may extend on the upper portion of the sidewall of the first connection electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0155360 filed on December 5, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a capacitor. Background Art

[0004] Semiconductor devices play an important role in the electronics industry due to their small size, versatility and / or low manufacturing cost. Data storage devices in semiconductor devices can store logical data. Data storage devices are increasingly integrated with the development of the electronics industry. As a result, the line width of components constituting data storage devices is continuously reduced.

[0005] In addition, with the high integration of data storage devices, high reliability is required. However, high integration may reduce the reliability of data storage devices. Therefore, various studies have been conducted to improve the reliability of data storage devices. Summary of the invention

[0006] Some exemplary embodiments of the inventive concepts provide semiconductor devices having enhanced integration.

[0007] According to some exemplary embodiments of the present invention, a semiconductor device may include an active pattern on a substrate. The active pattern may include a first source / drain region and a second source / drain region. The semiconductor device may also include a bit line electrically connected to the first source / drain region, a first connection electrode electrically connected to the second source / drain region, and a capacitor on the first connection electrode. The capacitor may include a first electrode, a second electrode, and a dielectric pattern between the first electrode and the second electrode. A lower portion of the dielectric pattern may overlap with a top surface of the first connection electrode, and the first electrode may extend over an upper portion of a sidewall of the first connection electrode.

[0008] According to some exemplary embodiments of the present invention, a semiconductor device may include an active pattern on a substrate. The active pattern may include a first source / drain region and a second source / drain region. The semiconductor device may also include a bit line electrically connected to the first source / drain region, a connecting electrode electrically connected to the second source / drain region, and a capacitor on the connecting electrode. The capacitor may include a first electrode, a second electrode, and a dielectric pattern between the first electrode and the second electrode. The first electrode may extend upward from an upper portion of a sidewall of the connecting electrode along an outer sidewall of the dielectric pattern, and the second electrode may extend upward from a top surface of a lower portion of the dielectric pattern along an inner sidewall of the dielectric pattern.

[0009] According to some exemplary embodiments of the present inventive concept, a semiconductor device may include a plurality of transistors on a substrate, a plurality of capacitors electrically connected to the plurality of transistors, and a support layer in contact with upper portions of the plurality of transistors. Each of the plurality of capacitors may include a first electrode, a second electrode, and a dielectric pattern between the first electrode and the second electrode, and the dielectric pattern may have a cylindrical shape with an open top. The support layer may contact an upper portion of an outer sidewall of a dielectric pattern of one of the plurality of capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Plan views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept are shown.

[0011] Figure 2A , Figure 2B and Figure 2C The Figure 1 Cross-sectional views taken along lines AA', BB' and CC'.

[0012] Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 and Fig.23 Plan views illustrating methods of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept are shown.

[0013] Figure 4A , Fig. 6A , Fig. 8A , Fig. 10A , Fig. 12A , Fig.14A , Fig.16A , Fig.18A , Fig. 20A , Fig.22A and Fig.24A The Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 and Fig.23 A cross-sectional view taken along line AA'.

[0014] Figure 4B, Figure 6B , Figure 8B , Fig. 10B , Fig. 12B , Fig. 14B , Fig. 16B , Fig.18B , Fig. 20B , Fig. 22B and Fig. 24B The Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 and Fig.23 A cross-sectional view taken along line BB'.

[0015] Figure 4C , Figure 6C , Figure 8C , Fig. 10C , Fig. 12C , Fig. 14C , Fig. 16C , Fig.18C , Fig. 20C , Fig. 22C and Fig.24C The Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 and Fig.23 A cross-sectional view taken along line CC'.

[0016] Fig.25 and Fig.26 Shown along Figure 1 1 is a cross-sectional view taken along line AA′ of FIG. 1 , illustrating semiconductor devices according to some exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0017] Figure 1 Plan views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept are shown. Figure 2A , Figure 2B and Figure 2C The Figure 1 Cross-sectional views taken along lines AA', BB' and CC'.

[0018] Reference Figure 1 and FIG. 2A to FIG. 2C, a device isolation layer ST defining an active pattern ACT may be disposed on the substrate 100. The substrate 100 may be, for example, a semiconductor substrate including silicon, germanium, or silicon germanium. The device isolation layer ST may include, for example, a silicon oxide layer.

[0019] When the upper portion of the substrate 100 is patterned, active patterns ACT may be formed. Each active pattern ACT may be formed on a surface that is adjacent to the top surface of the substrate 100 (eg, Figure 2A The active pattern ACT may be arranged two-dimensionally along the first direction D1 and the second direction D2. The active patterns ACT may be spaced apart from each other in the third direction D3. In some embodiments, the first direction D1 and the second direction D2 may be parallel to the top surface 100_T and the bottom surface 100_B of the substrate 100, and the first direction D1 may be perpendicular to the second direction D2. It should be understood that each of the first direction D1, the second direction D2, and the third direction D3 may be referred to as a horizontal direction.

[0020] Each active pattern ACT may have a width that decreases in a vertical direction (eg, fourth direction D4) toward the top surface of the substrate 100. The width of each active pattern ACT may decrease as the distance from the bottom surface 100_B of the substrate 100 increases. In some embodiments, the width of each active pattern ACT in the second direction D2 may decrease along the fourth direction D4, such as Figure 2A In some embodiments, the fourth direction D4 may be perpendicular to the top surface 100_T and the bottom surface 100_B of the substrate 100 and all of the first direction D1, the second direction D2, and the third direction D3. It should be understood that the fourth direction D4 may be referred to as a vertical direction.

[0021] A first trench TR1 and a second trench TR2 may be defined between the active patterns ACT. The device isolation layer ST may fill the first trench TR1 and the second trench TR2 between the active patterns ACT. The first trench TR1 may be defined between a pair of active patterns ACT adjacent to each other in a second direction D2. The second trench TR2 may be defined between a pair of active patterns ACT adjacent to each other in a third direction D3. It should be understood that "element A fills element B" (or similar language) used herein means that element A is in element B, but does not necessarily mean that element A completely fills element B. It will also be understood that "a pair of elements adjacent to each other in direction B" (or similar language) used herein may refer to the absence of other similar elements between the two elements A along direction B. For example, as Figure 2AAs shown, the two active patterns ACT defining opposite sides of the first trench TR1 may be referred to as a pair of active patterns ACT adjacent to each other in the second direction D2 because no active pattern ACT exists between the two active patterns ACT along the second direction D2.

[0022] The distance between a pair of active patterns ACT adjacent to each other in the second direction D2 may be smaller than the distance between a pair of active patterns ACT adjacent to each other in the third direction D3. In this way, the second trench TR2 may be deeper than the first trench TR1. For example, the bottom surface (e.g., bottom surface) of the second trench TR2 may be lower than the bottom surface of the first trench TR1. In some embodiments, the depth of the second trench TR2 may be greater than the depth of the first trench TR1, such as Figure 2B shown.

[0023] Each active pattern ACT may include a first segment LP and a second segment UP on the first segment LP. For example, the first segment LP may be a lower portion of the active pattern ACT, and the second segment UP may be an upper portion of the active pattern ACT. It is understood that "segment" used herein means "part".

[0024] Each active pattern ACT may include a first source / drain region SD1 and a pair of second source / drain regions SD2. For example, a second segment UP of the active pattern ACT may include a first source / drain region SD1 and a pair of second source / drain regions SD2. The first source / drain region SD1 may be disposed between the pair of second source / drain regions SD2.

[0025] A pair of third trenches TR3 may be defined on each active pattern ACT. Each third trench TR3 may be defined between the first source / drain region SD1 and the second source / drain region SD2. The third trench TR3 may extend downward from the top surface of the active pattern ACT toward the bottom surface 100_B of the substrate 100 while penetrating the second segment UP of the active pattern ACT. The bottom surface (e.g., bottom surface) of the third trench TR3 may be higher than the bottom surfaces of the first trench TR1 and the second trench TR2.

[0026] Each active pattern ACT may further include a pair of channel regions CH. For example, the first segment LP of the active pattern ACT may include a pair of channel regions CH. When viewed in a plan view, the channel region CH may be disposed between the first source / drain region SD1 and the second source / drain region SD2. The channel region CH may be disposed below the third trench TR3. Therefore, the channel region CH may be located at a lower position than the first source / drain region SD1 and the second source / drain region SD2.

[0027] The gate electrode GE may be disposed across the active pattern ACT and the device isolation layer ST. The gate electrode GE may be disposed in the third trench TR3. The gate electrodes GE may extend parallel to each other in the second direction D2 (e.g., extend longitudinally). A pair of gate electrodes GE may be disposed on a pair of channel regions CH of each active pattern ACT. A top surface of the gate electrode GE may be lower than a top surface 100_T of the active pattern ACT (e.g., a top surface of the first source / drain region SD1 or a top surface of the second source / drain region SD2).

[0028] Return to reference Figure 2C , the gate electrode GE may have an upper portion adjacent to the second segment UP of the active pattern ACT. The gate electrode GE may have a lower portion adjacent to the first segment LP of the active pattern ACT. For example, the lower portion of the gate electrode GE may be adjacent to the channel region CH.

[0029] Return to reference Figure 1 and FIG. 2A to FIG. 2C , the gate dielectric layer GI may be disposed between the gate electrode GE and the active pattern ACT. The gate cap layer GP may be disposed on the gate electrode GE. The gate cap layer GP may cover the top surface of the gate electrode GE. The top surface of the gate cap layer GP may be coplanar with the top surface of the active pattern ACT. It should be understood that "element A covers the surface of element B" (or similar language) used herein means that element A extends on the surface of element B, but does not necessarily mean that element A completely covers the surface of element B.

[0030] The gate electrode GE may include, for example, one or more of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). The gate dielectric layer GI may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. For example, the high-k dielectric material may include hafnium oxide, hafnium oxysilicide, lanthanum oxide, zirconium oxide, zirconium oxysilicide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. The gate cap layer GP may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0031] A first interlayer insulating layer IL1 may be disposed on the substrate 100. The first interlayer insulating layer IL1 may include a first contact hole CNH1 exposing the first source / drain region SD1 of the active pattern ACT.

[0032] A line structure LST extending in the first direction D1 may be disposed on the first interlayer insulating layer IL1. The line structures LST may be spaced apart from each other in the second direction D2. When viewed in a plan view, the line structures LST may cross or traverse the gate electrode GE (see FIG. 1 ). Fig.11A pair of spacers SP may be disposed on opposite sidewalls of each line structure LST. The spacers SP may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0033] Each line structure LST may include a conductive pattern CP, a blocking pattern BP, a bit line BL, and a mask pattern MP sequentially stacked on the substrate 100. The conductive pattern CP may include a contact portion CNP filling the first contact hole CNH1 and contacting the first source / drain region SD1. The blocking pattern BP may reduce or possibly prevent the metal material in the bit line BL from diffusing toward the conductive pattern CP. The bit line BL may be electrically connected to the first source / drain region SD1 through the blocking pattern BP and the conductive pattern CP.

[0034] The conductive pattern CP may include, for example, one of a doped semiconductor material (e.g., doped silicon or doped germanium), a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The blocking pattern BP may include, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The bit line BL may include, for example, a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0035] The second interlayer insulating layer IL2 may be disposed on the first interlayer insulating layer IL1. The second interlayer insulating layer IL2 may cover the spacer SP. The contact CNT may be disposed to penetrate the second interlayer insulating layer IL2 and the first interlayer insulating layer IL1 and be connected to the corresponding second source / drain region SD2. The spacer SP may separate the contact CNT from the bit line BL. The contact CNT may include, for example, one or more of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). In some embodiments, the contact CNT may contact the second source / drain region SD2, such as Figure 2A shown.

[0036] The dielectric layer IL3 and the ESL may be disposed on the second interlayer insulating layer IL2. The dielectric layer IL3 and the ESL may include a third interlayer insulating layer IL3 and an etch stop layer ESL sequentially stacked on the substrate 100. For example, the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and the third interlayer insulating layer IL3 may include a silicon oxide layer, and the etch stop layer ESL may include a silicon nitride layer.

[0037] The landing pad LPD may be arranged to penetrate the third interlayer insulating layer IL3 and be connected to the corresponding contact CNT. The landing pad LPD may be electrically connected to the corresponding second source / drain region SD2 through the contact CNT. The landing pad LPD may not be aligned with the contact CNT. The landing pad LPD may be horizontally offset from the center of the contact CNT. A portion of the bottom surface of the landing pad LPD may be in contact with the top surface of the contact CNT. In some embodiments, the center of the landing pad LPD in the second direction D2 may be offset from the center of the contact CNT in the second direction D2, such as Figure 2A shown.

[0038] The first connection electrode CEL1 may be disposed on a corresponding landing pad LPD. The top surface of each first connection electrode CEL1 may be higher than the top surface of the etch stop layer ESL. For example, the first connection electrode CEL1 may have an upper side wall USW (e.g., an upper portion of the side wall) that is not covered by the etch stop layer ESL. The landing pad LPD may include, for example, a metal. The first connection electrode CEL1 may include, for example, a metal and / or a conductive metal nitride. The term "and / or" used herein includes any and all combinations of one or more of the relevant listed items.

[0039] The capacitor CAP may be disposed on the corresponding first connection electrode CEL1. Each capacitor CAP may include a first electrode EL1, a dielectric pattern DI, and a second electrode EL2. The dielectric pattern DI may be disposed between the first electrode EL1 and the second electrode EL2. The support layer SUP may be disposed to connect the upper portions of the capacitors CAP to each other. The support layer SUP may physically or mechanically support the capacitors CAP. An empty space EPS may be defined and surrounded by the support layer SUP, the capacitor CAP, and the etching stop layer ESL. In some embodiments, the support layer SUP may surround the outer side wall of the upper portion of the capacitor CAP and may not be formed inside the capacitor CAP, such as Figure 1 and Figure 2A Therefore, in some embodiments, the support layer SUP may include a plurality of openings OP, such as Fig.26 It is understood that “element A surrounds element B” (or similar language) used herein means that element A at least partially surrounds element B, but does not necessarily mean that element A completely surrounds element B.

[0040] The dielectric pattern DI may have a cylindrical shape with an open top. When viewed in a plan view, the dielectric pattern DI may have a lower segment DLP shaped like a circle. The dielectric pattern DI may have a sidewall SW extending from the lower segment DLP of the dielectric pattern DI in the fourth direction D4. In some embodiments, the sidewall SW of the dielectric pattern DI may be inclined relative to the fourth direction D4, such as Figure 2AAs shown. The lower segment DLP of the dielectric pattern DI may directly contact the top surface of the first connection electrode CEL1. The dielectric pattern DI may include a high-k dielectric material, such as hafnium oxide, hafnium oxide silicide, lanthanum oxide, zirconium oxide, zirconium oxide silicide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. It should be understood that the "cylindrical shape" used herein refers to a shape including a bottom and two protruding portions protruding from the bottom. It should also be understood that the "cylindrical shape" used herein does not necessarily refer to a shape having two protruding portions parallel to each other, but may refer to a shape having two protruding portions parallel to each other. Figure 2A The shape of the dielectric pattern DI shown in is the same as or similar to that of the dielectric pattern DI shown in .

[0041] The sidewall SW of the dielectric pattern DI may include an outer sidewall OSW and an inner sidewall ISW. The support layer SUP may directly contact an upper portion of the outer sidewall OSW of the dielectric pattern DI, for example, as shown in FIG. Figure 2A and Figure 2C As shown. The support layer SUP may be physically connected to the dielectric pattern DI. The first electrode EL1 may be disposed on the outer sidewall OSW of the dielectric pattern DI, and the second electrode EL2 may be disposed on the inner sidewall ISW of the dielectric pattern DI. The first electrode EL1 and the second electrode EL2 may include, for example, a metal or a conductive metal nitride. For example, the first electrode EL1 and the second electrode EL2 may include the same material as the first connection electrode CEL1.

[0042] The first electrode EL1 may cover the upper side wall USW of the first connection electrode CEL1 and the outer side wall OSW of the dielectric pattern DI. The first electrode EL1 may have a cylindrical shape with a bottom and a top open. The first electrode EL1 may extend upward (e.g., vertically) along the outer side wall OSW of the dielectric pattern DI. The first electrode EL1 may extend from the upper side wall USW of the first connection electrode CEL1 along the outer side wall OSW of the dielectric pattern DI toward the support layer SUP. The first electrode EL1 may not cover the top surface of the etching stop layer ESL. The first electrode EL1 may not cover the bottom surface of the support layer SUP.

[0043] The second electrode EL2 may cover the top surface DTS of the lower segment DLP of the dielectric pattern DI and the inner sidewall ISW of the dielectric pattern DI. The second electrode EL2 may have a cylindrical shape with an open top. The second electrode EL2 may extend upward (e.g., vertically) along the inner sidewall ISW of the dielectric pattern DI. The second electrode EL2 may extend from the top surface DTS of the lower segment DLP of the dielectric pattern DI along the inner sidewall ISW of the dielectric pattern DI toward the support layer SUP. The second electrode EL2 may cover the top surface TS of the dielectric pattern DI. The second electrode EL2 may not cover the top surface of the support layer SUP. The top surface TS of the dielectric pattern DI may be coplanar with the top surface of the support layer SUP.

[0044] The second connection electrode CEL2 may be disposed on the second electrode EL2 and the support layer SUP. The second connection electrode CEL2 may cover the exposed surface of the second electrode EL2 and the exposed top surface of the support layer SUP. The second connection electrode CEL2 may be formed by a deposition process such as physical vapor deposition (PVD) (whose step coverage may be poor). The second connection electrode CEL2 may include, for example, one or more of a doped semiconductor material, a metal material, and a metal-semiconductor compound.

[0045] A residual pattern RP may be provided on the top surface of the lower segment of the second electrode EL2. The residual pattern RP may be formed simultaneously with the second connection electrode CEL2. Therefore, the material of the residual pattern RP may be the same as that of the second connection electrode CEL2. It should be understood that "formed simultaneously" (or similar language) used herein refers to being formed in the same manufacturing step at approximately (but not necessarily completely) the same time.

[0046] Although not shown, a plurality of connection line layers may be provided on the second connection electrode CEL2. Wiring in the connection line layer may be electrically connected to the second connection electrode CEL2 through a contact plug. In this case, one or more wirings in the connection line layer may be electrically connected to the second electrode EL2 of the capacitor CAP.

[0047] According to some exemplary embodiments of the inventive concept, the capacitor CAP may include a dielectric pattern DI shaped like an open cylinder, a first electrode EL1 covering an outer sidewall OSW of the dielectric pattern DI, and a second electrode EL2 covering an inner sidewall ISW of the dielectric pattern DI. Therefore, the capacitor CAP may have a relatively small diameter. The small diameter of the capacitor CAP may increase the integration density of the semiconductor device.

[0048] Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15, Fig.17 , Fig.19 , Fig.21 and Fig.23 Plan views illustrating methods of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept are shown. Figure 4A , Fig. 6A , Fig. 8A , Fig. 10A , Fig. 12A , Fig.14A , Fig.16A , Fig.18A , Fig. 20A , Fig.22A and Fig.24A The Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 and Fig.23 A cross-sectional view taken along line AA'. Figure 4B , Figure 6B , Figure 8B , Fig. 10B , Fig. 12B , Fig. 14B , Fig. 16B , Fig.18B , Fig. 20B , Fig. 22B and Fig. 24B The Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 and Fig.23 A cross-sectional view taken along line BB'. Figure 4C , Figure 6C , Figure 8C , Fig. 10C , Fig. 12C , Fig. 14C , Fig. 16C , Fig.18C , Fig. 20C , Fig. 22C and Fig.24C The Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 and Fig.23 A cross-sectional view taken along line CC'.

[0049] Reference Figure 3 and FIG. 4A to FIG. 4C , the upper portion of the substrate 100 may be patterned (eg, etched) to form active patterns ACT. Each active pattern ACT may be formed parallel to the top surface 100_T of the substrate 100 (see Figure 2A ) in a third direction D3 (eg, longitudinally). The active patterns ACT may be two-dimensionally arranged along the first direction D1 and the second direction D2. The active patterns ACT may be spaced apart from each other in the third direction D3.

[0050] A first trench TR1 and a second trench TR2 may be defined between the active patterns ACT. The first trench TR1 may be defined between a pair of active patterns ACT adjacent to each other in the second direction D2. The second trench TR2 may be defined between a pair of active patterns ACT adjacent to each other in the third direction D3.

[0051] Reference Figure 5 and FIG. 6A to FIG. 6C , a device isolation layer ST may be formed to fill the first trench TR1 and the second trench TR2. In some embodiments, the device isolation layer ST may be formed to completely fill the first trench TR1 and the second trench TR2 and cover the active pattern ACT. A planarization process may be performed on the device isolation layer ST until the top surface of the active pattern ACT is exposed.

[0052] The active pattern ACT and the device isolation layer ST may be patterned to form the third trenches TR3. When viewed in a plan view, each of the third trenches TR3 may have a linear shape extending in the second direction D2 (eg, extending longitudinally).

[0053] The formation of the third trench TR3 may include forming a mask layer (e.g., a hard mask pattern) having an opening, and then etching the exposed active pattern ACT and the device isolation layer ST using the mask layer as an etching mask. The third trench TR3 may be formed to be shallower than the first trench TR1. In some embodiments, the depth of the third trench TR3 is less than the depth of the first trench TR1, such as Figure 6C shown.

[0054] Reference Figure 7 and FIG. 8A to FIG. 8C, a gate dielectric layer GI, a gate electrode GE, and a gate cap layer GP may be formed in each third trench TR3. For example, the gate dielectric layer GI may be conformally formed in each third trench TR3. The gate dielectric layer GI may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material.

[0055] A conductive layer filling the third trench TR3 may be formed on the gate dielectric layer GI to form the gate electrode GE. The conductive layer may include, for example, one or more of a metal and a conductive metal nitride.

[0056] The gate dielectric layer GI and the gate electrode GE may be recessed, and then a gate capping layer GP may be formed on the recessed gate electrode GE. A top surface of the gate capping layer GP may be coplanar with a top surface of the active pattern ACT.

[0057] An ion implantation process may be performed on the active pattern ACT so that a first source / drain region SD1 and a pair of second source / drain regions SD2 may be formed in the second segment UP of the active pattern ACT. The pair of second source / drain regions SD2 may be spaced apart from each other in the third direction D3 across the first source / drain region SD1. For example, the first source / drain region SD1 and the second source / drain region SD2 may be doped with the same impurity. In some embodiments, the first source / drain region SD1 and the second source / drain region SD2 may include impurity atoms (e.g., dopants) having the same conductivity type.

[0058] A channel region CH may be defined in the first segment LP of the active pattern ACT, and the first segment LP is located under the gate electrode GE. When viewed in a plan view, the channel region CH may be disposed between the first source / drain region SD1 and the second source / drain region SD2. The gate electrode GE may be disposed on the top surface and opposite sidewalls of the channel region CH.

[0059] Reference Fig. 9 and FIG. 10A to FIG. 10C A first interlayer insulating layer IL1 may be formed on the substrate 100 (eg, the entire surface of the substrate 100). For example, the first interlayer insulating layer IL1 may include a silicon oxide layer. The first interlayer insulating layer IL1 may be patterned (eg, etched) to form a first contact hole CNH1 exposing the first source / drain region SD1 of the active pattern ACT.

[0060] The first conductive layer CL1, the barrier layer BAL, and the second conductive layer CL2 may be sequentially formed on the first interlayer insulating layer IL1. The first conductive layer CL1 may fill the first contact hole CNH1. For example, the first conductive layer CL1 may contact the first source / drain region SD1 of the active pattern ACT. The first interlayer insulating layer IL1 may separate the first conductive layer CL1 from the second source / drain region SD2 of the active pattern ACT in a vertical direction. The first conductive layer CL1 may include, for example, one of a doped semiconductor material, a metal material, and a metal-semiconductor compound.

[0061] The barrier layer BAL may be formed between the first conductive layer CL1 and the second conductive layer CL2. The barrier layer BAL may include, for example, a conductive metal nitride. The second conductive layer CL2 may include, for example, a metal material. The barrier layer BAL may reduce or prevent the metal material in the second conductive layer CL2 from diffusing toward the first conductive layer CL1.

[0062] Reference Fig.11 and FIG. 12A to FIG. 12C , line structures LST extending in the first direction D1 (eg, extending longitudinally) may be formed on the first interlayer insulating layer IL1 , and the line structures LST may be spaced apart from each other in the second direction D2 .

[0063] For example, the mask pattern MP may be formed on the second conductive layer CL2. The mask pattern MP may be formed to have a linear shape extending in the first direction D1 (eg, extending longitudinally). For example, the mask pattern MP may include a silicon nitride layer or a silicon oxynitride layer.

[0064] The mask pattern MP may be used as an etching mask to sequentially etch the second conductive layer CL2, the barrier layer BAL, and the first conductive layer CL1 to form a bit line BL, a barrier pattern BP, and a conductive pattern CP, respectively. The mask pattern MP, the bit line BL, the barrier pattern BP, and the conductive pattern CP may overlap each other in a vertical direction. The mask pattern MP, the bit line BL, the barrier pattern BP, and the conductive pattern CP may constitute a line structure LST. When viewed in a plan view, the bit line BL may extend while crossing the gate electrode GE.

[0065] The conductive pattern CP may include a contact portion CNP filling the first contact hole CNH1. The conductive pattern CP may be connected to the first source / drain region SD1 through the contact portion CNP. For example, the bit line BL may be electrically connected to the first source / drain region SD1 through the conductive pattern CP.

[0066] A pair of spacers SP may be formed on opposite sidewalls of each line structure LST. The formation of the spacers SP may include conformally forming a spacer layer on the substrate 100 (eg, the entire surface of the substrate 100), and performing an anisotropic etching process on the spacer layer.

[0067] Reference Fig.13 and FIG. 14A to FIG. 14C , a second interlayer insulating layer IL2 may be formed on the substrate 100. For example, the second interlayer insulating layer IL2 may include a silicon oxide layer. A planarization process may be performed on the second interlayer insulating layer IL2 until a top surface of the mask pattern MP is exposed.

[0068] The second interlayer insulating layer IL2 and the first interlayer insulating layer IL1 may be patterned (e.g., etched) to form a second contact hole CNH2 exposing the second source / drain region SD2 of the active pattern ACT. The second contact hole CNH2 may be filled with a conductive material so that a contact CNT may be formed in the corresponding second contact hole CNH2. The contact CNT may be connected to the second source / drain region SD2.

[0069] Reference Fig.15 and FIG. 16A to FIG. 16C , a third interlayer insulating layer IL3, an etch stop layer ESL, and a sacrificial layer SAC may be formed and sequentially stacked on the second interlayer insulating layer IL2. For example, the third interlayer insulating layer IL3 may include a silicon oxide layer, the etch stop layer ESL may include a silicon nitride layer, and the sacrificial layer SAC may include a silicon oxide layer.

[0070] The third interlayer insulating layer IL3, the etch stop layer ESL, and the sacrificial layer SAC may be patterned (e.g., etched) to form pad holes LPH. Each pad hole LPH may partially expose the top surface of the contact CNT. The pad hole LPH may be offset from the corresponding contact CNT. In some embodiments, the center of the pad hole LPH in the second direction D2 may be offset from the center of the corresponding contact CNT in the second direction D2, such as Fig.16A shown.

[0071] Reference Fig.17 and 18A to 18C , a landing pad LPD may be formed to fill a corresponding one of the pad holes LPH, and a first connection electrode CEL1 may be formed on the landing pad LPD. The formation of the landing pad LPD may include forming a first metal layer to fill the pad hole LPH, and recessing the first metal layer. The formation of the first connection electrode CEL1 may include forming a second metal layer on the landing pad LPD to fill the pad hole LPH, and performing a planarization process on the second metal layer until the top surface of the sacrificial layer SAC is exposed. For example, the first metal layer may include a metal, and the second metal layer may include a metal or a conductive metal nitride.

[0072] The mold layer MOL and the support layer SUP may be formed and sequentially stacked on the sacrificial layer SAC. For example, the mold layer MOL may include a polysilicon layer, and the support layer SUP may include a silicon nitride layer.

[0073] Reference Fig.19 and FIG. 20A to FIG. 20C The support layer SUP and the mold layer MOL may be patterned (eg, etched) to form capacitor holes CAH. The capacitor holes CAH may expose top surfaces of the first connection electrodes CEL1, respectively. For example, the capacitor holes CAH may overlap with the corresponding first connection electrodes CEL1 in a vertical direction.

[0074] The dielectric layer DIL may be conformally formed to partially fill the capacitor hole CAH. The dielectric layer DIL may cover the inner sidewall of the capacitor hole CAH and the top surface of the first connection electrode CEL1. The dielectric layer DIL may include a high-k dielectric material.

[0075] Reference Fig.21 and FIG. 22A to FIG. 22C , a planarization process may be performed on the dielectric layer DIL until the top surface of the support layer SUP is exposed, so that the dielectric layer DIL may be formed into a plurality of dielectric patterns DI. The dielectric patterns DI may be disposed in the corresponding capacitor holes CAH. Each dielectric pattern DI may have a cylindrical shape with an open top.

[0076] The mold layer MOL may be selectively removed to form an empty space EPS. The mold layer MOL may be selectively removed by an etching process using an etching recipe that selectively etches the mold layer MOL but does not etch the dielectric pattern DI, the support layer SUP, and the sacrificial layer SAC. For example, the removal of the mold layer MOL may use a wet and / or dry cleaning process.

[0077] Reference Fig.23 and FIG. 24A to FIG. 24C , selective removal may be performed on the sacrificial layer SAC exposed to the empty space EPS. The sacrificial layer SAC may be selectively removed by an etching process using an etching recipe that selectively etches the sacrificial layer SAC but does not etch the dielectric pattern DI, the support layer SUP, and the etching stop layer ESL. For example, the removal of the sacrificial layer SAC may use a chemical oxide removal (COR) mechanism of dry cleaning. Because the sacrificial layer SAC is removed, the empty space EPS may expose a portion of the upper side wall USW (e.g., the upper portion of the side wall) and the top surface of the first connection electrode CEL1.

[0078] The first electrode EL1 and the second electrode EL2 may be selectively formed on the dielectric pattern DI and the first connection electrode CEL1. The first electrode EL1 may be selectively formed on the outer sidewall OSW of the first connection electrode CEL1 and the dielectric pattern DI. The second electrode EL2 may be selectively formed on the inner sidewall ISW and the top surface TS of the dielectric pattern DI. Both the first electrode EL1 and the second electrode EL2 may not be formed on the support layer SUP and the etch stop layer ESL.

[0079] The formation of the first electrode EL1 and the second electrode EL2 may include forming a third metal layer using a deposition process in which a deposition material is selectively deposited on the metal material (e.g., the first connection electrode CEL1) and the high-k dielectric material (e.g., the dielectric pattern DI). The third metal layer may include, for example, a metal or a conductive metal nitride.

[0080] In some embodiments, a self-assembled layer may be selectively formed on the silicon nitride layer (e.g., the support layer SUP and the etching stop layer ESL). For example, a monolayer including an alkylsiloxane may be selectively formed on the surface of the silicon nitride layer. A relatively long incubation time may be required to deposit a third metal layer on the silicon nitride layer formed with the self-assembled layer. The incubation time of the silicon nitride layer on which the self-assembled layer is formed may be used to selectively form a third metal layer on the first connection electrode CEL1 and the dielectric pattern DI.

[0081] In some embodiments, an etching process may be performed after performing a deposition process. The deposition rate of the metal precursor may depend on the type of the underlying layer. The third metal layer may be formed thicker on the first connection electrode CEL1 and the dielectric pattern DI, and thinner on the support layer SUP and the etching stop layer ESL. Afterwards, a dry etching process may be performed until the third metal layer is completely removed from the support layer SUP and the etching stop layer ESL. In this case, the third metal layer may remain on the first connection electrode CEL1 and the dielectric pattern DI, and thus may constitute the first electrode EL1 and the second electrode EL2. In order to form a thicker third metal layer, a cycle including a deposition process and an etching process may be repeatedly performed.

[0082] For example, when a ruthenium precursor is used in the deposition process, ruthenium may be relatively thickly deposited on the first connection electrode CEL1 and the dielectric pattern DI. 4 ) is used in the deposition process, titanium or titanium nitride may be relatively thickly deposited on the first connection electrode CEL1 and the dielectric pattern DI.

[0083] Return to reference Figure 1 and FIG. 2A to FIG. 2C, the second connection electrode CEL2 may be formed on the second electrode EL2. The second connection electrode CEL2 may be formed by a deposition process such as physical vapor deposition (PVD) (whose step coverage may be poor). The second connection electrode CEL2 may include, for example, one or more of a doped semiconductor material, a metal material, and a metal-semiconductor compound. During the deposition process, a residual pattern RP may be formed on the top surface of the lower segment of the second electrode EL2. In some embodiments, the second connection electrode CEL2 and the residual pattern RP may include the same material.

[0084] Although not shown, a plurality of connection line layers may be formed on the second connection electrode CEL2. A contact plug may be formed to electrically connect the second connection electrode CEL2 to the wiring in the connection line layer.

[0085] Fig.25 and Fig.26 Shown along Figure 1 The cross-sectional view taken along the line AA' of FIG. 1 shows a semiconductor device according to some exemplary embodiments of the present invention. Figure 1 and FIG. 2A to FIG. 2C A detailed description of the technical features discussed will be omitted, and the detailed discussion will be related to the above referenced Figure 1 and FIG. 2A to FIG. 2C The differences in the technical characteristics of the semiconductor devices under discussion.

[0086] Reference Fig.25 , the capacitor CAP may be misaligned with the first connection electrode CEL1. The capacitor CAP may be horizontally offset from the center of the first connection electrode CEL1. The dielectric pattern DI may partially cover the top surface of the first connection electrode CEL1. The top surface CTS of the first connection electrode CEL1 may be exposed by the dielectric pattern DI. The first electrode EL1 may cover not only the upper side wall USW of the first connection electrode CEL1, but also the exposed top surface CTS of the first connection electrode CEL1. The first electrode EL1 may partially cover the bottom surface of the dielectric pattern DI.

[0087] Reference Fig.26 , the support layer SUP may have at least one opening OP. When viewed in a plan view, the opening OP may be formed between adjacent dielectric patterns DI.

[0088] The opening OP may be sealed with the second connection electrode CEL2 on the support layer SUP. Because the second connection electrode CEL2 is formed by a deposition process with poor step coverage, the opening OP may allow a conductive material to be deposited on the etch stop layer ESL when the second connection electrode CEL2 is formed. Therefore, the residual pattern RP may be disposed on the etch stop layer ESL. The residual pattern RP on the etch stop layer ESL may overlap with the opening OP in the vertical direction.

[0089] According to the inventive concept, a capacitor can be formed to have a relatively small diameter. The small diameter of the capacitor can increase the integration density of a semiconductor device.

[0090] Although the inventive concept has been described in conjunction with some exemplary embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential features of the inventive concept. Therefore, the foregoing detailed description should be considered illustrative rather than restrictive, and therefore, to the maximum extent permitted by law, the scope of the inventive concept is determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be limited or restricted by the foregoing detailed description.

Claims

1. A semiconductor device, comprising: an active pattern on a substrate, the active pattern comprising a first source / drain region and a second source / drain region; a bit line electrically connected to the first source / drain region; a first connection electrode electrically connected to the second source / drain region; a capacitor on the first connecting electrode, the capacitor comprising a first electrode, a second electrode, and a dielectric pattern between the first electrode and the second electrode; as well as a supporting layer contacting an outer sidewall of the dielectric pattern and including a lower surface facing the substrate and an upper surface opposite to the lower surface, wherein the second electrode does not cover the upper surface of the support layer, wherein the lower portion of the dielectric pattern overlaps with the top surface of the first connecting electrode, and The first electrode extends from the dielectric pattern to an upper portion of a sidewall of the first connecting electrode.

2. The semiconductor device according to claim 1, wherein The dielectric pattern has a cylindrical shape with an open top.

3. The semiconductor device according to claim 1, wherein The first electrode extends on the outer sidewall of the dielectric pattern, and The second electrode extends on an inner sidewall of the dielectric pattern.

4. The semiconductor device according to claim 1, further comprising an insulating layer between the first connection electrode and the bit line, in, The top surface of the first connection electrode is higher than the top surface of the insulating layer, and Wherein, the upper portion of the side wall of the first connecting electrode protrudes beyond the top surface of the insulating layer.

5. The semiconductor device according to claim 1, wherein The supporting layer supports the capacitor and contacts an upper portion of an outer sidewall of the dielectric pattern.

6. The semiconductor device according to claim 5, wherein: An upper surface of the support layer is coplanar with a top surface of the dielectric pattern.

7. The semiconductor device according to claim 5, further comprising: a second connecting electrode, which is on the second electrode and the supporting layer; as well as a residual pattern including the same material as that of the second connection electrode and spaced apart from the support layer in a vertical direction, wherein the support layer comprises an opening, and The residual pattern overlaps the opening.

8. The semiconductor device according to claim 1, wherein The center of the dielectric pattern is offset from the center of the first connecting electrode, wherein the top surface of the first connection electrode includes an exposed portion that does not overlap with the dielectric pattern, and Wherein, the first electrode extends on the exposed portion of the top surface of the first connecting electrode.

9. The semiconductor device according to claim 1, wherein: The lower portion of the dielectric pattern contacts the top surface of the first connection electrode.

10. A semiconductor device comprising: an active pattern on a substrate, the active pattern comprising a first source / drain region and a second source / drain region; a bit line electrically connected to the first source / drain region; a connecting electrode electrically connected to the second source / drain region; a capacitor on the connecting electrode, the capacitor comprising a first electrode, a second electrode, and a dielectric pattern between the first electrode and the second electrode; as well as a supporting layer contacting an outer sidewall of the dielectric pattern and including a lower surface facing the substrate and an upper surface opposite to the lower surface, wherein the first electrode extends upward from the upper portion of the side wall of the connecting electrode along the outer side wall of the dielectric pattern, and The second electrode extends upward from the top surface of the lower portion of the dielectric pattern along the inner sidewall of the dielectric pattern and does not cover the upper surface of the support layer.

11. The semiconductor device according to claim 10, wherein: The lower portion of the dielectric pattern overlaps a top surface of the connection electrode.

12. The semiconductor device according to claim 10, further comprising an insulating layer between the connection electrode and the bit line, in, The top surface of the connecting electrode is higher than the top surface of the insulating layer, and Wherein, the upper portion of the side wall of the connecting electrode protrudes beyond the top surface of the insulating layer.

13. The semiconductor device according to claim 10, in, The supporting layer supports the capacitor and contacts an upper portion of the outer sidewall of the dielectric pattern.

14. The semiconductor device according to claim 13, wherein: An upper surface of the support layer is coplanar with a top surface of the dielectric pattern.

15. A semiconductor device comprising: a plurality of transistors on a substrate; a plurality of capacitors electrically connected to the plurality of transistors, respectively; as well as a supporting layer contacting upper portions of the plurality of capacitors, wherein each of the plurality of capacitors comprises a first electrode, a second electrode, and a dielectric pattern between the first electrode and the second electrode, and the dielectric pattern has a cylindrical shape with an open top, and wherein the support layer contacts an upper portion of an outer sidewall of the dielectric pattern of one of the plurality of capacitors and includes a lower surface facing the substrate and an upper surface opposite to the lower surface, Wherein, the second electrode does not cover the upper surface of the supporting layer.

16. The semiconductor device according to claim 15, wherein: An upper surface of the support layer is coplanar with a top surface of the dielectric pattern.

17. The semiconductor device according to claim 15, wherein: The first electrode extends on the outer sidewall of the dielectric pattern, the second electrode extends on the inner sidewall of the dielectric pattern, and the inner sidewall of the dielectric pattern is opposite to the outer sidewall of the dielectric pattern.

18. The semiconductor device according to claim 17, wherein: The plurality of capacitors include a first capacitor and a second capacitor adjacent to each other, and The second electrode of the first capacitor and the second electrode of the second capacitor are spaced apart from each other.

19. The semiconductor device according to claim 15, further comprising a plurality of connection electrodes between the plurality of transistors and the plurality of capacitors, in, A lower portion of the dielectric pattern of the one of the plurality of capacitors overlaps a portion of a top surface of one of the plurality of connection electrodes, and The first electrode of the one of the plurality of capacitors extends on an upper portion of a side wall of the one of the plurality of connecting electrodes.

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