Display Panel

Abstract

The display panel may include a first hole, a second hole, a display element, a switch element, a wiring, and a conductive member. The second hole may be spaced apart from the first hole. The switch element may be electrically connected to the display element. The wiring may bypass the first hole in a plan view of the display panel and may be electrically connected to the switch element. The conductive member may surround each of the first hole and the second hole in a plan view of the display panel, may have an opening between the first hole and the second hole in a plan view of the display panel, and may partially cover the wiring. An edge portion of the conductive member may intersect with the wiring and may be placed between the display element and the first hole in a plan view of the display panel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0154782 filed in the Korean Intellectual Property Office on December 4, 2018; the disclosure of which is incorporated herein by reference in its entirety.

[0003] The technical field relates to a display panel and a display device including the display panel. Background Art

[0004] A display device generally has a display area for displaying an image. The display device may include a display panel for displaying an image.

[0005] The display device can perform one or more additional functions in the display area. For example, in addition to displaying images, the display area can also receive user input. Summary of the invention

[0006] One or more embodiments include a display panel including a display area including a plurality of openings or having functional components arranged therein. Embodiments may be related to a display device including the display panel.

[0007] According to one or more embodiments, a display panel includes the following elements: a substrate including a first area and a second area, a non-display area surrounding the first area and the second area, and a display area surrounding the non-display area; a plurality of display elements in the display area; a plurality of wirings bypassing at least a portion of an edge of each of the first area and the second area in the non-display area; and an electrode layer covering at least one of the plurality of wirings in the non-display area and having at least one opening between the first area and the second area.

[0008] The plurality of wirings may include a plurality of data lines extending in the first direction and applying data signals to the plurality of display elements.

[0009] The at least one opening may have a first width in the first direction and a second width in the first direction, and the first width may be different from the second width.

[0010] The at least one opening may have a first edge crossing the data line, and at least a portion of the first edge is a curved line.

[0011] The electrode layer may include a plurality of holes spaced apart from each other, and a size of each of the plurality of holes may be smaller than a size of the at least one opening.

[0012] The electrode layer may include a plurality of holes spaced apart from each other, and at least one of the plurality of holes may overlap with one or more of a plurality of wirings that bypass at least a portion of an edge of each of the first and second regions in the non-display region.

[0013] The at least one opening may not overlap with one or more wirings of the plurality of wirings that detour at least a portion of an edge of each of the first region and the second region in the non-display region.

[0014] The plurality of wirings may include: a plurality of data lines extending in a first direction and applying data signals to a plurality of display elements; and a plurality of initialization voltage lines extending in a second direction crossing the first direction and connected to the electrode layer, and the plurality of initialization voltage lines may have a constant voltage.

[0015] The electrode layer may have a constant voltage.

[0016] The plurality of display elements may include a pixel electrode, a counter electrode, and an emission layer between the pixel electrode and the counter electrode.

[0017] The electrode layer may include the same material as the pixel electrode.

[0018] The electrode layer may include a hole corresponding to each of the first region and the second region.

[0019] According to one or more embodiments, the display panel includes the following elements: a substrate including a first area and a second area, a non-display area surrounding the first area and the second area, and a display area surrounding the non-display area; a plurality of display elements arranged in the display area and each including a pixel electrode, a counter electrode, and an emission layer between the pixel electrode and the counter electrode; a plurality of wirings bypassing at least a portion of an edge of each of the first area and the second area in the non-display area; and an electrode layer covering at least one of the plurality of wirings in the non-display area and having at least one opening that crosses a virtual line connecting the center of the first area and the center of the second area and extends in a second direction.

[0020] The multiple wirings may include multiple data lines that extend in a first direction intersecting the second direction and apply data signals to multiple display elements, the multiple data lines may include a first data line and a second data line corresponding to at least one opening, and the size of an area of ​​the first data line overlapping the electrode layer may be different from the size of an area of ​​the second data line overlapping the electrode layer.

[0021] The electrode layer may include a plurality of holes spaced apart from each other, and at least one hole of the plurality of holes may surround the first region and the second region.

[0022] The plurality of wirings may include: a plurality of data lines extending in a first direction crossing the second direction and applying data signals to the plurality of display elements; and a plurality of initialization voltage lines extending in the first direction and connected to the electrode layer.

[0023] The plurality of initialization voltage lines may have a constant voltage, and the electrode layer may have the same voltage level as the plurality of initialization voltage lines.

[0024] The electrode layer may include the same material as the pixel electrode.

[0025] The display panel may further include an organic insulating layer under the electrode layer, and the electrode layer may expose at least a portion of the organic insulating layer through the at least one opening.

[0026] The display panel may further include: at least one groove provided in the non-display area and closer to the first area and the second area than the plurality of wirings; and an encapsulation layer covering the plurality of display elements and including an inorganic encapsulation layer and an organic encapsulation layer.

[0027] Embodiments may be associated with a display panel. The display panel may include a first hole, a second hole, a display element, a switching element, a first wiring, and a conductive member. The second hole may be spaced apart from the first hole. The switching element may be electrically connected to the display element. The first wiring may bypass the first hole in a plan view of the display panel and may be electrically connected to the switching element. The conductive member may surround each of the first hole and the second hole in a plan view of the display panel, may have a first opening between the first hole and the second hole in a plan view of the display panel, and may partially cover the first wiring. A first edge portion of the conductive member may intersect with the first wiring and may be placed between the display element and the first hole in a plan view of the display panel.

[0028] The first wiring may be a data line electrically connected to a source electrode of the switching element to apply a data signal to the display element.

[0029] The first opening may have a first width in the first direction and may have a second width in the first direction. The first width may not be equal to the second width.

[0030] The first opening may have a first edge crossing the data line and including at least a bent portion.

[0031] The conductive member may include holes spaced apart from each other. Each of the holes may be smaller than the first opening in a plan view of the display panel.

[0032] The conductive member includes holes spaced apart from each other. At least one of the holes may partially expose the first wiring.

[0033] The first opening may be spaced apart from the first wiring in a plan view of the display panel.

[0034] The display panel may further include an initialization voltage line electrically connected to the conductive member and configured to supply a constant voltage to the conductive member.

[0035] The conductive member may have a constant voltage not equal to 0V.

[0036] The display element may include a pixel electrode, a counter electrode, and an emission layer between the pixel electrode and the counter electrode.

[0037] The material of the conductive member may be the same as that of the pixel electrode.

[0038] The conductive member may include a third hole and a fourth hole corresponding to the first hole and the second hole, respectively.

[0039] An edge of the first opening may intersect a geometric line connecting a center of the first region and a center of the second region.

[0040] The display panel may include the following elements: a first data line intersecting the first opening and configured to transmit a first data signal; and a second data line intersecting the first opening and configured to transmit a second data signal. The total overlap between the first data line and the conductive member may be greater than the total overlap between the second data line and the conductive member.

[0041] The conductive member may include a third hole and a fourth hole that are spaced apart from each other and respectively surround the first hole and the second hole in a plan view of the display panel.

[0042] The first wiring may be electrically connected to the gate electrode of the switching element and may also bypass the second hole in a plan view of the display panel.

[0043] The display panel may include an initialization voltage line extending in a direction and having a constant voltage not equal to 0 V. The first opening may be located between the first hole and the second hole in the direction. The conductive member may have a constant voltage.

[0044] The bent portion of the first wiring may be covered by the conductive member and may be spaced apart from the first opening in a plan view of the display panel.

[0045] The display panel may include an organic insulating layer overlapping the conductive member. The conductive member may expose at least a portion of the organic insulating layer through the first opening.

[0046] The display panel may include a groove and an encapsulation layer. A portion of the groove may be placed between the first hole and a portion of the first wiring. The encapsulation layer may cover the display element, may include an inorganic encapsulation layer, and may include an organic encapsulation layer. A portion of the encapsulation layer may be placed inside the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a schematic perspective view of a display device according to an embodiment.

[0048] Figure 2A is a cross-sectional view of a display panel according to an embodiment.

[0049] Figure 2B is a cross-sectional view of a display panel according to an embodiment.

[0050] Figure 2C is a cross-sectional view of a display panel according to an embodiment.

[0051] Figure 3A is a cross-sectional view of a display panel according to an embodiment.

[0052] Figure 3B is a cross-sectional view of a display panel according to an embodiment.

[0053] Figure 3C is a cross-sectional view of a display panel according to an embodiment.

[0054] Figure 4 is a schematic plan view of a display panel according to an embodiment.

[0055] Figure 5A is an equivalent circuit diagram of a pixel according to the embodiment.

[0056] Figure 5B is an equivalent circuit diagram of a pixel according to the embodiment.

[0057] Figure 6 is a schematic plan view of a pixel circuit according to an embodiment.

[0058] Figure 7 is a schematic plan view of (a portion of) a display panel according to an embodiment.

[0059] Figure 8 According to the embodiment Figure 7 A cross-sectional view taken along line AA' and line BB'.

[0060] Fig. 9 According to the embodiment Figure 8 A cross-sectional view of a portion of a display panel.

[0061] Fig. 10A According to the embodiment Figure 7Plan view of area V.

[0062] Fig. 10B According to the embodiment Figure 7 Plan view of area V.

[0063] Fig.11 According to the embodiment Figure 7 Plan view of area W.

[0064] Fig.12 According to the embodiment Fig.11 A cross-sectional view taken along line CC'.

[0065] Fig.13 is a schematic plan view of (a portion of) a display panel according to an embodiment.

[0066] Fig.14 According to the embodiment Fig.13 A cross-sectional view taken along line XIV-XIV'.

[0067] Fig.15 is a schematic plan view of (a portion of) a display panel according to an embodiment.

[0068] Fig.16 is a schematic plan view of (a portion of) a display panel according to an embodiment. DETAILED DESCRIPTION

[0069] The exemplary embodiments are described with reference to the drawings. All changes, equivalents and substitutes are possible without departing from the spirit and technical scope of the exemplary embodiments.

[0070] Although the terms "first", "second", etc. can be used to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Without departing from the teaching of one or more embodiments, the first element can be referred to as the second element. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used herein to distinguish different categories or groups of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first type (or first group)", "second type (or second group)", etc.

[0071] When a first element is referred to as being “on” a second element, the first element may be directly or indirectly on the second element, and one or more intervening elements may be present between the first element and the second element.

[0072] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0073] The same reference numerals may refer to the same elements in this application. The term "and / or" may include any and all combinations of one or more related items. A statement such as "at least one of...", when following a list of elements, may modify the entire list of elements and may not modify individual elements in the list. The sizes of elements in the figures may be exaggerated for ease of explanation.

[0074] The term "device" may mean "equipment". The term "conductive" may mean "electrically conductive". The term "trace" may mean "conductive line". The term "connection" may mean "electrical connection". The term "insulation" may mean "electrical insulation". The term "opening" may mean "hole". The term "opening area" may mean "opening". The term "same as..." may mean "equal to...". The term "different" may mean "not equal to". The term "contact" may mean "direct contact". The term "first area" may mean "area corresponding to the first hole", "area of ​​the first hole" or "first hole". The term "second area" may mean "area corresponding to the second hole", "area of ​​the second hole" or "second hole". The expression that a hole / opening overlaps an element may mean that the hole / opening (at least partially) exposes the element, and / or that the hole / opening is located above the element. The term "separate" may mean "spaced apart". The term "electrode layer" may mean "conductive member".

[0075] Figure 1 is a schematic perspective view of a display device 1 according to the embodiment.

[0076] refer to Figure 1 , the display device 1 may include a display area DA for emitting light, and may include a non-display area NDA that does not emit light.

[0077] The display device 1 may provide an image at the display area DA. The display device 1 may include one of a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a quantum dot light emitting display, a field emission display, a surface conductive electron emitter display, a plasma display, a cathode ray display, etc. An organic light emitting display device is described as an example.

[0078] The display device 1 may include a first area OA1 and a second area OA2. The first area OA1 and the second area OA2 are where electronic components are arranged. The first area OA1 and the second area OA2 may include / may be a cavity, an opening area, and / or a transmission area through which light and / or sound may be output or received by the electronic components. Figure 1 The figure shows that there are two openings or transmissive areas, namely a first area OA1 and a second area OA2. There may be three or more transmissive areas.

[0079] According to an embodiment, when light passes through the first area OA1 or the second area OA2 , light transmittance may be equal to or greater than about 50%, more preferably, equal to or greater than about 70%, about 75%, about 80%, or about 85%.

[0080] The non-display area NDA may include a first non-display area NDA1 surrounding the first area OA1 and the second area OA2, and a second non-display area NDA2 surrounding the display area DA. The first non-display area NDA1 may substantially surround the first area OA1 and the second area OA2, the display area DA may substantially surround the first non-display area NDA1, and the second non-display area NDA2 may substantially surround the display area DA.

[0081] Figure 1 The figure shows that the first area OA1 and the second area OA2 are arranged at the upper right side of the display area DA. According to embodiments, the first area OA1 and the second area OA2 may be placed at other locations.

[0082] FIG. 2A to FIG. 2C According to the embodiment Figure 1 A cross-sectional view taken along line II-II'.

[0083] refer to Figure 2A The display device 1 may include a display panel 10 including a display element such as an organic light emitting diode OLED. The display panel 10 may include a first electronic element 20 and a second electronic element 30 corresponding to a first area OA1 and a second area OA2 of the display panel 10, respectively. Although not shown, components such as an input sensing member for sensing a touch input, an anti-reflection member including a polarizer and a retarder, a color filter and a black matrix, and a transparent window may be further arranged on the display panel 10.

[0084] The display panel 10 may include a substrate 100 , an encapsulation substrate 400A facing the substrate 100 , and a sealing member 450 between the substrate 100 and the encapsulation substrate 400A.

[0085] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose acetate propionate (CAP), etc. The substrate 100 including the polymer resin may be flexible, rollable or bendable. The substrate 100 may have a multilayer structure including a layer including the above-mentioned polymer resin and an inorganic layer (not shown). The encapsulation substrate 400A may include glass or the above-mentioned polymer resin.

[0086] The thin film transistor TFT, the organic light emitting diode OLED connected to the thin film transistor TFT, and the signal line SGL may be arranged in the display area DA of the substrate 100. The signal line SGL and the dummy thin film transistor TFT′ may be arranged in the first non-display area NDA1 of the substrate 100.

[0087] The signal lines SGL may provide specific signals (eg, data signals, scan signals, etc.) to the display elements spaced apart from each other.

[0088] The display panel 10 may include through holes corresponding to the first area OA1 and the second area OA2. For example, the substrate 100 and the encapsulation substrate 400A may include through holes 100H and 400AH corresponding to the first area OA1 and the second area OA2, respectively. A portion of the insulating layer IL or a component between the substrate 100 and the encapsulation substrate 400A corresponding to the first area OA1 and the second area OA2 may be removed.

[0089] Figure 2A The figure shows that the sealing member 450 is arranged at the side of the first area OA1 and the side of the second area OA2 in the cross-sectional view. Each of the first area OA1 and the second area OA2 is substantially surrounded by the sealing member 450 in the plan view.

[0090] The first electronic component 20 and the second electronic component 30 may be located in the first area OA1 and the second area OA2, respectively. The first electronic component 20 and the second electronic component 30 may be electronic components that use and / or generate light or sound. For example, at least one of the electronic components may be a sensor that receives and uses light, such as an infrared sensor, a camera that captures an image by receiving light, a sensor that measures distance or recognizes fingerprints (by outputting and sensing light or sound), a small lamp that outputs light, a speaker that outputs sound, and the like. In an embodiment, light of a predetermined wavelength range may be used, such as one or more of visible light, infrared light, ultraviolet light, and the like.

[0091] When the display panel 10 is Figure 2AWhen the through holes 100H and 400AH corresponding to the first area OA1 and the second area OA2 are included as shown in FIG. 5 , light or sound may be effectively output or received through the first electronic component 20 and the second electronic component 30 .

[0092] refer to Figure 2B , although the package substrate 400A may include the through holes 400AH corresponding to the first area OA1 and the second area OA2, the substrate 100 may not include the through holes. Figure 2C , the substrate 100 and the package substrate 400A may not include any through holes corresponding to the first area OA1 and the second area OA2. Figure 2B and Figure 2C When the through hole 100H is not included as shown in the figure, the light transmission for the first electronic component 20 and the second electronic component 30 can also be optimized by removing at least a portion of the insulating layer IL or a component corresponding to the first area OA1 and the second area OA2 between the substrate 100 and the packaging substrate 400A. Figure 2B and Figure 2C In the display panel 10 shown in FIG. 1 , the first electronic component 20 and the second electronic component 30 may be electronic components using light.

[0093] FIG. 3A to FIG. 3C According to the embodiment Figure 1 A cross-sectional view taken along line II-II'.

[0094] refer to Figure 3A , and the above reference Figure 2A Similar to the display device 1 described above, the display device 1 may include a display panel 10 including a display element, and may include a first electronic element 20 and a second electronic element 30 respectively corresponding to the first area OA1 and the second area OA2 of the display panel 10. Although not shown, the display device 1 may further include an input sensing member, an anti-reflection member, a window, etc., arranged on the display panel 10 for sensing a touch input.

[0095] The display panel 10 may include the thin film encapsulation layer 400B so that the flexibility of the display panel 10 may be optimized.

[0096] The thin film encapsulation layer 400B may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 3A The diagram illustrates a first inorganic encapsulating layer 410 , a second inorganic encapsulating layer 430 , and an organic encapsulating layer 420 between the first inorganic encapsulating layer 410 and the second inorganic encapsulating layer 430 .

[0097] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may include one or more inorganic insulating materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 420 may include a polymer material. The polymer material may include one of an acryl resin, an epoxy resin, PI, polyethylene, and the like.

[0098] The display panel 10 may include through holes 100H and 400BH corresponding to the first and second areas OA1 and OA2. For example, the substrate 100 and the thin film encapsulation layer 400B may include through holes 100H and 400BH corresponding to the first and second areas OA1 and OA2. The first and second electronic components 20 and 30 that use and / or generate light and / or sound may be arranged in the first and second areas OA1 and OA2.

[0099] refer to Figure 3B , although the thin film encapsulation layer 400B may include the through holes 400BH corresponding to the first area OA1 and the second area OA2, the substrate 100 may not include the through holes. Figure 3C , the substrate 100 and the thin film encapsulation layer 400B may not include any through holes corresponding to the first area OA1 and the second area OA2. Figure 3B and Figure 3C When the through hole 100H is not included as shown in FIG, light transmission for the first electronic component 20 and the second electronic component 30 may also be optimized by removing at least a portion of the insulating layer IL or a component between the substrate 100 and the thin film encapsulation layer 400B corresponding to the first area OA1 and the second area OA2.

[0100] When the thin film encapsulation layer 400B is Figure 3A and Figure 3B When the through hole 400BH is included as shown in FIG, each of the at least one inorganic encapsulation layer and the at least one organic encapsulation layer may include a hole corresponding to the through hole 400BH. The hole of the organic encapsulation layer may be larger than the hole of the inorganic encapsulation layer, so that the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may directly contact each other around the first area OA1 and the second area OA2.

[0101] When the thin film encapsulation layer 400B is Figure 3C When the through hole is not included as shown in FIG, each of the at least one inorganic encapsulation layer and the at least one organic encapsulation layer may cover the first area OA1 and the second area OA2. A portion of the insulating layer IL between the substrate 100 and the thin film encapsulation layer 400B may be removed. Figure 3CThe diagram shows that portions of the insulating layer IL corresponding to the first and second areas OA1 and OA2 are completely removed. Only some layers of the insulating layer IL including a plurality of layers may be removed.

[0102] Figure 4 is a schematic plan view of a display panel 10 according to an embodiment.

[0103] refer to Figure 4 , the display panel 10 may include a plurality of pixels P arranged in a display area DA. Each of the pixels P may include a display element, such as an organic light emitting diode. The pixel P may emit, for example, red, green, blue, or white light from the organic light emitting diode. In this specification, the pixel P may be a pixel that emits any one of the above-mentioned red, green, blue, and white light. The display area DA may be referred to as Figures 2A to 3C The described packaging structure covers and can be protected from foreign materials, moisture, etc.

[0104] The first non-display area NDA1 may surround both the first and second areas OA1 and OA2. The first non-display area NDA1 is an area where no image is realized, and signal lines providing signals to pixels P provided around the first and second areas OA1 and OA2 may be arranged in the first non-display area NDA1.

[0105] The second non-display area NDA2 may include a scan driver 1000 supplying a scan signal to the pixel P, a data driver 2000 supplying a data signal to the pixel P, a power line (not shown) supplying a driving voltage and a common voltage, and the like.

[0106] Figure 5A and Figure 5B is a schematic equivalent circuit diagram of a pixel of a display panel according to an embodiment.

[0107] refer to Figure 5A Each pixel P may include a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst.

[0108] The switching thin film transistor T2 may be connected to the scan line SL and the data line DL, and may transmit a data voltage input from the data line DL to the driving thin film transistor T1 according to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the switching thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transmitted from the switching thin film transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0109] The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED corresponding to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a specific brightness corresponding to the driving current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED may receive a common voltage ELVSS.

[0110] exist Figure 5A In , it is described that the pixel circuit PC includes two thin film transistors and one storage capacitor. The number of thin film transistors and the number of storage capacitors can be configured according to the design of the pixel circuit PC.

[0111] refer to Figure 5B The pixel circuit PC may include a plurality of thin film transistors and a plurality of storage capacitors. The plurality of thin film transistors and the plurality of storage capacitors may be connected to the signal lines SL, SIL, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0112] Figure 5B The figure shows that each pixel P is connected to signal lines SL, SIL, EL and DL, initialization voltage line VL, and driving voltage line PL. According to an embodiment, at least one of the signal lines SL, SIL, EL and DL, initialization voltage line VL, driving voltage line PL, etc. can be shared by adjacent pixels.

[0113] The plurality of thin film transistors may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 , and a second initialization thin film transistor T7 .

[0114] The signal lines may include a scan line SL transmitting a scan signal Sn, a previous scan line SIL transmitting a previous scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL transmitting an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SL and transmitting a data signal Dm. The driving voltage line PL may transmit a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL may transmit an initialization voltage Vint that initializes the driving thin film transistor T1 and the pixel electrode of the organic light emitting diode OLED.

[0115] The driving gate electrode G1 of the driving thin film transistor T1 can be connected to the first storage accumulation plate CE1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 can be connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 can be electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin film transistor T2, and can drive the driving current I OLED Supply to organic light emitting diode OLED.

[0116] The switching gate electrode G2 of the switching thin film transistor T2 may be connected to the scan line SL, the switching source electrode S2 of the switching thin film transistor T2 may be connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 may be connected to the driving source electrode S1 of the driving thin film transistor T1 and may be connected to the driving voltage line PL by operating the control thin film transistor T5. The switching thin film transistor T2 may perform a switching operation, whereby the switching thin film transistor T2 may be turned on according to the scan signal Sn transmitted through the scan line SL, and may transmit the data signal Dm received through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0117] The compensation gate electrode G3 of the compensation thin film transistor T3 may be connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 may be connected to the driving drain electrode D1 of the driving thin film transistor T1 and may be connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 may be connected to the first storage accumulation plate CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 may be turned on according to the scan signal Sn received through the scan line SL, and may electrically connect the driving gate electrode G1 to the driving drain electrode D1 of the driving thin film transistor T1 to diode-connect the driving thin film transistor T1.

[0118] The first initialization gate electrode G4 of the first initialization thin film transistor T4 may be connected to the previous scan line SIL.

[0119] The first initialization source electrode S4 of the first initialization thin film transistor T4 may be connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and the first initialization thin film transistor T4 may be connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL.

[0120] The first initialization drain electrode D4 may be connected to the first storage accumulation plate CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 may perform an initialization operation, whereby the first initialization thin film transistor T4 may transmit an initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1 by being turned on according to a previous scan signal Sn-1 transmitted through a previous scan line SIL, so as to initialize the voltage of the driving gate electrode G1 of the driving thin film transistor T1.

[0121] The operation control gate electrode G5 of the operation control thin film transistor T5 can be connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 can be connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 can be connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0122] The emission control gate electrode G6 of the emission control thin film transistor T6 can be connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 can be connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 can be electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0123] The operation control thin film transistor T5 and the emission control thin film transistor T6 may be simultaneously turned on according to the emission control signal En received through the emission control line EL, so that the driving voltage ELVDD may be transmitted to the organic light emitting diode OLED to allow the driving current I OLED Flow to the organic light emitting diode OLED.

[0124] The second initialization gate electrode G7 of the second initialization thin film transistor T7 may be connected to the previous scan line SIL, the second initialization source electrode S7 of the second initialization thin film transistor T7 may be connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 may be connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on according to the previous scan signal Sn-1 transmitted through the previous scan line SIL to initialize the pixel electrode of the organic light emitting diode OLED.

[0125] Figure 5BThe figure shows that the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SIL. According to another embodiment, the first initialization thin film transistor T4 can be connected to the previous scan line SIL to be driven according to the previous scan signal Sn-1, and the second initialization thin film transistor T7 can be connected to an additional signal line (e.g., the next scan line) to be driven according to a signal transmitted through the additional signal line.

[0126] The second storage accumulation plate CE2 of the storage capacitor Cst may be connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED may be connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED may receive the driving current I from the driving thin film transistor T1. OLED To emit light in order to display images.

[0127] Figure 5B The figure shows that the compensation thin film transistor T3 and the first initialization thin film transistor T4 have double gate electrodes. However, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

[0128] Figure 6 is a plan view of a pixel circuit that can be applied to a display panel according to an embodiment.

[0129] refer to Figure 6 , a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7 may be arranged along the semiconductor layer 1130. The semiconductor layer 1130 may be arranged on a substrate including a buffer layer as an inorganic insulating material.

[0130] One or more regions of the semiconductor layer 1130 may correspond to the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. In other words, the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 may be connected to each other and may have various curved shapes.

[0131] The semiconductor layer 1130 may include a channel region, and a source region and a drain region on both sides of the channel region, wherein the source region and the drain region may be a source electrode and a drain electrode of a corresponding thin film transistor. Hereinafter, for convenience, the source region and the drain region will be referred to as a source electrode and a drain electrode, respectively.

[0132] The driving thin film transistor T1 may include a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 on both sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 may have a curved shape such as an Ω shape, thereby having a large channel length in a small space. When the driving channel region has a large length, the driving range of the gate voltage can be increased, so that the grayscale of the light emitted from the organic light emitting diode OLED can be more finely controlled, and the quality of the display can be improved.

[0133] The switching thin film transistor T2 may include a switching gate electrode G2 overlapping the switching channel region, and a switching source electrode S2 and a switching drain electrode D2 on both sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0134] The compensation thin film transistor T3 may be a dual thin film transistor, may include a compensation gate electrode G3 overlapping two compensation channel regions, and may include a compensation source electrode S3 and a compensation drain electrode D3 arranged on both sides of the compensation gate electrode G3. The compensation thin film transistor T3 may be connected to the driving gate electrode G1 of the driving thin film transistor T1 through a node connection line 1174 to be described below.

[0135] The first initialization thin film transistor T4 may be a dual thin film transistor, may include a first initialization gate electrode G4 overlapping two first initialization channel regions, and may include

[0136] The first initialization source electrode S4 and the first initialization drain electrode D4.

[0137] The operation control thin film transistor T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 arranged at both sides of the operation control gate electrode G5. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0138] The emission control thin film transistor T6 may include an emission control gate electrode G6 overlapping the emission control channel region, and an emission control source electrode S6 and an emission control drain electrode D6 arranged on both sides of the emission control gate electrode G6. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0139] The second initialization thin film transistor T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 disposed at both sides of the second initialization gate electrode G7.

[0140] The above-mentioned thin film transistors may be connected to the signal lines SL, SIL, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0141] The scan line SL, the previous scan line SIL, the emission control line EL, and the driving gate electrode G1 may be disposed on the semiconductor layer 1130 with one or more insulating layers interposed therebetween.

[0142] The scan line SL may extend in the second direction. One or more regions of the scan line SL may correspond to the switch gate electrode G2 and the compensation gate electrode G3, respectively. For example, the region of the scan line SL, that is, the region overlapping the channel region of the switch thin film transistor T2 and the compensation thin film transistor T3, may be the switch gate electrode G2 and the compensation gate electrode G3, respectively.

[0143] The previous scan line SIL may extend in the second direction, and one or more regions of the previous scan line SIL may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. For example, the region of the previous scan line SIL, that is, the region overlapping the channel regions of the first initialization thin film transistor T4 and the second initialization thin film transistor T7, may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0144] The emission control line EL may extend in the second direction. One or more regions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively. For example, the region of the emission control line EL, that is, the region overlapping the channel region of the operation control thin film transistor T5 and the emission control thin film transistor T6, may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0145] The driving gate electrode G1 may include a floating electrode, and may be connected to the compensation thin film transistor T3 through the above-mentioned node connection line 1174 .

[0146] The electrode voltage line HL may be disposed on the above-mentioned scan line SL, the previous scan line SIL, the emission control line EL, and the driving gate electrode G1 with one or more insulating layers therebetween.

[0147] The electrode voltage line HL may extend in the second direction to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1 and may form a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may be a first storage accumulation plate CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may be a second storage accumulation plate CE2 of the storage capacitor Cst.

[0148] The second storage accumulation plate CE2 of the storage capacitor Cst may be electrically connected to the driving voltage line PL. In this regard, the electrode voltage line HL may be connected to the driving voltage line PL on the electrode voltage line HL through the contact hole CNT. Therefore, the electrode voltage line HL may have the same voltage level (constant voltage) as the driving voltage line PL. For example, the electrode voltage line HL may have a constant voltage of +5V. The electrode voltage line HL may be a driving voltage line in the lateral direction.

[0149] The driving voltage line PL may extend in a first direction, and the electrode voltage line HL electrically connected to the driving voltage line PL may extend in a second direction crossing the first direction, and thus, multiple driving voltage lines PL and multiple electrode voltage lines HL in the display area may form a mesh structure.

[0150] According to the present embodiment, the electrode voltage line HL may be disposed at a different layer from the driving voltage line PL, and a resistivity of the electrode voltage line HL may be greater than a resistivity of the driving voltage line PL.

[0151] The data line DL, the driving voltage line PL, the initialization link line 1173, and the node connection line 1174 may be disposed on the electrode voltage line HL with one or more insulating layers therebetween.

[0152] The data line DL may extend in the first direction, and may be connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. A portion of the data line DL may be the switching source electrode.

[0153] The driving voltage line PL may extend in the first direction and may be connected to the electrode voltage line HL through the contact hole CNT as described above. Also, the driving voltage line PL may be connected to the operation control thin film transistor T5 through the contact hole 1155. The driving voltage line PL may be connected to the operation control drain electrode D5 through the contact hole 1155.

[0154] One end of the initialization connection line 1173 may be connected to the first and second initialization thin film transistors T4 and T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to an initialization voltage line VL to be described below through the contact hole 1151 .

[0155] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157 .

[0156] The initialization voltage line VL may be disposed on the data line DL, the driving voltage line PL, the initialization link line 1173, and the node connection line 1174 with one or more insulating layers therebetween.

[0157] The initialization voltage line VL may extend in the second direction. The initialization voltage line VL may be connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through the initialization connection line 1173. The initialization voltage line VL may have a constant voltage (eg, -2V, etc.).

[0158] The initialization voltage line VL may be arranged on the same layer as the second storage accumulation plate CE2 (i.e., the electrode voltage line HL), and may include the same material as the second storage accumulation plate CE2. In the display area DA, the pixel electrode of the organic light emitting diode OLED may be connected to the emission control thin film transistor T6. The pixel electrode may be connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 may be connected to the emission control drain electrode D6 through the contact hole 1153.

[0159] Figure 7 is a schematic plan view of (a portion of) a display panel 10 according to an embodiment. Figure 8 According to the embodiment Figure 7 A cross-sectional view taken along lines AA' and BB'. Fig. 9 According to the embodiment Figure 8 1 is a cross-sectional view of a portion of the display panel 10 . Fig. 10A and Fig. 10B According to the embodiment Figure 7 Plan view of area V.

[0160] refer to Figure 7 and Figure 8 , the display panel 10 may include a first area OA1 and a second area OA2, a first non-display area NDA1 surrounding the first area OA1 and the second area OA2, and a display area DA surrounding the first non-display area NDA1. The first area OA1 and the second area OA2 may be spaced apart from each other in an island shape. The first area OA1 and the second area OA2 may have the same shape and the same size as each other. The first area OA1 and the second area OA2 may have different shapes, or the first area OA1 and the second area OA2 may have the same shape and different sizes.

[0161] When the edge of each of the first area OA1 and the second area OA2 is referred to as the first line E1, the first non-display area NDA1 may include a first-first non-display area NDA1-1 adjacent to the first line E1, and a first-second non-display area NDA1-2 surrounding the first-first non-display area NDA1-1. The remaining area of ​​the first non-display area NDA1 may be defined as a first-third non-display area NDA1-3. A boundary between the first-first non-display area NDA1-1 and the first-second non-display area NDA1-2 may be referred to as the second line E2, a boundary between the first-second non-display area NDA1-2 and the first-third non-display area NDA1-3 may be referred to as the third line E3, and a boundary between the first-third non-display area NDA1-3 and the display area DA may be referred to as the fourth line E4.

[0162] The pixels P may not be arranged in the first non-display area NDA1 and may be arranged in the display area DA. Some pixels P may be spaced apart from each other by at least the first non-display area NDA1. In a plan view, the pixels P may be arranged at opposite sides of the first non-display area NDA1.

[0163] Wiring (or signal line) for applying signals and voltages to the pixels P may be arranged in the first-second non-display area NDA1 - 2 having a ring shape having the second line E2 as an inner edge and having the third line E3 as an outer edge.

[0164] Signal lines adjacent to the first and second areas OA1 and OA2 may bypass the first and second areas OA1 and OA2. Some data lines DL passing through the display area DA may extend generally in the y direction to provide data signals to pixels P arranged above and below the first non-display area NDA1, and may bypass the first line E1 as an edge of the first and second areas OA1 and OA2 in the first-second non-display area NDA1-2. One or more scan lines SL passing through the display area DA may extend generally in the x direction to provide scan signals to pixels P arranged on the right and left sides of the first non-display area NDA1, and may bypass the first line E1 as an edge of the first and second areas OA1 and OA2 in the first-second non-display area NDA1-2.

[0165] After the scan line SL bypasses the edge E1 of the first area OA1, the scan line SL may cross the first to third non-display areas NDA1-3 between the first area OA1 and the second area OA2, and then may bypass the edge E1 of the second area OA2. The scan line SL passing through the first to third non-display areas NDA1-3 may have at least a portion extending in the x-direction.

[0166] One or more data lines DL' may cross the first to third non-display areas NDA1-3 and may extend in the y direction in the first to third non-display areas NDA1-3 without bypassing the edges of the first and second areas OA1 and OA2. The data lines DL' extending in the y direction without bypassing the edges of the first and second areas OA1 and OA2 may be arranged at or near a center point between the first and second areas OA1 and OA2. In an embodiment, one or more data lines DL' among the data lines DL crossing the first to third non-display areas NDA1-3 may bypass one or more edges of the first and second areas OA1 and OA2.

[0167] A margin space required to cut the first and second areas OA1 and OA2 along the first line E1 may be provided in the first-first non-display area NDA1 - 1 having a ring shape having the first line E1 as an inner edge and the second line E2 as an outer edge.

[0168] refer to Figure 8 , the display panel 10 may include a first area OA1 (which is an opening area), a display area DA, and a first non-display area NDA1 between the first area OA1 and the display area DA.

[0169] The pixel circuit PC on the substrate 100 , the pixel electrode 221 connected to the pixel circuit PC, and the intermediate layer 222 and the opposing electrode 223 sequentially disposed on the pixel electrode 221 may be disposed in the display area DA.

[0170] According to an embodiment, the substrate 100 may include a plurality of layers such as Figure 8 For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 that are sequentially stacked.

[0171] Each of the first substrate layer 101 and the second substrate layer 103 may include a polymer resin. For example, the first substrate layer 101 and the second substrate layer 103 may include PES, PAR, PEI, PEN, PET, PPS, polyarylate, PI, PC, triacetyl cellulose (TAC), CAP, etc., and may be flexible. The above polymer resin may be transparent.

[0172] Each of the first barrier layer 102 and the second barrier layer 104 may include a barrier layer for preventing penetration of external impurities, and may include a single layer or a multilayer including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0173] According to an embodiment, the substrate 100 may include a substrate mainly including SiO 2 The substrate 100 may be a glass material of, or a resin such as reinforced plastic, and may be rigid. The substrate 100 may have a stacked structure including a layer including the above-mentioned polymer resin and a barrier layer on the layer including the above-mentioned polymer resin. In this case, the substrate 100 may have improved flexibility. The barrier layer may include silicon oxide, silicon nitride and / or silicon oxynitride.

[0174] The pixel circuit PC may be arranged on the substrate 100 and may include a thin film transistor, a storage capacitor, etc. The organic light emitting diode OLED including the pixel electrode 221, the intermediate layer 222 including the emission layer, and the counter electrode 223 may emit specific light and may be covered by an encapsulation substrate or a thin film encapsulation layer facing the substrate 100.

[0175] refer to Fig. 9 A display layer 200 (or a pixel array layer or a display unit 200 ) including a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC may be arranged in the display area DA.

[0176] The thin film transistor TFT, the storage capacitor Cst, and the pixel electrode 221 electrically connected to the thin film transistor TFT and the storage capacitor Cst may be formed on the substrate 100. The pixel circuit PC may be disposed on the substrate 100, and the organic light emitting diode OLED may be located on the pixel circuit PC.

[0177] The substrate 100 may include a polymer resin or glass. Figure 8 Description given.

[0178] A buffer layer 201 may be formed on the substrate 100 to prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT. The buffer layer 201 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, and may include a single layer or multiple layers including the above inorganic insulating material.

[0179] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Fig. 9 The thin film transistor TFT shown in the figure can be compared with the reference Figure 5A A driving thin film transistor described or referenced Figure 5BThe emission control thin film transistor described corresponds to the above. According to the present embodiment, the figure shows a top gate transistor, in which the gate electrode GE is arranged on the semiconductor layer Act with the gate insulating layer 203 interposed therebetween. According to the embodiment, the thin film transistor TFT may be a bottom gate transistor.

[0180] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material, such as one of Mo, Al, Cu, Ti, etc., and may include a single layer or multiple layers including the above materials.

[0181] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 may include a single layer or multiple layers including the above materials.

[0182] The source electrode SE and the drain electrode DE may include a material having good conductivity. The source electrode SE and the drain electrode DE may include a conductive material such as Mo, Al, Cu, Ti, etc., and may include a single layer or a multilayer including the above materials. According to an embodiment, the source electrode SE and the drain electrode DE may include a multilayer of Ti / Al / Ti.

[0183] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other with a first interlayer insulating layer 205 therebetween. The storage capacitor Cst may overlap with the thin film transistor TFT. In this regard, Fig. 9 The figure shows that the gate electrode GE of the thin film transistor TFT is the lower electrode CE1 of the storage capacitor Cst. According to another embodiment, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207.

[0184] The first and second interlayer insulating layers 205 and 207 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first and second interlayer insulating layers 205 and 207 may include a single layer or multiple layers including the above materials.

[0185] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by the planarization insulating layer 209. The planarization insulating layer 209 may include an upper surface having a substantially flat portion. The planarization insulating layer 209 may include an organic insulating material, such as a general polymer, such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative with a phenolic group, an acryl polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a mixture thereof. According to an embodiment, the planarization insulating layer 209 may include PI. Alternatively, the planarization insulating layer 209 may include an inorganic insulating material, or may include an inorganic insulating material and an organic insulating material.

[0186] The pixel electrode 221 may be formed on the planarization insulating layer 209. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). According to an embodiment, the pixel electrode 221 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof. According to an embodiment, the pixel electrode 221 may further include a reflective layer including ITO, IZO, ZnO or In above / below the reflective layer. 2 O 3 layer.

[0187] The pixel defining layer 211 may be formed on the pixel electrode 221. The pixel defining layer 211 may include an opening exposing the upper surface of the pixel electrode 221, and may cover the edge of the pixel electrode 221. The pixel defining layer 211 may include an organic insulating material. Alternatively, the pixel defining layer 211 may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride. Alternatively, the pixel defining layer 211 may include an organic insulating material and an inorganic insulating material.

[0188] The intermediate layer 222 may include an emission layer 222b. The intermediate layer 222 may include a first functional layer 222a below the emission layer 222b and / or a second functional layer 222c above the emission layer 222b. The emission layer 222b may include a high molecular weight organic material or a low molecular weight organic material that emits light of a specific color.

[0189] The first functional layer 222a may include a single layer or multiple layers. For example, when the first functional layer 222a includes a high molecular weight material, the first functional layer 222a may include a hole transport layer (HTL) having a single layer structure including poly-(3,4)-ethylene-dihydroxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 222a includes a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and the HTL.

[0190] The second functional layer 222c may be optional. For example, when the first functional layer 222a and the emission layer 222b include a high molecular weight material, the second functional layer 222c may be formed. The second functional layer 222c may include a single layer or multiple layers. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0191] The first functional layer 222a and / or the second functional layer 222c of the intermediate layer 222 may be formed in common in all pixels. The emission layer 222b of the intermediate layer 222 may be individually arranged in each pixel in the display area DA. The emission layer 222b may be arranged in the opening of the pixel defining layer 211.

[0192] The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca or an alloy thereof. Alternatively, the counter electrode 223 may also include a conductive material including, for example, ITO, IZO, ZnO or In on the (semi) transparent layer including the above materials. 2 O 3 The counter electrode 223 may be formed not only in the display area DA but also in the first non-display area NDA1. The intermediate layer 222 and the counter electrode 223 may be formed by using thermal deposition.

[0193] The capping layer 230 may be located on the counter electrode 223. For example, the capping layer 230 may include LiF and may be formed by using thermal deposition. Alternatively, the capping layer 230 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The capping layer 230 may be optional.

[0194] A spacer 213 may be formed on the pixel defining layer 211. The spacer 213 may include an organic insulating material such as PI. Alternatively, the spacer 213 may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, or may include an organic insulating material and an inorganic insulating material.

[0195] The spacer 213 may include a material different from that of the pixel defining layer 211. Alternatively, the spacer 213 may include the same material as that of the pixel defining layer 211, and in this case, the pixel defining layer 211 and the spacer 213 may be formed together by a mask process using a half-tone mask, etc. According to an embodiment, the pixel defining layer 211 and the spacer 213 may include PI.

[0196] Reference again Figure 8 , the first non-display area NDA1 of the display panel 10 may include a first-first non-display area NDA1-1, a first-second non-display area NDA1-2, and a first-third non-display area NDA1-3, which are adjacent to the first opening 10H in the stated order.

[0197] The first-second non-display area NDA1 - 2 may be a bypass area in which one or more data lines DL bypassing the first area OA1 are arranged.

[0198] The first to third non-display areas NDA1-3 may be areas through which the data lines DL' extend in the y direction without bypassing the first area OA1. The first to third display areas NDA1-3 may be areas in which wiring is substantially linear without bypassing the first area OA1.

[0199] The scan lines SL may be alternately arranged in two layers in the first-second non-display area NDA1-2 with an insulating layer interposed therebetween, such as Figure 8 When adjacent scan lines SL are arranged above and below each other with an insulating layer (e.g., the first interlayer insulating layer 205) interposed, the gap (spacing) between adjacent scan lines SL may be reduced, and thus, the width of the first non-display area NDA1 may be reduced. Likewise, although not shown, the data lines DL may be alternately arranged in two layers with an insulating layer interposed in the first-second non-display area NDA1-2.

[0200] The scan line SL may be disposed on a layer different from that of the data line DL. For example, the scan line SL may be disposed below the data line DL. Figure 8 The scanning lines SL below the data lines DL' in the first to third non-display areas NDA1-3 are not shown, but this is because Figure 7 The scan line SL may be arranged under the data line DL' in the first to third non-display areas NDA1-3 because of the cutting direction intercepted by the line AA'.

[0201] like Figure 7As shown in , the electrode layer 221M may be arranged in the first-second non-display area NDA1-2 and the first-third non-display area NDA1-3. The electrode layer 221M may cover the bypassing portion of the bypassing areas OA1 and OA2 of the wiring (e.g., the data line DL and the scan line SL), and may partially cover the wiring (e.g., the data line DL and the scan line SL) passing through the first-third non-display area NDA1-3 between the areas OA1 and OA2. At least one insulating layer ( Figure 8 205, 207 and / or 209).

[0202] According to an embodiment, an edge of the electrode layer 221M adjacent to the display area DA may correspond to an edge of a combination of the first-second non-display area NDA1-2 and the first-third non-display area NDA1-3, which is adjacent to the display area DA. An edge of the electrode layer 221M adjacent to one of the first area OA1 and the second area OA2 may correspond to an edge of the first-second non-display area NDA1-2 adjacent to the one of the first area OA1 and the second area OA2.

[0203] According to an embodiment, when the first area OA1 and the second area OA2 are circular holes, the electrode layer 221M may include one or more through holes (221MO) corresponding to the first area OA1 and / or the second area OA2. The second radius R2 of the through hole 221MO of the electrode layer 221M may be greater than the first radius R1 of the first area OA1 or the second area OA2. The first radius R1 may represent the distance between the first center O1 of the first area OA1 or the second center O2 of the second area OA2 and the corresponding first line E1 as the edge of the first area OA1 or the second area OA2. The second radius R2 may be the same as the distance between the first center O1 or the second center O2 and the corresponding second line E2.

[0204] One or more initialization voltage lines VL extending in the x direction may be connected to the electrode layer 221M. One or more initialization voltage lines VL may be connected to the reference Figure 5B and Figure 6 The first initialization thin film transistor T4 and the second initialization thin film transistor T7 are described and may have a constant voltage.

[0205] The electrode layer 221M connected to the initialization voltage line VL may have the same voltage level as the initialization voltage line VL, and therefore, the electrode layer 221M may also have a constant voltage. One or more wirings (e.g., data lines DL and scan lines SL) may be at least partially covered (or shielded) by the electrode layer 221M. Coupling between adjacent wirings (e.g., data lines DL and scan lines SL) may be reduced.

[0206] According to the embodiment, reference Fig. 10A , the initialization voltage line VL may be formed integrally with the electrode layer 221M, or may be disposed on the same layer as the electrode layer 221M and connected to the electrode layer 221M.

[0207] According to an embodiment, the initialization voltage line VL may be arranged on the same layer as one or more wirings (e.g., the data line DL and the scan line SL), or may be arranged between some of the wirings (e.g., the data line DL and the scan line SL) and the electrode layer 221M. When the initialization voltage line VL is arranged on a layer different from the electrode layer 221M, a contact hole 221MC may be formed on a layer between the initialization voltage line VL and the electrode layer 221M so that the initialization voltage line VL and the electrode layer 221M may be connected to each other via the contact hole 221MC, as shown in FIG. Fig. 10B as shown in .

[0208] The electrode layer 221M may have at least one opening OP between the first area OA1 and the second area OA2 .

[0209] The opening OP may expose the layers below the electrode layer 221M (eg, Fig. 9 209), and therefore, the electrode layer 221M may not cover a portion substantially below or directly below the opening OP.

[0210] Since the electrode layer 221M includes the opening OP, a process defect such as a short circuit at a region between the electrode layer 221M and underlying wirings (e.g., data lines DL and scan lines SL) overlapping the electrode layer 221M may be prevented. The opening OP may be provided in the first to third non-display areas NDA1-3 between the first area OA1 and the second area OA2 to minimize the overlap between the electrode layer 221M and underlying wirings (e.g., data lines DL and scan lines SL).

[0211] The electrode layer 221M may cover the bypassed portions of the wirings (e.g., the data lines DL and the scan lines SL) in the first to second non-display areas NDA1-2, but may not cover at least one or more of the wirings (e.g., the data lines DL and the scan lines SL) in the first to third non-display areas NDA1-3. Figure 7 and Figure 8 as shown in .

[0212] The opening OP may have one or more of various shapes. One or more widths of the opening OP may be configured according to the embodiment.

[0213] refer to Figure 7, when the edge of the opening OP crossing the data line DL' is referred to as the first edge EG1, the widths defined by the first point P1 and the second point P2 as two different points on the first edge EG1 may be different from each other. That is, the first width w1 of the opening OP defined by the first point P1 in the y direction may not be equal to the second width w2 of the opening OP defined by the second point P2 in the y direction.

[0214] A first distance d1 between a first point P1 of the first edge EG1 of the opening OP and the fourth line E4 of the first to third non-display areas NDA1-3 may not be equal to a second distance d2 between a second point P2 of the first edge EG1 of the opening OP and the fourth line E4 of the first to third non-display areas NDA1-3.

[0215] The first distance d1 and the second distance d2 may be among the shortest distances between the edge of the opening OP and the display area DA.

[0216] According to an embodiment, the minimum distance between the first edge EG1 of the opening OP and the fourth line E4 of the first to third non-display areas NDA1-3 may be equal to the distance between a point of the first edge EG1 of the opening OP corresponding to the center CE of the opening OP and the fourth line E4 of the first to third non-display areas NDA1-3.

[0217] According to an embodiment, at least a portion of the first edge EG1 of the opening OP may be curved. The first edge EG1 may protrude toward the display area DA. The first edge EG1 of the opening OP may be a curve. The second edge EG2 of the opening OP may extend substantially in the y direction and may be a straight line. As another example, the shape of the opening OP may be substantially square with curved edges at the corners. As yet another example, the shape of the opening OP may be substantially circular or elliptical.

[0218] The opening OP may intersect a virtual line L (or a geometric line L) connecting a first center O1 of the first area OA1 and a second center O2 of the second area OA2. The opening OP may have a y-direction width greater than an x-direction width. Figure 7 As shown in , the center CE of the opening OP may be the midpoint of the dotted line L, and the width of the opening OP defined along the y direction from the center CE of the opening OP may be the maximum y-direction width of the opening OP.

[0219] The length d1 corresponding to the overlap between the first data line DL1 and the electrode layer 221M may not be equal to the length d2 corresponding to the overlap between the second data line DL2 and the electrode layer 221M.

[0220] The opening OP may expose a majority of the area between the first area OA1 and the second area OA2. In some embodiments, the maximum width of the opening OP in the y direction may be greater than the diameter (2×R1) of the first area OA1. In an embodiment, the maximum width of the opening OP in the y direction may be equal to the hole diameter (2×R2) of the electrode layer 221M. The hole diameter (2×R2) represents the diameter of the through hole 221MO of the electrode layer 221M.

[0221] like Figure 7 and Figure 8 As shown in , the electrode layer 221M may include holes 221H spaced apart from each other. A plurality of holes 221H may be spaced apart from the opening OP, and the size of each of the holes 221H may be smaller than the size of the opening OP. For example, the width of each of the holes 221H in the y direction may be less than one tenth of the width of the opening OP in the y direction.

[0222] The plurality of holes 221H may be exhaust holes formed to perform exhaust of the organic layer below the electrode layer 221M. Figure 8 As shown in , the plurality of holes 221H may be spaced apart from each other, so that exhaust of the planarization insulating layer 209 as the organic insulating layer under the electrode layer 221M may be easily performed.

[0223] An exhaust effect can also be obtained through the opening OP in the electrode layer 221M, and thus, potential pixel shrinkage can be prevented.

[0224] like Figure 8 As shown in FIG. 1 , the electrode layer 221M may include the same material as the pixel electrode 221 and may be arranged on the same layer as the pixel electrode 221. The initialization voltage line ( Figure 7 The initialization voltage line VL may also include the same material as the pixel electrode 221. The initialization voltage line VL may be disposed on a layer different from that of the electrode layer 221M, or may include a material different from that of the electrode layer 221M.

[0225] Fig.11 yes Figure 7 The plan view of the region W, and Fig.12 is along Fig.11 A cross-sectional view taken along line CC'.

[0226] refer to Fig.11, the first-first non-display area NDA1-1, the first-second non-display area NDA1-2, and the first-third non-display area NDA1-3 away from the first area OA1 in the stated order may be arranged. The electrode layer 221M may be arranged in the first-second non-display area NDA1-2 and the first-third non-display area NDA1-3. The first-second non-display area NDA1-2 may be an area in which a bypass portion of a wiring (e.g., a data line DL and a scan line SL) is arranged.

[0227] The opening OP of the electrode layer 221M may be located in the first to third non-display areas NDA1 - 3 , and the plurality of holes 221H may be spaced apart from the opening OP.

[0228] The holes 221H are alternately arranged in rows and / or columns. For example, in the holes 221H, the first hole and the second hole may be arranged in the holes of the first row, and the third hole adjacent to the first hole and the second hole may be arranged in the holes of the second row adjacent to the holes of the first row, wherein the third hole is arranged between the first hole and the second hole.

[0229] Some holes 221H may overlap (or partially expose) bypassed portions of wirings (e.g., data lines DL and scan lines SL), and may overlap (or partially expose) portions of non-bypassed wirings (e.g., DL1'), where the non-bypassed wirings may intersect with the opening OP. The opening OP may not expose the bypassed portions of the wirings (e.g., data lines DL and scan lines SL). The hole 221H may surround the first area OA1 and the second area OA2.

[0230] refer to Fig.12 , first to fourth parasitic capacitances Cp1, Cp2, Cp3, and Cp4 may occur between the data lines DL1', DL2', DL3', and DL4' and the electrode layer 221M, respectively. That is, as the overlap area increases, the parasitic capacitance may also increase.

[0231] refer to Fig.11 Since the first edge EG1 of the opening OP is curved, the overlapped area between the electrode layer 221M and the data lines DL1', DL2', DL3', and DL4' may gradually change from the first data line DL1' to the fourth data line DL4'. Therefore, the parasitic capacitance may also gradually change from the first data line DL1' to the fourth data line DL4'. The parasitic capacitance may decrease in the order of the first parasitic capacitance Cp1, the second parasitic capacitance Cp2, the third parasitic capacitance Cp3, and the fourth parasitic capacitance Cp4.

[0232] As the parasitic capacitance gradually changes, the wiring load between the adjacent data lines DL1 ′, DL2 ′, DL3 ′, and DL4 ′ may also gradually change to prevent display quality degradation due to a rapid change in the wiring load.

[0233] Fig.13 is a schematic plan view of (a portion of) a display panel 10 ′ according to an embodiment. Fig.14 is along Fig.13 A cross-sectional view taken along line XIV-XIV'.

[0234] In addition to the groove G being located in the first-first non-display area NDA1-1, Fig.13 and Fig.14 The embodiment shown in FIG. has the same Figures 1 to 12 Structures that are similar or substantially identical to one or more of the structures discussed herein.

[0235] refer to Fig.13 and Fig.14 , the substrate 100 may have a multi-layer structure including a polymer resin layer, thereby providing the display panel 10' with flexible characteristics. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 stacked in sequence, wherein the first base layer 101 and the second base layer 103 may include a polymer resin, and the first barrier layer 102 and the second barrier layer 104 may include an inorganic material for blocking. Figure 8 Examples of polymer resins and inorganic materials are described.

[0236] The first-first non-display area NDA1-1 may be a groove area in which a groove is arranged. Fig.13 and Fig.14 The figure shows three grooves G located in the first-first non-display area NDA1-1. The number of the grooves G may be configured according to the embodiment. The grooves G may be spaced apart from each other.

[0237] Each of the grooves G may be formed in a multilayer structure including a first layer and a second layer including materials different from each other. Fig.14 The drawing shows that the groove G is formed in at least one layer of the multi-layer structure provided in the substrate 100 .

[0238] According to an embodiment, the groove G may be formed by removing a portion of the second barrier layer 104 and a portion of the second base layer 103. The groove G may be formed before the intermediate layer 222 is formed.

[0239] A portion of the intermediate layer 222, for example, the first functional layer ( Fig. 9222a) and / or the second functional layer ( Fig. 9 222c), may be separated based on the groove G and thus may be formed outside the display area DA. Therefore, the extended portion of the intermediate layer 222 may provide additional protection against external moisture and may prevent external moisture having penetrated the first opening 10H from passing through the organic encapsulation layer 320 and advancing to the organic light emitting diode of the display area DA.

[0240] Since the first functional layer ( Fig. 9 222a) and / or the second functional layer ( Fig. 9 222c) can be separated based on the groove G, so that the first functional layer and the second functional layer ( Fig. 9 222a and 222c) and the emission layer ( Fig. 9 222b) is different, it can not only exist in Fig.13 The display area DA shown in FIG. 1 may also exist in the first non-display area NDA1 for providing additional protection against moisture intrusion.

[0241] like Fig.13 As shown in, since the groove G is arranged in the first-first non-display area NDA1-1, the groove G can be closer to the first area OA1 and the second area OA2 compared to one or more bypassing portions of the data line DL and / or the scan line SL that bypass the first line E1 (the first line E1 serves as the edge of the first area OA1 and the second area OA2).

[0242] According to an embodiment, in a plan view, the groove G may have a ring shape substantially surrounding each of the first area OA1 and the second area OA2 in the first-first non-display area NDA1 - 1 .

[0243] A radius of each of the grooves G with respect to the first center O1 of the first area OA1 may be greater than a first radius R1 which is a radius of the first area OA1 and may be smaller than a second radius R2 which is a radius of the through hole 221MO of the electrode layer 221M.

[0244] The organic light emitting diodes ( Fig. 9 The organic light emitting diode OLED) may be covered by the thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer.

[0245] According to an embodiment, Fig.14 The figure shows that the thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an intervening organic encapsulation layer 320. According to embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order of inorganic and organic encapsulation layers may be different.

[0246] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be formed by chemical vapor deposition (CVD), etc. The organic encapsulation layer 320 may include a polymer material. The polymer material may include a silicon resin, an acryl resin, an epoxy resin, polyimide, polyethylene, etc.

[0247] according to Fig.14 In the embodiment shown in , the first area OA1 of the display panel 10 ′ may include the first opening 10H and the grooves G. Each groove G may be spaced apart from the first opening 10H and may be recessed in the z direction as the thickness direction.

[0248] Fig.15 1 is a schematic plan view of a display panel 10 (part) according to an embodiment.

[0249] In addition to the structure including the opening OP in the electrode layer 221M, Fig.15 The embodiments shown in the reference Figures 1 to 14 Structures that are similar or substantially identical to one or more of the structures described herein.

[0250] refer to Fig.15 , a plurality of openings OP may be included in the electrode layer 221M. Fig.15 The figure shows that the number of openings OP is two and the two openings OP are arranged in the direction of the figure. Three or more openings OP may be provided in the electrode layer 221M, and the openings OP may be arranged side by side or in a diagonal direction in a plan view of the display panel 10 ″.

[0251] The number of openings OP and the positions of the openings OP may be adjusted to optimally reduce short defects, optimally shield wirings (eg, data lines DL and scan lines SL), and / or minimize parasitic capacitance.

[0252] In a region having relatively high parasitic capacitance between the electrode layer 221M and the data line DL, a bent portion of the edge of the opening OP may be increased compared to other regions so that the parasitic capacitance between the data lines DL changes smoothly.

[0253] Fig.15 The figures show that the plurality of openings OP have a circular (or elliptical) shape. The openings OP may have one or more other shapes including curved edge portions. At least two openings OP may have shapes different from each other.

[0254] Fig.16is a schematic plan view of (a portion of) a display panel 10 ′″ according to an embodiment.

[0255] In addition to the first area OA1 and the second area OA2 having different sizes from each other, Fig.16 The embodiments shown in the reference Figures 1 to 15 Structures that are similar or substantially identical to one or more of the structures described herein.

[0256] refer to Fig.16 , the hole radius R1 of the first area OA1 may not be equal to the hole radius R1' of the second area OA2. The size of each of the first area OA1 and the second area OA2 may be adjusted according to the size of a corresponding electronic component such as a sensor or a camera.

[0257] According to an embodiment, when the size of the first area OA1 is smaller than the size of the second area OA2, the maximum width of the opening OP provided in the electrode layer 221M in the y direction may be equal to the hole diameter (2×R2′) of the electrode layer 221M corresponding to the second area OA2. The opening OP may be large enough so that short circuit prevention and exhaust may be optimized.

[0258] In an embodiment, the maximum width of the opening OP in the y direction may have a value between the hole diameter (2×R2′) of the electrode layer 221M corresponding to the second area OA2 and the hole diameter (2×R2) of the electrode layer 221M corresponding to the first area OA1. The hole diameter (2×R2′) represents the diameter of the through hole 221MO′ of the electrode layer 221M, and the hole diameter (2×R2) represents the diameter of the through hole 221MO of the electrode layer 221M. When the opening OP has a reduced size due to design or the like, the maximum width of the opening OP in the y direction may be equal to the hole diameter (2×R2) of the electrode layer 221M corresponding to the first area OA1.

[0259] According to the embodiment, the display panels 10 , 10 ′, 10 ″, and 10 ′″ may optimize display quality by optimizing a rate of change of parasitic capacitance associated with wiring near electronic components such as a sensor or a camera.

[0260] The embodiments described herein should be considered in an illustrative sense and not for purposes of limitation. Descriptions of features or aspects associated with one embodiment may be applicable to other embodiments.

[0261] Although example embodiments have been described with reference to the drawings, various changes in form and details may be made in example embodiments without departing from the scope defined by the appended claims.

Claims

1. A display panel, comprising: First hole; a second hole spaced apart from the first hole in a first direction; Display components; a switch element electrically connected to the display element; a first wiring line between the first hole and the second hole in a plan view of the display panel and electrically connected to the switching element, the first wiring line extending in a second direction intersecting the first direction; as well as A conductive member having a first opening between the first hole and the second hole in the plan view of the display panel and partially covering the first wiring, wherein the first opening has a first width in the first direction and a second width in the second direction, wherein the first width is smaller than the second width, and wherein a first edge portion of the conductive member intersects the first wiring and is placed between the display element and the first hole in the plan view of the display panel. 2 . The display panel according to claim 1 , wherein the first wiring is a data line electrically connected to the switching element to apply a data signal to the display element. 3 . The display panel of claim 2 , wherein the first opening comprises a first curved edge crossing the data line. 4 . The display panel according to claim 1 , wherein the conductive member comprises holes spaced apart from each other, and wherein each of the holes is smaller than the first opening in the plan view of the display panel. 5 . The display panel of claim 1 , wherein the conductive member comprises holes spaced apart from each other, and wherein at least one of the holes partially exposes the first wiring. 6 . The display panel of claim 1 , further comprising a second wiring that bypasses an edge of the first hole, wherein the first opening is spaced apart from the second wiring in the plan view of the display panel.

7. The display panel according to claim 1, further comprising: An initialization voltage line is electrically connected to the conductive member and is configured to provide a constant voltage to the conductive member. The display panel according to claim 1 , wherein the conductive member has a constant voltage. 9 . The display panel according to claim 1 , wherein the display element comprises a pixel electrode, a counter electrode, and an emission layer between the pixel electrode and the counter electrode. 10 . The display panel according to claim 9 , wherein a material of the conductive member is the same as a material of the pixel electrode. 11 . The display panel of claim 1 , wherein the conductive member comprises a third hole and a fourth hole corresponding to the first hole and the second hole, respectively.

12. A display panel, comprising: A substrate comprising a first area and a second area, a non-display area surrounding the first area and the second area, and a display area surrounding the non-display area; a plurality of display elements arranged in the display region and each including a pixel electrode, a counter electrode, and an emission layer between the pixel electrode and the counter electrode; a plurality of wirings that bypass at least a portion of an edge of each of the first area and the second area in the non-display area; as well as an electrode layer covering at least one of the plurality of wirings in the non-display area and having an opening disposed between the first area and the second area, wherein: A first wiring and a second wiring among the plurality of wirings overlap the opening of the electrode layer, and a first width of a portion of the first wiring overlapping the opening is smaller than a second width of a portion of the second wiring overlapping the opening.

13. The display panel according to claim 12, wherein the plurality of wirings include a plurality of data lines that apply data signals to a plurality of pixel circuits that are respectively electrically coupled to the plurality of display elements, The first wiring includes a first data line, and the second wiring includes a second data line.

14. The display panel according to claim 12, wherein the electrode layer comprises a plurality of holes spaced apart from each other, and At least one hole of the plurality of holes is arranged to surround the first region and the second region.

15. The display panel according to claim 12, wherein: The plurality of wirings include: a plurality of data lines for applying data signals to a plurality of pixel circuits respectively electrically coupled to the plurality of display elements, and A plurality of initialization voltage lines are electrically connected to the electrode layer.

16. The display panel according to claim 15, wherein the plurality of initialization voltage lines have a constant voltage, and The electrode layer has the same voltage level as the plurality of initialization voltage lines. 17 . The display panel according to claim 12 , wherein the electrode layer comprises the same material as the pixel electrode.

18. The display panel according to claim 12, further comprising an organic insulating layer below the electrode layer, The electrode layer exposes at least a portion of the organic insulating layer through the opening.

19. The display panel according to claim 12, further comprising: at least one groove provided in the non-display area and closer to the first area and the second area than to the plurality of wirings; as well as The encapsulation layer covers the plurality of display elements and includes an inorganic encapsulation layer and an organic encapsulation layer.

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