A FPGA digital filter and its implementation method

Abstract

The present invention discloses an FPGA digital filter and its implementation method, including a triple integrator, a register group, an addition and subtraction combination logic circuit, a timer and a data output circuit; the input end of the triple integrator is connected to the input signal, the output end of the triple integrator is connected to the input end of the register group, the output end of the register group is connected to the input end of the addition and subtraction combination logic circuit, and the output end of the addition and subtraction combination logic circuit is connected to the data output circuit; the register group includes four registers connected in series, a high-frequency clock signal is respectively connected to the timer, the data output circuit, the register group and the triple integrator, the output signal of the timer is respectively connected to the enable end of the four registers, and data is stored in the register group at the same time interval. The filter of the present invention occupies less resources and the output will not have a large delay.

Description

Technical Field

[0001] The present invention relates to the field of digital filters, and in particular to an FPGA digital filter and an implementation method thereof. Background Art

[0002] Sinc3 digital filters are widely used in servo control systems. Bandwidth is an important indicator for measuring the response speed and processing capability of a servo system. To increase bandwidth, it is necessary to reduce the delay links of the servo control cycle. The sinc3 digital filter often used in servos is also one of the sources of sampling delay. There are two commonly used digital filters.

[0003] The first one is the FPGA IP core provided by ADI, which adopts the method of integration before differentiation.

[0004] The transfer function G(z) is decomposed as follows:

[0005]

[0006] It can be seen that the digital filter can be divided into a pure proportional link, three discrete accumulators 1 / (1-z -1 ), and 3 differentiators (1-z -DR ) are obtained by connecting in series.

[0007] The MCLKIN used is the input clock of the FPGA circuit, which is generally 20MHZ. WORD_CLK is the extracted clock, which is obtained by software frequency division of MCLKIN, and its clock period is DR=32 times of MCLKIN. Assuming that the frequency of MCLKIN is 20MHZ and the period is 50ns, then the period of WORD_CLK is 1600ns, that is, 1.6us. Since FPGA often uses registers as timing elements. Therefore, there is a lag of one beat (i.e., a transmission delay of one clock cycle) in the transmission between registers.

[0008] This implementation of the digital filter will result in an additional pure delay time of 3*MCLKIN*DR. If the ideal delay caused by the transfer function is added:

[0009] τ M For MCLKIN cycle

[0010] Then, at a sampling rate of DR=32, the total transmission delay (ideal transfer function transmission delay + designed digital controller delay) is 7.15us. From the multiple relationship, it can be seen that when DR=64, the delay will be more than 14us. This delay has a significant impact on the performance of the servo real-time control system (generally the control frequency is 10k).

[0011] like Figure 4 As shown in the figure, the second method is to use the traditional FIFO (first in first out) transfer function implementation method (FIFO filter for short). This method also has a relatively obvious disadvantage, that is, the number of registers used is too large. When DR = 32, 3*DR = 96 register groups are needed. Each register group in the IP core is generally composed of 37 registers, so it is equivalent to using 96*37 = 3552 registers. When the DR extraction rate is high, it will occupy a large amount of FPGA resources.

[0012] In summary, the first type of Sinc3 filter, which was originally produced by ADI, has a simple structure, but will cause extra pure delay. In the servo system, the pure delay in the loop will have a great impact on the servo bandwidth. The second type, the FIFO sinc3 filter, will not cause extra pure delay, but will cause a lot of resource occupation, which is not conducive to reducing production costs. Summary of the invention

[0013] In order to overcome the shortcomings and deficiencies of the prior art, the present invention provides an FPGA digital filter and an implementation method thereof, which have the advantages of low sampling delay and low resource occupancy.

[0014] The present invention adopts the following technical solution:

[0015] An FPGA digital filter includes a triple integrator, a register group, an addition and subtraction combinational logic circuit, a timer and a data output circuit;

[0016] The specific connection is:

[0017] The input end of the triple integrator is connected to the input signal, the output end of the triple integrator is connected to the input end of the register group, the output end of the register group is connected to the input end of the addition and subtraction combination logic circuit, and the output end of the addition and subtraction combination logic circuit is connected to the data output circuit;

[0018] The register group includes four registers connected in series;

[0019] The high-frequency clock signal is respectively connected to the timer, the data output circuit, the register group and the triple integrator. The output signal of the timer is respectively connected to the enable terminals of the four registers, and data is stored in the register group at the same time intervals.

[0020] The triple integrator is composed of three accumulators connected in series.

[0021] The addition-subtraction combinational logic circuit includes two three-input adders and one four-input adder-subtractor.

[0022] The output ends of two of the registers are connected to two three-input adders, amplified three times, and input into a four-input adder-subtractor together with the output signals of the other two registers to obtain the output result.

[0023] The time interval for the counter to control data storage is DR*T, where T is the period of the high-frequency clock signal.

[0024] A method for realizing an FPGA digital filter, wherein a triple integrator uses a high-frequency clock as a driving clock and outputs a signal value after accumulation, and a rear-stage output of the triple integrator is connected to an input end of a series register group, and the series register group uses a high-frequency clock as a driving clock. Under the control of an enable signal with equal time intervals sent by a counter, the data is stored in four registers of the series register group in a queue manner, and the output signals of the four registers of the register group are all input into an addition-subtraction logic circuit, and finally the final filtered signal is obtained from the output of the addition-subtraction logic circuit.

[0025] Beneficial effects of the present invention:

[0026] The filter of the present invention occupies less resources and uses a high-frequency clock signal MCLKIN for output instead of a divided clock, so that the output will not have a large delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural diagram of the present invention;

[0028] Figure 2 is a structural connection diagram of an embodiment of the present invention;

[0029] Figure 3 It is a performance comparison diagram of the present invention and the prior art;

[0030] Figure 4 It is a schematic diagram of the FIFO filter structure in the prior art. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below in conjunction with embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0032] Example

[0033] like Figure 1 and Figure 2 As shown, an FPGA digital filter includes a triple integrator, a register group, an addition and subtraction combinational logic circuit, a timer and a data output circuit;

[0034] The specific connection is:

[0035] The input end of the triple integrator is connected to the input signal, the output end of the triple integrator is connected to the input end of the register group, the output end of the register group is connected to the input end of the addition and subtraction combination logic circuit, and the output end of the addition and subtraction combination logic circuit is connected to the data output circuit;

[0036] The register group includes four registers connected in series;

[0037] The high-frequency clock signal is respectively connected to the timer, the data output circuit, the register group and the triple integrator. The output signal of the timer is respectively connected to the enable terminals of the four registers, and data is stored in the register group at the same time intervals.

[0038] The triple integrator is composed of three accumulators connected in series.

[0039] The addition-subtraction combinational logic circuit includes two three-input adders and one four-input adder-subtractor.

[0040] The four registers are X0, X1, X2 and X3. The outputs of the four registers are used as inputs of the addition and subtraction logic circuit. The outputs of X1 and X2 need to be increased by 3 times. Therefore, the X1 and X2 signals are input to two 3-input adders, and the results are X1+X1+X1=3*X1, X2+X2+X2=3*X2. Then these two results and X0 and X3 are input to a four-input adder-subtractor to obtain the final result OUTPUT=X0-3*X1+3*X2-X3.

[0041] The time interval for counter-controlled data storage is DR*T, and DR is generally 32.

[0042] The working process of the present invention is:

[0043] The triple integrator uses a high-frequency clock as a driving clock and outputs the accumulated signal value. The rear-stage output of the triple integrator is connected to the input end of the series register group. The series register group uses a high-frequency clock as a driving clock. Under the control of the enable signal with equal time intervals sent by the counter, the data is stored in the four registers of the series register group in a queue manner. The output signals of the four registers of the register group are all input into the addition and subtraction logic circuit, and finally the final filtered signal is obtained from the output of the addition and subtraction logic circuit.

[0044] The filter of the present invention occupies very little resources, adopts a high-frequency clock signal MCLKIN for output instead of a clock after frequency division, and the output will not be greatly delayed.

[0045] like Figure 3As shown, the working performance of the filter of the present invention is compared with two commonly used filters in the prior art. The hysteresis phenomenon of the IP core of ADI Company is the most obvious, and the output of the FIFO filter is closest to the ideal transfer function. The filter of this article is equivalent to the FIFO filter with zero-order hold at an interval of DR*T.

[0046] The output clock of the output register DATA of this method is driven by the high-frequency signal MCLKIN (instead of using the divided WORD_CLK), which means that every time the value in the X0~3 register group changes, DATA will be output in the next MCLKIN cycle. Compared with the original 3*T cycle delay of ADI, it has been greatly improved. And the registers used are only 4 groups instead of 3*DR groups, which occupies fewer resources than the traditional FIFO method.

[0047] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. An FPGA digital filter, characterized in that: It includes a triple integrator, a register group, an addition and subtraction combinational logic circuit, a timer and a data output circuit; The specific connection is: The input end of the triple integrator is connected to the input signal, the output end of the triple integrator is connected to the input end of the register group, the output end of the register group is connected to the input end of the addition and subtraction combination logic circuit, and the output end of the addition and subtraction combination logic circuit is connected to the data output circuit; The register group includes four registers connected in series; The high-frequency clock signal is respectively connected to the timer, the data output circuit, the register group and the triple integrator, the output signal of the timer is respectively connected to the enable terminals of the four registers, and the data is stored in the register group at the same time intervals; The addition-subtraction combinational logic circuit includes two three-input adders and one four-input adder-subtractor; The outputs of two of the registers are connected to two three-input adders, amplified three times, and then input into a four-input adder-subtractor together with the output signals of the other two registers to obtain the output result; The triple integrator is composed of three accumulators connected in series.

2. The FPGA digital filter according to claim 1, characterized in that: The time interval of the timer controlling data storage is DR*T, where T is the period of the high-frequency clock signal.

3. A method for implementing an FPGA digital filter according to any one of claims 1 to 2, characterized in that: The triple integrator uses a high-frequency clock as a driving clock and outputs the accumulated signal value. The rear-stage output of the triple integrator is connected to the input end of the series register group. The series register group uses a high-frequency clock as a driving clock. Under the control of the enable signal with equal time intervals sent by the timer, the data is stored in the four registers of the series register group in a queue manner. The output signals of the four registers of the register group are all input into the addition and subtraction logic circuit, and finally the final filtered signal is obtained from the output of the addition and subtraction logic circuit.

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