Adaptive hybrid scheduling accelerator based on FPGA (Field Programmable Gate Array) and implementation method thereof

Abstract

The invention provides a self-adaptive hybrid scheduling accelerator based on an FPGA (Field Programmable Gate Array) and an implementation method thereof. The accelerator comprises a control interface unit (CIU), a multi-level priority queue array (MPQA) and an adaptive scheduling core (ASH). The method aims at solving the problems of large task scheduling delay, slow interrupt response, system throughput bottleneck and the like caused by a traditional software scheduler in a heterogeneous multi-core SoC, a high-requirement embedded system and an edge computing node.

Description

Technical Field

[0001] This invention relates to the field of accelerator technology, and in particular to an FPGA-based adaptive hybrid scheduling accelerator and its implementation method. Background Technology

[0002] The operating system's task scheduler manages task execution order and resource allocation, and its performance directly impacts the response speed, throughput, and real-time performance of heterogeneous multi-core systems. Traditional Linux Completely Fair Scheduler (CFS) and real-time schedulers (SCHED_RR / SCHED_FIFO) run on general-purpose CPU kernels, requiring frequent traversal of red-black trees or linked list ready queues, updating vruntime, calculating time slices, and incurring overhead for interrupt handling and context saving / restoration. As the number of tasks and CPU cores increases, the scheduling path grows non-linearly, with context switching latency typically exceeding 5µs and interrupt response time approaching 10µs. This results in millisecond-level jitter in high-concurrency or hard real-time scenarios, failing to meet sub-millisecond deterministic requirements.

[0003] To reduce scheduling latency, scholars both domestically and internationally have proposed various hardware and software collaborative solutions, but all of them have significant shortcomings: In 2022, Xu et al. published "Real-time scheduling for communication delay awareness in FPGA multi-core systems" in Microprocessors and Microsystems. They adjusted task priorities after monitoring inter-core communication overhead through the FPGA, but the scheduling decision was still made on the CPU side. The measured context switching latency was still as high as 5.14µs and the interrupt response was 9.82µs.

[0004] In 2023, Rodriguez-Canal et al. proposed "preemptive task scheduling based on partial reconfiguration" in "Concurrency and Computation: Practice and Experience". It supports both EDF and RR algorithms, but the reconfiguration area occupies 40% of LUT resources and the policy switching takes 50ms, which leads to the risk of real-time tasks starving.

[0005] In 2024, Paul and Danelutto proposed "Data Center FPGA Power Aware Task Scheduling" in Euromicro PDP, which only accelerated task-FPGA binding decisions and did not involve end-to-end paths such as context saving and interrupt arbitration. The measured interrupt response was still >9µs.

[0006] In 2025, Karabulut et al. proposed THEMIS multi-tenant fair scheduler, which supports both time and energy consumption objectives. However, it adopts a static compilation method, and the task classification and scheduling strategy are fixed at compile time. It cannot be dynamically adjusted according to instantaneous load at runtime, and the average tardiness increases by 38% when real-time tasks arrive in bursts.

[0007] The common flaw of the above solutions is that: (1) The strategy is deeply coupled with the hardware. Switching the scheduling algorithm requires resynthesis or reconfiguration, resulting in large latency. (2) Only the "task selection" sub-step is accelerated, but the key paths such as context switching, interrupt arbitration, and cross-core migration are not hardware-based, resulting in limited improvement in end-to-end latency; (3) Lack of runtime awareness mechanism, unable to dynamically adjust scheduling strategy based on CPU utilization, real-time characteristics of tasks, queue length, etc., resulting in insufficient fairness in high-load scenarios and insufficient responsiveness in low-load scenarios. (4) It does not support heterogeneous multi-core expansion, lacks inter-core task stealing and load balancing units, and is difficult to achieve scalable deployment on CPU-FPGASoC platforms.

[0008] Therefore, existing technologies are still unable to complete the "perception-decision-switching" closed loop in microseconds, and cannot meet the comprehensive requirements of heterogeneous multi-core hard real-time systems for determinism, low latency, and high throughput. Summary of the Invention

[0009] This invention proposes an adaptive hybrid scheduling accelerator based on FPGA and its implementation method. By designing an adaptive hybrid scheduler on a Field-Programmable Gate Array (FPGA), this invention aims to solve problems such as large task scheduling latency, slow interrupt response, and system throughput bottlenecks caused by traditional software schedulers in heterogeneous multi-core SoCs, demanding embedded systems, and edge computing nodes.

[0010] The present invention is achieved through the following technical solution: The present invention proposes an FPGA-based adaptive hybrid scheduling accelerator, the accelerator including a control interface unit (CIU), a multi-level priority queue array (MPQA), and an adaptive scheduling core (ASH). The control interface unit (CIU) interacts with the ARM core via AXI-Lite, receives the current task set status and policy switching commands, and writes the selected next-task ID back to the kernel. The multi-level priority queue array (MPQA) instantiates N parallel FIFOs in the FPGA Block RAM, each corresponding to a priority. The head / tail pointers of the queues are synchronized using independent clock domains to ensure that all queue heads are read out in parallel in a single cycle. The adaptive scheduling core ASH contains a "policy decision machine" and a "task migration machine". The policy decision machine samples queue length, CPU utilization and task waiting time in the form of a hardware state machine. It switches between RR, SJF and AHS modes in a single cycle according to the threshold table without reconfiguring the bit stream. The task migration machine is responsible for cross-core load balancing. When it detects that a core is idle for more than 256 clock cycles, it automatically moves the task at the tail of the furthest non-empty queue to the idle core queue. The migration process is completed by DMA on the FPGA side and is transparent to the CPU.

[0011] This invention also proposes a method for implementing an adaptive hybrid scheduling accelerator based on the aforementioned FPGA, the method comprising: Step 1: System power-on and hardware resource initialization; The FPGA side completes global reset and clock domain synchronization, the CIU initializes internal registers, the MPQA clears all FIFO queues and verifies the available capacity of UltraRAM to ensure that at least 32 tasks' context storage space is supported; Step 2: Establishing shared memory mapping and data structures; On the ARM side, the scheduling driver module is loaded via insmod, and mmap() is called to map 2 MB of contiguous physical memory starting from physical address 0x1_0000_0000 into a user-mode virtual address space; A circular TCB pool is built in this shared area, with each TCB entry being 128 bytes, containing task ID, priority, remaining runtime, context pointer, and checksum; Step 3: Initial task TCB batch injection; Step 4: Initial loading of task context and allocation of UltraRAM; Step 5: Scheduler activation and monitoring mode startup; Step 6: Schedule event triggering and fast interrupt response; Step 7: Parallel arbitration and ASH dynamic decision-making; Step 8: Zero-copy context switch execution; Step 9: Adaptive strategy dynamic updates and seamless switching; Step 10: Anomaly monitoring and system consistency maintenance.

[0012] Furthermore, in step 3, the ARM side writes the TCB data of the initial task set to the shared RAM through the ioctl() interface according to the application requirements; every 16 TCBs written triggers a DMA batch transfer request of the CIU, and the CIU asynchronously moves the TCB data to the corresponding priority FIFO of the MPQA through the AXI-Lite bus. When the transfer is completed, the CIU sets the TCB_READY status flag.

[0013] Furthermore, in step 4, the ARM side uses the write() system call to write the initial context snapshot of each task into the data register of the CIU in the order of task ID; the address generation unit AGU in the CIU allocates a fixed UltraRAM address offset to each task, completes the on-chip storage of the context within 3 clock cycles, and establishes a direct mapping table from TCB to UltraRAM address.

[0014] Furthermore, in step 5, the ARM side writes 0x01 to the CIU command register, and the ASH enters the active monitoring state; at this time, the load monitoring unit inside the MPQA begins to count the depth of each priority queue, the task arrival rate and the service time, calculates the system load index ρ=λ / μ in real time, and writes it to the ASH visualization monitoring register for the ARM side to poll and read.

[0015] Furthermore, in step 6, when a timer interrupt or peripheral interrupt arrives, the ARM-side GIC performs only a simplified ISR: disables interrupt nesting and writes a 1-byte command to the CIU's SCHED_TRIGGER register before returning immediately; this operation compresses the ARM intervention delay to <20 ns, avoiding kernel-mode context saving overhead.

[0016] Furthermore, in step 7, the FPGA side reads the queue heads of the 16 FIFOs of MPQA simultaneously on the next rising edge of the clock and sends them to the parallel decision machine of ASH. ASH calculates the dynamic priority weight of each task according to the algorithm specified in the "current policy register" and performs a two-stage pipeline decision in combination with the load index ρ: the first stage filters the highest priority task, the second stage handles weight conflicts, and finally outputs the next-task ID, with a total decision delay of ≤2 clock cycles.

[0017] Furthermore, in step 8, after the ASH decision is completed, the engine switching is initiated immediately: Save phase: Write the 16 general-purpose registers of the current task + PC + PSR from the CPU interface back to the original address of UltraRAM in parallel via the wide-bit bus, which takes 1 clock cycle; Recovery phase: The new context is read from UltraRAM according to the next-task ID and written to the CPU register file through the AXI-HP port within 3 clock cycles; the entire process does not involve DDR and the switching latency is <50 ns.

[0018] Furthermore, in step 9, if the load monitoring unit detects a sudden change in ρ or a task timeout rate > 5%, it automatically triggers a policy update interrupt to ASH; ASH loads new policy parameters from the policy configuration table during idle periods and atomically updates the "current policy register"; subsequent enqueue operations of MPQA are immediately sorted according to the new policy, and the ongoing decision process is not affected, achieving zero jitter in policy switching.

[0019] Furthermore, in step 10, the CIU's built-in watchdog timer monitors the time consumed for each scheduling. If the switching time is greater than 100 ns, a SCHED_ERR interrupt is triggered to the ARM. The exception handler on the ARM side reads the CIU's diagnostic register and performs selective task termination or FPGA partial reconfiguration. At the same time, after completing every 128 scheduling cycles, the CIU automatically writes the MPQA queue statistics information into the audit area of ​​the shared RAM for the ARM side to perform long-term load analysis and energy consumption optimization.

[0020] The beneficial effects of this invention are: 1. End-to-end hardware implementation: The entire process of queue management, task decision, context switching, and interrupt arbitration is moved into the FPGA. The measured context switching time is 0.52µs and the interrupt response time is 2.03µs, which is 91% and 79% lower than the software solution, respectively.

[0021] 2. Microsecond-level strategy hot switching: Switching between RR, SJF, and AHS modes in a single cycle via an on-chip state machine and threshold register, eliminating the need for bitstream reconfiguration. Switching latency is <50ns, which is 10 times faster than some reconfiguration schemes. 6 times.

[0022] 3. Runtime heterogeneity awareness: The hardware samples queue length, CPU utilization, and task waiting time in real time, automatically assigning real-time tasks to the SJF channel and ordinary tasks to the RR channel, and supports cross-core DMA migration, improving CPU utilization by 25% and reducing task waiting time by 30%.

[0023] 4. Low resource consumption: All logic consumes only about 12% of the Zynq7020's LUT and 18% of its BRAM, with a power consumption increase of <0.3W, making it compatible with edge embedded scenarios; the interface complies with the AXI standard and can be smoothly migrated to next-generation SoCs such as Zynq UltraScale+ and Kria. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 This is a system scheduling architecture diagram. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The technical problem to be solved by this invention: The software scheduler has a large context switching latency (>5µs) and a slow interrupt response (≈10µs), which cannot meet the sub-microsecond deterministic requirements of hard real-time tasks. Existing hardware scheduling solutions only accelerate the "task selection" sub-step, without hardware-based implementation of end-to-end paths such as context saving / restoration, interrupt arbitration, and cross-core load balancing, resulting in limited overall latency improvement. Strategy switching relies on FPGA reconfiguration or kernel module reloading, which takes tens of milliseconds and cannot be dynamically adjusted according to instantaneous load. The lack of a heterogeneous multi-core awareness mechanism prevents runtime task migration based on real-time task characteristics and inter-core states, resulting in high-load cores queuing and low-load cores being idle, thus limiting system throughput.

[0028] In response to the above problems, combined with Figure 1 This invention proposes an FPGA-based adaptive hybrid scheduling accelerator that offloads the critical paths of the Linux scheduler—ready queue management, task selection, context switching, and interrupt arbitration—to FPGA programmable logic, achieving microsecond-level scheduling closed-loop. The accelerator includes a control interface unit (CIU), a multi-level priority queue array (MPQA), and an adaptive scheduling core (ASH). The control interface unit (CIU) interacts with the ARM core via AXI-Lite, receives the current task set status and policy switching commands, and writes the selected next-task ID back to the kernel. The multi-level priority queue array (MPQA) instantiates N parallel FIFOs in the FPGA Block RAM, each corresponding to a priority. The head / tail pointers of the queues are synchronized using independent clock domains to ensure that all queue heads are read out in parallel in a single cycle. The adaptive scheduling core ASH contains a "policy decision machine" and a "task migration machine". The policy decision machine samples queue length, CPU utilization and task waiting time in the form of a hardware state machine. It switches between RR, SJF and AHS modes in a single cycle according to the threshold table without reconfiguring the bit stream. The task migration machine is responsible for cross-core load balancing. When it detects that a core is idle for more than 256 clock cycles, it automatically moves the task at the tail of the furthest non-empty queue to the idle core queue. The migration process is completed by DMA on the FPGA side and is transparent to the CPU.

[0029] This invention also proposes a method for implementing an adaptive hybrid scheduling accelerator based on the aforementioned FPGA, the method comprising: Step 1: System power-on and hardware resource initialization; The FPGA side completes global reset and clock domain synchronization, the CIU (Control Interface Unit) initializes internal registers (command register, status register, policy register), and the MPQA (Multi-Priority Queue Arbiter) clears all FIFO queues and verifies the available capacity of UltraRAM (On-Chip High-Speed ​​Memory) to ensure that at least 32 tasks have sufficient context storage space. Step 2: Shared memory mapping and data structure establishment; On the ARM side, the scheduling driver module is loaded via insmod, and mmap() is called to map 2 MB of contiguous physical memory starting from physical address 0x1_0000_0000 into a user-mode virtual address space; A circular TCB pool is built in this shared area, with each TCB entry being 128 bytes, containing task ID (8 bits), priority (4 bits), remaining runtime (32 bits), context pointer (40 bits), and checksum (8 bits); Step 3: Initial Task TCB Batch Injection; In step 3, the ARM side writes the initial task set (up to 256) of TCB data to the shared RAM through the ioctl() interface according to application requirements; every 16 TCBs written triggers a CIU DMA batch transfer request, and the CIU asynchronously moves the TCB data to the corresponding priority FIFO of MPQA through the AXI-Lite bus (supporting a total of 16 priority levels). When the transfer is complete, the CIU sets the TCB_READY status flag.

[0030] Step 4: Initial loading of task context and allocation of UltraRAM; In step 4, the ARM side uses the write() system call to write the initial context snapshot (16 general-purpose registers + PC + PSR, a total of 288 bits) of each task into the data register of the CIU in the order of task ID; The address generation unit AGU in the CIU allocates a fixed UltraRAM address offset (task ID × 512 bits) for each task, completes the on-chip storage of the context within 3 clock cycles, and establishes a direct mapping table from TCB to UltraRAM address.

[0031] Step 5: Scheduler activation and monitoring mode startup; In step 5, 0x01 (START command) is written to the CIU command register on the ARM side, and ASH (adaptive scheduling hardware) enters active monitoring state; At this time, the load monitoring unit inside MPQA begins to count the depth of each priority queue, task arrival rate and service time, calculates the system load index ρ=λ / μ in real time, and writes it to the visualization monitoring register of ASH for ARM side to poll and read.

[0032] Step 6: Scheduled Event Triggering and Fast Interrupt Response; In step 6, when a timer interrupt (e.g., a 1 ms cycle) or peripheral interrupt (e.g., DMA completion) arrives, the ARM-side GIC (General Purpose Interrupt Controller) executes only a minimal ISR: disables interrupt nesting and writes a 1-byte command (0x02 for time slice exhaustion, 0x03 for I / O completion) to the CIU's SCHED_TRIGGER register before immediately returning. This operation compresses the ARM intervention delay to <20 ns, avoiding kernel-mode context saving overhead.

[0033] Step 7: Parallel Arbitration and ASH Dynamic Decision; In step 7, the FPGA side reads the queue heads of the 16 FIFOs of MPQA (a total of 16 candidate tasks) on the next rising edge of the clock and sends them to the parallel decision machine of ASH; ASH calculates the dynamic priority weight of each task according to the algorithm specified in the "Current Policy Register" (such as EDF, RMS or user-defined), and performs a two-stage pipeline decision in combination with the load index ρ: the first stage filters the highest priority task, the second stage handles weight conflicts, and finally outputs the next-task ID, with a total decision delay of ≤2 clock cycles (approximately 10 ns @ 200 MHz).

[0034] Step 8: Zero-copy context switch execution; In step 8, after the ASH decision is completed, the switching engine starts immediately: Save phase: Write the 16 general-purpose registers of the current task + PC + PSR from the CPU interface (AXI-HP) back to the original address of UltraRAM in parallel via the wide-bit bus (512 bits), which takes 1 clock cycle; Recovery phase: The new context is read from UltraRAM according to the next-task ID and written to the CPU register file through the AXI-HP port within 3 clock cycles; the entire process does not involve DDR and the switching latency is <50 ns.

[0035] Step 9: Adaptive policy dynamic update and seamless switching; In step 9, if the load monitoring unit detects a sudden change in ρ (e.g., |Δρ|>0.3) or a task timeout rate>5%, it automatically triggers a policy update interrupt to ASH; ASH loads new policy parameters from the policy configuration table (located in the high address area of ​​shared RAM) during idle periods (when there are no scheduling events) and atomically updates the "current policy register"; Subsequent enqueue operations of MPQA are immediately sorted according to the new policy, and the ongoing decision process is not affected, achieving zero jitter in policy switching.

[0036] Step 10: Anomaly Monitoring and System Consistency Maintenance. In Step 10, the CIU's built-in watchdog timer monitors the time consumed for each scheduling operation. If the switching time > 100 ns, a SCHED_ERR interrupt is triggered to the ARM. The ARM-side exception handler reads the CIU's diagnostic register (recording the fault task ID, FIFO overflow flag, and UltraRAM checksum error) and performs selective task termination or FPGA partial reconfiguration. Simultaneously, after every 128 scheduling operations, the CIU automatically writes the MPQA queue statistics information into the shared RAM's audit area for long-term load analysis and energy consumption optimization by the ARM side.

[0037] The MPQA and ASH use a parallel bus, with each queue head outputting 64 bits (task ID 32 bits + remaining time 24 bits + valid bit 1 bit + real-time flag 1 bit + reserved 6 bits). The ASH completes the comparison and outputs a 6-bit winning index in a single cycle. The CIU and MPQA are coupled through a dual-port RAM. The write port is controlled by the ARMAXI master, and the read port is controlled by the ASH, ensuring "no read / write conflicts". The cross-core migration channel uses AXI-Stream with a bandwidth of 12.8 GB / s, and the time taken to migrate a 256B task block is <2µs.

[0038] The present invention has the following advantages over the prior art: 1. Single-cycle parallel queue scanning + hardware state machine decision: Construct N priority FIFOs within the FPGA, with parallel output from the head pointer register. The highest priority task ID is obtained in a single cycle through a comparison tree. Simultaneously, using queue length, CPU utilization, and average waiting time as inputs, a hardware state machine is used to complete the RR (Recursive Regression) process. SJF AHS's three strategies enable microsecond-level hot switching without requiring bitstream reconfiguration.

[0039] 2. End-to-end hardware context switching: The task context (16×32 bit register + PC + PSR) is cached in the FPGA UltraRAM. After the scheduling event is triggered, the read-write is completed through the AXI-HP port in 3 clock cycles, realizing a 0.52 µs context switch. The CPU only writes 1 byte of command, and the rest is completed automatically by the hardware.

[0040] 3. Cross-core DMA task migration: When the idle count of a core is ≥256, the migration machine automatically starts AXI-Stream DMA to move the 256-byte task block at the end of the furthest non-empty queue to the idle core. The migration takes <2 µs. After the migration is completed, the dual-port RAM pointer is updated to achieve load balancing between cores.

[0041] 4. True dual-port conflict-free communication: The CIU and MPQA use true dual-port RAM, with independent clock domains for the ARM write port and ASH read port, and synchronized Gray code pointers to ensure that there are no read / write conflicts even when scheduling events and task enqueuing are executed concurrently.

[0042] The above provides a detailed description of the FPGA-based adaptive hybrid scheduling accelerator and its implementation method proposed in this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. An FPGA-based adaptive hybrid scheduling accelerator, characterized in that, The accelerator includes a control interface unit (CIU), a multi-level priority queue array (MPQA), and an adaptive scheduling core (ASH). The control interface unit (CIU) interacts with the ARM core via AXI-Lite, receives the current task set status and policy switching commands, and writes the selected next-task ID back to the kernel. The multi-level priority queue array (MPQA) instantiates N parallel FIFOs in the FPGA Block RAM, each corresponding to a priority. The head / tail pointers of the queues are synchronized using independent clock domains to ensure that all queue heads are read out in parallel in a single cycle. The adaptive scheduling core ASH contains a "policy decision machine" and a "task migration machine". The policy decision machine samples queue length, CPU utilization and task waiting time in the form of a hardware state machine. It switches between RR, SJF and AHS modes in a single cycle according to the threshold table without reconfiguring the bit stream. The task migration machine is responsible for cross-core load balancing. When it detects that a core is idle for more than 256 clock cycles, it automatically moves the task at the tail of the furthest non-empty queue to the idle core queue. The migration process is completed by DMA on the FPGA side and is transparent to the CPU.

2. A method for implementing an adaptive hybrid scheduling accelerator based on the FPGA of claim 1, characterized in that, The implementation method includes: Step 1: System power-on and hardware resource initialization; The FPGA side completes global reset and clock domain synchronization, the CIU initializes internal registers, the MPQA clears all FIFO queues and verifies the available capacity of UltraRAM to ensure that at least 32 tasks' context storage space is supported; Step 2: Establishing shared memory mapping and data structures; On the ARM side, the scheduling driver module is loaded via insmod, and mmap() is called to map 2 MB of contiguous physical memory starting from physical address 0x1_0000_0000 into a user-mode virtual address space; A circular TCB pool is built in this shared area, with each TCB entry being 128 bytes, containing task ID, priority, remaining runtime, context pointer, and checksum; Step 3: Initial task TCB batch injection; Step 4: Initial loading of task context and allocation of UltraRAM; Step 5: Scheduler activation and monitoring mode startup; Step 6: Schedule event triggering and fast interrupt response; Step 7: Parallel arbitration and ASH dynamic decision-making; Step 8: Zero-copy context switch execution; Step 9: Adaptive strategy dynamic updates and seamless switching; Step 10: Anomaly monitoring and system consistency maintenance.

3. The implementation method according to claim 2, characterized in that, In step 3, the ARM side writes the TCB data of the initial task set to the shared RAM through the ioctl() interface according to the application requirements. Every 16 TCBs written triggers a DMA batch transfer request of the CIU. The CIU asynchronously moves the TCB data to the corresponding priority FIFO of the MPQA through the AXI-Lite bus. When the transfer is completed, the CIU sets the TCB_READY status flag.

4. The implementation method according to claim 2, characterized in that, In step 4, the ARM side uses the write() system call to write the initial context snapshot of each task into the data register of the CIU in the order of task ID; the address generation unit AGU in the CIU allocates a fixed UltraRAM address offset for each task, completes the on-chip storage of the context within 3 clock cycles, and establishes a direct mapping table from TCB to UltraRAM address.

5. The implementation method according to claim 2, characterized in that, In step 5, the ARM side writes 0x01 to the CIU command register, and the ASH enters the active monitoring state. At this time, the load monitoring unit inside the MPQA begins to count the depth of each priority queue, the task arrival rate and the service time, calculates the system load index ρ=λ / μ in real time, and writes it to the ASH visualization monitoring register for the ARM side to poll and read.

6. The implementation method according to claim 2, characterized in that, In step 6, when a timer interrupt or peripheral interrupt arrives, the ARM-side GIC performs only a simplified ISR: disables interrupt nesting and writes a 1-byte command to the CIU's SCHED_TRIGGER register before returning immediately; this operation compresses the ARM intervention delay to <20 ns, avoiding kernel-mode context saving overhead.

7. The implementation method according to claim 2, characterized in that, In step 7, the FPGA side reads the queue heads of the 16 FIFOs of MPQA simultaneously on the next rising edge of the clock and sends them to the parallel decision machine of ASH. ASH calculates the dynamic priority weight of each task according to the algorithm specified in the "current policy register" and performs a two-stage pipeline decision based on the load index ρ: the first stage filters the highest priority task, the second stage handles weight conflicts, and finally outputs the next-task ID. The total decision delay is ≤2 clock cycles.

8. The implementation method according to claim 2, characterized in that, In step 8, after the ASH ruling is completed, the engine switching is initiated immediately: Save phase: Write the 16 general-purpose registers of the current task + PC + PSR from the CPU interface back to the original address of UltraRAM in parallel via the wide-bit bus, which takes 1 clock cycle; Recovery phase: The new context is read from UltraRAM according to the next-task ID and written to the CPU register file through the AXI-HP port within 3 clock cycles; the entire process does not involve DDR and the switching latency is <50 ns.

9. The implementation method according to claim 2, characterized in that, In step 9, if the load monitoring unit detects a sudden change in ρ or a task timeout rate > 5%, it automatically triggers a policy update interrupt to ASH. During the idle period, ASH loads the new policy parameters from the policy configuration table and atomically updates the "current policy register". Subsequent enqueue operations of MPQA are immediately sorted according to the new policy, and the ongoing decision process is not affected, achieving zero jitter in policy switching.

10. The implementation method according to claim 2, characterized in that, In step 10, the CIU's built-in watchdog timer monitors the time consumed for each scheduling. If the switching time is greater than 100 ns, a SCHED_ERR interrupt is triggered to the ARM. The exception handler on the ARM side reads the CIU's diagnostic register and performs selective task termination or partial FPGA reconfiguration. At the same time, after completing every 128 scheduling cycles, the CIU automatically writes the MPQA queue statistics information into the audit area of ​​the shared RAM for the ARM side to perform long-term load analysis and energy consumption optimization.

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