Techniques for computing platform initialization

Abstract

Embodiments generally relate to techniques for computing platform initialization, such as, for example, initializing one or more dependent bootable components (DBCs) of a computing platform by utilizing a field programmable gate array (FPGA). In one or more embodiments, after the computing platform is initialized, the FPGA may be reconfigured to perform runtime operations. In embodiments disclosed herein, the DBC may include initialization of any hardware or software components (such as silicon components and platform components) of the computing platform. In such embodiments, a boot sequence may include boot instructions for initializing a set of DBCs. In some such embodiments, the boot sequence may initialize the computing platform. In one or more embodiments, computing platform initialization may include preparing the computing platform for performing input / output (I / O) operations. In one or more such embodiments, the I / O operations may be performed via an operating system.

Description

Background Art

[0001] When a computing platform is initialized or booted, it may go through an initial series of processes. The initial series of processes may be referred to as a boot sequence. Typically, during the boot sequence, the computing platform may activate the necessary hardware and software components to enable the computing platform to perform input / output functions. For example, the boot sequence may conclude when the operating system has been loaded and is ready for user mode. The amount of time the boot sequence takes varies based on the various hardware and software components required by the computing platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 An embodiment of a first operating environment is illustrated.

[0003] Figure 2 An embodiment of a second operating environment is illustrated.

[0004] Figure 3 An embodiment of a third operating environment is illustrated.

[0005] Figure 4 An embodiment of a first logic flow to offload portions of platform initialization from a host processor to an FPGA is illustrated.

[0006] Figure 5 An embodiment of a second logic flow for distributing computing resources (eg, drivers) between a host processor and an FPGA for computing platform initialization is illustrated.

[0007] Figure 6 An embodiment of a third logic flow for executing a set of boot instructions for computing platform initialization is illustrated.

[0008] Figure 7 An embodiment of a storage medium is shown.

[0009] Figure 8 An embodiment of a computing architecture is illustrated.

[0010] Fig. 9 An embodiment of a communication architecture is illustrated. DETAILED DESCRIPTION

[0011] Embodiments generally relate to techniques for computing platform initialization, such as, for example, initializing one or more dependent bootable components (DBCs) of a computing platform by utilizing a field programmable gate array (FPGA). In one or more embodiments, after initialization of the computing platform, the FPGA may be reconfigured to perform runtime operations. In embodiments disclosed herein, the DBC may include initialization of any hardware or software component (such as, silicon components and platform components) of the computing platform. In such embodiments, a boot sequence may include execution of one or more boot instruction sets for initializing a DBC set. In some such embodiments, a boot sequence may initialize the computing platform. In one or more embodiments, computing platform initialization may include preparing the computing platform for performing input / output (I / O) operations. In one or more such embodiments, I / O operations may be performed via an operating system. For example, the computing platform may perform I / O operations through an application implemented by an operating system. In embodiments, the computing platform may be referred to as a platform.

[0012] Such embodiments described herein specifically relate to platforms that utilize both a host processor and an FPGA for platform initialization. In one embodiment, for example, a system for platform initialization may include a platform containing a set of DBCs, a host processor, and an FPGA. In one or more embodiments, as part of a boot sequence, a host processor may execute a first boot instruction set to initialize the platform for executing I / O instructions. In one or more such embodiments, a first boot instruction set may initialize each DBC in a first subset of a set of DBCs. In various embodiments, as part of a boot sequence, an FPGA may execute a second boot instruction set that is used to initialize each DBC in a second subset of a set of DBCs. These and other embodiments are described and claimed.

[0013] Some challenges faced by platform initialization include that the boot sequence includes a boot sequence with computationally intensive boot instructions. These challenges may arise from the inability to initialize the required number of DBCs in the boot sequence within an acceptable amount of time. For example, the host processor may have to execute all boot instructions in the boot sequence or at least an unnecessarily large portion of the boot instructions in the boot sequence. In some embodiments, this may cause the boot time to exceed the boot time requirement or target. For example, for security reasons, computer vision applications may have strict boot time requirements. In another example, a slow boot time may result in a non-responsive user interface. Adding further complexity, the boot sequence may include the booting of numerous DBCs with interdependencies. For example, a first DBC may include a library, and a second DBC may include a memory controller that must be loaded before the library can be accessed. This may result in additional delays in boot time. These and other factors may cause platform initialization to have poor performance and limited efficiency. Such limitations may greatly reduce the availability and applicability of the platform, resulting in an ineffective system with limited responsiveness and reduced capabilities.

[0014] The various embodiments disclosed herein include a computing platform having an FPGA that can reduce the boot time of the platform. In one or more embodiments, the constraints of sequentially initializing silicon components and platform components can be mitigated by using multi-processor firmware flows and the configurability of the FPGA. In one or more such embodiments, the separation of the boot process in the boot sequence can be used to initialize the platform between the host processor and the FPGA to mitigate these constraints. For example, as part of the boot sequence, the host processor can execute a first boot instruction set, and as part of the boot sequence, the FPGA can execute a second boot instruction set. In some embodiments, the FPGA can improve the boot time so that the computing platform can meet strict boot time goals, and in some such embodiments, the computing platform can have 2 seconds from startup until the software application runs. For example, meeting strict boot time goals can enable the computing platform to be used in autonomous driving applications (e.g., Internet of Things (IoT) automotive solutions). In some such instances, meeting strict boot time goals can improve the safety of autonomous driving applications. In various embodiments, after the platform has been initialized, the FPGA can be reconfigured for one or more runtime operations. In various such embodiments, the one or more runtime operations can enable the computing platform to achieve additional and advantageous features. In these and other ways, a computing platform may achieve reliable and efficient platform initialization to achieve improved boot times and beneficial and useful runtime features, resulting in several technical effects and advantages.

[0015] According to the general reference to the notation and nomenclature used in this article, one or more parts of the following specific embodiments can be presented in terms of the program process executed on a computer or computer network. These procedural descriptions and representations are used by those skilled in the art to most effectively convey the essence of their work to other technicians in the field. Process is generally understood to be a self-consistent sequence of operations that causes a desired result. These operations are those operations that require physical manipulation of physical quantities. Usually but not necessarily, these quantities take the form of electrical, magnetic or optical signals that can be stored, transmitted, combined, compared and otherwise manipulated. Mainly for the reason of common usage, it is sometimes proven to be convenient to refer to these signals as positions, values, elements, symbols, characters, items, numbers, etc. However, it should be noted that all of these and similar terms are intended to be associated with appropriate physical quantities and are only convenient labels applied to those quantities.

[0016] In addition, these manipulations are usually referred to in terms as additions or comparisons that are usually associated with mental operations performed by a human operator. However, in any of the operations described herein that form part of one or more embodiments, in most cases, such capabilities without a human operator are necessary or desirable. On the contrary, these operations are machine operations. Useful machines for performing the operations of each embodiment include general-purpose digital computers and / or include devices specially constructed for the required purpose, which are selectively activated or configured by a computer program stored therein and written according to the teachings herein. Each embodiment also relates to a device or system for performing these operations. These devices can be specially constructed for the required purpose, or can include a general-purpose computer. According to the given description, the required structure of various these machines will be apparent.

[0017] Reference will now be made to the accompanying drawings, with the same reference numerals used throughout to refer to the same elements. In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the description. However, it may be apparent that novel embodiments may be implemented without these specific details. In other examples, known structures and devices are shown in block diagram form to facilitate the description of these structures and devices. The present invention is intended to cover all modifications, equivalents, and alternatives within the scope of the claims.

[0018] Figure 1The figure shows an example of an operating environment 100 that can represent various embodiments. The operating environment 100 may include a computing platform 102 having a host processor 104, an FPGA 106, a set of DBCs 108, and logic 110. In the operating environment 100, the host processor 104 and the FPGA 106 can independently initialize different subsets of the DBC set to initialize the computing platform 102 as part of a boot sequence. In various embodiments, a boot sequence can be used to prepare the computing platform for performing I / O operations. For example, a boot sequence can be used to prepare the computing platform for interacting with one or more other computing platforms through a network through an application implemented via an operating system. In some embodiments, the logic 110 can initiate a boot sequence to initialize the computing platform 102. In one or more embodiments, one or more portions of the logic 110 can be implemented to be executed by the host processor 104 and / or the FPGA 106. The embodiments are not limited to this context.

[0019] In various embodiments, the computing platform 102 may include an apparatus and method for performing initialization of silicon components and platform components (e.g., DBC 108) using FPGA 106 to shorten the boot sequence of the platform. In many embodiments, the configurability of multiple processor firmware flows and FPGA 106 can reduce the limitations associated with sequentially initializing silicon components and / or platform components by virtue of the separation of the boot process between the host processor 104 and the FPGA 106, such as the unified extensible firmware interface (UEFI), CoreBoot, and / or boot loader. In some embodiments, this may be a key factor in meeting increasingly stringent boot time requirements. In various embodiments, the FPGA 106 can enable the computing platform 102 to have advantageous system integration and bill of materials (BOM) cost savings, and provide additional runtime operations or accelerate existing runtime operations when compared to a computing platform that does not have an FPGA capable of accelerating boot operations.

[0020] In some embodiments, the ability of computing platform 102 to configure and reconfigure FPGA 106 may allow for repurposing FPGA 106 configurations on the fly and / or on demand. For example, configuring FPGA 106 as a processor engine to assist and accelerate platform initialization may occur during the boot phase, while reconfiguring FPGA 106 for runtime operations such as deep learning, computer vision, and / or I / O expansion may occur after the boot sequence is complete. In many embodiments, the boot sequence may include one or more of platform virtualization and loading of an operating system.

[0021] In many embodiments, the computing platform 102 can significantly reduce its boot time by utilizing the FPGA 106 as a silicon component and / or platform component (e.g., DBC 108) for initializing simultaneously with or even earlier than the host processor 104. In some embodiments, the host processor 104 may not be able to exit reset until other dependencies are resolved. For example, the PMC and the Converged Security Engine (CSE) may need to be initialized before the processing core of the host processor 104 fetches the first function (e.g., boot code). In addition, the FPGA 106 may be an independent subsystem that can start execution earlier than the host processor 104. Therefore, in such instances, some initialization can be offloaded to the FPGA 106. In various embodiments, after the host processor 104 is started and running, the FPGA 106 may still coordinate with the host processor 104, such as to share other workloads to reduce the overall system boot time. For example, an embedded multimedia controller (eMMC) and / or a universal flash memory (UFS) may take a considerable amount of time to initialize. In such examples, FPGA 106 may begin boot device initialization ahead of time, and when host processor 104 needs to read data from the boot medium, FPGA 106 may have previously initialized the boot medium.

[0022] In various embodiments, reusing or reconfiguring FPGA 106 as needed at different system stages (e.g., boot stage, runtime stage, user mode, kernel mode, operating system stage, etc.) can achieve a considerable reduction in overall platform BOM cost and runtime platform power consumption. In some embodiments, certain DBCs 108 may be required only during certain system stages. For example, a traditional host SM bus (SMBus) controller may be required only during a memory initialization stage. In such examples, the SM bus controller may read serial presence detection (SPD) information from a dual in-line memory module (DIMM) and is not used thereafter. In some such examples, FPGA 106 may be configured to provide SM bus controller functionality in an early boot stage. In further such examples, resources utilized by FPGA 106 may be reclaimed and programmed as different functions required in the OS stage. In some embodiments, FPGA 106 may reduce BOM cost and power consumption by removing a traditional SM bus controller from a design (e.g., a system on chip (SoC) design).

[0023] One or more embodiments described herein may include a computing platform 102 having logic 110 for performing one or more of the following functions. In some embodiments, the logic 110 may initiate a boot sequence for initializing the platform, such as to perform an I / O operation. In various embodiments, the logic 110 may utilize a host processor to initialize a first subset of a set of DBCs 108, and utilize an FPGA 106 to initialize a second subset of a set of DBCs 108. For example, as part of the boot sequence, the host processor 104 may execute a first set of boot instructions to initialize each DBC in a first subset of a set of DBCs 108. In such examples, the FPGA 106 may execute a second set of boot instructions to initialize each DBC in a second subset of a set of DBCs 108.

[0024] In some embodiments, initialization of the first DBC by the host processor 104 may be dependent on initialization of the second DBC by the FPGA 106. In this and other embodiments, initialization of the third DBC by the FPGA 106 may be dependent on initialization of the fourth DBC by the host processor 104. In many embodiments, the first DBC in the first subset of DBCs may include an operating system, and the second DBC in the second subset of DBCs may include a firmware interface. In various embodiments, the computing platform 102 may perform I / O operations through an operating system executed by the host processor 104. In some embodiments, the first DBC in the first subset may include a power management controller (PMC), and the second DBC in the second subset may include a bus controller such as a system management bus (SMB) controller.

[0025] In many embodiments, a first DBC in the first subset may include a library, and initialization of the first DBC may include loading the library from a memory. In many such embodiments, a second DBC in the second subset may include a memory controller, and initialization of the second DBC may occur before initialization of the first DBC. In one or more embodiments, a DBC in the first subset of DBCs may include a device tree, and initialization of the DBC may include building the device tree. In some embodiments, a DBC in the second subset of DBCs may include a bus design, and initialization of the second DBC includes loading the bus design. In various embodiments, a DBC in the second set of DBCs may include a network design, and initialization of the DBC includes loading the network design.

[0026] In various embodiments, the DBCs in the first subset may include a core of a host processor. In some embodiments, the DBCs in the first subset may include a peripheral component interconnect express (PCIe) device mapping, and initialization of the DBC may include registering FPGA 106 as a PCIe endpoint device. In some such embodiments, initialization of the DBC may occur before initialization of a second DBC, and initialization of the second DBC may include PCI enumeration and / or resource allocation. In many embodiments, the DBCs in the second subset may include a soft processor of FPGA 106. In one or more embodiments, the second boot instruction set may be located in an FPGA memory or in a memory inside FPGA 106. In some embodiments, the FPGA may indicate to the host processor 104 that the DBCs in the second subset of DBCs are successfully initialized. In various embodiments, after completing the boot sequence, the logic may reconfigure the FPGA to perform runtime operations.

[0027] Figure 2 The figure illustrates an example of an operating environment 200 that may represent various embodiments. In addition to the components of the operating environment 100, the operating environment 200 may also include host boot instructions 204, FPGA boot instructions 206, silicon components 208, and platform components 210. In various embodiments, the host boot instructions 204 may be stored or loaded into a memory internal to the host processor 104, and the FPGA boot instructions 206 may be stored or loaded into a memory internal to the FPGA 106. In one or more embodiments described herein, the host processor 104 may execute the host boot instructions 204 and the FPGA 106 may execute the FPGA boot instructions 206 to initialize the silicon components 208 and the platform components 210. For example, the host processor 104 may initialize a first portion of the DBC 108, and the FPGA 106 may initialize a second portion of the DBC 108. The embodiments are not limited in this context.

[0028] In one or more embodiments, the boot sequence of computing platform 102 may rely on boot code that may be structured and partitioned to be loaded on both host processor 104 and FPGA 106. In some embodiments, two separate binaries or sets of binaries may be generated and programmed, one for each of host processor 104 and FPGA 106 (e.g., host boot instructions 204 and FPGA boot instructions 206). In various embodiments, the host processor binary may be stored in a non-volatile serial peripheral interface (SPI) and the FPGA binary may be stored in built-in boot flash memory.

[0029] In some embodiments, upon power-up, a built-in read-only memory (ROM) in the FPGA 106 may initialize the soft processor core. In some such embodiments, the soft processor may then load the FPGA boot code from the built-in flash memory to initialize one or more DBCs 108 in the set (such as silicon components or platform components), and then begin execution of the FPGA boot code to initialize a portion of the DBCs 108 in the computing platform 102. In various embodiments, the host processor 104 may also fetch the host processor boot code and begin execution of the host processor boot code to initialize another portion of the DBCs 108 in the computing platform 102. In various such embodiments, the host processor 104 may fetch the host processor boot code and begin execution of the host processor boot code simultaneously with the loading and beginning of execution of the FPGA boot code. In other such embodiments, the host processor 104 may fetch the host processor boot code and begin execution of the host processor boot code after the loading and beginning of execution of the FPGA boot code. For example, the host processor 104 may fetch the host processor boot code and begin execution of the host processor boot code only once it exits reset. In such instances, FPGA 106 may initialize one or more DBCs 108 before host processor 104 exits reset.

[0030] In various embodiments, at the end of a boot sequence for initializing computing platform 102 (e.g., after an operating system has been loaded), FPGA 106 can be reconfigured with a different bitstream for runtime operations, such as core applications. For example, core applications may include machine learning, computer vision, deep learning, and similar applications. In one or more embodiments, reconfiguring FPGA 106 can automatically reclaim previously used FPGA boot sequence resources.

[0031] In many embodiments, the capabilities of computing platform 102 described herein may be critical in enabling other platform design features, such as artificial intelligence, signal processing, and other computational intelligence technologies that may be implemented on or by FPGA 106. Short boot times may be critical in highly responsive computing platforms, and the longer it takes to initialize the platform, the longer the platform capabilities are blocked from being ready. In some embodiments, this may be particularly useful in supporting self-driving cars, machine vision camera modules, and the like.

[0032] As previously mentioned, the host processor 104 and FPGA 106 may each go through separate and distinct boot flows (e.g., different initialization processes). In embodiments of the FPGA 106 with built-in boot flash capability, the device may be initialized almost instantaneously and placed into a state pending input or instruction from the host processor 104. In some embodiments, the host processor 104 may have dependencies on other silicon components 208 and / or platform components 210 (e.g., PMC or security engine ready) in a sequential fashion before performing silicon initialization such as memory I / O, followed by platform initialization such as Universal Serial Bus (USB), Ethernet devices, graphics devices. In some such embodiments, the FPGA 106 may reduce or remove bottlenecks arising from dependencies to improve boot time of the computing platform 102.

[0033] Figure 3 The figure shows an example of an operating environment 300 that can represent various embodiments. The operating environment 300 may include an FPGA 106 having a soft processor 302 and functional configurations 304-1, 304-2, 304-n. In one or more embodiments described herein, the FPGA 106 can be reconfigured so that the soft processor 304 supports the desired functionality. In some embodiments, the FPGA 106 can be reconfigured by reinitializing the soft processor 302 to have a desired functional configuration, such as deep learning, machine learning, computer vision, hardware acceleration, etc. The embodiments are not limited in this context.

[0034] In some embodiments, upon power-up, a built-in read-only memory (ROM) in the FPGA 106 may initialize the soft processor core to have an initialization acceleration functional configuration (e.g., functional configuration 304-1). In some such embodiments, the soft processor may then load the FPGA boot code from the built-in flash memory to initialize one or more DBCs 108 in a set (such as silicon components or platform components), and then begin execution of the FPGA boot code to initialize a portion of the DBCs 108 in the computing platform 102. In various embodiments, the host processor 104 may also fetch the host processor boot code and begin execution of the host processor boot code to initialize another portion of the DBCs 108 in the computing platform 102. In various such embodiments, the host processor 104 may fetch the host processor boot code and begin execution of the host processor boot code simultaneously with the loading and beginning of execution of the FPGA boot code. In other such embodiments, the host processor 104 may fetch the host processor boot code and begin execution of the host processor boot code after the loading and beginning of execution of the FPGA boot code. For example, the host processor 104 may fetch the host processor boot code and begin execution of the host processor boot code only once it exits reset. In such an example, the FPGA 106 may initialize one or more DBCs 108 before the host processor 104 exits reset.

[0035] In various embodiments, at the end of a boot sequence for initializing the computing platform 102 (e.g., after an operating system has been loaded), the FPGA 106 can be reconfigured with a different bitstream for runtime operations, such as core applications. In other words, after initialization of the computing platform 102, the FPGA 106 and / or the soft processor 302 can be reconfigured to have a desired functional configuration in one or more functional configurations 304-1, 304-2, 304-n. For example, the core application may include functional configurations associated with machine learning, computer vision, deep learning, and similar applications. In one or more embodiments, reconfiguring the FPGA 106 can automatically reclaim previously used FPGA boot sequence resources.

[0036] In some embodiments, the ability of computing platform 102 to configure and reconfigure FPGA 106 may allow for reuse of FPGA 106 configurations on the fly and / or on an as-needed basis. For example, configuration of FPGA 106 as a processor engine to assist and accelerate platform initialization may occur during the boot phase, while reconfiguring FPGA 106 for runtime operations such as deep learning, computer vision, and / or I / O expansion may occur after the boot sequence is complete. In many embodiments, the boot sequence may include one or more of platform virtualization and loading of an operating system.

[0037] In various embodiments, reusing or reconfiguring FPGA 106 as needed at different system stages (e.g., boot stage, runtime stage, user mode, kernel mode, operating system stage, etc.) can achieve a considerable reduction in overall platform BOM cost and runtime platform power consumption. In some embodiments, certain DBCs 108 may be required only during certain system stages. For example, a traditional host SM bus controller may be required only during a memory initialization stage. In such examples, the SM bus controller may read serial presence detection (SPD) information from a dual in-line memory module (DIMM) and is not used thereafter. In some such examples, FPGA 106 may be configured to provide SM bus controller functionality in an early boot stage. In further such examples, resources utilized by FPGA 106 may be reclaimed and programmed as different functions required in the OS stage. In some embodiments, FPGA 106 may reduce BOM cost and power consumption by removing a traditional SM bus controller from a design (e.g., a system on chip (SoC) design).

[0038] Figure 4 FIG. 4 illustrates one embodiment of a logic flow 400 that may represent operations that may be performed in conjunction with platform initialization in various embodiments. Logic flow 400 may represent operations that may be performed by Figure 1-Figure 3 104, FPGA 106, and / or logic 110 of the operating environment 100, 200, 300. In one or more embodiments, logic flow 400 may illustrate the portion of platform initialization that is offloaded from the host processor to the FPGA. In one or more such embodiments, the portion of platform initialization performed by the FPGA may include complete peripheral device initialization. In further such embodiments, this may occur simultaneously with the initialization of the host processor. The embodiments are not limited in this context.

[0039] In the illustrated embodiment, it will be appreciated that the steps within the dashed box labeled with host processor 402 are performed by a host processor, such as host processor 104, and the steps within the dashed box labeled with FPGA 452 are performed by an FPGA, such as FPGA 106. In addition, one or more steps performed by host processor 402 may be performed by execution of host boot instructions 204, and one or more steps performed by FPGA 452 may be performed by execution of FPGA boot instructions 206.

[0040] Logic flow 400 may begin at block 404 "Power On". In various embodiments, in response to computing platform 102 being powered on, at block 406, host processor 402 may perform power management controller initialization. Next, at block 408, host processor 402 may perform security engine initialization. Additionally, in response to computing platform 102 being powered on, at block 456, FPGA 106 may perform soft processor initialization. Continuing to block 410, host processor 402 may perform core initialization. For example, host processor 402 may initialize one of its own cores. Referring back to block 456 "Soft Processor Initialization", after the initialization of the soft processor, at block 458, FPGA may begin silicon initialization. For example, one or more silicon components 208 may be initialized. In some embodiments, an indication of initialization success or status may be provided to host processor 402. In various embodiments, the performance of the core initialization at block 410 may depend on the silicon initialization performed in block 458.

[0041] Continuing to block 412, the host processor 402 may perform memory initialization. For example, the host processor may initialize a memory controller or a memory interface. At block 414, the host processor 402 may perform other silicon initialization. For example, the host processor 402 may initialize any silicon components in the silicon components 208 that have not yet been initialized by the FPGA 452, such as at block 458. Proceeding to block 416, "Platform Initialization," the host processor 402 may initialize one or more platform components, such as one or more of the platform components 210. Referring back to block 458, "Silicon Initialization," after the FPGA 452 initializes the silicon components at block 458, it may perform platform initialization 460. In various embodiments, the platform initialization at block 416 may initialize a first portion of the platform components 210, and the platform initialization at block 460 may initialize a second portion of the platform components 210.

[0042] Proceeding to block 462, "COMMUNICATE STATE MACHINE FOR INITIALIZED COMPONENTS TO HOST PROCESSOR," the FPGA 452 may transmit state machine information for the initialized components to the host processor 402. In other words, in some embodiments, the FPGA 452 may provide an indication to the processor 402 of the state of one or more components that it initialized. Referring to block 418, "BOOT TO OPERATING SYSTEM," once all silicon components 208 and platform components 210 are initialized, the host processor may boot to an operating system. Without referring to block 464, the FPGA 452 may load and initialize a bitstream from flash memory, such as to reconfigure itself for performing runtime operations. At block 420, one or more of the host processor 402 and the FPGA 452 may perform one or more runtime operations.

[0043] Figure 5FIG. 5 shows one embodiment of a logic flow 500 that may represent operations that may be performed in conjunction with platform initialization in various embodiments. Figure 1-Figure 3 102. The logic flow 500 may include some or all of the operations performed by one or more components of the operating environment 100, 200, 300, such as the host processor 104, FPGA 106, DBC 108, and / or logic 110. In one or more embodiments, the logic flow 500 may illustrate arbitration of drivers enabled by the computing platform 102. The embodiments are not limited in this context.

[0044] In the illustrated embodiment, it will be appreciated that the steps within the dashed boxes labeled with host processor 502 are performed by a host processor, such as host processor 104, and the steps within the dashed boxes labeled with FPGA processor 552 are performed by an FPGA, such as FPGA 106. In addition, one or more steps performed by host processor 502 may be performed by execution of host boot instructions 204, and one or more steps performed by FPGA 552 may be performed by execution of FPGA boot instructions 206.

[0045] In some embodiments, the computer platform 102 may provide an architecture that offloads silicon component and / or platform component initialization to the FPGA. In some such embodiments, one or more FPGA designs (e.g., functional configurations) may be included and / or stored in the FPGA. In many embodiments, during boot, the host processor 502 and the FPGA 552 may share the responsibility for completing the initialization of silicon components and platform components. In embodiments where the FPGA includes internal flash memory, it may be powered on and the soft processor may be initialized much earlier than the host processor 502. In various embodiments, the host processor 502 may act as the master controller of a state machine to configure the operation of the FPGA, such as loading sequences and parameters of various designs.

[0046] Logic flow 500 may begin at block 510, “Boot Driver Parameters”. In some embodiments, boot driver parameters may be loaded based on a detected computing platform (e.g., DBC 108, platform identifier, etc.). FPGA 552 may then be used to load appropriate designs, such as driver designs, in a defined order. In such cases, FPGA 552 may be used to perform initialization including loading of bus designs at block 512, loading of network designs at 514, and loading of other designs at block 516. In many embodiments, an error status may be propagated, such as by one or more of host processor 502 and FPGA 552. After block 516, in some embodiments, FPGA 552 may send a boot log (such as a boot log merged by FPGA 552) to host processor 502.

[0047] Referring back to block 510, in response to loading the boot driver parameters, the host processor 502 may perform library initialization 530. At block 532, the host processor 502 may generate a driver status printout 532. In one or more embodiments, the driver status printout 532 may be based on the boot log sent from the FPGA 552 to the host processor 502 after step 516. Proceeding to block 534, "Build Device Tree", the host processor 502 may perform operations for building a device tree. In some embodiments, the device tree may include an Advanced Configuration and Power Interface (ACPI) tree. In various embodiments, the host processor 502 may construct one or more ACPI parameters and a device tree based on output from the FPGA 552, such as output provided before passing control to the operating system kernel.

[0048] Figure 6 FIG. 6 illustrates one embodiment of a logic flow 600 that may represent operations that may be performed in conjunction with platform initialization in various embodiments. Logic flow 600 may represent operations that may be performed by Figure 1-Figure 3 Some or all of the operations performed by one or more components of operating environment 100, 200, 300, such as host processor 104, FPGA 106, DBC 108, and / or logic 110. The embodiments are not limited in this context.

[0049] exist Figure 6 , logic flow 600 may begin at block 602. At block 602, "Boot sequence initiated, the boot sequence initializes the platform to perform input / output (I / O) operations, the platform including a host processor and a field programmable gate array (FPGA)", the boot sequence initializes the platform including the host processor and the FPGA for performing I / O operations. For example, a boot sequence for initializing computing platform 102 may be initiated. In various embodiments, the boot sequence may be initiated in response to computing platform 102 being powered on. In some embodiments, the host processor may initiate the boot sequence.

[0050] Continuing to block 604, “Executing, with the host processor, as part of a boot sequence, a first set of boot instructions that initializes each of the first set of dependent bootable components (DBCs)”, as part of a boot sequence, a first set of boot instructions may be executed by the host processor, wherein the first set of boot instructions initializes each of the first set of DBCs. For example, the host processor 104 may execute the host boot instructions 204 to initialize one or more of the DBCs 108. In some embodiments, the host processor 104 may initialize one or more of the silicon components 208. In various embodiments, the host processor 104 may initialize one or more of the platform components 210.

[0051] Continuing to block 606, “Executing, with the FPGA, as part of a boot sequence, a second set of boot instructions, the second set of boot instructions initializing each DBC in a second set of DBCs,” as part of a boot sequence, a second set of boot instructions may be executed by the FPGA, wherein the second set of boot instructions initializes each DBC in a second set of DBCs. For example, the FPGA 106 may execute the host boot instructions 206 to initialize one or more of the DBCs 108. In some embodiments, the FPGA 106 may initialize one or more of the silicon components 208. In various embodiments, the FPGA 106 may initialize one or more of the platform components 210.

[0052] Figure 7 The figure shows an embodiment of a storage medium 700. The storage medium 700 may include any non-transitory computer-readable storage medium or machine-readable storage medium, such as an optical storage medium, a magnetic storage medium, or a semiconductor storage medium. In various embodiments, the storage medium 700 may include an article of manufacture. In some embodiments, the storage medium 700 may store computer-executable instructions, such as computer-executable instructions for implementing one or more of the logic flows or operations described herein, such as, for example, Figure 4 The logic flow 400, Figure 5 The logic flow 500 and Figure 6 For the logic flow 600 of the present invention, examples of computer-readable storage media or machine-readable storage media may include any tangible media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, etc. The embodiments are not limited in this context.

[0053] Figure 8The figure illustrates an embodiment of an exemplary computing architecture 800 that may be suitable for implementing various embodiments as previously described. In various embodiments, the computing architecture 800 may include an electronic device or may be implemented as a portion of an electronic device. In some embodiments, the computing architecture 800 may represent, for example, an electronic device that implements or utilizes Figure 1 Operating environment 100, Figure 2 operating environment 200, and / or Figure 3 The computing architecture 800 may represent, for example, one or more portions of a computing platform 102 that implements or utilizes one or more embodiments described herein. For example, the host processor 104 may be a central processing unit (CPU) that operates in conjunction with the computing architecture 800. The embodiments are not limited in this context.

[0054] As used in this application, the terms "system", "component" and "module" are intended to refer to computer-related entities (whether hardware, a combination of hardware and software, software, or software in execution), examples of which are provided by an exemplary computing architecture 800. For example, a component can be, but is not limited to: a process running on a processor, a processor, a hard drive, multiple storage drives (optical and / or magnetic storage media), an object, an executable code, an execution thread, a program, and / or a computer. As an illustration, both an application running on a server and the server can be a component. One or more components can reside in a process and / or an execution thread, and a component can be localized on a computer and / or distributed between two or more computers. Further, components can be communicatively coupled to each other through various types of communication media to coordinate operations. The coordination can involve unidirectional or bidirectional information exchange. For example, a component can transmit information in the form of a signal transmitted through a communication medium. The information can be implemented as a signal assigned to each signal line. In such an assignment, each message is a signal. However, further embodiments may alternatively employ data messages. Such data messages can be sent across various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.

[0055] The computing architecture 800 includes various common computing elements, such as one or more processors, multi-core processors, coprocessors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input / output (I / O) components, power supplies, etc. However, embodiments are not limited to implementation by the computing architecture 800.

[0056] like Figure 8 As shown in FIG. 8 , the computing architecture 800 includes a processing unit 804, a system memory 806, and a system bus 808. The processing unit 804 can be any of various commercially available processors, including but not limited to: Athlon Duron He Haolong processor; applications, embedded and security processors; of Dragon Ball and Processors; IBM and Cell processor; Celeron Core(2) Itanium Pentium Xeon and Processor; and similar processors. Dual microprocessors, multi-core processors, and other multi-processor architectures may also be used as the processing unit 804.

[0057] The system bus 808 provides an interface for system components, including but not limited to the system memory 806 to the processing unit 804. The system bus 808 can be any of several types of bus structures, which can use any of a variety of commercially available bus architectures to further interconnect to a memory bus (with or without a memory controller), a peripheral bus, and a local bus. Interface adapters can be connected to the system bus 808 via a slot architecture. Example slot architectures can include but are not limited to: Accelerated Graphics Port (AGP), Card Bus, (Extended) Industry Standard Architecture ((E)ISA), Micro Channel Architecture (MCA), Network User Bus (NuBus), Peripheral Component Interconnect (Extended) (PCI(X)), PCI Express (PCI Express), Personal Computer Memory Card International Association (PCMCIA), and the like.

[0058] The system memory 806 may include various types of computer-readable storage media in the form of one or more higher-speed memory units, such as read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), double data rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory (e.g., one or more flash memory arrays), polymer memory such as ferroelectric polymer memory, Osram memory, phase change or ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, device arrays such as redundant array of independent disks (RAID) drives, solid-state memory devices (e.g., USB memory, solid-state drive (SSD)), and any other type of storage medium suitable for storing information. Figure 8 In the illustrated embodiment shown in FIG. 8 , the system memory 806 may include non-volatile memory 810 and / or volatile memory 812. In some embodiments, the system memory 806 may include main memory. A basic input / output system (BIOS) may be stored in the non-volatile memory 810.

[0059] The computer 802 may include various types of computer-readable storage media in the form of one or more lower-speed memory units, including an internal (or external) hard disk drive (HDD) 814, a magnetic floppy disk drive (FDD) 816 for reading from or writing to a removable disk 818, and an optical drive 820 for reading from or writing to a removable optical disk 822 (e.g., a CD-ROM or DVD). The HDD 814, FDD 816, and optical drive 820 may be connected to the system bus 808 via a HDD interface 824, a FDD interface 826, and an optical drive interface 828, respectively. The HDD interface 824 for external drive implementation may include at least one or both of a universal serial bus (USB) and an Institute of Electrical and Electronics Engineers (IEEE) 994 interface technology. In various embodiments, these types of memory may not be included in the main memory or system memory.

[0060] The drives and associated computer-readable media provide volatile and / or nonvolatile storage of data, data structures, computer-executable instructions, and the like. For example, a number of program modules may be stored in the drives and memory units 810, 812, including an operating system 830, one or more application programs 832, other program modules 834, and program data 836. In one embodiment, the one or more application programs 832, other program modules 834, and program data 836 may include, for example, various applications and / or components of the computing platform 102, such as logic 110.

[0061] A user may enter commands and information into the computer 802 through one or more wired / wireless input devices, such as a keyboard 838 and a pointing device such as a mouse 840. Other input devices may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, a game controller, a stylus, a card reader, a dongle, a fingerprint reader, a glove, a drawing tablet, a joystick, a keyboard, a retina reader, a touch screen (e.g., capacitive, resistive, etc.), a trackball, a trackpad, a sensor, a stylus, and the like. These and other input devices are typically connected to the processing unit 804 through an input device interface 842 coupled to the system bus 808, but may also be connected through other interfaces such as a parallel port, an IEEE 994 serial port, a game port, a USB port, an IR port, and the like.

[0062] A monitor 844 or other type of display device is also connected to the system bus 808 via an interface, such as a video adapter 846. The monitor 844 may be internal or external to the computer 802. In addition to the monitor 844, computers typically include other peripheral output devices such as speakers, printers, and the like.

[0063] Computer 802 can operate in a networked environment using a logical connection to one or more remote computers (such as, remote computer 848) via wired and / or wireless communications. In various environments, one or more migrations can occur via a networked environment. Remote computer 848 can be a workstation, server computer, router, personal computer, portable computer, microprocessor-based entertainment device, peer device or other common network node, and typically includes many or all elements described relative to computer 802, but for the purpose of simplicity, only memory / storage device 850 is illustrated. The depicted logical connection includes wired / wireless connectivity to a larger network such as a local area network (LAN) 852 and / or a wide area network (WAN) 854. Such LAN and WAN networking environments are common in offices and companies, and facilitate enterprise-wide computer networks such as intranets, all of which can be connected to global communication networks such as the Internet.

[0064] When used in a LAN networking environment, the computer 802 is connected to the LAN 852 through a wired and / or wireless communication network interface or adapter 856. The adapter 856 can facilitate wired and / or wireless communication to the LAN 852, which may also include a wireless access point provided thereon for communicating using the wireless capabilities of the adapter 856.

[0065] When used in a WAN networking environment, the computer 802 may include a modem 1358, or be connected to a communications server on the WAN 854, or have other means for establishing communications on the WAN 854, such as through the Internet. The modem 858 is connected to the system bus 808 via the input device interface 842, and may be internal or external and may be a wired and / or wireless device. In a networking environment, program modules depicted relative to the computer 802, or portions thereof, may be stored in the remote memory / storage device 850. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between the computers may be used.

[0066] The computer 802 is operable to communicate using the IEEE 802 family of standards with wired and wireless devices or entities, such as wireless devices operatively arranged for wireless communication (e.g., IEEE 802.16 over-the-air modulation techniques). This includes at least Wi-Fi (or Wireless Fidelity), WiMax, and Bluetooth. TM Wireless technology, etc. Therefore, the communication can be a predefined structure like a conventional network, or just an ad hoc communication between at least two devices. Wi-Fi networks use radio technology called IEEE 802.1x (a, b, n, g, etc.) to provide secure, reliable, and fast wireless connectivity. Wi-Fi networks can be used to connect computers to each other, to the Internet, and to wired networks (which use IEEE 802.3 related media and functions).

[0067] Fig. 9 The figure shows a block diagram of an exemplary communication architecture 900 suitable for implementing various embodiments as previously described (such as virtual machine migration). The communication architecture 900 includes various common communication elements, such as transmitters, receivers, transceivers, radio devices, network interfaces, baseband processors, antennas, amplifiers, filters, power supplies, etc. However, the embodiments are not limited to implementation by the communication architecture 900.

[0068] like Fig. 9As shown in FIG. 1 , the communication architecture 900 includes one or more clients 902 and servers 904. The clients 902 and servers 904 are operatively connected to one or more respective client data stores 908 and server data stores 910 that can be used to store information local to the respective clients 902 and servers 904 (such as cookies and / or associated contextual information). In various embodiments, any of the servers 904 may implement one or more of the logic flows or operations described herein and coordinate the storage of data received from any of the clients 902. Figure 7 The storage medium 700 in the client data store 908 is located on any of the server data stores 910. In one or more embodiments, one or more of the client data stores 908 or the server data stores 910 may include memory accessible to the host processor 104 and / or the FPGA 106.

[0069] Client 902 and server 904 may communicate information between each other using a communication framework 906. Communication framework 906 may implement any well-known communication techniques and protocols. Communication framework 906 may be implemented as a packet-switched network (e.g., a public network such as the Internet, a private network such as an intranet, etc.), a circuit-switched network (e.g., a public switched telephone network), or a combination of packet-switched and circuit-switched networks (with appropriate gateways and switches).

[0070] The communication framework 906 can implement various network interfaces, which are arranged to receive, transmit and connect to the communication network. The network interface can be considered as a special form of input and output interface. The network interface can adopt a connection protocol, including but not limited to direct connection, Ethernet (such as thick, thin, twisted pair 10 / 100 / 1900Base T, etc.), token ring, wireless network interface, cellular network interface, IEEE 802.11ax network interface, IEEE 802.16 network interface, IEEE 802.20 network interface, etc. In addition, multiple network interfaces can be used to engage with various communication network types. For example, multiple network interfaces can be used to allow communication through broadcast, multicast and unicast networks. If the processing requirements specify a larger amount of speed and capacity, a distributed network controller architecture can be similarly used to pool, load balance and otherwise increase the communication bandwidth required by the client 902 and the server 904. The communication network can be any one or a combination of wired and / or wireless networks, including but not limited to direct interconnection, secure customized connection, proprietary network (e.g., corporate intranet), public network (e.g., Internet), personal area network (PAN), local area network (LAN), metropolitan area network (MAN), operating mission as a node on the Internet (OMNI), wide area network (WAN), wireless network, cellular network, and other communication networks.

[0071] Embodiments can be realized using hardware elements, software elements, or a combination of the two. Examples of hardware elements may include: processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, application program interfaces (APIs), instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether to use hardware elements and / or software elements to realize an embodiment may vary according to any number of factors, such as desired computing rates, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.

[0072] One or more aspects of at least one embodiment may be implemented by representative instructions of various logics within a processor stored on a machine-readable medium, which, when read by a machine, cause the machine to manufacture logic for performing the techniques described herein. Such representations, referred to as "IP cores," may be stored on tangible machine-readable media and provided to multiple customers or production facilities to be loaded into a manufacturing machine that actually manufactures the logic or processor. For example, some embodiments may be implemented using machine-readable media or articles that may store instructions or sets of instructions that, when executed by a machine, may cause the machine to perform methods and / or operations according to an embodiment. Such machines may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, etc., and may be implemented using any suitable combination of hardware and / or software. The machine-readable medium or article of manufacture may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and / or storage unit, such as memory, removable or non-removable media, erasable or non-erasable media, writable or rewritable media, digital or analog media, hard disk, floppy disk, compact disk read only memory (CD-ROM), compact disk recordable (CD-R), compact disk rewritable (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of digital versatile disks (DVDs), magnetic tapes, cassettes, etc. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc., implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language.

[0073] The following examples relate to further embodiments from which numerous permutations and configurations will be apparent.

[0074] Example 1 is a device for platform initialization, the device comprising: a memory; and logic, at least part of which is implemented in a circuit coupled to the memory, the logic being used to: initiate a boot sequence, the boot sequence initializing the platform for performing input / output (I / O) operations, the platform comprising a host processor and a field programmable gate array (FPGA); as part of the boot sequence, executing a first boot instruction set using the host processor, the first boot instruction set initializing each DBC in a first dependent bootable component (DBC) set; and as part of the boot sequence, executing a second boot instruction set using the FPGA, the second boot instruction set initializing each DBC in a second DBC set.

[0075] Example 2 includes the subject matter of Example 1, wherein initialization of a DBC in the first set of DBCs is dependent on initialization of another DBC in the second set of DBCs.

[0076] Example 3 includes the subject matter of Example 1, wherein a first DBC in the first set of DBCs comprises an operating system and a second DBC in the second set of DBCs comprises a firmware interface.

[0077] Example 4 includes the subject matter of Example 1, wherein the platform is to perform I / O operations via an operating system executed by a host processor.

[0078] Example 5 includes the subject matter of Example 1, wherein a first DBC in the first set comprises a power management controller and a second DBC in the second set comprises a bus controller.

[0079] Example 6 includes the subject matter of Example 1, a first DBC in the first set comprising a library, wherein initializing the first DBC comprises loading the library from memory.

[0080] Example 7 includes the subject matter of Example 6, wherein a second DBC in the second set comprises a memory controller, and initialization of the second DBC occurs before initialization of the first DBC.

[0081] Example 8 includes the subject matter of Example 1, the DBCs in the first set of DBCs comprising a device tree, wherein initializing the DBCs comprises building the device tree.

[0082] Example 9 includes the subject matter of Example 1, wherein the DBCs in the second set of DBCs include a bus design, wherein initializing the DBCs includes loading the bus design.

[0083] Example 10 includes the subject matter of Example 1, the DBC in the second set of DBCs comprising a network design, wherein initializing the second DBC comprises loading the network design.

[0084] Example 11 includes the subject matter of Example 1, wherein the DBCs in the first set comprise cores of a host processor.

[0085] Example 12 includes the subject matter of Example 1, wherein the DBC in the second set comprises a soft processor of the FPGA.

[0086] Example 13 includes the subject matter of Example 1, wherein the second set of boot instructions is located in an FPGA memory.

[0087] Example 14 includes the subject matter of Example 1, wherein the FPGA indicates to the host processor successful initialization of the DBCs in the second set of DBCs.

[0088] Example 15 includes the subject matter of Example 1, wherein logic is used to reconfigure the FPGA to perform runtime operations after the boot sequence is completed.

[0089] Example 16 is a system for platform initialization, the system comprising: a platform, the platform comprising a set of dependent boot components (DBCs); a host processor, as part of a boot sequence that initializes the platform for performing input / output (I / O) operations, the host processor being used to execute a first set of boot instructions that initialize each DBC in a first subset of the DBC set; and a field programmable gate array (FPGA), as part of the boot sequence, the FPGA being used to execute a second set of boot instructions that initialize each DBC in a second subset of the DBC set.

[0090] Example 17 includes the subject matter as described in Example, wherein initialization of a first DBC in the first subset is dependent on initialization of a second DBC in the second subset.

[0091] Example 18 includes the subject matter of Example 16, wherein a first DBC in the first subset comprises an operating system and a second DBC in the second subset comprises a firmware interface.

[0092] Example 19 includes the subject matter of Example 16, wherein the platform is to perform I / O operations via an operating system executed by a host processor.

[0093] Example 20 includes the subject matter of Example 16, wherein a first DBC in the first set comprises a power management controller and a second DBC in the second set comprises a bus controller.

[0094] Example 21 includes the subject matter of Example 16, a first DBC in the first set comprising a library, wherein initializing the first DBC comprises loading the library from memory.

[0095] Example 22 includes the subject matter of Example 21, wherein a second DBC in the second set comprises a memory controller, and initialization of the second DBC occurs before initialization of the first DBC.

[0096] Example 23 includes the subject matter of Example 16, the DBC in the first subset comprising a device tree, wherein initializing the DBC comprises building the device tree.

[0097] Example 24 includes the subject matter of Example 16, the DBC in the second subset comprising a bus design, wherein initializing the DBC comprises loading the bus design.

[0098] Example 25 includes the subject matter of Example 16, the DBC in the second subset comprising a network design, wherein initializing the DBC comprises loading the network design.

[0099] Example 26 includes the subject matter of Example 16, wherein the DBCs in the first subset comprise cores of a host processor.

[0100] Example 27 includes the subject matter of Example 16, wherein the DBC in the second subset comprises a soft processor of the FPGA.

[0101] Example 28 includes the subject matter of Example 16, wherein the second set of boot instructions is located in an FPGA memory.

[0102] Example 29 includes the subject matter of Example 16, wherein the FPGA indicates to the host processor successful initialization of the DBCs in the second subset of DBCs.

[0103] Example 30 includes the subject matter of Example 16, wherein the FPGA is configured to be reconfigured to perform runtime operations after a boot sequence is completed.

[0104] Example 31 is at least one non-transitory computer-readable medium, comprising an instruction set that, in response to being executed by a processor circuit, causes the processor circuit to: initiate a boot sequence that initializes a platform for performing input / output (I / O) operations, the platform comprising a host processor and a field programmable gate array (FPGA); as part of the boot sequence, execute a first boot instruction set using the host processor, the first boot instruction set initializing each DBC in a first dependent bootable component (DBC) set; and as part of the boot sequence, execute a second boot instruction set using the FPGA, the second boot instruction set initializing each DBC in a second DBC set.

[0105] Example 32 includes the subject matter of Example 31, wherein initialization of a DBC in the first set of DBCs is dependent on initialization of another DBC in the second set of DBCs.

[0106] Example 33 includes the subject matter of Example 31, wherein a first DBC in the first set of DBCs comprises an operating system and a second DBC in the second set of DBCs comprises a firmware interface.

[0107] Example 34 includes the subject matter of Example 31, wherein the platform is to perform I / O operations via an operating system executed by a host processor.

[0108] Example 35 includes the subject matter of Example 31, wherein a first DBC in the first set comprises a power management controller and a second DBC in the second set comprises a bus controller.

[0109] Example 36 includes the subject matter of Example 31, a first DBC in the first set comprising a library, wherein initializing the first DBC comprises loading the library from memory.

[0110] Example 37 includes the subject matter of Example 36, wherein a second DBC in the second set comprises a memory controller, and initialization of the second DBC occurs before initialization of the first DBC.

[0111] Example 38 includes the subject matter of Example 31, the DBCs in the first set of DBCs comprising a device tree, wherein initializing the DBCs comprises building the device tree.

[0112] Example 39 includes the subject matter of Example 31, the DBCs in the second set of DBCs comprising a bus design, wherein initializing the DBCs comprises loading the bus design.

[0113] Example 40 includes the subject matter of Example 31, the DBC in the second set of DBCs comprising a network design, wherein initializing the second DBC comprises loading the network design.

[0114] Example 41 includes the subject matter of Example 31, wherein the DBCs in the first set comprise cores of a host processor.

[0115] Example 42 includes the subject matter of Example 31, wherein the DBC in the second set comprises a soft processor of the FPGA.

[0116] Example 43 includes the subject matter of Example 31, wherein the second set of boot instructions is located in an FPGA memory.

[0117] Example 44 includes the subject matter of Example 31, wherein the FPGA indicates to the host processor successful initialization of the DBCs in the second set of DBCs.

[0118] Example 45 includes the subject matter of Example 31, comprising instructions which in response to being executed by a processor circuit cause the processor circuit to: reconfigure the FPGA to perform runtime operations after a boot sequence is completed.

[0119] Example 46 is a method for computer implementation, the method comprising: initiating a boot sequence, the boot sequence initializing a platform for performing input / output (I / O) operations, the platform comprising a host processor and a field programmable gate array (FPGA); as part of the boot sequence, executing a first boot instruction set using the host processor, the first boot instruction set initializing each DBC in a first dependent bootable component (DBC) set; and as part of the boot sequence, executing a second boot instruction set using the FPGA, the second boot instruction set initializing each DBC in a second DBC set.

[0120] Example 47 includes the subject matter of Example 46, wherein initialization of a DBC in the first set of DBCs is dependent on initialization of another DBC in the second set of DBCs.

[0121] Example 48 includes the subject matter of Example 46, wherein a first DBC in the first set of DBCs comprises an operating system and a second DBC in the second set of DBCs comprises a firmware interface.

[0122] Example 49 includes the subject matter of Example 46, comprising performing the I / O operation by an operating system executed by a host processor.

[0123] Example 50 includes the subject matter of Example 46, wherein a first DBC in the first set comprises a power management controller and a second DBC in the second set comprises a bus controller.

[0124] Example 51 includes the subject matter of Example 46, the first DBC in the first set comprising a library, wherein initializing the first DBC comprises loading the library from memory.

[0125] Example 52 includes the subject matter of Example 51, wherein a second DBC in the second set comprises a memory controller, and initialization of the second DBC occurs before initialization of the first DBC.

[0126] Example 53 includes the subject matter of Example 46, the DBCs in the first set of DBCs comprising a device tree, wherein initializing the DBCs comprises building the device tree.

[0127] Example 54 includes the subject matter of Example 46, the DBCs in the second set of DBCs comprising a bus design, wherein initializing the DBCs comprises loading the bus design.

[0128] Example 55 includes the subject matter of Example 46, the DBC in the second set of DBCs comprising a network design, wherein initializing the second DBC comprises loading the network design.

[0129] Example 56 includes the subject matter of Example 46, wherein the DBCs in the first set comprise cores of a host processor.

[0130] Example 57 includes the subject matter of Example 46, wherein the DBC in the second set comprises a soft processor of the FPGA.

[0131] Example 58 includes the subject matter of Example 46, wherein the second set of boot instructions is located in the FPGA memory.

[0132] Example 59 includes the subject matter of Example 46, comprising indicating to the host processor successful initialization of the DBCs in the second set of DBCs.

[0133] Example 60 includes the subject matter of Example 46, comprising reconfiguring the FPGA to perform runtime operations after the boot sequence is completed.

[0134] Example 61 is a device comprising: a device for initiating a boot sequence, the boot sequence initializing a platform for performing input / output (I / O) operations, the platform comprising a host processor and a field programmable gate array (FPGA); a device for executing a first boot instruction set using the host processor as part of the boot sequence, the first boot instruction set initializing each DBC in a first dependent bootable component (DBC) set; and a device for executing a second boot instruction set using the FPGA as part of the boot sequence, the second boot instruction set initializing each DBC in a second DBC set.

[0135] Example 62 includes the subject matter of Example 61, wherein initialization of a DBC in the first set of DBCs is dependent on initialization of another DBC in the second set of DBCs.

[0136] Example 63 includes the subject matter of Example 61, wherein a first DBC in the first set of DBCs comprises an operating system and a second DBC in the second set of DBCs comprises a firmware interface.

[0137] Example 64 includes the subject matter of Example 61, comprising: means for performing I / O operations by an operating system executed by a host processor.

[0138] Example 65 includes the subject matter of Example 61, wherein a first DBC in the first set comprises a power management controller and a second DBC in the second set comprises a bus controller.

[0139] Example 66 includes the subject matter of Example 61, a first DBC in the first set comprising a library, wherein initializing the first DBC comprises loading the library from memory.

[0140] Example 67 includes the subject matter of Example 66, wherein a second DBC in the second set comprises a memory controller, and initialization of the second DBC occurs before initialization of the first DBC.

[0141] Example 68 includes the subject matter of Example 61, the DBCs in the first set of DBCs comprising a device tree, wherein initializing the DBCs comprises building the device tree.

[0142] Example 69 includes the subject matter of Example 61, the DBCs in the second set of DBCs comprising a bus design, wherein initializing the DBCs comprises loading the bus design.

[0143] Example 70 includes the subject matter of Example 61, the DBC in the second set of DBCs comprising a network design, wherein initializing the second DBC comprises loading the network design.

[0144] Example 71 includes the subject matter of Example 61, wherein the DBCs in the first set comprise cores of a host processor.

[0145] Example 72 includes the subject matter of Example 61, wherein the DBC in the second set comprises a soft processor of the FPGA.

[0146] Example 73 includes the subject matter of Example 61, wherein the second set of boot instructions is located in the FPGA memory.

[0147] Example 74 includes the subject matter of Example 61, comprising means for indicating to a host processor successful initialization of a DBC in the second set of DBCs.

[0148] Example 75 includes the subject matter of Example 61, comprising means for reconfiguring the FPGA to perform runtime operations after a boot sequence is completed.

[0149] The foregoing description of example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the disclosure. The scope of the disclosure is not limited by this specific implementation but by the appended claims. Future applications claiming priority to the present application may claim the disclosed subject matter in different ways and may generally include any collection of one or more limitations as variously disclosed or otherwise presented herein.

Claims

1. A computer-implemented method comprising: Initiating a boot sequence, wherein the boot sequence initializes a platform for performing an input / output (I / O) operation, wherein the platform includes a host processor and a field programmable gate array (FPGA); executing, with the host processor, as part of the boot sequence, a first set of boot instructions that initialize each DBC in a first subset of the set of dependent bootable component DBCs; as well as As part of the boot sequence, a second set of boot instructions is executed using the FPGA, the second set of boot instructions initializing each DBC in a second subset of DBCs in the set of DBCs.

2. The computer-implemented method of claim 1, wherein: Initialization of a DBC in the first set of DBCs is dependent on initialization of another DBC in the second subset of DBCs.

3. The computer-implemented method of claim 1, wherein: The first DBC subset includes an operating system, and a second DBC in the second DBC subset includes a firmware interface.

4. The computer implemented method of claim 1, comprising performing I / O operations via an operating system executed by the host processor.

5. The computer-implemented method of claim 1, wherein: The first subset of DBCs includes a power management controller, and a second DBC in the second subset of DBCs includes a bus controller.

6. The computer-implemented method of claim 1, wherein: A first DBC in the first subset of DBCs includes a library, and initializing the first DBC includes loading the library from a memory.

7. The computer-implemented method of claim 6, wherein: A second DBC in the second subset of DBCs includes a memory controller, and initialization of the second DBC occurs before initialization of the first DBC.

8. The computer-implemented method of claim 1, wherein: The DBCs in the first DBC subset include a device tree, wherein initializing the DBCs includes building the device tree.

9. The computer-implemented method of claim 1, wherein: The DBCs in the second subset of DBCs include a bus design, wherein initializing the DBCs includes loading the bus design.

10. The computer-implemented method of claim 1, wherein: The DBCs in the second subset of DBCs include a network design, wherein initializing the second DBCs includes loading the network design.

11. The computer-implemented method of claim 1 , wherein: The first DBC subset includes cores of the host processor.

12. The computer-implemented method of claim 1, wherein: The second DBC subset includes a soft processor of the FPGA.

13. The computer-implemented method of claim 1, wherein: The second boot instruction set is located in the FPGA memory.

14. The computer-implemented method of claim 1, comprising: Successful initialization of the DBCs in the second subset of DBCs is indicated to the host processor.

15. The computer-implemented method of claim 1, comprising: After the boot sequence is complete, the FPGA is reconfigured to perform runtime operations.

16. A machine-readable medium comprising codes, which when executed cause a machine to perform the method according to any one of claims 1 to 15.

17. A device for platform initialization, the device comprising: Memory; as well as logic, at least part of which is implemented in circuitry coupled to the memory, the logic to: Initiating a boot sequence, wherein the boot sequence initializes a platform for performing an input / output (I / O) operation, wherein the platform includes a host processor and a field programmable gate array (FPGA); executing, with the host processor, as part of the boot sequence, a first set of boot instructions that initialize each DBC in a first subset of the set of dependent bootable component DBCs; as well as As part of the boot sequence, a second set of boot instructions is executed using the FPGA, the second set of boot instructions initializing each DBC in a second subset of DBCs in the set of DBCs.

18. The device of claim 17, wherein: Initialization of a DBC in the first subset of DBCs is dependent on initialization of another DBC in the second subset of DBCs.

19. The device of claim 17, wherein: The first DBC subset includes an operating system, and the second DBC subset includes a firmware interface.

20. The apparatus of claim 17, wherein: The first subset of DBCs includes a power management controller and the second subset of DBCs includes a bus controller.

21. The apparatus of claim 17, wherein: A first DBC in the first subset of DBCs includes a library, and initializing the first DBC includes loading the library from the memory.

22. The device of claim 21, wherein: A second DBC in the second subset of DBCs includes a memory controller, and initialization of the second DBC occurs before initialization of the first DBC.

23. The apparatus of claim 17, wherein: The DBCs in the first DBC subset include a device tree, and initializing the DBCs includes building the device tree.

24. The apparatus of claim 17, wherein: The DBCs in the second subset of DBCs include a bus design, wherein initializing the DBCs includes loading the bus design.

25. The apparatus of any one of claims 17 to 24, the platform being configured to perform I / O operations via an operating system executed by the host processor.

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