Solid-state camera devices and electronic devices

Abstract

The present technology relates to a solid-state imaging device and an electronic device capable of preventing dark characteristics from deteriorating. The solid-state imaging device according to the present invention is provided with: a photoelectric conversion unit that performs photoelectric conversion; a charge holding unit that temporarily holds the charge converted by the photoelectric conversion unit; and a first groove formed in a semiconductor substrate and located between the photoelectric conversion unit and the charge holding unit. In the depth direction of the semiconductor substrate, the first groove is formed higher than the photoelectric conversion unit. Alternatively, in the depth direction of the semiconductor substrate, the first groove is formed lower than the photoelectric conversion unit and higher than the charge holding unit. The present technology can be applied to a back-illuminated CMOS image sensor, for example.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging device and an electronic device, and more specifically, to a solid-state imaging device and an electronic device in which a P-type solid-phase diffusion layer and an N-type solid-phase diffusion layer are formed on the side walls of an inter-pixel light-shielding wall formed between pixels, thereby forming a strong electric field region to retain electric charge, thereby increasing the saturation charge amount Qs of each pixel. Background Art

[0002] Conventionally, a known technique is to form a P-type diffusion layer and an N-type diffusion layer on the side walls of a groove formed between pixels in order to increase the saturation charge amount Qs of each pixel of a solid-state imaging device, thereby forming a strong electric field region to hold the charge (see, for example, Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-162603 Summary of the invention

[0006] Technical Problems to be Solved by the Invention

[0007] However, in the structure disclosed in Patent Document 1, the pinning of the light incident side of the silicon (Si) substrate becomes weak. As a result, the generated charge flows into the photodiode, which may deteriorate the dark characteristics. For example, white spots may appear, or dark current may be generated.

[0008] The present technology has been made in view of the above circumstances, and aims to suppress the degradation of dark characteristics.

[0009] Technical solutions to technical problems

[0010] According to one aspect of the present technology, a first solid-state imaging device includes: a photoelectric conversion unit that performs photoelectric conversion; a charge holding unit that temporarily holds the charge converted by the photoelectric conversion unit; and a first groove formed in a semiconductor substrate between the photoelectric conversion unit and the charge holding unit; in the depth direction of the semiconductor substrate, the first groove is formed to be higher than the photoelectric conversion unit.

[0011] According to one aspect of the present technology, a first electronic device is an electronic device equipped with a solid-state imaging device, wherein the solid-state imaging device includes: a photoelectric conversion unit that performs photoelectric conversion; a charge holding unit that temporarily holds the charge converted by the photoelectric conversion unit; and a first groove formed in a semiconductor substrate between the photoelectric conversion unit and the charge holding unit; in the depth direction of the semiconductor substrate, the first groove is formed to be higher than the photoelectric conversion unit.

[0012] According to one aspect of the present technology, a second solid-state imaging device includes: a photoelectric conversion unit that performs photoelectric conversion; a charge holding unit that temporarily holds the charge converted by the photoelectric conversion unit; and a first groove formed between the photoelectric conversion unit and the charge holding unit in a semiconductor substrate; in the depth direction of the semiconductor substrate, the first groove is formed to be lower than the photoelectric conversion unit and higher than the charge holding unit.

[0013] According to one aspect of the present technology, a second electronic device is an electronic device equipped with a solid-state imaging device, wherein the solid-state imaging device includes: a photoelectric conversion unit that performs photoelectric conversion; a charge holding unit that temporarily holds the charge converted by the photoelectric conversion unit; and a first groove formed in a semiconductor substrate between the photoelectric conversion unit and the charge holding unit; in the depth direction of the semiconductor substrate, the first groove is formed to be lower than the photoelectric conversion unit and higher than the charge holding unit.

[0014] According to one aspect of the present technology, a first solid-state imaging device includes: a photoelectric conversion unit that performs photoelectric conversion; a charge holding unit that temporarily holds the charge converted by the photoelectric conversion unit; and a groove formed between the photoelectric conversion unit and the charge holding unit in a semiconductor substrate; in the depth direction of the semiconductor substrate, the groove is formed to be higher than the photoelectric conversion unit.

[0015] A first electronic device according to an aspect of the present technology includes the first solid-state imaging device.

[0016] According to one aspect of the present technology, a second solid-state imaging device includes: a photoelectric conversion unit that performs photoelectric conversion; a charge holding unit that temporarily holds the charge converted by the photoelectric conversion unit; and a groove formed between the photoelectric conversion unit and the charge holding unit in a semiconductor substrate; in the depth direction of the semiconductor substrate, the groove is formed to be lower than the photoelectric conversion unit and higher than the charge holding unit.

[0017] A second electronic device according to an aspect of the present technology includes the second solid-state imaging device.

[0018] Beneficial effects of the present invention

[0019] According to the present technology, it is possible to prevent the deterioration of dark characteristics.

[0020] Note that the effects described here are not necessarily restrictive, and any effects described in the present invention can be produced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a diagram showing a configuration example of an imaging device.

[0022] Figure 2 : is a diagram showing a configuration example of an image pickup element.

[0023] Figure 3 is a vertical cross-sectional view showing a first configuration example of a pixel to which the present technology is applied.

[0024] Figure 4 is a plan view of the front surface side of a pixel to which the present technology is applied according to the first embodiment.

[0025] Figure 5 It is the circuit diagram of a pixel.

[0026] Figure 6 It is a diagram for explaining a method of manufacturing the DTI 82 and its periphery.

[0027] Figure 7 is a vertical cross-sectional view showing a second configuration example of a pixel to which the present technology is applied.

[0028] Figure 8 is a vertical cross-sectional view showing a third configuration example of a pixel to which the present technology is applied.

[0029] Fig. 9 is a vertical cross-sectional view showing a fourth configuration example of a pixel to which the present technology is applied.

[0030] Fig.10 is a vertical cross-sectional view showing a fifth configuration example of a pixel to which the present technology is applied.

[0031] Fig.11 is a vertical cross-sectional view showing a sixth configuration example of a pixel to which the present technology is applied.

[0032] Fig.12 is a vertical cross-sectional view showing a seventh configuration example of a pixel to which the present technology is applied.

[0033] Fig.13 is a vertical cross-sectional view showing an eighth configuration example of a pixel to which the present technology is applied.

[0034] Fig.14 is a vertical cross-sectional view showing a ninth configuration example of a pixel to which the present technology is applied.

[0035] Fig.15 is a vertical cross-sectional view showing a tenth configuration example of a pixel to which the present technology is applied.

[0036] Fig.16 are a vertical cross-sectional view and a plan view illustrating an eleventh configuration example of a pixel to which the present technology is applied.

[0037] Fig.17 are a vertical cross-sectional view and a plan view showing a twelfth configuration example of a pixel to which the present technology is applied.

[0038] Fig.18 is a vertical cross-sectional view showing a thirteenth configuration example of a pixel to which the present technology is applied.

[0039] Fig.19 is a horizontal plan view showing a fourteenth configuration example of a pixel to which the present technology is applied.

[0040] Fig. 20 is a vertical cross-sectional view showing a fourteenth configuration example of a pixel to which the present technology is applied.

[0041] Fig.21 is a plan view showing a configuration example in the case where two pixels share a transistor.

[0042] Fig. 22 This is a diagram for explaining a method for manufacturing a pixel.

[0043] Fig.23 is a vertical cross-sectional view showing a fifteenth configuration example of a pixel to which the present technology is applied.

[0044] Fig.24 is a horizontal plan view showing a sixteenth configuration example of a pixel to which the present technology is applied.

[0045] Fig.25 is a vertical cross-sectional view showing a sixteenth configuration example of a pixel to which the present technology is applied.

[0046] Fig.26 is a horizontal plan view showing a seventeenth configuration example of a pixel to which the present technology is applied.

[0047] Fig. 27 is a vertical cross-sectional view showing a seventeenth configuration example of a pixel to which the present technology is applied.

[0048] Fig.28 is a horizontal plan view showing an eighteenth configuration example of a pixel to which the present technology is applied.

[0049] Fig.29 is a vertical cross-sectional view showing an eighteenth configuration example of a pixel to which the present technology is applied.

[0050] Fig.30is a horizontal plan view showing a nineteenth configuration example of a pixel to which the present technology is applied.

[0051] Fig.31 is a vertical cross-sectional view showing a nineteenth configuration example of a pixel to which the present technology is applied.

[0052] Fig.32 is a vertical cross-sectional view showing a nineteenth configuration example of a pixel to which the present technology is applied.

[0053] Fig.33 is a horizontal cross-sectional view showing a twentieth configuration example of a pixel to which the present technology is applied.

[0054] Fig.34 is a horizontal cross-sectional view showing a twentieth configuration example of a pixel to which the present technology is applied.

[0055] Fig.35 is a vertical cross-sectional view showing a twentieth configuration example of a pixel to which the present technology is applied.

[0056] Fig.36 is a horizontal cross-sectional view showing another example of the twentieth configuration example of a pixel to which the present technology is applied.

[0057] Fig.37 is a vertical cross-sectional view showing another example of the twentieth configuration example of the pixel to which the present technology is applied.

[0058] Fig.38 is a horizontal cross-sectional view showing another example of the twentieth configuration example of a pixel to which the present technology is applied.

[0059] Fig.39 is a vertical cross-sectional view showing another example of the twentieth configuration example of the pixel to which the present technology is applied.

[0060] Fig.40 is a horizontal cross-sectional view showing a twenty-first configuration example of a pixel to which the present technology is applied.

[0061] Fig.41 is a horizontal cross-sectional view showing a twenty-first configuration example of a pixel to which the present technology is applied.

[0062] Fig.42 is a horizontal cross-sectional view showing another example of the twenty-first configuration example of the pixel to which the present technology is applied.

[0063] Fig.43 is a horizontal cross-sectional view showing another example of the twenty-first configuration example of the pixel to which the present technology is applied.

[0064] Fig.44 is a horizontal cross-sectional view showing a twenty-second configuration example of a pixel to which the present technology is applied.

[0065] Fig.45 is a horizontal cross-sectional view showing a twenty-second configuration example of a pixel to which the present technology is applied.

[0066] Fig.46 is a horizontal cross-sectional view showing another example of the twenty-second configuration example of the pixel to which the present technology is applied.

[0067] Fig.47 is a horizontal cross-sectional view showing another example of the twenty-second configuration example of the pixel to which the present technology is applied.

[0068] Fig.48 is a horizontal cross-sectional view showing a twenty-third configuration example of a pixel to which the present technology is applied.

[0069] Fig.49 : is a vertical cross-sectional view showing a twenty-third configuration example of a pixel to which the present technology is applied.

[0070] Fig.50 : is a vertical cross-sectional view showing a twenty-third configuration example of a pixel to which the present technology is applied.

[0071] Fig.51 : is a vertical cross-sectional view showing a twenty-third configuration example of a pixel to which the present technology is applied.

[0072] Fig.52 is a vertical cross-sectional view showing another example of the twenty-third configuration example of the pixel to which the present technology is applied.

[0073] Fig.53 is a horizontal cross-sectional view showing a twenty-fourth configuration example of a pixel to which the present technology is applied.

[0074] Fig.54 is a vertical cross-sectional view showing a twenty-fourth configuration example of a pixel to which the present technology is applied.

[0075] Fig.55 This is a diagram for explaining light leakage from the PD to the memory.

[0076] Fig.56 It is a diagram for explaining the distance between grooves.

[0077] Fig.57 is a horizontal cross-sectional view showing another example of the twenty-fourth configuration example of the pixel to which the present technology is applied.

[0078] Fig.58 is a vertical cross-sectional view showing another example of the twenty-fourth configuration example of the pixel to which the present technology is applied.

[0079] Fig.59 is a horizontal cross-sectional view showing another example of the twenty-fourth configuration example of the pixel to which the present technology is applied.

[0080] Fig.60 is a vertical cross-sectional view showing another example of the twenty-fourth configuration example of the pixel to which the present technology is applied.

[0081] Fig.61 It is a diagram for explaining the structure of the hollow portion.

[0082] Fig.62 is a vertical cross-sectional view showing another example of the twenty-fourth configuration example of the pixel to which the present technology is applied.

[0083] Fig.63 It is a diagram for explaining a strong electric field region.

[0084] Fig.64 is a horizontal cross-sectional view showing a twenty-fifth configuration example of a pixel to which the present technology is applied.

[0085] Fig.65 is a horizontal cross-sectional view showing a twenty-sixth configuration example of a pixel to which the present technology is applied.

[0086] Fig.66 is a horizontal cross-sectional view showing a twenty-seventh configuration example of a pixel to which the present technology is applied.

[0087] Fig.67 : is a vertical cross-sectional view showing a twenty-seventh configuration example of a pixel to which the present technology is applied.

[0088] Fig.68 : is a vertical cross-sectional view showing a twenty-third configuration example of a pixel to which the present technology is applied.

[0089] Fig.69 is corresponding to Fig.48 A plan view of the twenty-third construction example shown.

[0090] Fig.70 is a vertical cross-sectional view showing a twenty-fourth configuration example of a pixel to which the present technology is applied.

[0091] Fig.71 is a vertical cross-sectional view showing a twenty-fifth configuration example of a pixel to which the present technology is applied.

[0092] Fig.72 : is a vertical cross-sectional view showing a twenty-sixth configuration example of a pixel to which the present technology is applied.

[0093] Fig.73 : is a plan view showing a configuration example in the case where two pixels share an FD and the like.

[0094] Fig.74 : is a diagram showing the outline of a configuration example of a stacked solid-state imaging device to which the technology according to the present invention can be applied.

[0095] Fig.75 : is a cross-sectional view showing a first configuration example of the stacked solid-state imaging device 23020.

[0096] Fig.76 23020 is a cross-sectional view showing a second configuration example of the stacked solid-state imaging device 23020.

[0097] Fig.77 is a cross-sectional view showing a third configuration example of the stacked solid-state imaging device 23020.

[0098] Fig.78 is a cross-sectional view showing another configuration example of a stacked solid-state imaging device to which the technology according to the present invention can be applied.

[0099] Fig.79 is a block diagram showing an example of a schematic configuration of an internal information acquisition system.

[0100] Fig.80 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0101] Fig.81 It is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0102] Hereinafter, the best mode for carrying out the present technology (hereinafter referred to as an embodiment) will be described in detail with reference to the drawings.

[0103] Since the present technology can be applied to an image pickup device, the case where the present technology is applied to an image pickup device is described as an example. Note that here, the description will be given by taking an image pickup device as an example, but the present technology is not limited to being applied to an image pickup device, and can be widely applied to electronic devices that use an image pickup device for an image pickup section (photoelectric conversion section), such as: image pickup devices including digital cameras and video cameras, etc.; mobile terminal devices such as mobile phones that have an image pickup function; and copiers that use an image pickup device for an image reader. It should be noted that a modular structure (i.e., a camera module) mounted on an electronic device can be defined as an image pickup device.

[0104] Figure 1 1 is a block diagram illustrating a configuration example of an image pickup device as an example of an electronic device according to the present invention. Figure 1 As shown, the imaging device 10 includes: an optical system including a lens group 11, etc., an imaging element 12, a DSP circuit 13 used as a camera signal processor, a frame memory 14, a display unit 15, a recording unit 16, an operating system 17, a power supply system 18, etc.

[0105] Furthermore, in this configuration, the DSP circuit 13, the frame memory 14, the display section 15, the recording section 16, the operation system 17, and the power supply system 18 are interconnected by a bus 19. The CPU 20 controls each section in the image pickup device 10.

[0106] The lens group 11 acquires incident light (image light) from the subject and forms an image on the imaging surface of the imaging element 12. The imaging element 12 converts the amount of incident light of the image formed on the imaging surface by the lens group 11 into an electrical signal pixel by pixel, and outputs the electrical signal as a pixel signal. As the imaging element 12, an imaging element (image sensor) including pixels described below can be used.

[0107] The display section 15 includes a panel type display section such as a liquid crystal display section or an organic electroluminescence (EL: electro luminescence) display section, and displays a moving image or a still image captured by the imaging element 12. The recording section 16 records the moving image or the still image captured by the imaging element 12 on a recording medium such as a video tape or a digital versatile disk (DVD: digital versatile disk).

[0108] The operating system 17 issues operation commands to various functions of the imaging device according to operations performed by the user. The power supply system 18 appropriately supplies various power sources as operating power sources for the DSP circuit 13, frame memory 14, display unit 15, recording unit 16 and operating system 17 to these power supply targets.

[0109] <Structure of Image Pickup Element>

[0110] Figure 2 2 is a block diagram showing a configuration example of the image pickup element 12. The image pickup element 12 can be a complementary metal oxide semiconductor (CMOS) image sensor.

[0111] The image pickup element 12 includes a pixel array section 41, a vertical driver 42, a column processor 43, a horizontal driver 44, and a system controller 45. The pixel array section 41, the vertical driver 42, the column processor 43, the horizontal driver 44, and the system controller 45 are formed on a semiconductor substrate (chip) not shown.

[0112] In the pixel array section 41, unit pixels (eg, Figure 3The pixels 50 in the image sensor are arranged two-dimensionally in a matrix manner, and each unit pixel has a photoelectric conversion element, which generates and stores photoelectric charges, and the amount of photoelectric charges generated corresponds to the amount of incident light. Note that hereinafter, the photoelectric charge corresponding to the amount of incident light may be referred to as a "charge", and the unit pixel may be referred to as a "pixel".

[0113] The pixel array section 41 is provided with pixel drive lines 46 and vertical signal lines 47 for pixels arranged in a matrix. The pixel drive line 46 is formed for each row along the horizontal direction in the figure (the arrangement direction of pixels in each pixel row), and the vertical signal line 47 is formed for each column along the vertical direction in the figure (the arrangement direction of pixels in each pixel column). One end of the pixel drive line 46 is connected to the output end of the vertical driver 42 corresponding to each row.

[0114] The imaging element 12 further includes a signal processor 48 and a data storage unit 49. The signal processor 48 and the data storage unit 49 may be implemented by an external signal processor (e.g., a digital signal processor (DSP)) provided on a substrate different from the imaging element 12; or may be implemented by software processing; or may be provided on the same substrate as the imaging element 12.

[0115] The vertical driver 42 is a pixel driver that includes a shift register and an address decoder, etc., and drives all pixels in the pixel array section 41 at the same time, or drives the pixels in the pixel array section 41 row by row, for example. Although the specific configuration of the vertical driver 42 is not shown, the vertical driver 42 has a configuration including a read scanning system and a scan-out scanning system. Alternatively, the vertical driver 42 has a configuration in which batch scan-out and batch transfer are performed.

[0116] The read scanning system selectively scans the unit pixels in the pixel array section 41 in row units sequentially so as to read signals from the unit pixels. In the case of row driving (rolling shutter operation), when the sweep-out operation is performed, the read scanning operation is performed by the read scanning system at a time corresponding to the shutter speed before the read scanning operation. In addition, in the case of global exposure (global shutter operation), the batch sweep-out operation is performed at a time corresponding to the shutter speed before the batch transfer operation.

[0117] Due to the above-mentioned sweeping operation, unnecessary charges are swept out (reset) from the photoelectric conversion element of the unit pixel in the read row. Then, by sweeping out (resetting) the unnecessary charges, the so-called electronic shutter operation is performed. In this case, the electronic shutter operation refers to an operation of removing the photoelectric charges in the photoelectric conversion element and restarting exposure (starting to accumulate photoelectric charges).

[0118] The signal read by the reading operation of the reading scanning system corresponds to the amount of light received just before the reading operation or the amount of light received after the electronic shutter operation. In the case of row driving, the time period from the reading time of the previous reading operation or the sweeping time of the electronic shutter operation to the reading time of the current reading operation is set as the accumulation period (exposure period) of the photocharge in the unit pixel. In the case of global exposure, the period from batch sweeping to batch transfer is set as the accumulation period (exposure period).

[0119] Pixel signals output from unit pixels in a pixel row selectively scanned by the vertical driver 42 are supplied to the column processor 43 through corresponding vertical signal lines 47. The column processor 43 performs predetermined signal processing on pixel signals output from unit pixels in a selected row through the vertical signal lines 47 for each pixel column of the pixel array section 41, and temporarily stores the pixel signals that have been subjected to the predetermined signal processing.

[0120] Specifically, the column processor 43 performs at least noise removal processing (e.g., correlated double sampling (CDS) processing) as signal processing. Due to the correlated double sampling performed by the column processor 43, fixed pattern noise unique to the pixel (e.g., reset noise and threshold variation of the amplifier transistor) is removed. Note that in addition to the noise removal function, the column processor 43 may also have, for example, an analog-to-digital (AD) conversion function, and the column processor 43 outputs a signal level in digital form.

[0121] The horizontal driver 44 includes a shift register and an address decoder, etc., and selects unit circuits corresponding to each column of pixels in the column processor 43 one by one. Due to the selective scanning by the horizontal driver 44, pixel signals subjected to signal processing by the column processor 43 are sequentially output to the signal processor 48.

[0122] The system controller 45 includes a timing generator and the like that generates various timing signals, and controls driving of the vertical driver 42 , the column processor 43 , the horizontal driver 44 and the like based on the various timing signals generated by the timing generator.

[0123] The signal processor 48 has at least an addition processing function, and performs various signal processing such as addition processing on the pixel signal output from the column processor 43. The data storage section 49 temporarily stores data necessary for the signal processor 48 to perform signal processing.

[0124] <Unit Pixel Structure>

[0125] Next, the specific structure of each unit pixel 50 arranged in a matrix form in the pixel array section 41 will be described. The following pixel 50 can reduce the size of the silicon (Si) substrate ( Figure 3The pinning on the light incident side of the Si substrate 70 in the photodiode is weakened and the generated charge thus flows into the photodiode ( Figure 3 The possibility of deterioration of dark characteristics (i.e., generation of white spots or generation of dark current) due to the PD 71 in the display.

[0126] <Configuration Example of Pixel According to First Embodiment>

[0127] Figure 3 is a vertical cross-sectional view of a pixel 50a according to a first embodiment of a pixel 50 to which the present technology is applied, Figure 4 is a plan view of the front surface side of the pixel 50a. Note that Figure 3 Corresponding to along Figure 4 The position of the line X-X' in.

[0128] Hereinafter, the pixel 50 is described as an example of a back-illuminated type. However, the present technology can also be applied to a front-illuminated type.

[0129] Figure 3 The pixel 50 shown has a photodiode (PD) 71, which is a photoelectric conversion element of each pixel formed inside a Si substrate 70. A P-type region 72 is formed on the light incident side of the PD 71 (in the figure, the lower side as the back side), and a planarization film 73 is further formed below the P-type region 72. The boundary between the P-type region 72 and the planarization film 73 is defined as a back Si interface 75.

[0130] A light shielding film 74 is formed in the planarizing film 73. The light shielding film 74 is provided to prevent light from leaking into adjacent pixels, and is formed between adjacent PDs 71. The light shielding film 74 contains a metal material such as tungsten (W), for example.

[0131] An on-chip lens (OCL) 76 for focusing incident light onto the PD 71 is formed on the planarization film 73 and on the back side of the Si substrate 70. An inorganic material can be used for the OCL 76. For example, SiN, SiO, or SiO x N y (0 <x≤1,0<y≤1)。

[0132] Despite Figure 3 Although not shown in the figure, a glass cover or a transparent plate such as a resin plate may be bonded to the OCL 76. Figure 3 Although not shown in the figure, a color filter layer may be formed between the OCL 76 and the planarization film 73. Furthermore, in the color filter layer, a plurality of color filters may be provided for each pixel, and the colors of the color filters may be arranged in, for example, a Bayer arrangement.

[0133] An active region (Pwell) 77 is formed on the side opposite to the light incident side (upper side in the figure, ie, front surface side) of the PD 71. In the active region 77, an element isolation region (hereinafter referred to as shallow trench isolation (STI)) 78 for isolating pixel transistors and the like is formed.

[0134] A wiring layer 79 is formed on the front surface side (upper side in the figure) of the Si substrate 70 and the active region 77 , and a plurality of transistors are formed in the wiring layer 79 . Figure 3 An example in which a transfer transistor 80 is formed is shown. The transfer transistor (gate) 80 is a vertical transistor. That is, in the transfer transistor (gate) 80, an opening of a vertical transistor trench 81 is formed, and a transfer gate (TG) 80 for reading charges from the PD 71 is formed therein.

[0135] In addition, pixel transistors such as an amplifier (AMP) transistor, a select (SEL) transistor, and a reset (RST) transistor are formed on the front surface side of the Si substrate 70. Figure 4 The arrangement of these transistors will be described with reference to Figure 5 The circuit diagram in illustrates the operation.

[0136] A trench is formed between the pixels 50a. The trench is called a deep trench isolation (DTI: deep trench isolation) 82. The DTI 82 is formed between adjacent pixels 50a and penetrates the Si substrate 70 in the depth direction (vertical direction in the figure, i.e., the direction from the front surface to the back surface). In addition, the DTI 82 also acts as a light shielding wall between pixels so that unnecessary light does not leak to adjacent pixels 50a.

[0137] Between the PD 71 and the DTI 82, a P-type solid phase diffusion layer 83 and an N-type solid phase diffusion layer 84 are sequentially formed from the DTI 82 toward the PD 71. The P-type solid phase diffusion layer 83 is formed along the DTI 82 and contacts the back Si interface 75 of the Si substrate 70. The N-type solid phase diffusion layer 84 is formed along the DTI 82 and contacts the P-type region 72 of the Si substrate 70.

[0138] It should be noted that the solid phase diffusion layer refers to a layer in which a P-type layer and an N-type layer generated by impurity doping are formed according to a method described later. However, in the present technology, the method is not limited to the solid phase diffusion method, and a P-type layer and an N-type layer generated by other methods (e.g., ion implantation) may be provided between the DTI 82 and the PD 71. In addition, the PD 71 in the embodiment includes an N-type region. Photoelectric conversion is performed in a partial region or the entire region of the N-type region.

[0139] The P-type solid phase diffusion layer 83 is formed in contact with the back Si interface 75 , whereas the N-type solid phase diffusion layer 84 is not in contact with the back Si interface 75 . Therefore, there is a gap between the N-type solid phase diffusion layer 84 and the back Si interface 75 .

[0140] With such a structure, the PN junction region between the P-type solid diffusion layer 83 and the N-type solid diffusion layer 84 forms a strong electric field region and holds the charge generated in the PD 71. According to such a structure, the P-type solid diffusion layer 83 and the N-type solid diffusion layer 84 formed along the DTI 82 form a strong electric field region and are able to hold the charge generated in the PD 71.

[0141] If the N-type solid-phase diffusion layer 84 is formed along the DTI 82 and contacts the back Si interface 75 of the Si substrate 70, the pinning of the charges is weakened in the portion where the N-type solid-phase diffusion layer 84 contacts the back Si interface 75 on the light incident surface side of the Si substrate 70, causing the generated charges to flow into the PD 71. As a result, the dark characteristics may be degraded. For example, white spots may appear, or dark current may be generated.

[0142] However, in Figure 3 In the pixel 50a shown, the N-type solid phase diffusion layer 84 does not contact the back Si interface 75 of the Si substrate 70, and the N-type solid phase diffusion layer 84 is formed along the DTI 82 and contacts the P-type region 72 of the Si substrate 70. With such a structure, it is possible to prevent the pinning of charges from being weakened, and therefore, it is possible to prevent the dark characteristic from being deteriorated due to the inflow of charges into the PD 71.

[0143] In addition, Figure 3 In the illustrated pixel 50 a , a sidewall film 85 composed of SiO 2 is formed on the inner wall of the DTI 82 , and a filler 86 composed of polysilicon is embedded inside the sidewall film 85 .

[0144] The pixel 50a according to the first embodiment has a configuration in which the P-type region 72 is provided on the back side, and the PD 71 and the N-type solid-phase diffusion layer 84 are not present near the back Si interface 75. As a result, the pinning near the back Si interface 75 is not weakened. Therefore, it is possible to prevent the dark characteristic from being deteriorated due to the inflow of charges into the PD 71.

[0145] Note that, regarding the DTI 82, SiN may be used instead of SiO2 for the sidewall film 85. Furthermore, doped polysilicon may be used instead of polysilicon for the filler 86. In the case of filling with doped polysilicon, or in the case of doping with N-type or P-type impurities after filling with polysilicon, by applying a negative bias to the resulting filler, pinning of the sidewall of the DTI 82 can be enhanced, and therefore, dark characteristics can be further improved.

[0146] Reference Figure 4 and 5 The arrangement of transistors formed in the pixel 50a and the operation of each transistor are described. Figure 4 From the front surface side ( Figure 3 The arrangement of the pixel array section 41 ( Figure 2 ) is a plan view of 9 pixels 50a of 3×3, Figure 5 It is used to illustrate Figure 4 A circuit diagram showing the connection relationship between transistors.

[0147] exist Figure 4 In FIG. 5 , a rectangle represents a pixel 50a. Figure 4 As shown, DTI 82 is formed around pixel 50a (PD 71 is included in pixel 50a). In addition, transfer transistor (gate) 80, floating diffusion (FD) 91, reset transistor 92, amplification transistor 93 and selection transistor 94 are formed on the front surface of pixel 50a.

[0148] The PD 71 generates and accumulates charges (signal charges) corresponding to the amount of received light. An anode terminal of the PD 71 is grounded, and a cathode terminal is connected to the FD 91 via the transfer transistor 80 .

[0149] When the transfer transistor 80 is turned on by the transfer signal TR, the transfer transistor 80 reads the charges generated in the PD 71 and transfers the generated charges to the FD 91 .

[0150] The FD 91 holds the charge read from the PD 71. When the reset transistor 92 is turned on by the reset signal RST, the reset transistor 92 resets the potential of the FD 91 by discharging the charge accumulated in the FD 91 to the drain (constant voltage source Vdd).

[0151] The amplifier transistor 93 outputs a pixel signal according to the potential of the FD 91. That is, the amplifier transistor 93 and a load MOS (not shown) as a constant current source connected via the vertical signal line 33 constitute a source follower circuit, and a pixel signal representing a level according to the charge accumulated in the FD 91 is output from the amplifier transistor 93 via the selection transistor 94 and the vertical signal line 47 to the column processor 43 ( Figure 2 ).

[0152] When the pixel 31 is selected by the selection signal SEL, the selection transistor 94 is turned on and the pixel signal of the pixel 31 is output to the column processor 43 via the vertical signal line 33. The signal line to which the transmission signal TR, the selection signal SEL and the reset signal RST are transmitted corresponds to Figure 2 Pixel drive line 46 in.

[0153] The pixel 50a can be constructed as described above, but the pixel 50a is not limited to having the above-described structure. The pixel 50a may also have other structures.

[0154] <Method of manufacturing DTI 82 and its periphery>

[0155] Figure 6 It is a diagram for explaining the method of manufacturing DTI 82 and its periphery.

[0156] As Figure 6 shown in A of , when forming the DTI 82 by opening in the Si substrate 70, the regions on the Si substrate 70 other than the position where the DTI 82 is to be formed are covered with a hard mask using SiN and SiO2, and the regions not covered by the hard mask are dry-etched. Thus, the groove is opened to a predetermined depth in the Si substrate 70 in the vertical direction.

[0157] Next, a SiO2 film containing phosphorus (P) as an N-type impurity is formed inside the opened groove, and then heat treatment is performed, so that phosphorus (P) is doped from a part of the SiO2 film into the Si substrate 70 (hereinafter referred to as solid-phase diffusion).

[0158] Then, as Figure 6 shown in B of , after removing the SiO2 film containing P formed in the opened groove, heat treatment is performed again to diffuse phosphorus (P) into the interior of the Si substrate 70. Thus, an N-type solid-phase diffusion layer 84 self-aligned with the current groove shape is formed. After that, the bottom of the groove is dry-etched, so that the groove extends in the depth direction.

[0159] Next, as Figure 6 shown in C of , a SiO2 film containing boron (B) as a P-type impurity is formed inside the extended groove, and then heat treatment is performed. Through this treatment, boron (B) diffuses from the SiO2 film into the Si substrate 70 by solid-phase diffusion, thus forming a P-type solid-phase diffusion layer 83 self-aligned with the shape of the extended groove.

[0160] After that, the SiO2 film containing boron (B) formed on the inner wall of the groove is removed.

[0161] Next, as Figure 6 shown in D of , a sidewall film 85 containing SiO2 is formed on the inner wall of the opened groove and filled with polysilicon. Thus, the DTI 82 is formed. After that, pixel transistors and wirings are formed. Then, the Si substrate 70 is thinned from the back side. When the Si substrate 70 is thinned, the bottom of the DTI 82 including the P-type solid-phase diffusion layer 83 is thinned simultaneously. The thinning process is performed until the depth of the N-type solid-phase diffusion layer 84 is not reached.

[0162] Through the above steps, a strong electric field region composed of the N-type solid diffusion layer 84 not in contact with the back Si interface 75 and the P-type solid diffusion layer 83 in contact with the back Si interface 75 can be formed adjacent to the PD 71 .

[0163] <Second Embodiment>

[0164] Figure 7 is a vertical cross-sectional view of a pixel 50 b according to a second embodiment to which the present technology is applied.

[0165] The second embodiment is different from the first embodiment in that the DTI 82 is formed in the STI 78, and the other configurations are the same as the first embodiment. Therefore, the same parts as in the first embodiment are represented by the same reference numerals, and the description thereof will be appropriately omitted. In the following description of the pixel 50, the same parts of the pixel 50b as in the first embodiment are represented by the same reference numerals, and the description thereof will be appropriately omitted.

[0166] exist Figure 7 In the pixel 50b shown, the STI 78b formed in the active region 77 is formed up to the portion where the DTI 82b is formed (formed to the end of the pixel 50b). Then, the DTI 82b is formed under the STI 78b.

[0167] In other words, the STI 78 b is formed at a portion where the DTI 82 b is formed, and the STI 78 b and the DTI 82 b are formed at a position where the STI 78 b and the DTI 82 b are in contact with each other.

[0168] By forming in this way, compared with the case where the STI 78b and the DTI 82b are formed at different positions (for example, the pixel 50a ( Figure 3 )), the size of pixel 50b can be reduced.

[0169] The pixel 50 b according to the second embodiment can also provide the same effect as the pixel 50 a according to the first embodiment, that is, provide an effect of preventing the dark characteristic from deteriorating.

[0170] <Third Embodiment>

[0171] Figure 8 is a vertical cross-sectional view of a pixel 50 c according to a third embodiment to which the present technology is applied.

[0172] The third embodiment is different from the pixels 50a and 50b in the first and second embodiments in that a film 101 having a negative fixed charge is formed on the side wall of the DTI 82c, and the inside of the film 101 is filled with SiO2 as a filler 86c.

[0173] The pixel 50a in the first embodiment has a structure in which a sidewall film 85 including SiO2 is formed on the sidewall of the DTI 82 and is filled with polysilicon, while in the pixel 50c in the third embodiment, a film 101 having a negative fixed charge is formed on the sidewall of the DTI 82c and the inside of the film 101 is filled with SiO2.

[0174] The film 101 having a negative fixed charge formed on the side wall of the DTI 82c can be, for example, a hafnium oxide (HfO2) film, an aluminum oxide (Al2O3) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, or a titanium oxide (TiO2) film. The above-mentioned type of film has been used as a gate insulating film of an insulated gate field effect transistor, etc., and therefore, a film forming method has been established. Therefore, such a film can be easily formed.

[0175] Examples of the above film formation method include chemical vapor deposition, sputtering, atomic layer deposition, etc. If the atomic layer deposition method is used, it is preferable to simultaneously form a SiO2 layer with a thickness of about 1 nm for reducing the interface energy level during film formation.

[0176] In addition, examples of materials other than the above materials include: lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3) and yttrium oxide (Y2O3).

[0177] Furthermore, the film 101 having negative fixed charge can be formed using a hafnium nitride film, an aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film.

[0178] Silicon (Si) or nitrogen (N) may be added to the film 101 having a negative fixed charge as long as the insulating property is not impaired. The concentration of the additive may be appropriately determined as long as the insulating property of the film is not impaired. However, in order to prevent image defects such as white spots, it is preferred to add additives such as silicon or nitrogen to the surface of the film 101 having a negative fixed charge, that is, the surface opposite to the PD 71. As described above, by adding silicon (Si) and nitrogen (N), the heat resistance of the film can be improved, and the ability to prevent ion implantation during processing can be improved.

[0179] In the third embodiment, it is possible to enhance the pinning on the trench sidewalls of the DTI 82. Therefore, when compared with, for example, the pixel 50a in the first embodiment, the pixel 50c can more reliably prevent the dark characteristic from deteriorating.

[0180] In order to form the DTI 82 in the third embodiment, such a process as described below can be performed. Specifically, in Figure 6 In the state shown in D of FIG. 1 , the back surface is polished until the polysilicon added as the filler 86 is exposed. Then, the filler 86 (polysilicon) and the sidewall film 85 (SiO2) inside the groove are removed by photoresist and wet etching, thereby forming a film 101. Thereafter, the groove is filled with SiO2.

[0181] Note that the inside of the groove may be filled with a metal material such as tungsten (W) instead of SiO 2 as a filler. In this case, obliquely incident light is suppressed from being transmitted through the DTI 82, so that color mixing can be reduced.

[0182] <Fourth Embodiment>

[0183] Fig. 9 is a vertical cross-sectional view of a pixel 50 d according to a fourth embodiment to which the present technology is applied.

[0184] The fourth embodiment differs from the pixel 50a in the first embodiment in that the N-type solid-phase diffusion layer 84d formed along the DTI 82 has a concentration gradient in the depth direction of the Si substrate 70. The other configurations are the same as those of the pixel 50a in the first embodiment.

[0185] The N-type impurity concentration of the N-type solid phase diffusion layer 84 of the pixel 50a in the first embodiment is constant regardless of the depth direction, while the N-type impurity concentration of the N-type solid phase diffusion layer 84d of the pixel 50d in the fourth embodiment varies in the depth direction.

[0186] That is, the N-type solid phase diffusion layer 84d-1 near the front surface of the N-type solid phase diffusion layer 84d of the pixel 50d has a high N-type impurity concentration, while the N-type solid phase diffusion layer 84d-2 near the back surface has a low N-type impurity concentration.

[0187] The pixel 50d according to the fourth embodiment can provide the same effect as the pixel 50a according to the first embodiment. In addition, since a concentration gradient is provided in the N-type solid phase diffusion layer 84d, the potential on the back side becomes shallower, so the pixel 50d can also provide another effect that charges can be easily read.

[0188] For example, a concentration gradient can be provided in the N-type solid phase diffusion layer 84d in the following manner: Specifically, when forming an opening of a groove for the DTI 82, etching damage is caused to the sidewall of the groove, and thus a concentration gradient can be provided by utilizing a difference in the doping amount of solid phase diffusion caused by the damage amount.

[0189] Note that, as an alternative to providing a concentration gradient in the N-type solid-phase diffusion layer 84d, the P-type impurity concentration in the P-type solid-phase diffusion layer 83d near the front surface may be reduced, and the P-type impurity concentration in the P-type solid-phase diffusion layer 83d near the back surface may be increased. In this case, the same effect as that obtained when providing a concentration gradient in the N-type solid-phase diffusion layer 84d can be obtained.

[0190] In addition, both the N-type solid-phase diffusion layer 84d and the P-type solid-phase diffusion layer 83d may have a concentration gradient.

[0191] <Fifth Embodiment>

[0192] Fig.10 is a vertical cross-sectional view of a pixel 50 e according to a fifth embodiment to which the present technology is applied.

[0193] The pixel 50e according to the fifth embodiment is different from that of the first embodiment in that the sidewall film 85e including SiO2 formed on the inner wall of the DTI 82e is formed thicker than the sidewall film 85 of the pixel 50a according to the first embodiment. The other configuration is the same as that of the first embodiment.

[0194] The light refractive index of SiO2 is lower than that of Si. Therefore, light entering the Si substrate 70 is reflected according to Snell's law, thereby preventing the light from being transmitted to the adjacent pixel 50. However, if the sidewall film 85 is thin, Snell's law does not fully hold true, and the transmitted light may increase.

[0195] The side wall film 85e of the pixel 50e in the fifth embodiment is formed thicker. Therefore, the deviation from Snell's law can be reduced, and the reflection of the incident light on the side wall film 85e is increased. As a result, the transmission of the incident light to the adjacent pixel 50e can be reduced. Therefore, the pixel 50e according to the fifth embodiment can provide the same effect as the pixel 50a according to the first embodiment, and can further provide the effect of preventing the adjacent pixel 50e from mixing colors due to oblique incident light.

[0196] <Sixth Embodiment>

[0197] Fig.11 is a vertical cross-sectional view of a pixel 50 f according to a sixth embodiment to which the present technology is applied.

[0198] The pixel 50f according to the sixth embodiment is different from the pixel 50a in the first embodiment in that a P-type impurity is doped in the region 111 between the PD 71 and the back Si interface 75, thereby setting a concentration gradient so that the P-type impurity concentration on the back side of the Si substrate 70 is higher than the P-type impurity concentration on the front surface side. The other structures are the same as those of the pixel 50a in the first embodiment.

[0199] Refer again Figure 3 In the pixel 50a of the first embodiment, the Si substrate 70 does not have a concentration gradient, and a P-type region 72 is formed between the PD 71 and the back Si interface 75. In the pixel 50f according to the sixth embodiment, the Si substrate 70 has a concentration gradient. The concentration gradient is such that the P-type impurity concentration on the back side (the P-type region 111 side) is higher than the P-type impurity concentration on the front surface side.

[0200] The pixel 50 f according to the sixth embodiment having such a concentration gradient can provide the same effect as the pixel 50 a according to the first embodiment, and can further provide an effect that charges are easier to read than the pixel 50 a in the first embodiment.

[0201] <Seventh Embodiment>

[0202] Fig.12 is a vertical cross-sectional view of a pixel 50g according to a seventh embodiment to which the present technology is applied.

[0203] The pixel 50g according to the seventh embodiment is different from the pixel 50a according to the first embodiment in that the Si substrate 70 of the pixel 50g is thicker than that of the pixel 50a, and the DTI 82 and the like are formed deeper as the thickness of the Si substrate 70 increases.

[0204] The pixel 50g in the seventh embodiment has a thick Si substrate 70g. As the thickness of the Si substrate 70g increases, the area (volume) of the PD 71g increases, and the DTI 82g is deeper. In addition, since the DTI 82g is formed deeper, the P-type solid-phase diffusion layer 83g and the N-type solid-phase diffusion layer 84g are also formed deeper (wider).

[0205] Since the P-type solid-phase diffusion layer 83g and the N-type solid-phase diffusion layer 84g are wider, the area of ​​the PN junction region formed by the P-type solid-phase diffusion layer 83g and the N-type solid-phase diffusion layer 84g increases. Therefore, the pixel 50g according to the seventh embodiment can provide the same effect as the pixel 50a according to the first embodiment, and can further provide the following effect: the saturation charge amount Qs is increased compared to the pixel 50a according to the first embodiment.

[0206] <Eighth Embodiment>

[0207] Fig.13 is a vertical cross-sectional view of a pixel 50h according to an eighth embodiment to which the present technology is applied.

[0208] In the pixel 50h according to the eighth embodiment, as Fig.12 As in the pixel 50g according to the seventh embodiment shown in FIG. 1 , the length of the Si substrate 70 in the depth direction is increased.

[0209] In pixel 50h, P-type region 121-1, N-type region 122, and P-type region 121-2 are formed by ion implantation in PD 71 on the back side. A strong electric field is generated at the PN junction formed by P-type region 121-1, N-type region 122, and P-type region 121-2, thereby being able to hold charges.

[0210] Therefore, the pixel 50h according to the eighth embodiment can provide the same effect as the pixel 50g according to the seventh embodiment, and can also provide the effect of increasing the saturation charge amount Qs.

[0211] <Ninth Embodiment>

[0212] Fig.14 is a vertical cross-sectional view of a pixel 50 i according to a ninth embodiment to which the present technology is applied.

[0213] The pixel 50i according to the ninth embodiment is different from the pixel 50a according to the first embodiment in that a MOS capacitor 131 and a pixel transistor (not shown) are formed on the front surface side of the Si substrate 70. The other configurations are the same as those of the pixel 50a in the first embodiment.

[0214] Generally, even if the saturation charge amount Qs of the PD 71 increases, the output is still affected by the vertical signal line VSL ( Figure 2 The amplitude of the vertical signal line 47 shown in the figure is limited, so it is difficult to fully utilize the increased saturation charge amount Qs.

[0215] In order to reduce the conversion efficiency of PD 71, it is necessary to provide FD 91 ( Figure 4 ) Adding capacitance. In view of this, the pixel 50i according to the ninth embodiment has a configuration in which a MOS capacitor 131 is added as a capacitor to be added to the FD 91 ( Fig.14 Capacitor not shown).

[0216] The pixel 50i according to the ninth embodiment can provide the same effect as the pixel 50a according to the first embodiment. In addition, since the MOS capacitor 131 is added to the FD 91, the pixel 50i can reduce the conversion efficiency of the PD 71 and can fully utilize the increased saturation charge amount Qs.

[0217] <Tenth Embodiment>

[0218] Fig.15 is a vertical cross-sectional view of a pixel 50 j according to a tenth embodiment to which the present technology is applied.

[0219] The pixel 50j according to the tenth embodiment is different from the pixel 50a according to the first embodiment in that two contacts 152 are formed in a well contact 151 formed in an active region 77, and the contacts 152 are connected to a Cu wiring 153. The other configurations are the same as those of the pixel 50a according to the first embodiment.

[0220] As described above, a well contact 151 may be provided. Note that although Fig.15 Although an example in which two contacts 152 are formed is shown, more than two contacts 152 may be formed in the well contact portion 151 .

[0221] The pixel 50 j according to the tenth embodiment can provide the same effects as the pixel 50 a according to the first embodiment, and can also provide an effect of improving a critical yield defect.

[0222] <Eleventh Embodiment>

[0223] Fig.16 A vertical cross-sectional view and a plan view of a pixel 50 k according to an eleventh embodiment to which the present technology is applied are shown.

[0224] The pixel 50k according to the eleventh embodiment is different from the pixel 50a according to the first embodiment in that a transfer transistor (gate) 80k is formed by forming a vertical transistor trench 81k opening in the center of the pixel 50k. The other configurations are the same as those of the pixel 50a in the first embodiment.

[0225] exist Fig.16 In the pixel 50k shown, the position of the transfer transistor (gate) 80k is equidistant from the outer periphery of the PD 71. Therefore, the pixel 50k according to the eleventh embodiment can provide the same effect as the pixel 50a according to the first embodiment, and further, since the position of the transfer transistor (gate) is equidistant from the outer periphery of the PD 71, the pixel 50k according to the eleventh embodiment can also improve the transfer of charges.

[0226] <Twelfth Embodiment>

[0227] Fig.17 A vertical cross-sectional view and a plan view of a pixel 50 m according to a twelfth embodiment to which the present technology is applied are shown.

[0228] The pixel 50m according to the twelfth embodiment is different from the pixel 50a according to the first embodiment in that the transfer transistor 80m includes two vertical transistor trenches 81-1 and 81-2. The other configurations are the same as those of the pixel 50a in the first embodiment.

[0229] According to the pixel 50a ( Figure 3 ) has a configuration in which the transfer transistor 80 includes one vertical transistor trench 81, while the pixel 50m according to the twelfth embodiment has a configuration in which the transfer transistor 80m includes two vertical transistor trenches 81-1 and 81-2.

[0230] Since the above structure includes two vertical transistor trenches 81-1 and 81-2, it is possible to improve the tracking of the potential of the region between the two vertical transistor trenches 81-1 and 81-2 when the potential of the transfer transistor 80k is changed. Therefore, it is possible to improve the modulation degree. As a result, it is possible to improve the transfer efficiency of the charge.

[0231] Furthermore, the same effects as those of the pixel 50 a according to the first embodiment can also be obtained.

[0232] It should be noted that although in the above description, the transfer transistor 80 k includes two vertical transistor trenches 81 - 1 and 81 - 2 as an example, more than two vertical transistor trenches 81 may be provided in each pixel region.

[0233] In addition, an example in which two vertical transistor trenches 81-1 and 81-2 are formed to have the same size (length and thickness) has been described. However, in the case of forming a plurality of vertical transistor trenches 81, the plurality of vertical transistor trenches 81 may have different sizes. For example, one of the two vertical transistor trenches 81-1 and 81-2 may be longer than the other vertical transistor trench, or thicker than the other vertical transistor trench.

[0234] <Thirteenth Embodiment>

[0235] Fig.18 A vertical cross-sectional view of a pixel 50n according to a thirteenth embodiment to which the present technology is applied is shown.

[0236] The pixel 50 n according to the thirteenth embodiment is different from the pixel 50 a according to the first embodiment in the configuration of the light shielding film 74 , and the other configurations are the same as those of the pixel 50 a .

[0237] In the pixel 50n according to the thirteenth embodiment, the light shielding film 74n-2 and the light shielding film 74n-1 are formed above and below the DTI 82n, respectively. Figure 3 ) has a light shielding film 74 that covers the back side (lower side in the figure) of the DTI 82 on the back side of the pixel 50a, and on the back side of the pixel 50n ( Fig.18 ), the DTI 82n is covered with the same metal material (eg, tungsten) as that of the light shielding film 74, and the front surface side (upper side in the figure) of the Si substrate 70 is also covered with the metal material.

[0238] In other words, each pixel region is surrounded by metal material except for the back side (light incident side). However, it should be noted that in the configuration where the pixel 50n is surrounded by metal material except for its back side, an opening is appropriately formed in a necessary portion. For example, the portion of the light shielding film 74n-2 where the transfer transistor 80n is located is opened, and a terminal for connecting to the outside is formed therein.

[0239] Note that the light shielding film 74 and the like may be made of a metal material other than tungsten (W).

[0240] According to the pixel 50n in the thirteenth embodiment, incident light can be prevented from leaking into the adjacent pixel 50n, so that color mixture can be suppressed.

[0241] In addition, light incident from the back surface but reaching the front surface without being photoelectrically converted is reflected by the metal material (light shielding film 74n-2) and again enters PD 71. Therefore, the pixel 50n according to the thirteenth embodiment can provide the same effect as the pixel 50a according to the first embodiment, and can further provide an effect of improving the sensitivity of PD 71.

[0242] <Fourteenth Embodiment>

[0243] Fig.19 is a horizontal plan view of a pixel 50p according to a fourteenth embodiment to which the present technology is applied, Fig. 20 It is along Fig.19 A vertical cross-sectional view of the pixel 50 p taken along line AA′ in the pixel 50 p is shown.

[0244] The pixel 50p according to the fourteenth embodiment includes the above-described pixel 50 (for example, the pixel 50a here) and a charge holding region (corresponding to the memory 211 described below). Since the charge holding region is provided, a global shutter can be realized.

[0245] The pixels 50a to 50p in the first to fourteenth embodiments are all back-illuminated sensors. Generally, a CMOS image sensor is a rolling shutter type that reads each pixel sequentially, so image distortion may occur due to differences in exposure timing.

[0246] As a countermeasure to the occurrence of such distortion, a global shutter method has been proposed in which all pixels are read simultaneously by setting a charge holding portion in the pixel. According to the global shutter method, after all pixels are read simultaneously to the charge holding portion, the read pixels can be read sequentially. Therefore, in each pixel, the exposure timing can be set to be the same, and image distortion can be suppressed.

[0247] like Fig. 20As shown, in the case where the PD 71p (photoelectric conversion section) and the memory 211 (charge holding section) are provided on the same substrate, light leaking from the PD 71p may enter the memory 211. If this occurs, a false image may occur.

[0248] To prevent this, Fig. 20 As shown, a hole is drilled in a portion between the PD 71p and the memory 211 of the substrate, and a light shielding material is embedded in the drilled portion. The drilled portion and the material embedded in the drilled portion are denoted as DTI 201.

[0249] The pixel 50p has a PD 71p formed in a Si substrate 70p and a memory 211. The memory 211 is a region having a high N-type impurity concentration like the PD 71p. The memory 211 is provided as a charge holding portion that temporarily holds the charge photoelectrically converted by the PD 71p.

[0250] As in other embodiments, for example, Figure 3 As in the pixel 50a shown in FIG. 1 , the pixel 50p is surrounded by the DTI 82p formed so as to penetrate the Si substrate 70p in the depth direction. Fig. 20 In the pixel 50p shown, DTI 82p-1 is formed on the right side and DTI 82p-2 is formed on the left side. Fig.19 As shown in the plan view of , the DTI 82p is formed in a manner surrounding the pixel 50p (including the area of ​​the PD 71p and the memory 211).

[0251] In the DTI 82p surrounding the pixel 50p, as in other embodiments, a P-type solid phase diffusion layer 83 and an N-type solid phase diffusion layer 84 are formed. A strong electric field region is formed due to the P-type solid phase diffusion layer 83 and the N-type solid phase diffusion layer 84. Therefore, as in the above-mentioned embodiment, the effect of preventing the dark characteristic from deteriorating can be obtained.

[0252] The DTI 201 is disposed between the PD 71p and the memory 211 and does not penetrate the Si substrate 70p in the depth direction. Unlike the DTI 82p surrounding the pixel 50p, the DTI 201 does not penetrate the Si substrate 70p. In other words, the DTI 201 formed between the PD 71p and the memory 211 is a groove formed by drilling while retaining the Pwell region 77 above the DTI 201 (the upper part in the figure).

[0253] A read gate 213 is formed on the DTI 201 formed in a non-penetrating manner. The read gate 213 includes a vertical transistor trench 214, and the vertical transistor trench 214 reaches the inside of the PD 71p. That is, the read gate 213 for reading charges from the PD 71p extends in the vertical direction and the horizontal direction relative to the PD 71p, and the read gate 213 (vertical transistor trench 214) extending in the vertical direction is formed in contact with the PD 71p.

[0254] Note that although the description will be continued assuming that the vertical transistor trench 214 reaches the inside of the PD 71p, the vertical transistor trench 214 may be formed in a manner of contacting only the PD 71p, or may not contact the PD 71p (with a little distance therebetween). This similarly applies to other vertical transistor trenches.

[0255] The write gate 216 is formed in a region adjacent to the read gate 213. The write gate 216 is provided with a vertical transistor trench 217, and the vertical transistor trench 217 reaches (contacts) the inside of the memory 211.

[0256] The charge stored in the PD 71p is read by the read gate 213, and the read charge is written into the memory 211 by the write gate 216. In other words, the DTI 201 is configured not to penetrate the Si substrate 70p so as to provide regions for forming the read gate 213 and the write gate 216, thereby enabling the above-described process.

[0257] The read gate 220 is formed in a region adjacent to the write gate 216. The read gate 220 includes a vertical transistor trench 219, and the vertical transistor trench 219 reaches (contacts) the inside of the memory 211.

[0258] The charge written (stored) in the memory 211 is read by the read gate 220 and then transferred to the amplifier transistor 93 ( Fig.19 ). refer to Fig.19 The reading gate 220 and the amplifier transistor 93 are connected via the FD wiring 232. In addition, the amplifier transistor 93 is connected to the N+ diffusion layer 222.

[0259] The N+ diffusion layer 222 is a region provided to suppress blooming, and has a high N-type impurity concentration. Fig. 20, an N+ diffusion layer 222 is formed above the upper right of the PD 71p. An STI 78 is formed in the upper right region of the PD 71p. That is, this region is located on the opposite side of the side where the memory 211 is located. Here, as an example, the N+ diffusion layer 222 is formed at a position away from the accumulation region (memory 211). However, the N+ diffusion layer 222 can be formed near the accumulation region. In addition, the N+ diffusion layer 222 is biased to the voltage VDD.

[0260] Since a DTI 201 is formed between the PD 71p and the memory 211, charge can be prevented from flowing from the PD 71p to the memory 211. However, when the PD 71p is saturated, since there is a Pwell region 77 above the DTI 201, charge may flow from the PD 71p to the memory 211. The N+ diffusion layer 222 is formed such that when the PD 71p is saturated, charge does not flow from the PD 71p into the memory 211.

[0261] In the case where the PD 71p is saturated, the charge in the PD 71p flows into the N+ diffusion layer 222 formed above the PD 71p. Therefore, charge can be prevented from flowing from the PD 71p to the memory 211 when the PD 71p is saturated.

[0262] As Fig. 20 shown, without using the surface of the Si substrate 70p, the PD 71p and the memory 211 of the buried pixel 50p are embedded. Since the PD 71p and the memory 211 are buried, high light spillage can be further suppressed.

[0263] In the case where both the PD 71p and the memory 211 are buried, when the Fig. 20 vertical direction in is defined as the height direction, the following relationships are satisfied (where the height of the PD 71p is defined as height H1, the height of the memory 211 is defined as height H2, and the height of the DTI 201 is defined as height H3):

[0264] The height H1 of the PD 71p < the height H3 of the DTI 201

[0265] The height H2 of the memory 211 < the height H3 of the DTI 201

[0266] As described above, the pixel 50p has a buried PD 71p and a memory 211. Therefore, charge is read from the PD 71p through the read gate 213 including the vertical transistor trench 214. In addition, the read gate 213 is configured to transfer charge to the memory 211 above the DTI 201.

[0267] Furthermore, in the pixel 50 p , the N+ diffusion layer 222 is formed so that the charge from the PD 71 p does not flow into the memory 211 when the PD 71 p is saturated.

[0268] Since the PD 71p is embedded and surrounded by the DTI 82p, the charges are only transferred upward ( Fig. 20 In addition, an N+ diffusion layer 222 biased to a voltage VDD is formed in the direction where blooming may occur. Therefore, charges overflowing from the PD 71p flow into the N+ diffusion layer 222, and thus blooming does not occur.

[0269] In addition, if Fig.19 As shown, the N+ diffusion layer 222 is connected to the reset transistor 92 , so that the charge flowing into the N+ diffusion layer 222 can be discharged by turning on the reset transistor 92 during the standby period.

[0270] As described above, according to the pixel 50 p , the same effects as those of the pixel 50 a in the first embodiment can be obtained, and further, an effect of suppressing blooming of highlights can be obtained.

[0271] Will refer to Fig.19 The structure of the pixel 50p will be further described. Fig.19 1 is a plan view of the pixel 50 p as viewed from the wiring layer side (the side opposite to the light incident surface). Fig.19 The arrangement in the pixel array section 41 ( Figure 2 ) in the 2×2 four pixels. Focus on one of the four pixels, 50p. Fig.19 In FIG. 5 , the left side of the pixel 50 p is a region where the memory 211 is provided, and the right side is a region where the PD 71 p is provided.

[0272] The reset transistor 92, the amplifying transistor 93, the selecting transistor 94, and the well contact 231 are formed on the PD 71p. In addition, the reading gate 213 is formed to straddle the PD 71p and the memory 211 and to extend on the DTI 201 formed in a non-penetrating manner.

[0273] The write gate 216 and the read gate 220 are formed on the memory 211. Furthermore, as described above, the read gate 220, the amplifier transistor 93, and the N+ diffusion layer 222 are connected by means of the FD wiring 232. The FD wiring 232 is formed to extend over the DTI 201 formed in a non-penetrating manner.

[0274] In addition, the pixel 50p is surrounded by the DTI 82P (DTI 82p-1 and DTI 82p-2) penetrating the Si substrate 70p. That is, the pixel 50p has a completely separated structure in which pixels are completely separated from each other.

[0275] Will refer to Fig. 20 The structure of the back side (light incident side) of the pixel 50p is described. The light shielding film 74 is formed on the back side of the pixel 50p. The light shielding film 74-1 is connected to the filler 86 formed in the DTI 82p-1. For example, since the light shielding film 74-1 can include a metal material such as tungsten (W), the filler 86 can also include a metal material forming the light shielding film 74-1, so the filler 86 and the light shielding film 74-1 can be formed integrally (continuously). In the following description, the filler 86 and the light shielding film 74 are continuously formed using the same material.

[0276] The filler 86 in the DTI 82p-2, the light shielding film 74-2, and the filler in the DTI 201 are also continuously formed using the same material. The light shielding film 74-2 is formed on the light incident surface side of the memory 211. With this configuration, light does not enter the memory 211 from the light incident surface side by virtue of the light shielding film 74-2, and stray light from the adjacent pixel 50p (PD71p) does not enter the memory 211 by virtue of the DTI 82p-2 and the DTI 201.

[0277] As described above, the pixel 50p is configured so that light does not enter the memory 211. On the other hand, the PD 71p is formed with an opening that allows light to enter. The OCL 76 is formed in alignment with the center of the opening (the center of the PD 71p in the horizontal direction).

[0278] Note that when the pixel 50 p is used as a pixel for detecting a phase difference on an image plane (ZAF pixel), half of the opening in the PD 71 p is blocked by the light shielding film 74 , and the height and curvature of the OCL 76 are adjusted so that light is focused on the light shielding film 74 .

[0279] Due to the configuration of the pixel 50 p described above, the same effects as those of the pixel 50 a according to the first embodiment can be obtained, and in addition, an effect of suppressing blooming of highlights can be obtained.

[0280] Here, the case where each pixel 50p includes a transistor such as the selection transistor 94 has been described as an example. Fig.21 As shown, the present technology is applicable to the case where a plurality of pixels 50p share a predetermined transistor. Fig.21 A case where two pixels 50 p arranged in the vertical direction share the reset transistor 92 and the selection transistor 94 will be described.

[0281] Fig.21 The pixel array section 41 ( Figure 2 ) in a 2×2 array. Pixels 50p-1 and 50p-2 arranged in the vertical direction are shared pixels.

[0282] The amplification transistor 93-1, the selection transistor 94, the well contact 231-1 and the N+ diffusion layer 222-1 are formed on the PD 71P-1 of the pixel 50p-1. The read gate 213-1 is formed to extend above the PD 71P-1 and the memory 211-1 on the pixel 50p-1. In addition, the write gate 216-1 and the read gate 220-1 are formed on the memory 211-1 on the pixel 50p-1.

[0283] The amplification transistor 93-2, the reset transistor 92, the well contact 231-2 and the N+ diffusion layer 222-2 are formed on the PD 71P-2 of the pixel 50p-2. The read gate 213-2 is formed in a manner extending above the PD 71P-2 and the memory 211-2 on the pixel 50p-2. In addition, the write gate 216-2 and the read gate 220-2 are formed on the memory 211-2 of the pixel 50p-2.

[0284] The amplifier transistor 93-2 of pixel 50p-2, the N+ diffusion layer 222-2 of pixel 50p-2, the amplifier transistor 93-1 of pixel 50p-1, the N+ diffusion layer 222-1 of pixel 50p-1, the reading gate 220-1 of pixel 50p-1, and the reading gate 220-2 of pixel 50p-2 are connected by means of FD wiring 241.

[0285] As described above, the reset transistor 92 and the select transistor 94 may be shared by two pixels.

[0286] Fig.21 The configuration shown is only an example. Fig.21 In the illustrated configuration, as an example, the amplifying transistor 93 is formed in each of the pixel 50p-1 and the pixel 50p-2. However, for example, the amplifying transistor may be shared. That is, the amplifying transistor 93 may be formed in either the pixel 50p-1 or the pixel 50p-2.

[0287] Furthermore, in a configuration in which one amplifier transistor 93 is formed in either the pixel 50 p - 1 or the pixel 50 p - 2 , the region in which the amplifier transistor 93 is provided can be increased, so that a large amplifier transistor 93 can be formed.

[0288] Furthermore, the positions of the reset transistor 92 and the amplification transistor 93 - 2 may be interchanged.

[0289] In such Fig.21 In the case where two amplifier transistors 93 are formed as shown, or in the case where one large amplifier transistor 93 is formed, random noise can be suppressed.

[0290] In addition, due to Fig.21The structure shown has a plurality of pixels sharing a predetermined transistor, so that the pixel size can be reduced, thereby enabling size reduction of the image pickup device.

[0291] <Manufacturing of 50p pixels>

[0292] Will refer to Fig. 22 The manufacture of the pixel 50p is briefly described.

[0293] In step S101, a Si substrate 70p is prepared and a groove is formed in the Si substrate 70p. Thus, a portion corresponding to the DTI 82p is formed. The formed DTI 82p is doped with P-type impurities by a solid phase diffusion process, thereby forming a P-type solid phase diffusion layer 83.

[0294] Doping (forming the P-type solid-phase diffusion layer 83) can be performed by oblique ion implantation or plasma doping instead of solid-phase diffusion. In addition, a method may be used in which a P-type impurity layer is formed in advance by performing ion implantation multiple times from the surface using a resist mask before forming the DTI 82p.

[0295] For example, refer to Figure 6 The described processing involving solid phase diffusion can be applied to processing such as solid phase diffusion in step S101.

[0296] In step S102, after forming a SiO2 film in the DTI 82p, the DTI 82p is filled with polysilicon 242. Thereafter, a read gate 213 having a vertical transistor trench 214, a write gate 216 having a vertical transistor trench 217, and a read gate 220 having a vertical transistor trench 219 are formed, respectively. Then, the Si substrate 70p is polished from the incident surface side (the lower side in the figure), and the Si substrate 70p is thinned until its thickness becomes, for example, about 4 μm.

[0297] In step S103, the DTI 201 (DTI formed in a non-penetrating manner) is formed by etching the Si substrate 70p from the light incident surface side (the surface opposite to the surface where the transistor is formed in step S102). Thereafter, the polysilicon 242 filling the DTI 82p is removed. Due to the above-mentioned process, both the DTI 82p and the DTI 201 are in a state where no filler is filled.

[0298] The DTI 82p and the DTI 201 are filled with a metal material such as tungsten. In addition, a film (referred to as a metal film) is formed on the light incident surface side of the Si substrate 70p using a metal material. The metal film on the light incident side of the PD 71p is removed by a process such as etching, thereby forming an opening in the PD 71p. Thereafter, the PD 71p, the memory 211, the color filter, the OCL 76, and the like are formed.

[0299] In this way, the DTI 82 p that surrounds the pixel 50 p and penetrates the Si substrate 70 p and the DTI 201 that is formed in a non-penetrating manner between the PD 71 p and the memory 211 are formed at different times.

[0300] Generally, solid phase diffusion treatment is performed at high temperature, and after this treatment is performed at high temperature (step S101), a metal film serving as the light shielding film 74 is formed (step S103). Therefore, the metal film is processed without being exposed to high temperature.

[0301] As described above, in the pixel 50p according to the fourteenth embodiment, the side surfaces of the PD 71p are surrounded by the DTI 82. Therefore, the charge can be prevented from flowing from the PD 71p to the memory 211, so that blooming toward the memory 211 can be suppressed.

[0302] Furthermore, since the N+ diffusion layer 222 is formed above the PD 71p, the N+ diffusion layer 222 can receive charges overflowing from the PD 71p when the PD 71p is saturated. Therefore, even when the PD 71p is saturated, charges can be prevented from flowing from the PD 71p into the memory 211, thereby suppressing blooming toward the memory 211.

[0303] Furthermore, DTI 82p formed on the side of PD 71p and memory 211 has a strong electric field region formed by P-type solid diffusion layer 83p and N-type solid diffusion layer 84p, thereby increasing the capacity of PD 71p and memory 211 and ensuring the saturation signal amount Qs.

[0304] <Fifteenth Embodiment>

[0305] Fig.23 is a vertical cross-sectional view of a pixel 50q according to a fifteenth embodiment to which the present technology is applied.

[0306] The fifteenth embodiment is different from the fourteenth embodiment in that the DTI 82 is formed in the STI 78, and the other configurations are the same as those of the fourteenth embodiment. Therefore, the same parts as those of the fourteenth embodiment are denoted by the same reference numerals, and description thereof will be appropriately omitted.

[0307] exist Fig.23 In the illustrated pixel 50q, the STI 78q formed in the active region 77 is formed to the portion where the DTI 82q is formed (formed to the end of the pixel 50q). Then, the DTI 82q is formed under the STI 78q.

[0308] In other words, the STI 78q is formed at a portion where the DTI 82q is formed, and the STI 78q and the DTI 82q are formed at a position where the STI 78q and the DTI 82q are in contact with each other.

[0309] By forming in this way, it is possible to obtain a pixel 50p in the fourteenth embodiment in a different manner from the case where the STI 78q and the DTI 82q are formed at different positions (for example, the pixel 50p in the fourteenth embodiment). Fig. 20 )) compared, the size of the pixel 50q can be reduced.

[0310] The pixel 50 q according to the fifteenth embodiment can also provide the same effect as the pixel 50 p according to the fourteenth embodiment, that is, provide the effect of preventing the deterioration of dark characteristics and suppressing blooming of highlights.

[0311] <Sixteenth Embodiment>

[0312] Fig.24 is a horizontal plan view of a pixel 50r according to a sixteenth embodiment to which the present technology is applied, Fig.25 It is along Fig.24 A vertical cross-sectional view of the pixel 50 r taken along line AA′ of the pixel 50 r is shown.

[0313] In the fourth and fifteenth embodiments described above, the PD 71 and the memory 211 are both embedded as examples. However, the present technology is also applicable to a pixel 50 in which one of the PD 71 and the memory 211 is embedded and the other is not embedded. Fig.16 In the pixel 50r in the embodiment of FIG. 1 , the PD 71r is of an embedded type, while the memory 211r is of a non-embedded type.

[0314] Fig.25 The memory 211r of the pixel 50r shown is also formed using the surface of the Si substrate 70. With this configuration, charges can be accumulated near the surface of the Si substrate 70r just below the gate, and the capacity of the memory 211r can be increased.

[0315] In pixel 50r, when Fig.25 When the vertical direction in is defined as the height direction, the following relationship is satisfied, wherein the height of the PD 71r is defined as a height H1, the height of the memory 211r is defined as a height H2, and the height of the DTI 201 is defined as a height H3.

[0316] The height H1 of PD 71r < the height H3 of DTI 201 < the height H2 of memory 211r

[0317] As described above, since the memory 211r has a non-embedded structure, a gate without a vertical transistor trench can be used. That is, as Fig.25 shown, the write gate 216r for writing the charge read from PD 71r into the memory 211r is composed of a gate without a vertical transistor trench. In addition, the write gate 216r also serves as a memory gate for reading the charge from the memory 211r.

[0318] In addition, a transfer transistor gate 261 is also formed above the memory 211r. In the plan view, as Fig.25 shown, the transfer transistor gate 261 is formed on the end side of the region where the memory 211r is formed.

[0319] As Fig.24 shown, a reset transistor 92, an amplification transistor 93, a selection transistor 94, and a well contact portion 231 are formed on the PD 71r of the pixel 50r. In addition, a read gate 213 is formed on the DTI 201 and extends across the PD 71r and the memory 211r. The write gate 216r and the transfer transistor gate 261 are formed on the memory 211r.

[0320] As Fig.25 shown, an N+ diffusion layer 222 is formed in the pixel 50r. Therefore, when the PD 71r is saturated, the charge from the PD 71r does not flow into the memory 211r.

[0321] The pixel 50r according to the sixteenth embodiment can also provide the same effects as the pixel 50p according to the fourteenth embodiment, that is, the effects of preventing the deterioration of the dark characteristics and suppressing the high-light overflow.

[0322] <The Seventeenth Embodiment>

[0323] Fig.26 is a horizontal plan view of a pixel 50s according to the seventeenth embodiment to which the present technology is applied, Fig. 27 is a vertical cross-sectional view of the pixel 50s taken along the line A-A' in the pixel 50s as Fig.26 shown.

[0324] The difference between the pixel 50s according to the seventeenth embodiment and the pixel 50p according to the fourteenth embodiment is that a transfer gate 271 is added. Other structures are the same as those of the pixel 50p according to the fourteenth embodiment.

[0325] Refer to Fig. 27The pixel 50s shown has: a read gate 213 for reading charges from PD71s; a transfer gate 271 for transferring the read charges to the memory 211s; a write gate 216 for writing the transferred charges to the memory 211s; and a read gate 220 for reading the charges written to the memory 211s.

[0326] Among these gates, the read gate 213 , the write gate 216 , and the read gate 220 include a vertical transistor trench 214 , a vertical transistor trench 217 , and a vertical transistor trench 219 , respectively.

[0327] return Fig.26 The plan view of the gate arrangement will further illustrate this. Fig.26 As shown, a reset transistor 92, a select transistor 94, and a well contact 231 are formed on the PD 71s of the pixel 50s. In addition, a read gate 213 is formed on the DTI 201s-1 and extends across the PD 71s and the memory 211s.

[0328] In addition, a transmission gate 271 is formed on the Pwell region 77 between the PD 71s and the memory 211s. The transmission gate 271 is formed to extend across the DTI 201s-2. In addition, an N+ diffusion layer 272 ( Fig.26 ).

[0329] The write gate 216, the read gate 220, and the amplifier transistor 93 are formed on the memory 211s.

[0330] refer to Fig.26 and 27 In the illustrated pixel 50 s , a DTI 201 s - 1 and a DTI 201 s - 2 are formed between the PD 71 s and the memory 211 s , and a Pwell region 77 is provided between the DTI 201 s - 1 and the DTI 201 s - 2 .

[0331] Here, the case where two DTIs (i.e., DTI 201s-1 and DTI 201s-2) are formed is described as an example. However, only one of DTI 201s-1 or DTI 201s-2 may be formed. In addition, DTI 201s-1 and DTI 201s-2 may have the same shape, or may have different shapes. For example, one of them may be thicker than the other, or may be higher than the other.

[0332] Notice, Fig.26 and 27The arrangement position, shape, size, etc. of the gate of the pixel 50s shown are examples, and other arrangement positions, shapes, sizes, etc. may be adopted. For example, the transfer gate 271 may be longer than the illustrated transfer gate, and the read gate 213 may be shorter than the illustrated read gate.

[0333] refer to Fig. 27 , DTI 201s-1, DTI 201s-2 and DTI 82s-2 are continuously formed in a manner connected by the light shielding film 74s-2. As described above, in the pixel 50s according to the seventeenth embodiment, the PD 71s is of a buried type and is surrounded by the DTI 82s-1 and DTI 201s-1, so that the charge is only toward the upper side ( Fig. 27 The upper side of the incident surface, that is, the opposite side of the incident surface) overflows.

[0334] In addition, the N+ diffusion layer 222 biased to the voltage VDD is formed in the direction in which blooming may occur. Therefore, the charges overflowing from the PD 71s flow into the N+ diffusion layer 222, and thus, blooming does not occur.

[0335] In addition, two DTIs, DTI 201s-1 and DTI 201s-2, are formed between PD 71s and memory 211s. This can enhance the effect of suppressing smear on memory 211s. In addition, since two DTIs are formed, the possibility of blooming can be reduced compared to the case where only one DTI is formed.

[0336] Furthermore, by providing the transfer gate 271, it is possible to more reliably transfer charges from the PD 71s to the memory 211. In the pixel 50s, the charges read from the PD 71s are temporarily held in the region under the transfer gate 271, or are held in both the region under the transfer gate 271 and the memory 211s. Then, after the read gate 213 is turned off, all the charges are moved from the region under the transfer gate 271 to the memory 211s.

[0337] Since the read gate 213 is off when the charge is transferred to the memory 211s, it is possible to prevent the charge from flowing back to the PD 71s. Therefore, according to the pixel 50s, the charge can be transferred from the PD 71s to the memory 211 more reliably.

[0338] The pixel 50s according to the seventeenth embodiment can also provide the same effect as the pixel 50p according to the fourteenth embodiment, that is, the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50s in the seventeenth embodiment, the charge can be transferred from the PD 71s to the memory 211 more reliably.

[0339] <Eighteenth Embodiment>

[0340] Fig.28 is a horizontal plan view of pixel 50t according to the eighteenth embodiment to which the present technology is applied. Fig.29 is along Fig.28 a vertical cross-sectional view of pixel 50t taken along line A-A' in pixel 50t shown in

[0341] Pixel 50t of the eighteenth embodiment has a structure obtained by combining the structure of pixel 50r according to the sixteenth embodiment and the structure of pixel 50s according to the seventeenth embodiment. That is, pixel 50t in the eighteenth embodiment has the following structure: wherein, like pixel 50r in the sixteenth embodiment, memory 211t is non-embedded, and like pixel 50s in the seventeenth embodiment, it has transfer gate 271.

[0342] Memory 211t of pixel 50t is also formed using the surface of Si substrate 70. With such a structure, charges can accumulate near the surface of Si substrate 70t directly under the gate, and the capacity of memory 211t can be increased.

[0343] In pixel 50t, when the Fig.29 vertical direction in is defined as the height direction, the following relationship is satisfied, wherein the height of PD 71t is defined as height H1, the height of memory 211t is defined as height H2, and the height of DTI 201 is defined as height H3.

[0344] Height H1 of PD 71t < Height H3 of DTI 201 < Height H2 of memory 211t.

[0345] As described above, since memory 211t has a non-embedded structure, a gate without a vertical transistor trench can be used. That is, as Fig.29 shown, transfer gate 271 and storage gate 281 for transferring the charges read from PD 71t to memory 211t are formed by a gate without a vertical transistor trench. Storage gate 281 is a gate for writing and reading charges from memory 211t.

[0346] Since transfer gate 271 is provided, the charges read from PD 71t are temporarily held in the region under transfer gate 271, or are held both in the region under transfer gate 271 and in memory 211t. Then, after read gate 213 is turned off, all the charges move from the region under transfer gate 271 to memory 211t. Therefore, charges can be more reliably transferred from PD 71t to memory 211t.

[0347] As Fig.28As shown, a reset transistor 92, an amplifying transistor 93, a selecting transistor 94, and a well contact 231 are formed on the PD 71t of the pixel 50t. In addition, a reading gate 213 is formed on the DTI 201t-1 and extends across the PD 71t and the memory 211t.

[0348] In addition, a transfer gate 271 is formed on the Pwell region 77 between the PD 71t and the memory 211t. The transfer gate 271 is formed to extend across the DTI 201t-2. In addition, an N+ diffusion layer 272 is also formed in the Pwell region 77 between the PD 71t and the memory 211t. A storage gate 281 and a transfer transistor gate 261 are formed on the memory 211t.

[0349] like Fig.29 As shown, an N+ diffusion layer 222 is formed in the pixel 50t. Therefore, when the PD 71t is saturated, the charge from the PD 71t does not flow into the memory 211t.

[0350] The pixel 50t according to the eighteenth embodiment can also provide the same effect as the pixel 50p according to the fourteenth embodiment, that is, the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50t in the eighteenth embodiment, it is possible to more reliably transfer charge from the PD 71t to the memory 211t.

[0351] <Nineteenth Embodiment>

[0352] Fig.30 is a horizontal plan view of a pixel 50u according to a nineteenth embodiment to which the present technology is applied, Fig.31 It is along Fig.30 A vertical cross-sectional view of the pixel 50u taken along the line AA′ in the pixel 50u shown in FIG. Fig.32 It is along Fig.30 A vertical cross-sectional view of the pixel 50u taken along line BB′ in the pixel 50u is shown.

[0353] In the above-described fourteenth to eighteenth embodiments, the PD 71 is of an embedded type as an example. However, the present technology is also applicable to a pixel 50 in which the PD 71 is not of an embedded type. Figure 30 to Figure 32 In the pixel 50u shown, the PD 71u is not formed in an embedded manner, but the memory 211r is formed in an embedded manner.

[0354] Fig.31 The PD 71u of the pixel 50u shown is also formed using the surface of the Si substrate 70. With this configuration, the electric field can be ensured, and the saturation signal amount Qs can be increased.

[0355] In pixel 50u, when Fig.31 When the vertical direction in Fig.31 is defined as the height direction, the following relationships are satisfied. Herein, the height of PD 71u is defined as height H1, the height of memory 211u is defined as height H2, and the height of DTI 201 is defined as height H3.

[0356] The height H2 of memory 211u < the height H3 of DTI 201 < the height H1 of PD 71u.

[0357] As described above, since PD 71u has a non-embedded structure, a gate without a vertical transistor trench can be used. That is, as Fig.31 shown, the read gate 291 for reading charge from PD 71u is composed of a gate without a vertical transistor trench.

[0358] Since memory 211u is an embedded type, the write gate 216 has a vertical transistor trench 217, and the read gate 220 has a vertical transistor trench 219.

[0359] In pixel 50u, the N+ diffusion layer 293 is formed such that when PD 71u is saturated, the charge from PD 71u does not flow into memory 211u. As Fig.32 shown, the N+ diffusion layer 293 is formed near the amplification gate 292 and between DTI 201 and the amplification gate 292. In this case, the N+ diffusion layer 293 is formed at the drain of the amplification transistor 93.

[0360] In addition, as Fig.30 shown in the plan view, the N+ diffusion layer 222u is also formed at the drain of the reset transistor 92. The N+ diffusion layer 293 and the N+ diffusion layer 222u are biased to the voltage VDD.

[0361] In pixel 50u, when PD 71u is saturated, the charge flows into the N+ diffusion layer 293 and the N+ diffusion layer 222u. In addition, PD71u is surrounded by DTI 82u-1 and DTI 201. Therefore, the occurrence of high-light overflow can be prevented.

[0362] As Fig.30 shown, in the plan view of pixel 50u, the read gate 291 is formed on DTI 201 and extends across PD 71u and memory 211u. In addition, the reset transistor 92, the amplification transistor 93, the selection transistor 94, and the well contact portion 231 are formed on memory 211u. In addition, as described above, the N+ diffusion layer 222u is formed at the drain of the reset transistor 92, and the N+ diffusion layer 293 is formed at the drain of the amplification transistor 93.

[0363] As described above, since the N+ diffusion layer 222u and the N+ diffusion layer 293 are formed, when the PD 71u is saturated, charges do not flow from the PD 71u in the pixel 50u into the memory 211u.

[0364] can be achieved by connecting to the above-mentioned pixel 50 (for example, pixel 50p ( Fig. 20 )) is manufactured by the same manufacturing process as the manufacturing process of the pixel 50u (for example, reference Fig. 22 During the manufacturing process, the N+ diffusion layer 293 (N+ diffusion layer 222u) of the pixel 50u is formed at a position as described below.

[0365] In the case of pixel 50u, no STI is formed between N+ diffusion layer 293 (N+ diffusion layer 222u) and PD 71u. Therefore, N+ diffusion layer 293 (N+ diffusion layer 222u) and PD 71u need to be spaced apart from each other to prevent the potential barrier in this portion from being lowered.

[0366] On the other hand, if the distance between the N+ diffusion layer 293 (N+ diffusion layer 222u) and the PD 71u is too large, the potential barrier becomes too high and may not function as a destination of blooming. The distance between the N+ diffusion layer 293 (N+ diffusion layer 222u) and the PD 71u is set in consideration of these factors. As an example, the distance between the N+ diffusion layer 293 (N+ diffusion layer 222u) and the PD 71u can be set to about 0.2 μm to 1 μm.

[0367] The pixel 50 u according to the nineteenth embodiment can also provide the same effects as the pixel 50 p according to the fourteenth embodiment, that is, provide the effects of preventing deterioration of dark characteristics and suppressing blooming of highlights.

[0368] Note that, although not shown, the nineteenth embodiment can be combined with the fourteenth to eighteenth embodiments.

[0369] For example, it is also possible to combine the fifteenth embodiment ( Fig.23 ) and the nineteenth embodiment form a DTI 82 in the STI 78. In addition, the seventeenth embodiment ( Fig. 27 ) and the nineteenth embodiment in which the read gate 291 ( Fig.31 ) and the write gate 216 to form a gate corresponding to the transfer gate 271.

[0370] <Twentieth Embodiment>

[0371] Fig.33 is a horizontal plan view of a pixel 50v according to a twentieth embodiment to which the present technology is applied, Fig.34 It is shown Fig.33FIG. 5 is a diagram showing the positional relationship between the PD 71v and the memory 211v in the pixel 50v. Fig.35 It is along Fig.33 A vertical cross-sectional view of the pixel 50 v taken along line AA′ in the pixel 50 v is shown.

[0372] The twentieth embodiment can be applied to any of the above-described fourteenth to nineteenth embodiments. That is, the twentieth embodiment described below can be applied to the case where both the PD 71 and the memory 211 are embedded and the case where either the PD 71 or the memory 211 is embedded.

[0373] Here, the description will be continued by taking the case where the PD 71 is of an embedded type and the memory 211 is of a non-embedded type as an example.

[0374] The basic configuration of the pixel 50v according to the twentieth embodiment is similar to that of the pixel 50t according to the eighteenth embodiment. Fig.28 and 29 ) are the same as the basic structure of the pixel 50t according to the eighteenth embodiment, so the detailed description thereof will be omitted. Like the pixel 50t according to the eighteenth embodiment, the pixel 50v according to the twentieth embodiment includes a transfer gate 271v, but the transfer gate 271v of the pixel 50v is longer than the transfer gate 271 of the pixel 50t.

[0375] refer to Fig.33 , along the side where the DTI 82v-2 is formed, a transmission gate 271v is formed in a portion other than a portion where the read gate 213 and the storage gate 281 are formed. As described above, since the transmission gate 271v is long, the PD 71v and the memory 211v can be arranged at positions away from each other. This will refer to Fig.34 Provide explanation.

[0376] Fig.34 2 is a horizontal plan view of a pixel 50v showing the positions of a PD 71v and a memory 211v. In the upper right of the pixel 50v in the figure, a PD 71v is formed in a rectangular shape. Fig.33 Referring together, the PD 71 v is formed in a region in which the reset transistor 92 , the amplification transistor 93 , the selection transistor 94 , and the well contact 231 are formed.

[0377] In the lower part of the pixel 50v in the figure, the memory 211v is formed in a rectangular shape. Fig.33 Referring together, the memory 211v is formed right below the storage gate 281v.

[0378] The PD 71v is surrounded by a DTI 82v penetrating the Si substrate 70 except for a portion forming the DTI 201. The portion surrounded by the DTI 82v has a structure capable of preventing light from leaking from the PD 71v to the memory 211v.

[0379] The DTI 201 does not penetrate the Si substrate 70. There is a possibility that light leaks from the PD 71v to the memory 211v through the portion where the DTI 201 is formed (in other words, the Pwell region 77 where the DTI 201 does not penetrate). However, the distance from the PD 71v to the memory 211v via the DTI 201v and the Pwell region 77 just below the transmission gate 271v is long, and the memory 211v is not formed near the DTI 201v. Therefore, it is possible to prevent light from leaking from the PD 71v to the memory 211v.

[0380] That is, since the PD 71v and the memory 211v are positioned away from each other, the pixel 50v according to the twentieth embodiment can suppress more stray light components than the above-described embodiments.

[0381] Taking reference as the vertical cross-section of pixel 50v Fig.35 Here, as an example, the memory 211v is non-embedded. Fig.35 As shown, the memory 211v is formed using the surface of the Si substrate 70. With this configuration, charges can be accumulated near the surface of the Si substrate 70v just below the gate, and the capacity of the memory 211v can be increased.

[0382] In addition, Fig.29 As with the pixel 50t shown in FIG. 1 , the transfer gate 271 and the storage gate 281 that transfer the charge read from the PD 71v to the memory 211v are composed of gates without vertical transistor trenches. Since the transfer gate 271v is provided, the charge read from the PD 71v is once held in the area below the transfer gate 271v, or is held in the area below the transfer gate 271v and in the memory 211v. Then, after the read gate 213 is turned off, all the charge is moved from the area below the transfer gate 271v to the memory 211v. Therefore, the charge can be more reliably transferred from the PD 71v to the memory 211v.

[0383] exist Figures 33 to 35 In the pixel 50v shown, as an example, only one DTI 201v is formed. However, for example, Fig.28 and 29The two DTIs corresponding to the DTI 201 t - 1 and DTI 201 t - 2 shown are DTI 201 v - 1 and DTI 201 v - 2 .

[0384] The pixel 50v according to the twentieth embodiment also has the N+ diffusion layer 222. Therefore, when the PD 71v is saturated, the charge from the PD 71v does not flow into the memory 211v.

[0385] The pixel 50v according to the twentieth embodiment can also provide the same effect as the pixel 50a according to the fourteenth embodiment, that is, the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50v in the twentieth embodiment, the charge can be more reliably transferred from the PD 71v to the memory 211v. In addition, according to the pixel 50v in the twentieth embodiment, the stray light component can be further suppressed.

[0386] <Example 20-2>

[0387] Will refer to Figure 33 to Figure 35 The embodiment described is referred to as Embodiment 20-1. In the pixel 50v according to Embodiment 20-1, since the PD 71v and the memory 211v are located away from each other, the transfer gate 271v is formed long. When the transfer gate 271v is formed long, the transfer efficiency may be reduced.

[0388] In order to improve the efficiency of charge transfer from PD 71v to memory 211v, as Fig.36 and 37 As shown, multiple transmission gates can be set. Fig.36 and 37 The pixel 50 v ′ shown is referred to as Embodiment 20-2, and in order to distinguish from the components in the pixel 50 v , components different from those of the pixel 50 v according to Embodiment 20-1 are indicated by one dot.

[0389] Fig.36 is a horizontal plan view of a pixel 50v' according to Example 20-2 to which the present technology is applied, Fig.37 It is along Fig.36 A vertical cross-sectional view of the pixel 50v' is shown taken along line AA' in the pixel 50v'.

[0390] Pixel 50v' with Fig.33 The pixel 50v shown is different in that the transfer gate 271v' has a two-stage structure including a transfer gate 271v'-1 and a transfer gate 271v'-2. The other configurations are the same as those of the pixel 50v.

[0391] Since the transfer gate 271 v ′ has the multi-stage structure as described above, even if the distance for transferring charges from the PD 71 v to the memory 211 v is long, it is possible to prevent the transfer efficiency from being reduced.

[0392] Note that although the case where the transfer gate 271 v ′ has two stages has been described as an example, the transfer gate 271 v ′ may have three stages or more.

[0393] exist Fig.36 and 37 In the illustrated pixel 50v', only one DTI 201v' is formed as an example. However, two or more non-penetrating DTIs can also be formed.

[0394] The pixel 50v' according to Embodiment 20-2 further has the N+ diffusion layer 222. Therefore, when the PD 71v is saturated, the charge from the PD 71v does not flow into the memory 211v.

[0395] The pixel 50v' according to the embodiment 20-2 can also provide the effect of preventing the dark characteristic from deteriorating and suppressing the highlight overflow. In addition, according to the pixel 50v' in the embodiment 20-2, the charge can be more reliably transferred from the PD 71v to the memory 211v. In addition, according to the pixel 50v' in the embodiment 20-2, the stray light component can be further suppressed.

[0396] <Example 20-3>

[0397] Still another configuration of the pixel 50v will be described. Fig.38 is a horizontal plan view of a pixel 50v" according to Example 20-3 to which the present technology is applied, Fig.39 It is along Fig.38 A vertical cross-sectional view of the pixel 50 v ″ taken along line BB′ in the pixel 50 v ″ is shown. Fig.35 The cross-sectional view of is used as a vertical cross-sectional view of the pixel 50v" taken along the line AA' of the pixel 50v".

[0398] The basic structure of the pixel 50v" according to the embodiment 20-3 is the same as the basic structure of the pixel 50v according to the embodiment 20-1. Therefore, the same parts are represented by the same figure marks, and their descriptions will be omitted. The difference between the pixel 50v" according to the embodiment 20-3 and the pixel 50v according to the embodiment 20-1 is that the drain discharge portion 273 is added. The other structures are the same as the structure of the pixel 50v.

[0399] The drain drain 273 is formed in a region between a region where the transfer gate 271v" is formed and the DTI 82v-4. Fig.39In the cross-sectional view shown in FIG. 1 , the drain discharge portion 273 has a cross-sectional view with the N+ diffusion layer 222 ( Fig.35 ) and is a region with a high N-type impurity concentration. STI 78 is formed on each side of the drain drain portion 273. In addition, the drain drain portion 273 is connected to an N+ layer 274 formed in the Si substrate 70.

[0400] The N+ layer 274 is formed so as not to be in contact with the transfer gate 271 v ″. In other words, the N+ layer 274 is formed to avoid the region on the surface side of the Si substrate 70 where the transfer gate 271 v ″ is formed.

[0401] In addition, the drain drain portion 273 is biased to the voltage VDD. By applying the voltage VDD to the drain drain portion 273 , the charges accumulated in the N+ layer 274 are discharged from the drain drain portion 273 .

[0402] As described above, since the drain discharge portion 273 is formed, even if light entering the PD 71v" leaks toward the side where the transfer gate 271v" is formed through the non-penetrating portion of the DTI 201v, the light is photoelectrically converted in the N+ layer 274, and the photoelectrically converted charges can be discharged from the drain discharge portion 273. Therefore, the stray light component can be suppressed.

[0403] Fig.38 The pixel 50v" shown is obtained by Fig.33 ) is formed by adding a drain discharge portion 273. However, it is also possible to use the pixel 50v' ( Fig.36 ) a drain discharge portion 273 is added. That is, a structure in which a drain discharge portion 273 is added and a multi-stage transfer gate 271v" is formed may be adopted.

[0404] Furthermore, although as an example, in Fig.38 Only one DTI 201v is formed in the pixel 50v" shown, but two or more non-penetrating DTIs may also be formed.

[0405] The pixel 50 v ″ according to Embodiment 20-3 also has the N+ diffusion layer 222. Therefore, when the PD 71 v is saturated, the charge from the PD 71 v does not flow into the memory 211 v.

[0406] According to the pixel 50v" in embodiment 20-3, it is also possible to provide the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50v" in embodiment 20-3, electric charge can be more reliably transferred from the PD 71v to the memory 211v. In addition, according to the pixel 50v" in embodiment 20-3, stray light components can be further suppressed.

[0407] <Twenty-first embodiment>

[0408] Fig.40 2 is a horizontal plan view of a pixel 50w according to the twenty-first embodiment to which the present technology is applied, when viewed from the wiring layer side. Fig.35 The cross-sectional view along Fig.40 A vertical cross-sectional view of the pixel 50w taken along line AA' of the pixel 50w is shown. Fig.41 When viewed from the light incident side Fig.40 Horizontal plan view of pixel 50w shown.

[0409] The twenty-first embodiment can also be applied to any of the above-described fourteenth to nineteenth embodiments. That is, the twenty-first embodiment described below can be applied to the case where both the PD 71 and the memory 211 are embedded and the case where either the PD 71 or the memory 211 is embedded.

[0410] Here, the description will be continued by taking the case where the PD 71 is an embedded type and the memory 211 is a non-embedded type as an example.

[0411] The basic configuration of the pixel 50w according to the twenty-first embodiment is similar to that of the pixel 50v according to the twentieth embodiment. Fig.33 ) are the same as the basic structure of the pixel 50 according to the 21st embodiment, and therefore, a detailed description thereof will be omitted. Like the pixel 50v according to the 20th embodiment, the pixel 50w according to the 21st embodiment includes a transfer gate 271w, but the transfer gate 271w of the pixel 50w is longer than the transfer gate 271v of the pixel 50v. In addition, the reading gate 213w of the pixel 50w is formed longer than the reading gate 213v of the pixel 50v.

[0412] refer to Fig.40 , the transmission gate 271w is formed along the side where the DTI 82w-2 is formed, and one end of the transmission gate 271w is bent and extended toward the storage gate 281w. The transmission gate 271w is formed in an L shape. The read gate 213w is also formed in an L shape. The read gate 213w is formed along the side where the DTI 82w-5 is formed, and one end of the read gate 213w is bent and extended toward the PD71w.

[0413] refer to Fig.41 , a light shielding film 275 is formed on the light incident surface side of the pixel 50w. The light shielding film 275 is formed in a region of the pixel 50w except for a region where the PD 71w is formed. In other words, the light shielding film 275 is formed in a region where the memory 211w and the transfer gate 271w are formed. The light shielding film 275 is formed on the memory 211w so that incident light does not enter the memory 211w.

[0414] like Fig.41As shown, the PD 71w is formed in a region of the upper right portion of the pixel 50w where the light shielding film 275 is not formed. The memory 211w is formed in a rectangular shape at the lower portion of the pixel 50w in the figure.

[0415] Although not shown, in the pixel 50 of other embodiments, the portion other than the PD 71 is also covered with the light shielding film 275 so that the stray light component does not enter the memory or the like.

[0416] The PD 71w is surrounded by the DTI 82w penetrating the Si substrate 70 except for the portion where the DTI 201w is formed. The portion surrounded by the DTI 82w has a structure capable of preventing light from leaking from the PD 71w to the memory 211w.

[0417] The DTI 201w does not penetrate the Si substrate 70. Light entering the PD 71w may leak to an area outside the PD 71w through the portion where the DTI 201w is formed. However, the distance from the PD 71w to the memory 211w via the DTI 201w and the Pwell region 77 just below the transmission gate 271w is long, and the memory 211w is not formed near the DTI 201w. Therefore, it is possible to prevent light from leaking from the PD 71w to the memory 211w.

[0418] DTI 201w is formed in a position parallel to the long side of memory 211w. Since DTI 201w is formed in such a position, even if light obliquely enters PD 71w and leaks through the non-penetrating portion of DTI 201w, such light reaches the DTI 82w-5 side and is unlikely to reach memory 211w.

[0419] Since the PD 71w and the memory 211w are positioned away from each other, the pixel 50w according to the twenty-first embodiment can suppress stray light components.

[0420] exist Fig.40 In the pixel 50w shown, as an example, only one DTI 201w is formed. However, for example, Fig.28 and 29 The two DTIs corresponding to the DTI 201 t - 1 and DTI 201 t - 2 shown are DTI 201 w - 1 and DTI 201 w - 2 .

[0421] The pixel 50w according to the twenty-first embodiment further has the N+ diffusion layer 222. Therefore, when the PD 71w is saturated, the charge from the PD 71w does not flow into the memory 211w.

[0422] The pixel 50w according to the twenty-first embodiment can also provide the same effect as the pixel 50p according to the fourteenth embodiment, that is, the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50w in the twenty-first embodiment, the charge can be more reliably transferred from the PD 71w to the memory 211w. In addition, according to the pixel 50w in the twenty-first embodiment, the stray light component can be further suppressed.

[0423] <Example 21-2>

[0424] Will refer to Fig.40 The embodiment described is referred to as Embodiment 21-1. In the pixel 50w according to Embodiment 21-1, since the PD 71w and the memory 211w are positioned away from each other, the transfer gate 271w is formed longer. When the transfer gate 271w is formed longer, the transfer efficiency may be reduced.

[0425] In order to improve the efficiency of transferring charge from PD 71w to memory 211w, the following can be set: Fig.42 The multi-stage transmission gate shown. Fig.42 The pixel 50 w ′ shown is referred to as Embodiment 21-2, and components different from those of the pixel 50 w according to Embodiment 21-1 are indicated by one dot in order to distinguish from components in the pixel 50 w .

[0426] Fig.42 is a horizontal plan view of a pixel 50w' according to Example 21-2 to which the present technology is applied. Fig.37 The cross-sectional view along Fig.42 A vertical cross-sectional view of the pixel 50w' taken along line AA' of the pixel 50w' is shown.

[0427] Pixel 50w' and Fig.40 The pixel 50w shown is different in that the transfer gate 271w' has a two-stage structure including a transfer gate 271w'-1 and a transfer gate 271w'-2. The other configurations are the same as those of the pixel 50w.

[0428] Since the transfer gate 271w' has the multi-stage structure as described above, even if the distance for transferring charges from the PD 71w to the memory 211w is long, it is possible to prevent the transfer efficiency from being reduced.

[0429] It should be noted that although the case where the transmission gate 271 w ′ has two stages has been described as an example, the transmission gate 271 w ′ may have three or more stages.

[0430] exist Fig.42In the illustrated pixel 50w', only one DTI 201w' is formed as an example. However, two or more non-penetrating DTIs may also be formed.

[0431] The pixel 50w' according to Embodiment 21-2 further has the N+ diffusion layer 222. Therefore, when the PD 71w is saturated, the charge from the PD 71w does not flow into the memory 211w.

[0432] The pixel 50w' according to the embodiment 21-2 can also provide the effect of preventing the dark characteristic from deteriorating and suppressing the highlight overflow. In addition, according to the pixel 50w' in the embodiment 21-2, the charge can be more reliably transferred from the PD 71w to the memory 211w. In addition, according to the pixel 50w' in the embodiment 21-2, the stray light component can be further suppressed.

[0433] <Example 21-3>

[0434] Still another configuration of the pixel 50w will be described. Fig.43 2 is a horizontal plan view of a pixel 50w" according to Example 21-3 to which the present technology is applied. Fig.35 The cross-sectional view is a vertical cross-sectional view of the pixel 50w" taken along the line AA' of the pixel 50w". Fig.39 The cross-sectional view along Fig.43 A vertical cross-sectional view of the pixel 50 w ″ taken along line BB′ of the pixel 50 w ″ is shown.

[0435] The basic structure of the pixel 50w" according to Example 21-3 is the same as the basic structure of the pixel 50w according to Example 21-1. Therefore, the same parts are represented by the same figure marks, and their descriptions will be omitted. The difference between the pixel 50w" according to Example 21-3 and the pixel 50w according to Example 21-1 is that the drain discharge portion 273w is added. The other structures are the same as the other structures of the pixel 50w.

[0436] The drain drain portion 273w is formed in a region between a region where the transfer gate 271w" is formed and the DTI 82w-4. Fig.39 As in the pixel 50v" of the embodiment 20-3, the drain discharge portion 273w has a connection with the N+ diffusion layer 222 ( Fig.35 ) and is a region with a high N-type impurity concentration. STI 78 is formed on each side of the drain discharge portion 273. In addition, the drain discharge portion 273 is connected to an N+ layer 274 formed in the Si substrate 70.

[0437] The N+ layer 274 is formed so as not to be in contact with the transfer gate 271 w ″. In other words, the N+ layer 274 is formed to avoid the region on the surface side of the Si substrate 70 where the transfer gate 271 w ″ is formed.

[0438] In addition, the drain drain portion 273w is biased to the voltage VDD. By applying the voltage VDD to the drain drain portion 273w, the charges accumulated in the N+ layer 274 are discharged from the drain drain portion 273w.

[0439] As described above, since the drain discharge portion 273w is formed, even if the light entering the PD 71w" leaks toward the side where the transfer gate 271w" is formed through the non-penetrating portion of the DTI 201w, the light is photoelectrically converted in the N+ layer 274, and the photoelectrically converted charge can be released from the drain discharge portion 273. Therefore, the stray light component can be suppressed.

[0440] Fig.43 The pixel 50w" shown is obtained by using the pixel 50w ( Fig.40 ) is formed by adding a drain discharge portion 273w. However, it is also possible to use the pixel 50w' ( Fig.42 ) a drain discharge portion 273w is added. That is, a structure in which a drain discharge portion 273w is added and a multi-stage transfer gate 271w" is formed may be adopted.

[0441] Furthermore, although as an example, in Fig.43 Only one DTI 201w is formed in the pixel 50w″ shown, but two or more non-penetrating DTIs may also be formed.

[0442] The pixel 50w″ according to Embodiment 21-3 also has the N+ diffusion layer 222. Therefore, when the PD 71w is saturated, the charge from the PD 71w does not flow into the memory 211w.

[0443] According to the pixel 50w″ in embodiment 21-3, it is also possible to provide the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50w″ in embodiment 21-3, the charge can be more reliably transferred from the PD 71w to the memory 211w. In addition, according to the pixel 50w″ in embodiment 21-3, the stray light component can be further suppressed.

[0444] <Twenty-second embodiment>

[0445] Fig.44 2 is a horizontal plan view of a pixel 50x according to a twenty-second embodiment to which the present technology is applied, when viewed from the wiring layer side. Fig.35 The cross-sectional view along Fig.44A vertical cross-sectional view of the pixel 50x taken along line AA' of the pixel 50x is shown.

[0446] The 22nd embodiment can also be applied to any of the above-described 14th to 19th embodiments. That is, the 22nd embodiment described below can be applied to the case where both the PD 71 and the memory 211 are embedded and the case where either the PD 71 or the memory 211 is embedded.

[0447] Here, the description will be continued by taking the case where the PD 71 is an embedded type and the memory 211 is a non-embedded type as an example.

[0448] The basic configuration of the pixel 50x according to the twenty-second embodiment is similar to that of the pixel 50w according to the twenty-first embodiment. Fig.40 ) are the same in basic configuration, and therefore, detailed description thereof will be omitted. Like the pixel 50w according to the twenty-first embodiment, the pixel 50x according to the twenty-second embodiment includes a transfer gate 271x, but the transfer gate 271x of the pixel 50x is longer than the transfer gate 271w of the pixel 50w.

[0449] In addition, the light receiving surface of the PD 71x of the pixel 50x in the twenty-second embodiment is larger than the light receiving surface of the PD 71w of the pixel 50w in the twenty-first embodiment. Since the PD 71x is formed larger, the transfer gate 271x formed along one side of the PD 71x is also formed longer. Since the light receiving surface of the PD 71x of the pixel 50x in the twenty-second embodiment is larger than the light receiving surface of the PD 71w of the pixel 50w in the twenty-first embodiment, the sensitivity of the PD 71x is higher than that of the PD 71w.

[0450] refer to Fig.44 The transfer gate 271x is formed along the side where the DTI 82x-2 is formed. The read gate 213x is formed in an L shape. Specifically, the read gate 213x extends along the side where the DTI 82x-6 is formed, and one end of the read gate 213x is bent and extends toward the PD 71x.

[0451] Fig.45 2 is a diagram showing a vertical arrangement of pixels 50x. When the pixel 50x-1 and the pixel 50x-2 as the pixel 50x are arranged vertically, the pixel 50x-1 and the pixel 50x-2 are arranged symmetrically in the horizontal direction. For example, the transfer gate 271x-1 of the pixel 50x-1 is arranged on the left side of the figure, and the transfer gate 271x-2 of the pixel 50x-2 is arranged on the right side of the figure.

[0452] The storage gate 281x-1 (memory 211x-1) of the pixel 50x-1, the transfer gate 261x-1 of the pixel 50x-1, and the reading gate 213x-2 of the pixel 50x-2 are arranged in a linear manner between the PD 71x-1 of the pixel 50x-1 and the PD 71x-2 of the pixel 50x-2.

[0453] Reference again Fig.44 , except for the portion where the DTI 201x is formed, the PD 71x is surrounded by the DTI 82x penetrating the Si substrate 70. The portion surrounded by the DTI 82x has a structure capable of preventing light from leaking from the PD 71x to the memory 211x.

[0454] The DTI 201x does not penetrate the Si substrate 70. Light entering the PD 71x may leak to an area outside the PD 71x through the portion where the DTI 201x is formed. However, the distance from the PD 71x to the memory 211x via the DTI 201x and the Pwell region 77 just below the transmission gate 271x is long, and the memory 211x is not formed near the DTI 201x. Therefore, it is possible to prevent light from leaking from the PD 71x to the memory 211x.

[0455] DTI 201x is formed in a position parallel to the long side of memory 211x. Since DTI 201x is formed in such a position, even if light obliquely enters PD 71x and leaks through the non-penetrating portion of DTI 201x, such light travels toward the DTI 82x-6 side and is unlikely to reach memory 211x.

[0456] Since the PD 71x and the memory 211x are positioned away from each other, the pixel 50x according to the twenty-second embodiment can suppress stray light components.

[0457] In the pixel 50x according to the twenty-second embodiment, compared with the pixel 50w according to the twenty-first embodiment ( Fig.40 ), the PD 71x and the memory 211x are further apart. Therefore, the pixel 50x according to the twenty-second embodiment is more capable of suppressing stray light components than the pixel 50w according to the twenty-first embodiment. In addition, the light receiving surface of the PD 71x of the pixel 50x according to the twenty-second embodiment is larger than the light receiving surface of the PD 71w of the pixel 50w according to the twenty-first embodiment. Therefore, the pixel 50x according to the twenty-second embodiment is capable of further improving sensitivity compared to the pixel 50w according to the twenty-first embodiment.

[0458] exist Fig.44In the pixel 50x shown, as an example, only one DTI 201x is formed. However, for example, Fig.28 and 29 The two DTIs corresponding to the DTI 201 t - 1 and DTI 201 t - 2 shown are DTI 201 x - 1 and DTI 201 x - 2 .

[0459] The pixel 50x according to the twenty-second embodiment further has the N+ diffusion layer 222. Therefore, when the PD 71x is saturated, the charge from the PD 71x does not flow into the memory 211x.

[0460] The pixel 50x according to the twenty-second embodiment can also provide the same effect as the pixel 50p according to the fourteenth embodiment, that is, the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50x in the twenty-second embodiment, the charge can be more reliably transferred from the PD 71x to the memory 211x. In addition, according to the pixel 50x in the twenty-second embodiment, the stray light component can be further suppressed.

[0461] <Example 22-2>

[0462] Will refer to Fig.44 The embodiment described is referred to as Embodiment 22-1. In the pixel 50x according to Embodiment 22-1, since the PD 71x and the memory 211x are positioned away from each other, the transfer gate 271x is formed long. When the transfer gate 271x is formed long, the transfer efficiency may be reduced.

[0463] In order to improve the efficiency of transferring charge from PD 71x to memory 211x, the following can be set: Fig.46 The multi-stage transmission gate shown. Fig.46 The pixel 50x' shown is referred to as Embodiment 22-2, and in order to distinguish from the components in the pixel 50x, components different from those of the pixel 50x according to Embodiment 22-1 are indicated by one dot.

[0464] Fig.46 is a horizontal plan view of a pixel 50x' according to Example 22-2 to which the present technology is applied. Fig.37 The cross-sectional view along Fig.46 A vertical cross-sectional view of the pixel 50x' is shown taken along line AA' of the pixel 50x'.

[0465] Pixel 50x' and Fig.44 The pixel 50x shown is different in that the transfer gate 271x' has a two-stage structure including a transfer gate 271x'-1 and a transfer gate 271x'-2. The other configurations are the same as those of the pixel 50x.

[0466] Since the transfer gate 271x' has the multi-stage structure as described above, even if the distance for transferring charges from the PD 71x to the memory 211x is long, it is possible to prevent the transfer efficiency from being reduced.

[0467] It should be noted that although the case where the transfer gate 271 x ′ has two stages has been described as an example, the transfer gate 271 x ′ may have three or more stages.

[0468] exist Fig.46 In the illustrated pixel 50x', only one DTI 201x' is formed as an example. However, two or more non-penetrating DTIs may also be formed.

[0469] The pixel 50x' according to Embodiment 22-2 further has the N+ diffusion layer 222. Therefore, when the PD 71x is saturated, the charge from the PD 71x does not flow into the memory 211x.

[0470] According to the pixel 50x' of Example 22-2, it is also possible to provide the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50x' in Example 22-2, the charge can be more reliably transferred from the PD 71x to the memory 211x. In addition, according to the pixel 50x' in Example 22-2, the stray light component can be further suppressed.

[0471] <Example 22-3>

[0472] Still another configuration of the pixel 50x will be described. Fig.47 2 is a horizontal plan view of a pixel 50x" according to Example 22-3 to which the present technology is applied. Fig.35 The cross-sectional view is a vertical cross-sectional view of the pixel 50x" taken along the line AA' of the pixel 50x". Fig.39 The cross-sectional view along Fig.47 A vertical cross-sectional view of the pixel 50x" taken along line BB' of the pixel 50x" is shown.

[0473] The basic structure of the pixel 50x" according to Example 22-3 is the same as the basic structure of the pixel 50x according to Example 22-1. Therefore, the same parts are represented by the same figure marks, and their descriptions will be omitted. The difference between the pixel 50x" according to Example 22-3 and the pixel 50x according to Example 22-1 is that the drain discharge portion 273x is added. The other structures are the same as the other structures of the pixel 50x.

[0474] The drain drain portion 273x is formed in a region between a region where the transfer gate 271x" is formed and the DTI 82x-4. Fig.39Similar to the pixel 50v" of the embodiment 20-3, the drain discharge portion 273x has a Fig.35 ) and is a region with a high N-type impurity concentration. STI 78 is formed on each side of the drain discharge portion 273x. In addition, the drain discharge portion 273x is connected to the N+ layer 274 formed in the Si substrate 70.

[0475] In addition, the drain drain portion 273x is biased to a voltage VDD. By applying the voltage VDD to the drain drain portion 273x, the charges accumulated in the N+ layer 274 are discharged from the drain drain portion 273x.

[0476] As described above, since the drain discharge portion 273x is formed, even if the light entering the PD 71x" leaks toward the side where the transfer gate 271x" is formed through the non-penetrating portion of the DTI 201x, the light is photoelectrically converted in the N+ layer 274, and the photoelectrically converted charge can be discharged from the drain discharge portion 273x. Therefore, the stray light component can be suppressed.

[0477] Fig.47 The pixel 50x" shown is obtained by Fig.44 ) is formed by adding a drain discharge portion 273x. However, it is also possible to add a drain discharge portion 273x to the pixel 50x' ( Fig.46 ) a drain discharge portion 273x is added. That is, a structure in which a drain discharge portion 273x is added and a multi-stage transfer gate 271x" is formed may be adopted.

[0478] Furthermore, although as an example, in Fig.47 Only one DTI 201x is formed in the pixel 50x" shown, but two or more non-penetrating DTIs may also be formed.

[0479] The pixel 50x″ according to Embodiment 22-3 also has the N+ diffusion layer 222. Therefore, when the PD 71x is saturated, the charge from the PD 71x does not flow into the memory 211x.

[0480] According to the pixel 50x" in Example 22-3, it is also possible to provide the effect of preventing dark characteristic degradation and suppressing highlight overflow. In addition, according to the pixel 50x" in Example 22-3, electric charge can be more reliably transferred from the PD 71x to the memory 211x. In addition, according to the pixel 50x" in Example 22-3, stray light components can be further suppressed.

[0481] Note that although the above-described embodiment as an example explains the case where the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are formed on the side wall of the DTI 82, the present technology can be applied to the pixel 50 in which the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are not formed. That is, the present technology can be applied to a pixel without a solid-phase diffusion layer.

[0482] In addition, although the DTI 82 is formed by a groove penetrating the Si substrate, a light shielding material can be buried in the groove so that the groove acts as a light shielding wall.

[0483] <Example 23-1>

[0484] Fig.48 is a horizontal plan view of a pixel 50y according to Example 23-1 to which the present technology is applied, when viewed from the wiring layer side. Fig.49 It is along Fig.48 A vertical cross-sectional view of the pixel 50y taken along line AA′ of the pixel 50y is shown. Fig.50 It is along Fig.48 A vertical cross-sectional view of the pixel 50y taken along line BB′ of the pixel 50y is shown. Fig.51 It is along Fig.48 A vertical cross-sectional view of the pixel 50y taken along line CC′ of the pixel 50y is shown.

[0485] The twenty-third embodiment (Embodiments 23-1 and 23-2) can be applied to any of the above-mentioned fourteenth to twenty-second embodiments. That is, the twenty-third embodiment described below can be applied to the case where both the PD 71 and the memory 211 are embedded and the case where either the PD 71 or the memory 211 is embedded.

[0486] The basic configuration of the pixel 50y according to Embodiment 23-1 is similar to that of the pixel 50p according to Embodiment 14 ( Fig.19 and 20 ) are the same in basic structure. Therefore, the same parts are represented by the same reference numerals, and their description will be appropriately omitted.

[0487] The pixel 50y is different from the pixel 50p in that an anti-reflection film 301 is added to the pixel 50p. Figures 48 to 51 The pixel 50y shown is different from the pixel 50p in that the reading gate 213 is divided into two. Figures 48 to 51 The pixel 50y shown also differs from pixel 50p in that a gate such as read gate 213 has two vertical transistor trenches.

[0488] refer to Fig.49In the cross-sectional view of the pixel 50y shown in FIG. 1 , the anti-reflection film 301 is formed above the Pwell region 77 (on the wiring layer side). Fig.48 In the plan view of the pixel 50y shown, the anti-reflection film 301 is formed in the region where the reading gate 213y, the transfer gate 271y, the writing gate 216y, and the reading gate 220y are arranged, which includes the region above the DTI 201 formed in a non-penetrating manner.

[0489] The Si substrate 70 and the wiring layer 79 ( Fig.49 Reflection may occur near the interface between the Si substrate 70 and the wiring layer 79. Light entering the PD 71y may be reflected on the non-penetrating portion of the DTI 201y near the interface between the Si substrate 70 and the wiring layer 79, and may enter the memory 211y. The anti-reflection film 301 is formed near the interface to prevent reflection near the interface and prevent light from leaking into the memory 211y.

[0490] Examples of materials that can be used for the anti-reflective film 301 include silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2Ta5), titanium oxide (TiO2), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3) and yttrium oxide (Y2O3).

[0491] Since the antireflection film 301 is formed, reflection near the interface can be suppressed.

[0492] Forming the anti-reflection film 301 reduces the efficiency of charge transfer near the interface. Fig.49 and 50 As shown, the gate for reading charge from the PD 71y and transferring the charge to the memory 211y is divided into two. Fig. 20 For comparison. Fig. 20 In the illustrated pixel 50 p , the gate for reading charges from the PD 71 p and transferring the charges to the memory 211 is a read gate 213 including a vertical transistor trench 214 .

[0493] Fig.49The pixel 50y shown includes a read gate 213y-1 for reading charges from the PD 71y and a transfer gate 271y-1 for transferring the read charges to the memory 211y. The read gate 213y-1 has a vertical transistor trench 214y.

[0494] The gates of the pixel 50y corresponding to the reading gate 213 of the pixel 50p include a reading gate 213y-1 and a transfer gate 271y-1. As described above, since a gate for reading charges from the PD 71y and a gate for transferring the read charges are separately provided, charge transfer can be performed using the side surface. Therefore, even when the anti-reflection film 301 is formed near the interface, charges can be transferred without reducing the transfer efficiency.

[0495] In addition, if Fig.48 As shown, two read gates 213y, two transfer gates 271y, two write gates 216y, and two read gates 220y are formed. In other words, when the read gate 213y, the transfer gate 271y, the write gate 216y, and the read gate 220y are regarded as one group, two groups of gates related to reading and writing are formed.

[0496] Since two sets of gates related to reading and writing are formed in this manner, efficiency related to reading and writing can be improved.

[0497] Note that although the description will continue here by taking the case where the read gate 213y-1 and the transfer gate 271y-1 are provided as an example, Fig. 20 As with the pixel 50p shown in FIG. 1 , a structure in which one read gate 213 is provided can also be adopted by appropriately designing the material of the anti-reflection film 301, the portion where the anti-reflection film 301 is formed (for example, the anti-reflection film 301 is not formed directly under the gate), etc. In addition, although the description will continue by taking the case where two sets of gates related to reading and writing are provided as an example, the present technology is also applicable to the case where one set of gates is provided and the case where two or more sets of gates are provided.

[0498] refer to Fig.49 , the transfer gate 271y-1 is arranged above the non-penetrating DTI 201y, and its depth is shallower than the depth of the vertical transistor trenches 214y, 217y and 219y.

[0499] like Fig.49As shown by the thick arrow in , light entering the PD 71y may hit the bottom of the transmission gate 271y-1 and may be reflected. The reflected light hits the DTI 201y and returns to the inside of the PD 71y. Even in the non-penetrating portion of the DTI 201y, light is prevented from leaking from the PD 71y to the memory 211y in the area where the transmission gate 271y is formed.

[0500] In addition, reference Fig.50 Even if light entering the PD 71y reaches the non-penetrating portion of the DTI 201, the anti-reflection film 301 is formed in the region where the gate is not formed, thereby preventing the light from being reflected near the interface. Therefore, it is possible to suppress light leakage into the memory 211y.

[0501] In addition, reference Fig.51 Even if light from the PD 71y enters between the transmission gate 271y-1 and the transmission gate 271y-2, the light is not reflected near the interface due to the formation of the anti-reflection film 301. Therefore, the light passes toward the wiring layer 79 side, thereby preventing the light from the PD 71y from leaking into the memory 211.

[0502] As described above, it is possible to prevent light from leaking from the PD 71 y to the memory 211 y , thereby improving parasitic light sensitivity (PLS: parasitic light sensitivity).

[0503] <Example 23-2>

[0504] Another configuration of the pixel 50y will be described. Fig.52 is a horizontal plan view of a pixel 50y' according to Example 23-2 to which the present technology is applied. Fig.52 The cross-sectional view shown corresponds to the cross-sectional view along Fig.48 A cross-sectional view of pixel 50y taken along line AA' of pixel 50y shown in FIG. Fig.48 The cross section of the pixel 50y' according to the embodiment 23-2 is cut by a line corresponding to the line BB' of the pixel 50y shown in FIG. Fig.50 The cross-section of the pixel 50y shown is the same.

[0505] The basic structure of the pixel 50y' according to the embodiment 23-2 is the same as the basic structure of the pixel 50y according to the embodiment 23-1. Therefore, the same parts are represented by the same reference numerals, and their descriptions will be omitted. The pixel 50y' in the embodiment 23-2 is different from the pixel 50y according to the embodiment 23-1 in that each gate is buried in the Si substrate 70. The other structures are the same as the other structures of the pixel 50y.

[0506] Reference again Fig.49 For example, the reading gate 213y-1 is formed to extend in the vertical direction and the horizontal direction with respect to the PD 71y, and the reading gate 213y-1 (vertical transistor trench 214y) extending in the vertical direction is in contact with the PD 71y.

[0507] refer to Fig.52 For example, the reading gate 213y'-1 is formed to extend in the vertical direction with respect to the PD 71y', and the reading gate 213y'-1 extending in the vertical direction (corresponding to the vertical transistor trench 214y) is in contact with the PD 71y.

[0508] As described above, the read gate 213y'-1 is buried in the Si substrate 70. Note that although a contact is connected to the buried read gate 213y'-1, Fig.52 The contact is not shown in FIG.

[0509] Like the read gate 213y', the transfer gate 271y', the write gate 216y' and the read gate 220y' are also buried in the Si substrate 70. In other words, the read gate 213y', the transfer gate 271y', the write gate 216y' and the read gate 220y' respectively include portions corresponding to the vertical transistor trenches.

[0510] The embodiment in which the gate is buried in the Si substrate 70 as in Embodiment 23-2 can be applied to the pixel 50 according to any one of the first to twenty-second embodiments described above. In such a configuration, charges are transferred from the PD 71y' to the memory 211y' using the side of the buried gate rather than using the surface of the Si substrate 70.

[0511] The pixel 50y' having such a gate can be formed in such a manner that a groove for forming a buried gate is formed in the Si substrate 70, polysilicon is then formed on the entire surface of the groove, and etched back.

[0512] In Example 23-2, as in Example 23-1, the antireflection film 301y' is formed in a region located near a position where the gate is formed on the Si substrate 70 and including a region above the DTI 201y' formed in a non-penetrating manner.

[0513] Therefore, in the pixel 50y' according to Embodiment 23-2, as in the pixel 50y in Embodiment 23-1, reflection of light does not occur near the interface, and leakage of light from the PD 71y' to the memory 211y' can be prevented.

[0514] In addition, the influence of light reflected at the bottom of the gate can be reduced. Fig.51 For example, in the case where light from PD 71y passes through the anti-reflection film 301 and strikes the bottom (horizontal portion relative to PD 71y) of the read gate 213y-1, such light may be reflected at the bottom and return to PD 71y, or leak into the memory 211y.

[0515] In the pixel 50y'( Fig.52 ) has no horizontal portion relative to the PD 71y'. Therefore, light does not hit the bottom of the read gate 213y' when passing through, thereby preventing the light from returning to the PD 71y' or leaking into the memory 211y'. Therefore, the PLS can be further improved.

[0516] As described above, it is possible to prevent light from leaking from the PD 71y to the memory 211y, thereby improving the PLS.

[0517] <Example 24-1>

[0518] Fig.53 is a horizontal plan view of a pixel 50z according to Embodiment 24-1 to which the present technology is applied, when viewed from the wiring layer side. Fig.54 It is along Fig.53 A vertical cross-sectional view of the pixel 50z taken along line AA′ of the pixel 50z is shown.

[0519] The twenty-fourth embodiment can be applied to any of the above-described fourteenth to twenty-third embodiments. That is, the twenty-fourth embodiment described below can be applied to the case where both the PD 71 and the memory 211 are embedded and the case where either the PD 71 or the memory 211 is embedded.

[0520] The basic configuration of the pixel 50z according to the twenty-fourth embodiment is similar to that of the pixel 50p according to the fourteenth embodiment. Fig.19 and 20 ) are the same in basic configuration. Therefore, the same parts are denoted by the same reference numerals, and description thereof will be appropriately omitted.

[0521] The pixel 50z is different from the pixel 50p in that the read gate 213z is provided near the DTI 201z formed in a non-penetrating manner. The other structures are the same as those of the pixel 50p. Fig.54 , the vertical transistor trench 214z of the read gate 213z does not contact the DTI 201z, but is arranged as close to the DTI 201z as possible. Fig.53 In the plan view of FIG. 201 , the read gate 213z is formed to be longer than the opening (the length in the vertical direction in the figure) of the non-penetrating DTI 201z.

[0522] Since the read gate 213z (its vertical transistor trench 214z) is formed near the non-penetrating DTI 201z, the vertical transistor trench 214z can function as a light shielding wall for shielding light leaking from the PD 71z to the memory 211z. This will refer to Fig.55 Provide explanation.

[0523] Fig.55 According to the fourteenth embodiment Fig. 20 A cross-sectional view of a pixel 50p is shown. Fig.55 When light reaches the non-penetrating portion of the non-penetrating DTI 201 from the PD 71p, the light may be reflected on the interface of the Si substrate 70 or the read gate 213p and leak into the memory 211p.

[0524] like Fig.54 As shown, when the vertical transistor trench 214z is disposed as close as possible to the non-penetrating DTI 201z, light from the PD 71z impinges on the vertical transistor trench 214z without reaching the non-penetrating portion of the DTI 201z. Therefore, it is possible to prevent the light from reaching the memory 211z.

[0525] like Fig.53 As shown, the vertical transistor trench 214z is longer than the non-penetrating DTI 201, in other words, longer than the non-penetrating portion (hereinafter referred to as the opening) of the penetrating DTI 82z for setting the gate. In other words, the vertical transistor trench 214z is formed in a manner covering the opening (non-penetrating portion).

[0526] Since the opening is covered with the vertical transistor trench 214z, it is possible to prevent unnecessary light from leaking from the PD 71z into the memory 211z.

[0527] As described above, the PLS can be improved by placing the vertical transistor trench 214z closer to the DTI 201z. Fig.56 The distance between the vertical transistor trench 214z and the DTI 201z is illustrated.

[0528] The read gate 213z including the vertical transistor trench 214z is formed using polysilicon. The vertical transistor trench 214z is formed such that a groove is formed in the Si substrate 70 and the groove is filled with polysilicon. A gate oxide film 224 is formed between the vertical transistor trench 214z and the Si substrate 70.

[0529] When the distance between the side wall of the vertical transistor trench 214z (the side wall of the gate oxide film 224) and the side wall of the DTI 201z is defined as d, the distance d is, for example, approximately 50 nm to 500 nm.

[0530] When the distance d is less than 50 nm, the vertical transistor trench 214z may contact the DTI 201z. In the case where the vertical transistor trench 214z and the DTI 201z can be formed separately with a precision that prevents them from contacting each other, the distance d may be set to 50 nm or less. When the distance d is greater than 500 nm, the vertical transistor trench 214z and the DTI 201z are too far apart, so that the function of the vertical transistor trench 214z as a light shielding wall may be reduced.

[0531] Note that the function as a light shielding wall can be further improved by increasing the thickness of the gate oxide film 224. When the vertical transistor trench 214z is formed so that the crystal orientation is <110> When the gate oxide film 224 becomes thicker, the light shielding performance can be improved.

[0532] As described above, it is possible to prevent light from leaking from the PD 71z into the memory 211z, thereby being able to improve the PLS.

[0533] Note that, by applying the twenty-third embodiment, the pixel 50z according to Embodiment 24-1 may be provided with the anti-reflection film 301, or may be configured such that, for example, the reading gate 213z has two vertical transistor trenches 214z.

[0534] <Example 24-2>

[0535] Fig.57 is a horizontal plan view of a pixel 50z' according to Embodiment 24-2 to which the present technology is applied, when viewed from the wiring layer side. Fig.58 It is along Fig.57 A vertical cross-sectional view of the pixel 50z' taken along line AA' of the pixel 50z' is shown.

[0536] The basic structure of the pixel 50z' according to the embodiment 24-2 is similar to that of the pixel 50z according to the embodiment 24-1 ( Fig.53 and 54 ) is the same as the basic structure of the pixel 50z. The difference between the pixel 50z' and the pixel 50z is that a material with high light shielding property is buried in the vertical transistor trench 214z' to improve the light shielding property. The other structures are the same as those of the pixel 50z.

[0537] refer to Fig.57 and 58 , the read gate 213z' (its vertical transistor groove 214z') is formed near the DTI 201z' and covers the non-penetrating portion (opening) of the DTI 201z'. This is the same as the pixel 50z in the above-mentioned embodiment 24-1. The difference between pixel 50z' and pixel 50z is that a light shielding material 305 is also formed inside the vertical transistor groove 214z'.

[0538] The light shielding material 305 is a material having a high light shielding property. For example, a single-layer metal film including titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), tungsten nitride (WN), etc. can be used. In addition, a stacked film of these metals (for example, a stacked film of titanium and tungsten, a stacked film of titanium nitride and tungsten, etc.) can also be used as the light shielding material 305.

[0539] In addition, the light shielding material 305 can be formed to have a light shielding property due to the difference in refractive index between the light shielding material 305 and the polysilicon layer formed around the light shielding material 305. For example, SiO2 can be used as the light shielding material 305.

[0540] Since the light shielding material 305 is formed in the vertical transistor trench 214z', the light shielding property can be further improved, and light can be prevented from leaking from the PD 71z' to the memory 211z'. Therefore, the PLS can be improved.

[0541] <Example 24-3>

[0542] Fig.59 is a horizontal plan view of a pixel 50z" according to Example 24-3 to which the present technology is applied, when viewed from the wiring layer side. Fig.60 It is along Fig.59 A vertical cross-sectional view of the pixel 50z" taken along line AA' of the pixel 50z" is shown.

[0543] The basic structure of the pixel 50z" according to the embodiment 24-3 is similar to that of the pixel 50z' according to the embodiment 24-2. Fig.57 and 58 ) has the same basic structure. Like pixel 50z' according to embodiment 24-2, pixel 50z" has a structure that further improves the light-shielding performance. The difference between pixel 50z" and pixel 50z' is that a hollow portion 308 is formed in the vertical transistor groove 214z" instead of the light-shielding material 305. The other structures are the same as those of pixel 50z'.

[0544] refer to Fig.59 and 60 , the reading gate 213z" (its vertical transistor trench 214z") is formed at a position close to the DTI 201z" and covers the non-penetrating portion (opening) of the DTI 201z". This is the same as the pixel 50z (50z') in the above-mentioned embodiments 24-1 and 24-2.

[0545] The hollow portion 308 is as follows Fig.61As shown. A read gate 213z" including a vertical transistor trench 214z" is formed using polysilicon. The vertical transistor trench 214z" is formed by forming a groove in the Si substrate 70z" and filling the groove with polysilicon. A gate oxide film 224z" is formed between the vertical transistor trench 214z" and the Si substrate 70z".

[0546] In addition, a hollow portion 308 is formed in the vertical transistor groove 214z". Since the hollow portion 308 is formed as described above, the transmission of light is suppressed in the hollow portion 308 due to the difference in refractive index between polysilicon and the hollow portion. Therefore, the vertical transistor groove 214z" can play the role of a light shielding portion.

[0547] Since the hollow portion 308 is formed in the vertical transistor trench 214z", the light shielding property can be further improved, and light leakage from the PD 71z" to the memory 211z" can be prevented. Therefore, the PLS can be improved.

[0548] <Example 24-4>

[0549] Fig.62 2 is a cross-sectional view of a pixel 50z'' according to Example 24-4 to which the present technology is applied. Specifically, Fig.62 It is along Fig.53 A cross-sectional view of pixel 50z''' taken along line AA' of pixel 50z is shown.

[0550] Embodiments 24-1 to 24-3 describe the case where the read gate 213z (its perpendicular transistor trench 214z) is formed at a position close to the DTI 201z. The write gate 216z (its perpendicular transistor trench 217z) can also be formed at a position close to the DTI 201z.

[0551] exist Fig.62 In the pixel 50z"' shown according to Example 24-4, the read gate 213z"' (its vertical transistor trench 214z"') is formed near the DTI 201z"', and the write gate 216z"' (its vertical transistor trench 217z"') is also formed near the DTI 201z"'.

[0552] As described above, due to the configuration in which the vertical transistor trench 217z'" is also formed at a position close to the DTI 201z'"', it is possible to further suppress the leakage of light from the PD 71z'"' to the memory 211z'"'. Therefore, the PLS can be improved.

[0553] Fig.62The case where Example 24-4 is applied to the pixel 50z according to Example 24-1 is shown. However, Example 24-4 is also applicable to the pixel 50z' according to Example 24-2. That is, either or both of the vertical transistor groove 214z'' or the vertical transistor groove 217z''' may be provided with a light shielding material 305.

[0554] In addition, by applying Embodiment 24-4 to the pixel 50z″ according to Embodiment 24-3, either or both of the vertical transistor trench 214z′″ or the vertical transistor trench 217z′″ may be provided with the hollow portion 308 .

[0555] <About the shape of the strong electric field area>

[0556] For example, Fig.63 As shown, the pixel 50 in the above-mentioned first to twenty-fourth embodiments is formed to be surrounded by the DTI 82 in a plan view. A PN junction region is formed on the side wall of the DTI 82 due to the formation of the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84. The PN junction region forms a strong electric field region. Note that in the above and following descriptions, the PN junction region obviously includes a PN junction region including only the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84P, and also includes a PN junction region having a depletion layer region between the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84.

[0557] like Fig.63 As shown, the PD 71 is surrounded by an N-type solid phase diffusion layer 84 . The N-type solid phase diffusion layer 84 is surrounded by a P-type solid phase diffusion layer 83 . Furthermore, the P-type solid phase diffusion layer 83 is surrounded by a DTI 82 .

[0558] As described above, the PN junction region is formed by the P-type solid phase diffusion layer 83 and the N-type solid phase diffusion layer 84, and therefore, a strong electric field region is formed around the PD 71. Therefore, the saturation charge amount can be increased. Next, the shape of the PN junction region in the plan view will be described, and the shape is similar to that shown in FIG. Fig. 20 The saturation charge amount can be further increased compared to the case where the PN junction region is formed in a straight line shape.

[0559] Hereinafter, the shape of the strong electric field region will be described as twenty-fifth to twenty-seventh embodiments, and any one of the twenty-fifth to twenty-seventh embodiments can be combined with any one of the above-mentioned first to twenty-fourth embodiments.

[0560] In addition, the 25th to 27th embodiments will be described by taking the pixel having the memory 211 described in the 14th to 24th embodiments as an example. However, the 25th to 27th embodiments can be applied to the pixel not having the memory 211 as described in the 1st to 13th embodiments.

[0561] Furthermore, in the above and below descriptions, as an example, the PN junction region includes the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 sequentially arranged from the DTI 82 side to the PD 71 side. However, depending on the configuration of the PD 71, the PN junction region may include the N-type solid-phase diffusion layer 84 and the P-type solid-phase diffusion layer 83 sequentially arranged from the DTI 82 side to the PD 71 side. The present technology is applicable to a case where the PN junction region provided on the sidewall of the DTI 82 includes a first impurity region containing a first impurity and a second impurity region containing a second impurity, the first impurity being an N-type impurity and the second impurity being a P-type impurity, or the first impurity being a P-type impurity and the second impurity being an N-type impurity.

[0562] In addition, the P-type impurity or N-type impurity described above and below means an impurity that acts as a P-type or N-type with respect to a predetermined material. Here, the pixel using the Si substrate 70 will be described as an example. Therefore, for example, in the following description, an impurity that acts as a P-type with respect to silicon (Si) is defined as a P-type impurity, and an impurity that acts as an N-type with respect to Si is defined as an N-type impurity.

[0563] <Twenty-fifth embodiment>

[0564] Fig.64 is a horizontal cross-sectional view (plan view) of a pixel 50aa according to a twenty-fifth embodiment to which the present technology is applied.

[0565] In the pixel 50aa according to the twenty-fifth embodiment, the strong electric field region surrounding the PD 71aa and the memory 211aa has a convex-concave shape. Fig.64 In the illustrated pixel 50aa, when attention is paid to the PD 71aa and the memory 211aa included in the pixel 50aa, the DTI 82aa has a convex portion (concave portion) along the side surrounding the PD 71aa and the memory 211aa.

[0566] In the description here, the DTI 82aa has a convex portion. However, whether the DTI 82aa has a convex portion or a concave portion can be determined based on the side defined as the reference. Here, in the following description, the portion of the DTI 82aa that is continuously formed in a linear shape ( Fig.63 The portion illustrated as DTI 82aa in FIG. 1 is defined as a reference, and the portion protruding from the reference portion of DTI 82aa is referred to as a protruding portion.

[0567] The P-type solid-phase diffusion layer 83aa is also formed to have a protrusion that matches the shape of the DTI 82aa. In addition, the N-type solid-phase diffusion layer 84aa is also formed to have a protrusion that matches the shape of the P-type solid-phase diffusion layer 83aa (the protrusion of the P-type solid-phase diffusion layer 83aa corresponds to the concave portion of the N-type solid-phase diffusion layer 84aa).

[0568] Since the protrusion is formed on the P-type solid phase diffusion layer 83aa, the contact area with the N-type solid phase diffusion layer 84aa can be increased. As a result, the PN junction area formed by the P-type solid phase diffusion layer 83aa and the N-type solid phase diffusion layer 84aa increases, thereby increasing the strong electric field area. As the strong electric field area increases, the amount of charge that can be retained in the strong electric field area increases, thereby increasing the saturation charge amount.

[0569] exist Fig.64 In the pixel 50aa shown, for example, three protrusions are formed on each of the four sides of the DTI 82aa surrounding the PD 71aa and the memory 211aa. The number of protrusions is an example, and one or more protrusions may be formed. In addition, the protrusion is not limited to having a rectangular shape, but may have other shapes. For example, as described later in the twenty-sixth embodiment, the protrusion may have a triangular shape.

[0570] Furthermore, although as an example, in Fig.64 The pixel 50aa shown has three protrusions formed on each of the four sides surrounding the PD 71aa and the memory 211aa, but the protrusions may be formed on at least one of the four sides. Although not shown, the protrusions may be formed on one, two or three of the four sides.

[0571] Since the protrusions are formed, the strong electric field region can be increased, but the light receiving area of ​​PD 71aa may be reduced. The size of each protrusion can be set in association with the size of PD 71aa. In addition, as described above, by setting the side where the protrusions are provided (whether the protrusions are formed on one, two, three, or all four sides of the four sides), the size of the protrusions can be modulated. In addition, the size of the strong electric field region can be adjusted by adjusting the size of the protrusions.

[0572] Furthermore, since the strong electric field region can be increased by providing the protrusion, the size of the memory 211aa can be reduced compared to the case where the protrusion is not provided. Since the memory 211aa is reduced in size, the PD 71aa can be increased, thereby improving the light receiving sensitivity of the PD 71aa.

[0573] As described above, by providing a protrusion in the P-type solid phase diffusion layer 83, the bonding area between the P-type solid phase diffusion layer 83 and the N-type solid phase diffusion layer 84 can be increased. Therefore, the saturation charge amount can be increased. In this case, the saturation charge amount of the PD 71aa and the memory 211aa can be increased. In addition, the memory 211aa can be reduced, and the PD 71aa can be increased.

[0574] <Twenty-sixth embodiment>

[0575] Fig.65 is a plan view of a pixel 50ab according to a twenty-sixth embodiment to which the present technology is applied.

[0576] In the pixel 50ab according to the twenty-sixth embodiment, as in the pixel 50aa according to the twenty-fifth embodiment, the strong electric field region surrounding the PD 71ab and the memory 211ab has the convex portions and the concave portions. Fig.65 The pixel 50ab shown is Fig.64 The pixel 50aa shown is different in that the protrusion of the pixel 50ab has a triangular shape. The other configurations are substantially the same as those of the pixel 50aa, and therefore redundant descriptions will not be repeated.

[0577] exist Fig.65 In the illustrated pixel 50ab, convex portions are formed on all four sides surrounding the PD 71. The pixel 50ab can be configured such that the convex portion is formed on at least one of the four sides surrounding the PD 71, that is, formed on one, two, three or four of the four sides.

[0578] exist Fig.65 In the pixel 50ab shown, for example, two triangular protrusions are formed on the left side of the four sides of the DTI 82ab surrounding the PD 71ab and the memory 211ab. The number of protrusions is an example, and one or more protrusions may be formed. Moreover, the protrusion may have a triangle with a rounded vertex or a triangle with a curved side instead of a straight side. In addition, as an alternative to a triangle, the protrusion may have a semicircular shape, a shape close to an ellipse, or a polygon.

[0579] As with the pixel 50aa according to the twenty-fifth embodiment, the pixel 50ab according to the twenty-sixth embodiment can also be constructed such that: the length of the P-type solid-phase diffusion layer 83aa is greater than the distance between two edges parallel to each other among the four edges surrounding the PD 71aa. Therefore, the PN junction area can be increased, thereby increasing the strong electric field region. In other words, by setting the length of the side wall of the DTI 82ab to be greater than the distance between the edges of the DTI 82ab parallel to each other in the DTI 82ab surrounding the PD 71ab and the memory 211ab, the PN junction area can be increased, thereby increasing the strong electric field region.

[0580] As described above, the bonding area between the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 can be increased by providing a protrusion in the P-type solid-phase diffusion layer 83. Therefore, the saturation charge amount can be increased. In this case, the saturation charge amount of the PD 71ab and the memory 211ab can be increased. In addition, the memory 211ab can be reduced, and the PD 71ab can be enlarged.

[0581] <Twenty-sixth embodiment>

[0582] Fig.66 is a plan view of a pixel 50ac according to a twenty-sixth embodiment to which the present technology is applied. Fig.67 It is along Fig.66 A vertical cross-sectional view of the pixel 50ac taken along line BB′ of the pixel 50ac is shown.

[0583] In the pixel 50ac according to the twenty-sixth embodiment, a strong electric field extension region is formed in a part of the memory 211ac to extend the strong electric field region. The strong electric field extension region is a PN junction region formed to extend the strong electric field region. Fig.66 An example is shown in which rectangular strong electric field regions are formed near the four corners of the memory 211ac.

[0584] The rectangular strong electric field regions 311-1 to 311-4 formed near the corners of the memory 211ac respectively have the same structure as the strong electric field regions formed around the memory 211ac and the PD 71ac. Specifically, the strong electric field regions 311-1 to 311-4 are each formed with a DTI 312 penetrating the Si substrate 70 at the center, and a P-type solid-phase diffusion layer 313 is formed around the DTI 312. In addition, an N-type solid-phase diffusion layer 314 is formed around the P-type solid-phase diffusion layer 313.

[0585] Fig.66 An example in which the strong electric field region is a rectangle is shown. However, the strong electric field region may have other shapes such as a circle or a polygon. In addition, Fig.66FIG. 2 shows a case where rectangular strong electric field regions are formed near the four corners of the memory 211ac. However, it is sufficient to form at least one strong electric field region. In addition, the size of a strong electric field region is not limited to Fig.66 Dimensions shown.

[0586] Furthermore, by combining the twenty-sixth embodiment with the twenty-fourth or twenty-fifth embodiment, the strong electric field region formed on the side wall of the DTI 82ac surrounding the memory 211ac and the PD 71ac can be provided with the protrusions and the recesses.

[0587] As described above, since a strong electric field extension region composed of a P-type solid phase diffusion layer 313 and an N-type solid phase diffusion layer 314 is formed in the region outside the DTI 82ac surrounding the memory 211Ac, the strong electric field region formed in a pixel 50ac can be expanded, thereby increasing the saturation charge amount.

[0588] Like the pixel 50aa according to the twenty-fourth embodiment, the pixel 50acc according to the twenty-sixth embodiment can also be configured so that the length of the P-type solid-phase diffusion layer 83 (313) is large. Therefore, the PN junction area can be increased, thereby increasing the strong electric field region.

[0589] In the pixel 50ac according to the twenty-sixth embodiment, the length of the P-type solid-phase diffusion layer 83ac is the sum of the length of the side wall of the DTI 82ac and the length of the P-type solid-phase diffusion layer 313 included in the rectangular strong electric field region 311 formed near the four corners of the memory 211ac. Therefore, as described above, the length of the P-type solid-phase diffusion layer 83ac can be increased.

[0590] Therefore, the PN junction area can be increased, and the strong electric field region can be increased.

[0591] <Twenty-sixth embodiment>

[0592] Fig.68 is a vertical cross-sectional view of a pixel 50ad according to a twenty-sixth embodiment to which the present technology is applied. Fig.69 is a plan view of a pixel 50ad including an AL pad take-out portion included in the twenty-sixth embodiment.

[0593] A configuration including an AL pad for connecting the pixel 50 to another semiconductor substrate or the like will be described as the twenty-sixth embodiment. Fig.68 Shown in Figure 3 The first embodiment is shown as an example in which an AL pad is provided in pixel 50a. However, by combining with the twenty-sixth embodiment, an AL pad can be provided in any pixel 50 among pixels 50b to 50u according to the second to nineteenth embodiments.

[0594] like Fig.68 and 69 As shown, a pixel array section 41 ( Figure 2 ), an AL pad extraction portion 501 is provided on the right side of the figure. Regarding the AL pad extraction portion 501, an AL pad 502 is formed on the substrate surface (upper side in the figure), and the AL pad 502 is a connection terminal between the pixel 50ad and other semiconductor substrates, etc.

[0595] like Fig.68 As shown, a solid phase diffusion groove 503 is formed around each AL pad 502 in the AL pad extraction portion 501. The solid phase diffusion groove 503 is formed in the same manner as the DTI 82 in the first embodiment. Therefore, each AL pad 502 can be electrically isolated from the pixel array portion 41 and other peripheral circuit portions (not shown).

[0596] Note that, for example, the solid-phase diffusion groove 503 formed in the AL pad take-out portion 501 can be used as a mark of the photoresist. Moreover, thereby, the solid-phase diffusion groove 503 can also be used as a mark for alignment in a subsequent process.

[0597] <Twenty-seventh embodiment>

[0598] Fig.70 is a vertical cross-sectional view of a pixel 50ad' according to a twenty-seventh embodiment to which the present technology is applied.

[0599] A configuration including the pixel 50 and the peripheral circuit portion will be described as a twenty-seventh embodiment. Fig.70 Shown in Figure 3 The first embodiment is shown as an example in which a peripheral circuit is provided for the pixel 50a. However, by combining with the twenty-seventh embodiment, a peripheral circuit can be provided in any pixel 50 among the pixels 50b to 50u according to the second to nineteenth embodiments.

[0600] like Fig.70 As shown, a pixel array section 41 ( Figure 2 ), a peripheral circuit portion 511 is provided on the right side of the figure. A solid-phase diffusion groove 521 is formed in the peripheral circuit portion 511. The solid-phase diffusion groove 521 is formed in the same manner as the DTI 82 in the first embodiment.

[0601] The front surface side (upper side in the figure) of the P-type solid-phase diffusion layer 83 formed along the solid-phase diffusion groove 521 is electrically connected to the P+ diffusion layer 512 formed in the front surface of the Si substrate 70. In addition, the back side (lower side in the figure) of the P-type solid-phase diffusion layer 83 is electrically connected to the Pwell region 513 formed near the back Si interface 75, or is electrically connected to the hole layer 515 formed by the pinning film near the back interface of the Si substrate 70.

[0602] The Pwell region 513 is connected to the light shielding film 74 including a metal material such as tungsten (W) via the back contact 514. As a result, the front surface side and the back surface side of the Si substrate 70 are electrically connected to each other and fixed to the potential of the light shielding film 74.

[0603] In the twenty-seventh embodiment, the P-type solid-phase diffusion layer 83 can also be used as a Pwell region which is conventionally necessary to connect the front surface side and the back surface side of the Si substrate 70. Therefore, the number of steps for forming the Pwell region can be reduced.

[0604] <Twenty-eighth Embodiment>

[0605] Fig.71 2 is a vertical cross-sectional view of a pixel 50ad" according to a twenty-eighth embodiment to which the present technology is applied.

[0606] Similar to the twenty-seventh embodiment, a configuration including the pixel 50 and the peripheral circuit portion will be described as the twenty-eighth embodiment. Fig.71 Shown in Figure 3 The first embodiment is shown as an example in which a peripheral circuit is provided for the pixel 50a. However, by combining with the twenty-eighth embodiment, a peripheral circuit can be provided in any pixel 50 among the pixels 50b to 50u according to the second to twenty-second embodiments.

[0607] As with the pixel 50ad according to the twenty-seventh embodiment, Fig.71 As shown, the pixel 50ad" according to the twenty-eighth embodiment has a pixel array portion 41 on the left side of the figure and a peripheral circuit portion 531 on the right side of the figure. A solid-phase diffusion groove 521ad" is formed in the peripheral circuit portion 531. The solid-phase diffusion groove 521ad" is formed in a manner similar to the DTI 82 in the first embodiment.

[0608] A solid-phase diffusion groove 521ad" is formed in the peripheral circuit portion 531. The solid-phase diffusion groove 521ad" is formed in a manner similar to the DTI 82 in the first embodiment. The front surface side (upper side in the figure) of the P-type solid-phase diffusion layer 83ad" formed along the solid-phase diffusion groove 521ad" is electrically connected to the P+ diffusion layer 512ad" formed in the front surface of the Si substrate 70 via the Pwell region 532. This is similar to Fig.70 The pixel 50ad' shown is different.

[0609] In addition, the back side (lower side in the figure) of the P-type solid-phase diffusion layer 83ad" is electrically connected to the Pwell region 513 or the hole layer 515 formed near the back Si interface 75. The Pwell region 513 is connected to the shielding film 74 including a metal material such as W via the back contact 514. As a result, the front surface side and the back side of the Si substrate 70 are electrically connected to each other and are fixed to the potential of the shielding film 74.

[0610] In the twenty-eighth embodiment, the P-type solid-phase diffusion layer 83ad can also be used as a Pwell region which is conventionally necessary for connecting the front surface side and the back surface side of the Si substrate 70. Therefore, the number of steps for forming the Pwell region can be reduced.

[0611] <Twenty-ninth embodiment>

[0612] Fig.72 is a vertical cross-sectional view of a pixel 50ae according to a twenty-ninth embodiment to which the present technology is applied.

[0613] Similar to the twenty-seventh embodiment, a configuration including the pixel 50 and the peripheral circuit portion will be described as a twenty-ninth embodiment. Fig.72 Shown in Figure 3 The first embodiment is shown as an example in which a peripheral circuit is provided for the pixel 50a. However, by combining with the twenty-ninth embodiment, a peripheral circuit can be provided in any pixel 50 among the pixels 50b to 50ad" according to the second to twenty-eighth embodiments.

[0614] As with the pixel 50ad′ according to the twenty-seventh embodiment, Fig.72 As shown, the pixel 50ae according to the twenty-ninth embodiment has a pixel array section 41 on the left side of the figure and a peripheral circuit section 571 on the right side of the figure.

[0615] The solid-phase diffusion trench 503 ae is formed at a boundary portion 572 located at a boundary between the pixel array portion 41 and the peripheral circuit portion 571 .

[0616] Therefore, the pixel 50ae according to the twenty-ninth embodiment can provide the same effect as the pixel 50a according to the first embodiment, and can further prevent the light generated in the peripheral circuit portion 571 from entering the pixel array portion 41 due to the solid-phase diffusion groove 503ae.

[0617] Note that the above-described first to twenty-ninth embodiments can be combined as appropriate.

[0618] <First Modification>

[0619] In the above-described first to twenty-ninth embodiments, each pixel 50 has FD 91 ( Figure 4 ) and a pixel transistor (eg, reset transistor 92 ( Figure 2 ) etc.). However, the FD 91 or the pixel transistor may be shared by a plurality of pixels 50.

[0620] Fig.73 A plan view is shown in the case where two pixels 50 adjacent to each other in the vertical direction share the FD 91 and the pixel transistor.

[0621] exist Fig.73 In the example shown, for example, the lower right pixel 50-1 and the pixel 50-2 located above the pixel 50-1 share the FD 91 and the pixel transistor. The FD 91'-1 of the pixel 50-1, the FD 91'-2 of the pixel 50-2, the conversion efficiency switching transistor 612 of the pixel 50-2, and the amplification transistor 93'-2 are connected by the wiring 611-1.

[0622] Furthermore, the MOS capacitor 613 of the pixel 50 - 1 and the conversion efficiency switching transistor 612 of the pixel 50 - 2 are connected by a wiring 611 - 2 .

[0623] When the sharing structure is applied as described above, the number of elements per pixel is reduced, and the occupied area per pixel is sufficiently large. Therefore, the conversion efficiency switching transistor 612 and the MOS capacitor 613 added to the FD 91' can be provided.

[0624] The conversion efficiency switching transistor 612 can be switched to high conversion efficiency for applications aiming to improve sensitivity output, and can be switched to low conversion efficiency for applications aiming to increase the saturation charge amount Qs.

[0625] The MOS capacitor 613 added to the FD 91' can increase the FD capacity. Therefore, low conversion efficiency can be achieved, and thus, the saturation charge amount Qs can be increased.

[0626] <Other Modifications>

[0627] For example, as described below, the first to twenty-ninth embodiments can also be applied to the pixel 50 formed by stacking a plurality of substrates.

[0628] <Configuration Example of Stacked Solid-State Image Capturing Device to Which the Technology According to the Present Invention Can be Applicable>

[0629] Fig.74 : is a diagram showing a configuration example of a stacked solid-state imaging device to which the technology according to the present invention can be applied.

[0630] Fig.74 A shows a schematic configuration example of a non-stacked solid-state imaging device. Fig.74As shown in A, the solid-state imaging device 23010 includes a single bare chip (semiconductor substrate) 23011. The bare chip 23011 has a pixel area 23012, in which pixels are arranged in an array, and the bare chip 23011 is also equipped with a control circuit 23013 and a logic circuit 23014 for signal processing, and the control circuit 23013 controls the driving of the pixels and performs other various controls.

[0631] Fig.74 B and C show schematic configuration examples of stacked solid-state imaging devices. Fig.74 As shown in B and C, in the solid-state imaging device 23020, two dies, namely, a sensor die 23021 and a logic die 23024 are stacked and electrically connected to each other. In this way, the solid-state imaging device 23020 is constructed as a single semiconductor chip.

[0632] exist Fig.74 In B, the sensor die 23021 includes a pixel region 23012 and a control circuit 23013, and the logic die 23024 includes a logic circuit 23014, and the logic circuit 23014 includes a signal processing circuit for performing signal processing.

[0633] exist Fig.74 In C, the sensor die 23021 includes a pixel area 23012, and the logic die 23024 includes a control circuit 23013 and a logic circuit 23014.

[0634] Fig.75 : is a cross-sectional view showing a first configuration example of the stacked solid-state imaging device 23020.

[0635] The sensor die 23021 includes a photodiode (PD), a floating diffusion (FD), and a transistor (Tr) (MOSFET) constituting a pixel arranged in the pixel region 23012, and a Tr that becomes a control circuit 23013, etc. In addition, a wiring layer 23101 is formed in the sensor die 23021. The wiring layer 23101 includes a plurality of layers, and in this example, three layers of wiring 23110. Note that the control circuit 23013 (Tr that becomes the control circuit 23013) can be formed in the logic die 23024 instead of in the sensor die 23021.

[0636] The logic die 23024 includes a Tr constituting the logic circuit 23014. In addition, the logic die 23024 includes a wiring layer 23161 having a plurality of layers, in this example, a three-layer wiring 23170. In addition, in the logic die 23024, a connection hole 23171 is formed. The connection hole 23171 has an insulating film 23172 formed on the inner wall surface thereof. A connection conductor 23173 to be connected to the wiring 23170 or the like is embedded in the connection hole 23171.

[0637] The sensor die 23021 and the logic die 23024 are bonded to each other so that their wiring layers 23101 and 23161 face each other. Thus, a stacked solid-state imaging device 23020 is formed in which the sensor die 23021 and the logic die 23024 are stacked. A film 23191 such as a protective film is formed on the surface where the sensor die 23021 and the logic die 23024 are bonded to each other.

[0638] The sensor die 23021 is formed with a connection hole 23111 that passes through the sensor die 23021 from the back side (the side where light enters the PD) (upper side) of the sensor die 23021 and reaches the uppermost wiring 23170 of the logic die 23024. In addition, the sensor die 23021 is formed with a connection hole 23121 that is located near the connection hole 23111 and reaches the first layer wiring 23110 from the back side of the sensor die 23021. An insulating film 23112 is formed on the inner wall surface of the connection hole 23111, and an insulating film 23122 is formed on the inner wall surface of the connection hole 23121. Then, connection conductors 23113 and 23123 are embedded in the connection holes 23111 and 23121, respectively. The connection conductor 23113 and the connection conductor 23123 are electrically connected on the back surface side of the sensor die 23021. Therefore, the sensor die 23021 and the logic die 23024 are electrically connected to each other via the wiring layer 23101, the connection via 23121, the connection via 23111, and the wiring layer 23161.

[0639] Fig.76 23020 is a cross-sectional view showing a second configuration example of the stacked solid-state imaging device 23020.

[0640] In the second construction example of the solid-state imaging device 23020, the sensor die 23021 (wiring layer 23101 of the sensor die 23021 (wiring 23110 of the wiring layer 23101)) and the logic die 23024 (wiring layer 23161 of the logic die 23024 (wiring 23170 of the wiring layer 23161)) are electrically connected to each other via a single connection hole 23211 formed in the sensor die 23021.

[0641] That is, in Fig.76 In the embodiment, the connection hole 23211 passes through the sensor die 23021 from the back side of the sensor die 23021 and reaches the uppermost wiring 23170 of the logic die 23024 and the uppermost wiring 23110 of the sensor die 23021. An insulating film 23212 is formed on the inner wall surface of the connection hole 23211, and a connection conductor 23213 is embedded in the connection hole 23211. Fig.75 In FIG. 2 , the sensor die 23021 and the logic die 23024 are electrically connected to each other through two connection holes 23111 and 23121. Fig.76 In the embodiment, the sensor die 23021 and the logic die 23024 are electrically connected to each other through a single connection hole 23211.

[0642] Fig.77 is a cross-sectional view showing a third configuration example of the stacked solid-state imaging device 23020.

[0643] Fig.77 The solid-state imaging device 23020 shown does not include a film 23191 such as a protective film on the surface where the sensor die 23021 and the logic die 23024 are bonded to each other, and therefore, Fig.77 The solid-state imaging device 23020 shown in FIG. Fig.75 The illustrated configuration is different in that a film 23191 such as a protective film is formed on the surfaces where the sensor die 23021 and the logic die 23024 are bonded to each other.

[0644] Fig.77 The solid-state imaging device 23020 shown is formed in the following manner. Specifically, the sensor die 23021 and the logic die 23024 overlap each other so that the wirings 23110 and 23170 are in direct contact. Then, the wirings 23110 and 23170 are directly bonded by heating them while applying necessary pressure.

[0645] Fig.78 is a cross-sectional view showing another configuration example of a stacked solid-state imaging device to which the technology according to the present invention can be applied.

[0646] exist Fig.78 In the figure, the solid-state imaging device 23401 has a three-layer stacked structure in which three bare chips, namely a sensor bare chip 23411, a logic bare chip 23412 and a memory bare chip 23413, are stacked together.

[0647] For example, the memory die 23413 includes a memory circuit that stores data temporarily required for signal processing performed in the logic die 23412 .

[0648] exist Fig.78 , the logic die 23412 and the memory die 23413 are sequentially stacked below the sensor die 23411. However, the logic die 23412 and the memory die 23413 may also be stacked below the sensor die 23411 in the reverse order, that is, the memory die 23413 and the logic die 23412 are stacked below the sensor die 23411 in this order.

[0649] Note that Fig.78 In the embodiment, the PD serving as the photoelectric conversion portion of the pixel and the source / drain regions of the pixel Tr are formed in the sensor bare chip 23411.

[0650] A gate electrode is formed around the PD through a gate insulating film, and the pixel Tr 23421 and the pixel Tr 23422 are formed by the gate electrode and a pair of source / drain regions.

[0651] The pixel Tr 23421 adjacent to the PD is used as a transfer Tr, and one of the paired source and drain regions constituting the pixel Tr 23421 is used as an FD.

[0652] In addition, an interlayer insulating film is formed in the sensor die 23411, and a connection hole is formed in the interlayer insulating film. In the connection hole, a connection conductor 23431 connected to the pixel Tr 23421 and the pixel Tr 23422 is formed.

[0653] Furthermore, the sensor die 23411 is provided with a wiring layer 23433 having multi-layer wirings 23432 connected to the corresponding connection conductors 23431 .

[0654] Furthermore, an aluminum pad 23434 used as an electrode for external connection is formed in the lowermost layer of the wiring layer 23433 of the sensor die 23411. That is, in the sensor die 23411, the aluminum pad 23434 is formed at a position closer to the surface 23440 bonded to the logic die 23412 than the wiring 23432. The aluminum pad 23434 is used as one end of a wiring related to inputting / outputting a signal to / from the outside.

[0655] Furthermore, the sensor die 23411 is formed with a contact 23441 for electrical connection with the logic die 23412. The contact 23441 is connected to a contact 23451 of the logic die 23412, and is also connected to an aluminum pad 23442 of the sensor die 23411.

[0656] Furthermore, the sensor die 23411 is formed with a pad hole 23443 that reaches the aluminum pad 23442 from the back side (upper side) of the sensor die 23411 .

[0657] As described above, the technology according to the present invention can be applied to a solid-state imaging device.

[0658] <Application example of internal information acquisition system>

[0659] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be applied to an endoscopic surgery system.

[0660] Fig.79 is a block diagram showing an example of a schematic configuration of a system for acquiring internal information of a patient using an endoscope capsule, to which a technology according to the present invention (the present technology) can be applied.

[0661] The internal information acquisition system 10001 includes an endoscope capsule 10100 and an external control device 10200 .

[0662] The patient swallows the endoscope capsule 10100 during the examination. The endoscope capsule 10100 has an imaging function and a wireless communication function. The endoscope capsule 10100 sequentially captures images of the inside of organs such as the stomach and intestines (hereinafter also referred to as internal images) at predetermined intervals while moving inside the relevant organ by peristaltic motion or the like until the patient naturally expels the endoscope capsule 10100, and sequentially transmits information about the internal images to the external control device 10200 outside the body in a wireless manner.

[0663] The external control device 10200 overall controls the operation of the internal information acquisition system 10001. In addition, the external control device 10200 receives information about internal images transmitted from the endoscopic capsule 10100, and based on the received information about internal images, generates image data for displaying internal images on a display device (not shown).

[0664] In this manner, using the internal information acquisition system 10001 , images representing the internal state of the patient during the period from swallowing the endoscopic capsule 10100 to excretion of the endoscopic capsule 10100 can be continuously obtained.

[0665] The configuration and function of the endoscopic capsule 10100 and the external control device 10200 will be described in more detail.

[0666] The endoscopic capsule 10100 includes a capsule-shaped shell 10101 , and includes a light source unit 10111 , a camera unit 10112 , an image processor 10113 , a wireless communication unit 10114 , a power supply unit 10115 , a power supply unit 10116 and a controller 10117 housed in the capsule-shaped shell 10101 .

[0667] For example, the light source unit 10111 includes a light source such as a light emitting diode (LED), and the light source unit 10111 irradiates an imaging area of ​​the imaging unit 10112 with light.

[0668] The imaging unit 10112 includes an imaging element and an optical system composed of a plurality of lenses arranged in front of the imaging element. The reflected light (hereinafter referred to as observation light) of the light irradiated to the body tissue as the observation target is converged by the optical system and enters the imaging element. The imaging unit 10112 performs photoelectric conversion on the observation light entering the imaging element and generates an image signal corresponding to the observation light. The image signal generated by the imaging unit 10112 is provided to the image processor 10113.

[0669] The image processor 10113 includes a processor such as a central processing unit (CPU) or a graphics processing unit (GPU), and performs various signal processing on the image signal generated by the camera section 10112. The image processor 10113 supplies the image signal subjected to the signal processing to the wireless communication section 10114 as raw data.

[0670] The wireless communication unit 10114 performs predetermined processing (e.g., modulation processing, etc.) on the image signal processed by the image processor 10113, and transmits the obtained image signal to the external control device 10200 via the antenna 10114A. In addition, the wireless communication unit 10114 receives a control signal related to the drive control of the endoscope capsule 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 provides the control signal received from the external control device 10200 to the controller 10117.

[0671] The power supply unit 10115 includes an antenna coil for receiving power, a power regeneration circuit for regenerating power from a current generated in the antenna coil, a booster circuit, etc. In the power supply unit 10115, power is generated using the principle of so-called contactless charging.

[0672] The power supply unit 10116 includes a secondary battery and stores the power generated by the power supply unit 10115. In order to prevent the drawings from being complicated, Fig.79 An arrow or the like used to indicate the power receiving end of the power supply unit 10116 is not shown, but the power stored in the power supply unit 10116 is supplied to the light source unit 10111, the camera unit 10112, the image processor 10113, the wireless communication unit 10114 and the controller 10117, and can be used to drive these components.

[0673] The controller 10117 includes a processor such as a CPU, and appropriately controls the driving of the light source section 10111 , the imaging section 10112 , the image processor 10113 , the wireless communication section 10114 , and the power supply section 10115 according to a control signal transmitted from the external control device 10200 .

[0674] The external control device 10200 may be a processor such as a CPU or a GPU or a device such as a microcomputer or a control board on which a processor and a storage element (e.g., a memory) are mounted. The external control device 10200 controls the operation of the endoscopic capsule 10100 by sending a control signal to the controller 10117 of the endoscopic capsule 10100 via the antenna 10200A. In the endoscopic capsule 10100, for example, the illumination condition under which the light source unit 10111 illuminates the observation target with light can be changed by a control signal from the external control device 10200. In addition, the imaging condition (e.g., the frame rate and exposure level in the imaging unit 10112, etc.) can be changed by a control signal from the external control device 10200. In addition, the processing content in the image processor 10113 and the condition under which the wireless communication unit 10114 transmits the image signal (e.g., the transmission interval and the number of images to be transmitted, etc.) can be changed by a control signal from the external control device 10200.

[0675] In addition, the external control device 10200 performs various types of image processing on the image signal sent from the endoscopic capsule 10100, and generates image data for displaying the captured internal image on the display device. As image processing, various known signal processing can be performed, for example, development processing (demosaic processing), image quality improvement processing (for example, band enhancement processing, super-resolution processing, noise reduction (NR) processing, and / or jitter correction processing, etc.), and / or magnification processing (electronic zoom processing), etc. The external control device 10200 controls the driving of the display device, and causes the display device to display the captured internal image based on the generated image data. Alternatively, the external control device 10200 can also cause a recording device (not shown) to record the generated image data, or cause a printing device (not shown) to print out the generated image data.

[0676] An example of the internal information acquisition system to which the technology according to the present invention can be applied has been described above. In the above configuration, the technology according to the present invention can be applied to the imaging unit 10112.

[0677] <Application example of mobile object>

[0678] The technology according to the present invention (the present technology) can be applied to various products. For example, the technology according to the present invention can be implemented as a device installed on any type of mobile body, such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0679] Fig.80 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present invention can be applied.

[0680] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Fig.80 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0681] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating the drive force of the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle.

[0682] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system; a smart key system; a power window device; or various lights such as a headlight, a reverse light, a brake light, a signal light, or a fog light. In this case, the body system control unit 12020 is capable of receiving radio waves transmitted from a portable device that can be used as a key or signals from various switches. The body system control unit 12020 receives input of these radio waves or signals and controls the door lock device, the power window device, and the lights of the vehicle.

[0683] The vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform a process of detecting an object such as a pedestrian, a vehicle, an obstacle, a traffic sign, or letters on the road surface, or a process of detecting the distance thereof.

[0684] The imaging unit 12031 is an optical sensor for receiving light and outputting an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0685] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 may include a camera for capturing an image of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 may calculate the driver's fatigue level or concentration level, or may determine whether the driver is dozing off.

[0686] Based on the information about the outside and inside of the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device, and can output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes: collision avoidance or collision mitigation of the vehicle, following driving based on the distance between vehicles, speed maintenance driving, collision warning of the vehicle, or lane departure warning of the vehicle, etc.

[0687] In addition, based on the information about the vehicle's surrounding conditions obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform collaborative control such as automatic driving that enables the vehicle to travel automatically without the need for driver operation by controlling the driving force generating device, steering mechanism or braking device, etc.

[0688] In addition, based on the information about the outside of the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control for achieving anti-glare, which includes: controlling the headlights based on the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030 and switching the high beam to the low beam.

[0689] The sound / image output unit 12052 sends at least one of a sound output signal and an image output signal to an output device that can visually or auditorily notify passengers on the vehicle or people outside the vehicle of information. Fig.80 In the example of FIG. 1 , as examples of output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0690] Fig.81 This is a diagram showing an example of the installation position of the camera unit 12031.

[0691] exist Fig.81 In the figure, as the camera unit 12031, the vehicle 12100 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0692] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are arranged at the following positions: for example, the front nose, rearview mirror, rear bumper or rear door, and the upper part of the windshield in the vehicle compartment of the vehicle 12100. The camera unit 12101 of the front nose and the camera unit 12105 of the upper part of the windshield in the vehicle compartment both mainly obtain images of the environment in front of the vehicle 12100. The camera units 12102 and 12103 of the rearview mirror mainly obtain images of the side environment of the vehicle 12100. The camera unit 12104 of the rear bumper or rear door mainly obtains images of the rear environment of the vehicle 12100. The images of the environment in front of the vehicle obtained by the camera units 12101 and 12105 are mainly used to detect the preceding vehicle, pedestrians, obstacles, traffic lights, traffic signs or lanes, etc.

[0693] Notice, Fig.81An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 of the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 of the rearview mirrors, respectively, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 of the rear bumper or rear door. For example, by superimposing the image data acquired by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0694] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element including pixels for phase difference detection.

[0695] For example, the microcomputer 12051 obtains the distance between the vehicle 12100 and each three-dimensional object within the imaging range 12111 to 12114 and the change in the distance over time (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract, as the leading vehicle, a three-dimensional object that is closest to the vehicle 12100 on the road on which the vehicle 12100 is traveling and that is traveling at a predetermined speed (for example, greater than or equal to 0 km / h) in a direction that is almost the same as the traveling direction of the vehicle 12100. In addition, the microcomputer 12051 can perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start driving control) and the like by presetting the distance to be ensured between the vehicle 12100 and the leading vehicle. In this way, cooperative control aimed at realizing automatic driving and the like that does not require driver operation can be performed.

[0696] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into motorcycles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as electric poles, extract the three-dimensional object data of the above three-dimensional objects, and use these data to automatically avoid obstacles. For example, the microcomputer 12051 classifies the obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk used to represent the degree of danger of collision with each obstacle. When the collision risk is higher than or equal to the set value and therefore there is a possibility of collision, the microcomputer 12051 can output a warning to the driver through the audio speaker 12061 or the display unit 12062, or perform driving assistance for avoiding collision by forcibly decelerating or performing collision avoidance steering through the drive system control unit 12010.

[0697] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 may identify a pedestrian by determining whether an image captured by the camera units 12101 to 12104 includes a pedestrian. For example, the method for identifying a pedestrian includes the following steps: extracting feature points in an image captured by the camera units 12101 to 12104 as infrared cameras; and performing pattern matching processing on a series of feature points representing the contour of an object, thereby determining whether the object is a pedestrian. When the microcomputer 12051 determines that the image captured by the camera units 12101 to 12104 includes a pedestrian and identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a superimposed rectangular contour line on the identified pedestrian to emphasize the pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 to display an icon or the like for representing a pedestrian at a desired position.

[0698] An example of a vehicle control system to which the technology according to the present invention can be applied has been described above. In the above configuration, the technology according to the present invention can be applied to the imaging unit 12031 and the like.

[0699] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, but various modifications can be made without departing from the gist of the present technology.

[0700] The present technology may also have the following configurations. (1)

[0702] A solid-state imaging device, comprising:

[0703] a photoelectric conversion unit that performs photoelectric conversion;

[0704] a charge holding portion that temporarily holds the charge converted by the photoelectric conversion portion; and

[0705] a first trench formed in a semiconductor substrate between the photoelectric conversion portion and the charge holding portion,

[0706] The first trench is formed to be higher than the photoelectric conversion portion in a depth direction of the semiconductor substrate. (2)

[0708] According to the solid-state imaging device described in (1) above,

[0709] Here, in the depth direction of the semiconductor substrate, the first trench is formed to be higher than the charge holding portion. (3)

[0711] According to the solid-state imaging device described in (1) above,

[0712] Here, in the depth direction of the semiconductor substrate, the first trench is formed to be lower than the charge holding portion. (4)

[0714] The solid-state imaging device according to any one of (1) to (3) above, further comprising:

[0715] An N+ diffusion layer receives charges when the photoelectric conversion unit is saturated. (5)

[0717] The solid-state imaging device according to any one of (1) to (4) above, further comprising:

[0718] a read gate that reads the charge from the photoelectric conversion unit,

[0719] The reading gate is formed to extend in a vertical direction and a horizontal direction relative to the photoelectric conversion unit. (6)

[0721] The solid-state imaging device according to (5) above, further comprising:

[0722] A transfer gate transfers the charge read by the read gate to the charge holding portion. (7)

[0724] The solid-state imaging device according to any one of (1) to (6) above, further comprising:

[0725] a second trench formed in each of the pixels adjacent to each other, the second trench penetrating the semiconductor substrate in the depth direction; and

[0726] A PN junction region is formed on a sidewall of the second trench, and the PN junction region includes a P-type region and an N-type region. (8)

[0728] According to the solid-state imaging device described in (7) above,

[0729] Wherein, the second trench is formed in the element isolation region. (9)

[0731] According to the solid-state imaging device described in (7) above,

[0732] Wherein, the first groove and the second groove are filled with light shielding material. (10)

[0734] According to the solid-state imaging device described in (1) above,

[0735] The first groove is formed at a position parallel to the long side of the charge holding portion. (11)

[0737] An electronic device equipped with a solid-state imaging device,

[0738] The solid-state imaging device comprises:

[0739] a photoelectric conversion unit that performs photoelectric conversion;

[0740] a charge holding portion that temporarily holds the charge converted by the photoelectric conversion portion; and

[0741] a first trench formed in a semiconductor substrate between the photoelectric conversion portion and the charge holding portion,

[0742] The first trench is formed to be higher than the photoelectric conversion portion in a depth direction of the semiconductor substrate. (12)

[0744] A solid-state imaging device, comprising:

[0745] a photoelectric conversion unit that performs photoelectric conversion;

[0746] a charge holding portion that temporarily holds the charge converted by the photoelectric conversion portion; and

[0747] a first trench formed in a semiconductor substrate between the photoelectric conversion portion and the charge holding portion,

[0748] The first trench is formed to be lower than the photoelectric conversion portion and higher than the charge holding portion in the depth direction of the semiconductor substrate. (13)

[0750] The solid-state imaging device according to (12) above, further comprising:

[0751] An N+ diffusion layer receives charges when the photoelectric conversion unit is saturated. (14)

[0753] According to the solid-state imaging device described in (13) above,

[0754] The N+ diffusion layer is formed between the photoelectric conversion unit and the charge holding unit. (15)

[0756] According to the solid-state imaging device described in (13) above,

[0757] The N+ diffusion layer and the photoelectric conversion unit are formed at positions 0.2 μm to 1.0 μm apart from each other. (16)

[0759] The solid-state imaging device according to any one of (12) to (15) above, further comprising:

[0760] a writing gate for writing the charge converted by the photoelectric conversion unit into the charge holding unit,

[0761] The write gate is formed to extend in a vertical direction and a horizontal direction relative to the charge holding portion. (17)

[0763] The solid-state imaging device according to any one of (12) to (16) above, further comprising:

[0764] a second trench formed in each of the pixels adjacent to each other, the second trench penetrating the semiconductor substrate in the depth direction; and

[0765] A PN junction region is formed on a sidewall of the second trench, and the PN junction region includes a P-type region and an N-type region. (18)

[0767] According to the solid-state imaging device described in (17) above,

[0768] Wherein, the second trench is formed in the element isolation region. (19)

[0770] According to the solid-state imaging device described in (17) above,

[0771] Wherein, the first groove and the second groove are filled with light shielding material. (20)

[0773] An electronic device equipped with a solid-state imaging device,

[0774] The solid-state imaging device comprises:

[0775] a photoelectric conversion unit that performs photoelectric conversion;

[0776] a charge holding portion that temporarily holds the charge converted by the photoelectric conversion portion; and

[0777] a first trench formed in a semiconductor substrate between the photoelectric conversion portion and the charge holding portion,

[0778] The first trench is formed to be lower than the photoelectric conversion portion and higher than the charge holding portion in the depth direction of the semiconductor substrate.

[0779] Reference numerals list

[0780] 10. Camera

[0781] 12 Camera Components

[0782] 41 Pixel array unit

[0783] 50 pixels

[0784] 70 Si substrate

[0785] 71 PD

[0786] 72 P-type region

[0787] 74 shading film

[0788] 76 OCL

[0789] 77 Active Area

[0790] 75 Back Si interface

[0791] 78 STI

[0792] 81 Vertical transistor trench

[0793] 82 DTI

[0794] 83 P-type solid diffusion layer

[0795] 84 N-type solid diffusion layer

[0796] 85 Sidewall membrane

[0797] 86 Filler

[0798] 101 Membrane

[0799] 121 P-type region

[0800] 122 N-type area

[0801] 131 MOS capacitor

[0802] 151 Well contact

[0803] 152 Contacts

[0804] 153 Cu wiring

[0805] 211 Memory

[0806] 213 Read Gate

[0807] 214 Vertical transistor trench

[0808] 216 Write Gate

[0809] 217 Vertical transistor trench

[0810] 219 Vertical transistor trench

[0811] 220 Read gate

[0812] 222 N+ diffusion layer

[0813] 224 Gate oxide film

[0814] 231 Well contact

[0815] 232 FD wiring

[0816] 241 FD wiring

[0817] 242 Polysilicon

[0818] 261 Pass transistor gate

[0819] 271 Transmission Gate

[0820] 272 N+ diffusion layer

[0821] 273 Drain discharge unit

[0822] 275 shading film

[0823] 281 Storage Gate

[0824] 291 Read Gate

[0825] 292 Amplifier Gate

[0826] 293 N+ diffusion layer

[0827] 301 shading film

[0828] 305 shading material

[0829] 308 Hollow

[0830] 501 AL pad removal unit

[0831] 502 AL pad

[0832] 503 Solid phase diffusion groove

[0833] 511 Peripheral Circuit Department

[0834] 512 P+ diffusion layer

[0835] 513 Pwell Area

[0836] 514 Back contact

[0837] 515 Hole Layer

[0838] 521 Peripheral Circuit Department

[0839] 532 Pwell Area

[0840] 571 Peripheral Circuit Department

[0841] 572 Border Department

[0842] 612 Conversion Efficiency Switching Transistor

[0843] 613 MOS capacitor

Claims

1. A solid-state imaging device, comprising: a photoelectric conversion unit that performs photoelectric conversion; a charge holding portion that temporarily holds the charge converted by the photoelectric conversion portion; two first trenches formed in a semiconductor substrate between the photoelectric conversion portion and the charge holding portion; a read gate that reads charges from the photoelectric conversion unit; as well as a transfer gate that transfers the charges read by the read gate to the charge holding portion and is formed to extend across the first trench adjacent to the charge holding portion among the two first trenches, In a cross-sectional view, the two first trenches are formed to be higher than the photoelectric conversion portion in a depth direction of the semiconductor substrate.

2. The solid-state imaging device according to claim 1, further comprising: An N+ diffusion layer receives charges when the photoelectric conversion unit is saturated.

3. The solid-state imaging device according to claim 1, in, The reading gate is formed to extend in a vertical direction and a horizontal direction with respect to the photoelectric conversion portion.

4. The solid-state imaging device according to claim 1, further comprising: a second groove formed in each of the pixels adjacent to each other, the second groove penetrating the semiconductor substrate in the depth direction; as well as A PN junction region is formed on a sidewall of the second trench, and the PN junction region includes a P-type region and an N-type region.

5. The solid-state imaging device according to claim 4, in, The second trench is formed in an element isolation region.

6. The solid-state imaging device according to claim 4, in, The two first trenches and the second trench are filled with a light shielding material.

7. The solid-state imaging device according to claim 1, in, The two first grooves are formed at positions parallel to the long sides of the charge holding portion in a horizontal plan view of the solid-state imaging device.

8. An electronic device equipped with a solid-state imaging device, in, The solid-state imaging device is the solid-state imaging device according to any one of claims 1 to 7.

9. A solid-state imaging device comprising: a photoelectric conversion unit that performs photoelectric conversion; a charge holding portion that temporarily holds the charge converted by the photoelectric conversion portion; two first trenches formed in a semiconductor substrate between the photoelectric conversion portion and the charge holding portion; a read gate that reads charges from the photoelectric conversion unit; as well as a transfer gate that transfers the charges read by the read gate to the charge holding portion and is formed to extend across the first trench adjacent to the charge holding portion among the two first trenches, In a cross-sectional view, the two first trenches are formed to be lower than the photoelectric conversion portion in a depth direction of the semiconductor substrate.

10. The solid-state imaging device according to claim 9, further comprising: An N+ diffusion layer receives charges when the photoelectric conversion unit is saturated.

11. The solid-state imaging device according to claim 10, in, The N+ diffusion layer is formed between the photoelectric conversion portion and the charge holding portion.

12. The solid-state imaging device according to claim 10, in, The N+ diffusion layer and the photoelectric conversion portion are formed at positions 0.2 μm to 1.0 μm away from each other.

13. The solid-state imaging device according to claim 12, in, The two first trenches are not formed at positions between the N+ diffusion layer and the photoelectric conversion portion.

14. The solid-state imaging device according to any one of claims 9 to 13, further comprising: a writing gate for writing the charge converted by the photoelectric conversion unit into the charge holding unit, The write gate is formed to extend in a vertical direction and a horizontal direction relative to the charge holding portion.

15. The solid-state imaging device according to any one of claims 9 to 13, further comprising: a second groove formed in each of the pixels adjacent to each other, the second groove penetrating the semiconductor substrate in the depth direction; as well as A PN junction region is formed on a sidewall of the second trench, and the PN junction region includes a P-type region and an N-type region.

16. The solid-state imaging device according to claim 15, in, The second trench is formed in an element isolation region.

17. The solid-state imaging device according to claim 15, in, The two first trenches and the second trench are filled with a light shielding material.

18. An electronic device equipped with a solid-state imaging device, in, The solid-state imaging device is the solid-state imaging device according to any one of claims 9 to 17.

Images