Semiconductor packaging equipment and manufacturing methods thereof

Abstract

A semiconductor packaging device includes: a substrate, an electronic component, an annular frame, an encapsulant, a thermally conductive material, and a cap. The electronic component is disposed on the substrate. The annular frame is disposed on the substrate and surrounds the electronic component. The encapsulant encapsulates the electronic component and a first portion of the annular frame. The encapsulant exposes a second portion of the annular frame. The encapsulant and the second portion of the annular frame define a space. The thermally conductive material is disposed within the space. The cap is disposed on the thermally conductive material and connected to the second portion of the annular frame.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor packaging device, and more specifically, to a semiconductor packaging device including a heat dissipation structure and a method of manufacturing the same. Background Technology

[0002] Heat dissipation has become increasingly important for various electronic devices. Thermally conductive materials are typically used between semiconductor dies / assemblies and heat dissipation structures such as heat sinks. However, due to temperature cycling during the manufacturing process, a portion of the thermally conductive material may melt and leak out, and the remaining portion of the thermally conductive material between the semiconductor die / assembly and the heat dissipation structure may not be sufficient for heat dissipation. Summary of the Invention

[0003] In one aspect, according to some embodiments, a semiconductor packaging device includes a substrate, an electronic component, a ring frame, an encapsulant, a thermally conductive material, and a cap. The electronic component is disposed on the substrate. The ring frame is disposed on the substrate and surrounds the electronic component. The encapsulant encapsulates the electronic component and a first portion of the ring frame. The encapsulant exposes a second portion of the ring frame. The encapsulant and the second portion of the ring frame define a space. The thermally conductive material is disposed in the space. The cap is disposed on the thermally conductive material and connected to the second portion of the ring frame.

[0004] In another embodiment, a semiconductor packaging device includes a substrate, electronic components, an encapsulant, a shielding cap, and a thermally conductive material. The electronic components are disposed on the substrate. The encapsulant encapsulates the electronic components. The shielding cap is disposed on the encapsulant. The shielding cap and the encapsulant define a space. The thermally conductive material is disposed within said space.

[0005] In another aspect, according to some embodiments, a method of manufacturing a semiconductor packaging device includes: providing a carrier having a release film thereon; forming an annular frame on the release film, wherein a first end of the annular frame is inserted into the release film; forming an encapsulant to encapsulate the annular frame; forming a redistribution layer on the encapsulant; removing the carrier and the release film to form a receiving space between the encapsulant and the first end of the annular frame; and placing a thermally conductive material in the receiving space. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale, and the dimensions of features depicted in the drawings may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A A cross-sectional view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0008] Figure 1Billustrate Figure 1A An enlarged view of a portion of the semiconductor packaging equipment.

[0009] Figure 1C A top view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0010] Figure 1D A cross-sectional view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0011] Figure 2A A cross-sectional view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0012] Figure 2B illustrate Figure 2A An enlarged view of a portion of the semiconductor packaging equipment.

[0013] Figure 3A A cross-sectional view illustrating a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K and Figure 4L This is a cross-sectional view of a semiconductor packaging device manufactured at various stages according to some embodiments of the present disclosure.

[0015] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K and Figure 5L This is a cross-sectional view of a semiconductor packaging device manufactured at various stages according to some embodiments of the present disclosure.

[0016] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0017] According to some embodiments of this disclosure, by forming a shielding structure, such as an annular frame or a cap, around a thermally conductive material, the thermally conductive material can be contained between the semiconductor die / assembly and the heat dissipation structure during various operations of the manufacturing process, and the heat dissipation performance can be enhanced.

[0018] Figure 1A A cross-sectional view of a semiconductor packaging device 1a according to some embodiments of the present disclosure is shown.

[0019] Semiconductor packaging equipment 1a includes: a substrate 10, electronic components 20 and 30, an annular frame 40, an encapsulant 50, a thermally conductive material 60, a cap 70, and a connecting element 90.

[0020] Substrate 10 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. Substrate 10 may include interconnect structures, such as a redistribution layer (RDL) or grounding elements. In some embodiments, the grounding element is a via exposed from the surface of substrate 10. In some embodiments, the grounding element is a metal layer exposed from the surface of substrate 10. In some embodiments, the grounding element is a metal trace exposed from the surface of substrate 10.

[0021] Electronic component 20 is disposed on substrate 10. Electronic component 20 may be electrically connected to substrate 10 via conductive element 22. Electronic component 20 may be a chip or die containing a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. The integrated circuit device may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. Electronic component 30 is disposed on substrate 10 and close to electronic component 20. Electronic component 30 may be electrically connected to substrate 10 via conductive element 32. In some embodiments, electronic component 30 has similar features to electronic component 20.

[0022] An annular frame 40 is disposed on the substrate 10. The annular frame 40 surrounds the electronic component 20 and the electronic component 30. The annular frame 40 may have an annular shape. Viewed from above, the annular frame 40 may have a closed profile. The annular frame 40 may be circular, square (e.g., for various applications) Figure 1C (as shown in the image) or any suitable shape. The annular frame 40 has portions 42 and 44. Portion 42 is covered or enclosed by encapsulation 50. Portion 44 is exposed from encapsulation 50.

[0023] The annular frame 40 may contain a conductive material, such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel, or mixtures, alloys, or other combinations thereof. In some embodiments, the annular frame 40 is electrically connected to the substrate 10. The annular frame 40 may be grounded via a grounding element in the substrate 10. The annular frame 40 may serve as an electromagnetic interference (EMI) shielding structure for electronic components 20 and 30. In some embodiments, the annular frame 40 may not contain a conductive material. Figure 1A In the embodiment shown, the annular frame 40 is in contact with the substrate 10. The annular frame 40 can support the overall structure of the semiconductor packaging device 1a and reduce warpage during the manufacturing of the semiconductor packaging device 1a.

[0024] Encapsulation 50 is disposed on substrate 10 and encapsulates electronic components 20 and 30. A portion of electronic component 20 and a portion of electronic component 30 are exposed from encapsulation 50. For example, surface 201 (e.g., back surface) of electronic component 20 and surface 301 (e.g., back surface) of electronic component 30 are exposed from encapsulation 50. For example, surface 201 of electronic component 20 and surface 301 of electronic component 30 are substantially coplanar with surface 501 of encapsulation 50. Encapsulation 50 encapsulates or surrounds portion 42 of annular frame 40. Encapsulation 50 exposes portion 44 of annular frame 40. Portion 44 of annular frame 40 protrudes beyond encapsulation 50. Encapsulation 50 and portion 44 of annular frame 40 define a space S1. Encapsulation 50 may contain epoxy resin with filler, molding material (e.g., epoxy molding material or other molding material), polyimide, phenolic compound or material, material in which silicone is dispersed, or combinations thereof.

[0025] A thermally conductive material 60 (or thermal interface material) is disposed in the space S1. The thermally conductive material 60 may not completely fill the space S1. For example, there may be a gap between the thermally conductive material 60 and the annular frame 40. That is, the volume of the space S1 is larger than the volume of the thermally conductive material 60. In some embodiments, the ratio of the volume of the space S1 to the volume of the thermally conductive material 60 is between 1.2 and 1.5. The thermally conductive material 60 is disposed on the surface 501 of the encapsulation 50. The thermally conductive material 60 is disposed on the surface 201 of the electronic component 20 and / or the surface 301 of the electronic component 30. The thermally conductive material 60 is in contact with the surface 201 of the electronic component 20 and / or the surface 301 of the electronic component 30. Figure 1AIn the embodiments shown, the thermally conductive material 60 completely contacts or completely covers the surfaces 201 of the electronic component 20 and 301 of the electronic component 30. The thermally conductive material 60 is surrounded by a portion 44 of the annular frame 40. In some embodiments, the thermally conductive material 60 is completely surrounded by a portion 44 of the annular frame 40. For example, from a top view, the portion 44 of the annular frame 40 may have a continuous contour that completely surrounds the thermally conductive material 60 (e.g., ...). Figure 1C (As shown in the image).

[0026] The cap 70 is mounted on the heat-conducting material 60 and the annular frame 40. The cap 70 is in contact with the heat-conducting material 60. Figure 1A As shown, the thermally conductive material 60 has a surface 601 that contacts or fully contacts the cover 70. From a top view, electronic components 20 and / or 30 are located within the contour of the surface 601 of the thermally conductive material 60. The cover 70 may contain a conductive material, such as Al, Cu, Cr, Sn, Au, Ag, Ni, or stainless steel, or mixtures, alloys, or other combinations thereof. The cover 70 may contain or be a heat sink, heat diffuser, or any other suitable heat dissipation structure.

[0027] The cap 70 is connected to part 44 of the annular frame 40. Figure 1A In the embodiment shown, the cap 70 is connected to a portion 44 of the annular frame 40 by an adhesive material 75. The adhesive material 75 is continuously disposed between the portion 44 of the annular frame and the cap 70. For example, from a top view, the adhesive material 75 may form a continuous profile surrounding the heat-conducting material 60. In some embodiments, the adhesive material 75 may be discontinuously disposed between the portion 44 of the annular frame and the cap 70. For example, the adhesive material 75 may be partially disposed between the portion 44 of the annular frame and the cap 70 (e.g., Figure 1C (As shown in the illustration). In some embodiments, the cover 70 may be electrically connected to the annular frame 40. In some embodiments, the cover 70 may be grounded via the annular frame 40. In some embodiments, the cover 70 and the annular frame 40 may provide EMI shielding for electronic components 20 and 30.

[0028] like Figure 1A As shown, the distance H1 between the encapsulation 50 and the cap 70 is greater than the distance (or height, length) H2 of the portion 44 of the annular frame 40 exposed from the encapsulation 50. In some embodiments, the ratio of distance H2 to distance H1 is greater than 0.7, for example, between 0.7 and 1. This configuration prevents the thermally conductive material 60 from flowing out of the annular frame 40 during the manufacture of the semiconductor packaging apparatus 1a.

[0029] Connecting element 90 is disposed on surface 101 of substrate 10. Connecting element 90 is electrically connected to conductive lines, traces, vias, or posts in substrate 10. Connecting element 90 may include solder balls.

[0030] Figure 1B illustrate Figure 1A An enlarged view of part 1b of the semiconductor packaging device 1a. (See diagram below.) Figure 1B As shown, the encapsulation 50 includes filler 55. Near the interface 502 (which is also a surface of the encapsulation 50) between the encapsulation 50 and the substrate 10, some of the filler 55 intersects the interface 502 and has a surface coplanar with the interface 502. Conversely, in some embodiments, at surface 501 (see...) Figure 1A The filler of the encapsulation 50 near the surface 501 may be complete and may not intersect with the surface 501.

[0031] Figure 1C A top view illustrating a semiconductor packaging apparatus 1c according to some embodiments of the present disclosure is shown. The semiconductor packaging apparatus 1c may have... Figure 1A Similar features to semiconductor packaging device 1a. The cap 70 is omitted for clarity. (As shown) Figure 1C As shown, the annular frame 40 has a continuous profile surrounding the thermally conductive material 60. The adhesive material 75 is disposed discontinuously or partially along the profile of the annular frame 40, which surrounds the thermally conductive material 60. The electronic component 20 is completely covered by the thermally conductive material 60.

[0032] Figure 1D This illustration shows a cross-sectional view of a semiconductor packaging apparatus 1d according to some embodiments of the present disclosure. The semiconductor packaging apparatus 1d is similar to... Figure 1A The semiconductor packaging device 1a in the text has some differences as described below.

[0033] The encapsulation 50 and the substrate 10 do not extend beyond the sides of the annular frame 40. Therefore, the size of the semiconductor packaging device 1d can be smaller than [the size of the encapsulation 50]. Figure 1A The size of the semiconductor packaging device 1a in the middle. In addition, the surface 301 of the electronic component 30 is not exposed from the encapsulation 50.

[0034] According to configurations of some embodiments of this disclosure, thermally conductive material 60 is confined by a portion 44 of an annular frame 40 to cover (or completely cover) electronic component 20 and / or electronic component 30. Due to the configuration of the annular frame 40, the thermally conductive material 60 will not leak from the areas of electronic component 20 and / or electronic component 30 due to temperature cycling during the manufacturing process. This configuration can improve heat dissipation via the thermally conductive material 60 and a cap 70, which may be a heat sink, heat diffuser, or any other suitable heat dissipation structure.

[0035] Figure 2A A cross-sectional view of a semiconductor packaging apparatus 2a according to some embodiments of the present disclosure is shown. The semiconductor packaging apparatus 2a is similar to... Figure 1A The semiconductor packaging device 1a in the text has some differences as described below.

[0036] The annular frame 40 does not contact the substrate 10. The annular frame 40 (or a portion 42 of the annular frame 40) is spaced apart from the substrate 10 by a portion of the encapsulation 50. In some embodiments, because the annular frame 40 does not contact the substrate 10, stress that could accumulate at the junction between the substrate 10 and the portion 42 of the annular frame 40 can be prevented. Stress can be generated by temperature cycling, mismatch of coefficients of thermal expansion (CTE) between different materials, warping and / or deformation during various manufacturing processes.

[0037] Figure 2B illustrate Figure 2A An enlarged view of part 2b of the semiconductor packaging equipment 2a. (See diagram below.) Figure 2B As shown, the encapsulation 50 includes filler 55. Near the interface 502 between the encapsulation 50 and the substrate 10 (which is also the surface of the encapsulation 50), some of the filler 55 intersects the interface 502 and has a surface that is coplanar with the interface 502.

[0038] Figure 3A A cross-sectional view illustrating a semiconductor packaging apparatus 3a according to some embodiments of the present disclosure is shown. The semiconductor packaging apparatus 3a is similar to... Figure 1A Semiconductor packaging equipment 1a and / or Figure 2A The semiconductor packaging device 2a in the text has some differences as described below.

[0039] The combination of the cover 70 and the annular frame 40 is omitted. The shielding cover 80 is disposed on the encapsulation 50 and the thermally conductive material 60. The shielding cover 80 and the encapsulation 50 define a space S1 for accommodating the thermally conductive material 60. The shielding cover 80 is in contact with the thermally conductive material 60. In some embodiments, the surface 601 of the thermally conductive material 60 is in complete contact with the shielding cover 80 and completely covers the electronic component 20 and / or the electronic component 30.

[0040] The shielding cover 80 includes an annular frame 82 and a cap 84. The annular frame 82 includes a portion 822 disposed within the encapsulation 50 and a portion 824 exposed from the encapsulation 50. The portion 822 of the shielding cover 80 extends into or protrudes into the encapsulation 50. Figure 3A In the embodiment shown, a portion 822 of the shielding cover 80 is spaced apart from the substrate 10 by a portion of the encapsulation 50. In some other embodiments, a portion 822 of the shielding cover 80 may contact the substrate 10.

[0041] The shielding cover 80 may comprise a conductive material, such as Al, Cu, Cr, Sn, Au, Ag, Ni, or stainless steel, or mixtures, alloys, or other combinations thereof. The shielding cover 80 may be electrically connected to the substrate 10. The shielding cover 80 may be grounded via a grounding element in the substrate 10. The shielding cover 80 may provide EMI shielding for electronic components 20 and 30. In some embodiments, the shielding cover 80 may not comprise a conductive material.

[0042] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K and Figure 4L This is a cross-sectional view of a semiconductor packaging device 4l manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for a better understanding of the aspects of this disclosure.

[0043] See Figure 4A Provides a CR substrate. The CR substrate may contain glass or other materials. See also Figure 4B The release membrane RF is mounted on the carrier CR. See [link / reference] Figure 4C Electronic components 20 and 30 are mounted on the release film RF. See also Figure 4D An annular frame 40 is formed or disposed on the release film RF. The annular frame 40 includes a portion 42 and a portion 44. The portion 44 (which may be an end of the annular frame 40) is inserted into or protrudes into the release film RF.

[0044] See Figure 4E Encapsulation 50 is formed on release film RF to encapsulate electronic components 20 and 30 and annular frame 40. A portion 44 of the annular frame 40 is exposed from encapsulation 50. Encapsulation 50 can be formed by a molding operation. See also Figure 4F A grinding operation is performed to remove a portion of the encapsulation 50, thereby exposing the conductive elements (or electrical contacts) 22 of the electronic component 20, the conductive elements 32 (or electrical contacts) of the electronic component 30, and a portion 42 of the annular frame 40. The grinding operation can remove a portion of the conductive elements 22 of the electronic component 20, a portion of the conductive elements 32 of the electronic component 30, and a portion (or end) of the portion 42 of the annular frame 40.

[0045] See Figure 4GA substrate (which may be or may include a redistribution layer) 10 is disposed on the encapsulation 50, electronic components 20 and 30, and annular frame 40. The substrate 10 is in contact with conductive elements 22 of electronic component 20, conductive elements 32 of electronic component 30, and annular frame 40. The substrate 10 is electrically connected to the conductive elements 22 of electronic component 20, conductive elements 32 of electronic component 30, and annular frame 40.

[0046] See Figure 4H The carrier CR is removed, which can be done using ultraviolet light. See [link / reference]. Figure 4I The release film RF is removed, which can be operated using ultraviolet light. A space (or containment space) S1 is formed between the surface 501 of the encapsulation 50 and a portion 44 of the annular frame 40.

[0047] See Figure 4J A thermally conductive material 60 is disposed in space S1. The thermally conductive material 60 is disposed on electronic components 20 and 30 and encapsulation 50. The thermally conductive material 60 can be disposed via a dispensing operation. An adhesive material 75 is disposed on portion 44 of the annular frame 40. The adhesive material 75 can be disposed via a dispensing operation. See [link / reference] Figure 4K The cover 70 is placed on the thermally conductive material 60 and on portion 44 of the annular frame 40. The cover 70 is attached to portion 44 of the annular frame 40 by an adhesive material 75. The thermally conductive material 60 is pressed by the cover 70. The thermally conductive material 60 completely covers electronic components 20 and 30. The surface 601 of the thermally conductive material 60 is in complete contact with the cover 70 and, from a top view, completely covers electronic components 20 and 30.

[0048] See Figure 4L Connecting element 90 is disposed on surface 102 of substrate 10. Connecting element 90 can be disposed via a ball-mounting process that may include reflow soldering. This forms semiconductor packaging device 41. Semiconductor packaging device 41 can be used with… Figure 1A The semiconductor packaging equipment 1a is similar to or the same as that used in semiconductor packaging equipment.

[0049] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K and Figure 5L This is a cross-sectional view of a semiconductor packaging device 5l manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for better understanding of the aspects of the present disclosure.

[0050] See Figure 5AProvides a CR substrate. The CR substrate may contain glass or other materials. See also Figure 5B The release membrane RF is mounted on the carrier CR. See [link / reference] Figure 5C Electronic components 20 and 30 are mounted on the release film RF. See also Figure 5D An annular frame 40 is formed or disposed on the release film RF. The annular frame 40 includes a portion 42 and a portion 44. The portion 44 (which may be an end of the annular frame 40) is inserted into or protrudes into the release film RF.

[0051] See Figure 5E Encapsulation 50 is formed on release film RF to encapsulate electronic components 20 and 30 and annular frame 40. A portion 44 of the annular frame 40 is exposed from encapsulation 50. Encapsulation 50 can be formed by a molding operation. See also Figure 5F A grinding operation is performed to remove a portion of the encapsulation 50, thereby exposing the conductive elements (or electrical contacts) 22 of the electronic component 20 and the conductive elements 32 (or electrical contacts) of the electronic component 30. A portion of the conductive elements 22 of the electronic component 20 and a portion of the conductive elements 32 of the electronic component 30 can be removed by the grinding operation. A portion 42 of the annular frame 40 is not exposed from the encapsulation 50. The portion 42 of the annular frame 40 is spaced apart from the surface 501 of the encapsulation 50 by a portion of the encapsulation 50. In some embodiments, because the portion 42 of the annular frame 40 is not grounded during the grinding operation, the productivity of the grinding operation can be improved and the service life of the grinding tool can be extended.

[0052] See Figure 5G A substrate (which may be or may include a redistribution layer) 10 is disposed on the encapsulation 50 and the electronic components 20 and 30. The substrate 10 is in contact with the conductive elements 22 of the electronic component 20 and the conductive elements 32 of the electronic component 30. The substrate 10 is electrically connected to the conductive elements 22 of the electronic component 20 and the conductive elements 32 of the electronic component 30.

[0053] See Figure 5H The carrier CR is removed, which can be done using ultraviolet light. See [link / reference]. Figure 5I The release film RF is removed, which can be operated using ultraviolet light. A space (or containment space) S1 is formed between the surface 501 of the encapsulation 50 and a portion 44 of the annular frame 40.

[0054] See Figure 5J A thermally conductive material 60 is disposed in space S1. The thermally conductive material 60 is disposed on electronic components 20 and 30 and encapsulation 50. The thermally conductive material 60 can be disposed via a dispensing operation. An adhesive material 75 is disposed on portion 44 of the annular frame 40. The adhesive material 75 can be disposed via a dispensing operation. See [link / reference] Figure 5KThe cover 70 is placed on the thermally conductive material 60 and on portion 44 of the annular frame 40. The cover 70 is attached to portion 44 of the annular frame 40 by an adhesive material 75. The thermally conductive material 60 is pressed by the cover 70. The thermally conductive material 60 completely covers electronic components 20 and 30. The surface 601 of the thermally conductive material 60 is in complete contact with the cover 70 and, from a top view, completely covers electronic components 20 and 30.

[0055] See Figure 5L Connecting element 90 is disposed on surface 102 of substrate 10. Connecting element 90 can be disposed via a ball-mounting process that may include reflow soldering. This forms semiconductor packaging device 51. Semiconductor packaging device 51 can be used with… Figure 2A The semiconductor packaging equipment 2a is similar to or the same as that used in semiconductor packaging equipment.

[0056] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two numerical values ​​may be considered “substantially” or “about” the same. For example, "essentially parallel" can refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "essentially perpendicular" can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0057] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces are considered to be coplanar or substantially coplanar. If the difference between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface is considered to be planar or substantially planar.

[0058] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component), and situations where one or more intermediate components are located between the preceding and following components.

[0059] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes may be made and equivalent components may be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to variations in manufacturing processes, etc. Other embodiments of this disclosure may exist that are not specifically described. This specification and the drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular situations, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A method for manufacturing a semiconductor packaging device, comprising: Provide a carrier with a release film on it; An annular frame is formed on the release film, wherein a first end of the annular frame is inserted into the release film; Form an encapsulation to encapsulate the annular frame; A redistribution layer is formed on the encapsulation; Remove the carrier and the release film to form a receiving space between the encapsulation and the first end of the annular frame; as well as The heat-conducting material is placed in the containment space.

2. The method of claim 1, further comprising placing electronic components on the release film prior to forming the encapsulation.

3. The method of claim 2, further comprising removing a portion of the encapsulation and a portion of the electrical contacts of the electronic component prior to forming the redistribution layer.

4. The method of claim 3, wherein the redistribution layer is formed on the electrical contacts of the electronic component.

5. The method of claim 1, further comprising removing the second end of the annular frame.

6. The method of claim 5, wherein the redistribution layer is formed on the second end of the annular frame.

7. The method of claim 1, further comprising placing a cap on the first end of the annular frame.

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