Method for trench filling and controlling silicon wafer warpage and semiconductor device
By making a back seal layer and a stress buffer layer on the back of the silicon wafer in semiconductor device manufacturing, a multi-layer intermetallic dielectric layer is formed, which solves the problem of silicon wafer warping and trench filling difficulties, and improves the yield and complete filling of the device sex.
Patent Information
- Application Number
- CN201811544857.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2018-12-17
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2038-12-17
AI Technical Summary
During the manufacturing process of semiconductor devices, the silicon wafer is prone to warping due to thick interlayer dielectric layer and metal layer, resulting in difficulty in filling the trench and affecting the yield of the device.
A back seal layer is made on the back of the silicon wafer, and a stress buffer layer is formed to cover the bottom and side walls of the trench. A multi-layer intermetallic dielectric layer is formed through HDP and PETEOS deposition to control the bending of the silicon wafer and ensure that the trench filling is complete.
It effectively reduces the warpage of the silicon wafer, avoids the risks of chip transfer, slide or debris, and improves the yield of semiconductor devices.
Smart Images
Figure CN111326426B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a method for trench filling and controlling silicon wafer warpage, and a semiconductor device. Background Art
[0002] During the manufacturing process of semiconductor devices with trench structures, silicon wafers are prone to warping. Figure 1-6 The figure shows the manufacturing process of a 0.35 micron BiCMOS (a semiconductor device process) device. Figure 1 The silicon wafer 101 is used as a substrate. Figure 2 As shown, an interlayer dielectric layer 102 is formed on the front side of the silicon wafer 101, and the interlayer dielectric layer 102 is silicon dioxide. Figure 3 , forming a first metal layer 103, patterning the first metal layer 103, and etching to form a first groove 104. Then, HDP (high density plasma) deposition is first performed, followed by PETEOS (plasma enhanced tetraethyl orthosilicate) deposition, and then CMP (Chemical Mechanical Polishing), such as Figure 4 As shown, an intermetallic dielectric layer 105 is formed, and the intermetallic dielectric layer 105 fills the first trench 104. Next, as shown in FIG. Figure 5 As shown, a second metal layer 106 is fabricated, and the second metal layer 106 is patterned and etched to form a second groove 107. Finally, referring to Figure 6 , a passivation layer 108 is produced. Figure 1-6 This is just a schematic representation. In the actual manufacturing process, the silicon wafer 101 will undergo the following Figure 7 The upward warping shown. The warping of the silicon wafer 101 is related to the thickness of the interlayer dielectric layer 102, the first metal layer 103, the intermetallic dielectric layer 105, the second metal layer 106, and the passivation layer 108. The greater the thickness of the interlayer dielectric layer 102, the first metal layer 103, the intermetallic dielectric layer 105, the second metal layer 106, and the passivation layer 108, the greater the warping of the silicon wafer 101. The warping refers to the difference between the maximum distance and the minimum distance between the center plane of the silicon wafer in an unclamped state and the reference plane. The warping is measured according to ASTM Std F-657-80 (a standard test method of the American Society for Testing and Materials).
[0003] Power devices usually require relatively thick interlayer dielectric layers, intermetallic dielectric layers, metal layers, and passivation layers. For example, the thickness of the interlayer dielectric layer is 3 microns, and the thickness of the metal layer is 2 microns. The problem caused by the thick dielectric layer is that the warpage of the silicon wafer is relatively large, which affects the subsequent photolithography, etching, thin film deposition and other processes. In addition, the thicker metal layer will easily cause gaps when depositing the HDP layer and filling the groove.
[0004] That is, thick interlayer dielectric layers and metal layers lead to the following problems when depositing the HDP layer:
[0005] First, thick interlayer dielectric layers and metal layers are prone to produce large stress, resulting in large warpage of silicon wafers. In thin film deposition, especially HDP, which has high requirements for silicon wafer warpage and particles on the back of silicon wafers, it is easy to have alarms during wafer transfer and HDP processes, and there is a risk of silicon wafer slippage or even fragmentation. Silicon wafer warpage can also easily lead to uneven or insufficient back cooling during HDP, resulting in melting of the metal layer.
[0006] Second, the thick metal layer leads to a corresponding increase in the thickness of the intermetallic dielectric layer, which also makes trench filling more difficult. Summary of the invention
[0007] The technical problem to be solved by the present invention is to overcome the defect in the prior art that, when manufacturing semiconductor devices with trench structures, silicon wafers are severely warped, which brings difficulties to trench filling and affects the yield of semiconductor devices, and to provide a method and semiconductor device for trench filling and controlling silicon wafer warpage.
[0008] The present invention solves the above technical problems through the following technical solutions:
[0009] A method for trench filling and controlling the warpage of a silicon wafer, the method is used to manufacture a semiconductor device with a trench structure, the semiconductor device comprises a first metal layer, a second metal layer, and an intermetallic dielectric layer, the intermetallic dielectric layer is arranged between the first metal layer and the second metal layer, the first metal layer is provided with a first trench, the intermetallic dielectric layer comprises a first filling portion, and the first filling portion fills the first trench;
[0010] The method comprises the following steps:
[0011] Making a back seal on the back side of the silicon wafer;
[0012] A stress buffer layer is formed, which covers the bottom surface and sidewalls of the first groove and the upper surface of the first metal layer; HDP deposition is performed on the upper surface of the stress buffer layer to form a first intermetallic dielectric layer; PETEOS deposition is performed on the upper surface of the first intermetallic dielectric layer to form a second intermetallic dielectric layer; the stress buffer layer, the first intermetallic dielectric layer and the second intermetallic dielectric layer constitute an intermetallic dielectric layer.
[0013] Preferably, after forming the stress buffer layer, the absolute value of the curvature of the silicon wafer is not greater than 100 microns. The curvature refers to the degree of concavity or convexity of the entire silicon wafer when the silicon wafer is not clamped or placed on a vacuum chuck. The unit of curvature is micrometer, and it can be measured according to ASTM Std F-534-84 (a standard test method of the American Society for Testing and Materials).
[0014] Preferably, the step of forming the stress buffer layer includes: performing PETEOS deposition to form the stress buffer layer.
[0015] Preferably, the back seal is a composite film layer of oxide and nitride.
[0016] Preferably, the thickness of the composite film layer is not greater than 10 microns.
[0017] Preferably, after the step of making a back seal on the back side of the silicon wafer, the method further comprises the following steps:
[0018] An interlayer dielectric layer is formed on the front side of the silicon wafer;
[0019] A first metal layer is formed on the upper surface of the interlayer dielectric layer.
[0020] Preferably, the thickness of the interlayer dielectric layer is 2-5 microns; the thickness of the first metal layer is 1-3 microns.
[0021] Preferably, after forming the second intermetallic dielectric layer, the method further comprises the following steps:
[0022] The second intermetallic dielectric layer is chemically mechanically polished.
[0023] Preferably, after the step of chemically mechanically polishing the second intermetallic dielectric layer, the method further comprises the following steps:
[0024] manufacturing a second metal layer, wherein the second metal layer comprises a second groove;
[0025] A passivation layer is manufactured, wherein the passivation layer includes a second filling portion, and the second filling portion fills the second trench.
[0026] The present invention also provides a semiconductor device, comprising a first metal layer, a second metal layer, and an intermetallic dielectric layer, wherein the intermetallic dielectric layer is disposed between the first metal layer and the second metal layer, the first metal layer is provided with a first groove, the intermetallic dielectric layer comprises a first filling portion, and the first filling portion fills the first groove;
[0027] The semiconductor device is manufactured by adopting the method for trench filling and controlling the warpage of silicon wafer of the present invention.
[0028] The positive improvement effect of the present invention is that the present invention can effectively reduce the warpage of silicon wafers, ensure complete filling of grooves, avoid the risk of wafer transfer, wafer sliding and even fragmentation, and improve the yield rate of semiconductor device manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 The present invention is a schematic diagram of a silicon wafer in a process for manufacturing a semiconductor device with a trench structure in the prior art.
[0030] Figure 2 The present invention is a schematic diagram of the steps of manufacturing an interlayer dielectric layer in a process for manufacturing a semiconductor device with a trench structure in the prior art.
[0031] Figure 3 The present invention is a schematic diagram of the step of manufacturing a first metal layer in a process for manufacturing a semiconductor device with a trench structure in the prior art.
[0032] Figure 4 The present invention is a schematic diagram of the steps of manufacturing an intermetallic dielectric layer in a process for manufacturing a semiconductor device with a trench structure in the prior art.
[0033] Figure 5 The present invention is a schematic diagram of the step of manufacturing a second metal layer in a process for manufacturing a semiconductor device with a trench structure in the prior art.
[0034] Figure 6 The present invention is a schematic diagram of the steps of manufacturing a passivation layer in a process for manufacturing a semiconductor device with a trench structure in the prior art.
[0035] Figure 7 A schematic diagram of a warping state of a silicon wafer of a semiconductor device manufactured by a process for manufacturing a semiconductor device with a trench structure in the prior art.
[0036] Figure 8 The present invention is a flowchart of a method for trench filling and controlling silicon wafer warpage according to a preferred embodiment of the present invention.
[0037] Fig. 9 The figure is a schematic diagram of the steps of making a back seal in a method for trench filling and controlling silicon wafer warpage according to a preferred embodiment of the present invention.
[0038] Fig.10 A schematic diagram of the warping state of a silicon wafer after the step of making a back seal in a method for trench filling and controlling the warpage of a silicon wafer according to a preferred embodiment of the present invention.
[0039] Fig.11 The figure is a schematic diagram of the steps of manufacturing an interlayer dielectric layer in a method for trench filling and controlling silicon wafer warpage according to a preferred embodiment of the present invention.
[0040] Fig.12 The figure is a schematic diagram of the steps of making the first metal layer in the method for trench filling and controlling the warpage of silicon wafer according to a preferred embodiment of the present invention.
[0041] Fig.13 The diagram is a schematic diagram of the steps of making a stress buffer layer in a method for trench filling and controlling silicon wafer warpage according to a preferred embodiment of the present invention.
[0042] Fig.14 The diagram is a schematic diagram of the steps of manufacturing the first intermetallic dielectric layer in a method for trench filling and controlling silicon wafer warpage according to a preferred embodiment of the present invention.
[0043] Fig.15 The diagram is a schematic diagram of the steps of making a second intermetallic dielectric layer in a method for trench filling and controlling silicon wafer warpage according to a preferred embodiment of the present invention.
[0044] Fig.16 The figure is a schematic diagram of the steps of making the second metal layer in the method for trench filling and controlling the warpage of silicon wafer according to a preferred embodiment of the present invention.
[0045] Fig.17 The figure is a schematic diagram of the steps of making a passivation layer in a method for trench filling and controlling silicon wafer warpage according to a preferred embodiment of the present invention. DETAILED DESCRIPTION
[0046] The present invention is further described below by way of a preferred embodiment, but the present invention is not limited to the scope of the embodiment.
[0047] This embodiment provides a method for trench filling and controlling the warpage of a silicon wafer, the method is used to manufacture a semiconductor device with a trench structure, Figure 8 The method for trench filling and controlling silicon wafer warpage of this embodiment includes the following steps:
[0048] Step S301: making a back seal on the back side of the silicon wafer. Fig. 9 The state where the back seal 201 is formed on the back surface of the silicon wafer 101 is shown. Fig. 9 This is just an illustration. After the back seal 201 is formed, the silicon wafer 101 will actually produce the following Fig.10 The downward warping of the silicon wafer 101 is shown. The degree of downward warping of the silicon wafer 101 is related to the thickness of the back seal 201. In this embodiment, the back seal 201 is a composite film layer of oxide and nitride. The thickness of the composite film layer is not greater than 10 microns. In this step, the silicon wafer 101 is warped downward, which can reduce the degree of upward warping of the silicon wafer 101 when the semiconductor device is completed.
[0049] Step S302: fabricate an interlayer dielectric layer on the front side of the silicon wafer. Fig.11 , an interlayer dielectric layer 102 is formed on the front side of the silicon wafer 101. The thickness of the interlayer dielectric layer is 2-5 microns.
[0050] Step S303: fabricate a first metal layer on the upper surface of the interlayer dielectric layer. Fig.12 A metal layer is formed on the upper surface of the interlayer dielectric layer 102, and the metal layer is patterned and etched to form a first groove 104, so as to form a first metal layer 103. The thickness of the first metal layer is 1-3 microns.
[0051] Step S304: forming a stress buffer layer, wherein the stress buffer layer covers the bottom surface and sidewalls of the first trench and covers the upper surface of the first metal layer. Fig.13 , PETEOS is deposited to form a stress buffer layer 202. After the stress buffer layer 202 is formed, the downward warping degree of the silicon wafer 101 is reduced, which is beneficial to the subsequent production of the intermetallic dielectric layer and avoids the completion of the filling portion of the first trench 104 and the formation of a gap. In other optional implementations of this embodiment, after the stress buffer layer is formed, the absolute value of the curvature of the silicon wafer is not greater than 100 microns, that is, the silicon wafer is in a state of slight downward warping, straightness, and slight upward warping.
[0052] Step S305: HDP deposition is performed on the upper surface of the stress buffer layer to form a first intermetallic dielectric layer. Fig.14 , HDP deposition is performed on the upper surface of the stress buffer layer 202 to form a first intermetallic dielectric layer 203 .
[0053] Step S306: deposit PETEOS on the upper surface of the first intermetallic dielectric layer to form a second intermetallic dielectric layer. Fig.15 As shown, PETEOS is deposited on the upper surface of the first intermetallic dielectric layer 203 to form a second intermetallic dielectric layer 204 .
[0054] Step S307 , chemical mechanical polishing the second intermetallic dielectric layer. The stress buffer layer 202 , the first intermetallic dielectric layer 203 and the second intermetallic dielectric layer 204 constitute an optimized intermetallic dielectric layer 205 . The optimized intermetallic dielectric layer 205 includes a first filling portion, and the first filling portion fills the first trench 104 .
[0055] Step S308: fabricate a second metal layer, wherein the second metal layer includes a second groove. Fig.16 As shown, a metal layer is deposited on the upper surface of the optimized intermetallic dielectric layer 205 , and the metal layer is patterned and etched to form a second trench 107 , so as to form a second metal layer 106 .
[0056] Step S309: manufacturing a passivation layer, wherein the passivation layer includes a second filling portion, and the second filling portion fills the second groove. Fig.17 As shown, a passivation layer 108 is manufactured. The passivation layer 108 includes a second filling portion. The second filling portion fills the second trench 107 .
[0057] The method for trench filling and controlling silicon wafer warpage of this embodiment can effectively reduce the warpage of the silicon wafer, ensure complete trench filling, avoid the risk of wafer transfer, wafer sliding and even fragmentation, and improve the yield of semiconductor device manufacturing.
[0058] This embodiment also provides a semiconductor device, such as Fig.17 As shown, the semiconductor device includes, from bottom to top, a back seal 201 , a silicon wafer 101 , an interlayer dielectric layer 102 , a first metal layer 103 , an optimized intermetallic dielectric layer 205 , a second metal layer 106 , and a passivation layer 108 .
[0059] The first metal layer 103 is provided with a first trench 104. The optimized intermetallic dielectric layer 205 is composed of a stress buffer layer 202, a first intermetallic dielectric layer 203 and a second intermetallic dielectric layer 204. The optimized intermetallic dielectric layer 205 includes a first filling portion, and the first filling portion fills the first trench 104.
[0060] A second trench 107 is disposed on the second metal layer 106 . The passivation layer 108 includes a second filling portion, and the second filling portion fills the second trench 107 .
[0061] The semiconductor device of this embodiment is manufactured using the method for trench filling and controlling silicon wafer warpage of this embodiment, and the specific process will not be described in detail.
[0062] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that these are only examples, and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.
Claims
1. A method for trench filling and controlling silicon wafer warpage, characterized in that: The method is used to manufacture a semiconductor device with a groove structure, the semiconductor device is applied to a power device, the semiconductor device comprises a first metal layer, a second metal layer, and an intermetallic dielectric layer, the intermetallic dielectric layer is arranged between the first metal layer and the second metal layer, the first metal layer is provided with a first groove, the intermetallic dielectric layer comprises a first filling portion, and the first filling portion fills the first groove; The method comprises the following steps: Making a back seal on the back side of the silicon wafer; A stress buffer layer is formed, the stress buffer layer covers the bottom surface and side walls of the first groove and covers the upper surface of the first metal layer; HDP deposition is performed on the upper surface of the stress buffer layer to form a first intermetallic dielectric layer; PETEOS deposition is performed on the upper surface of the first intermetallic dielectric layer to form a second intermetallic dielectric layer; the stress buffer layer, the first intermetallic dielectric layer and the second intermetallic dielectric layer constitute the intermetallic dielectric layer.
2. The method for trench filling and controlling silicon wafer warpage according to claim 1, characterized in that: After the stress buffer layer is formed, the absolute value of the curvature of the silicon wafer is no more than 100 micrometers.
3. The method for trench filling and controlling silicon wafer warpage according to claim 1, characterized in that: The step of forming the stress buffer layer includes: performing PETEOS deposition to form the stress buffer layer.
4. The method for trench filling and controlling silicon wafer warpage according to claim 1, characterized in that: The back seal is a composite film layer of oxide and nitride.
5. The method for trench filling and controlling silicon wafer warpage according to claim 4, characterized in that: The thickness of the composite film layer is no more than 10 microns.
6. The method for trench filling and controlling silicon wafer warpage according to claim 1, characterized in that: After the step of making a back seal on the back side of the silicon wafer, the method further comprises the following steps: Making an interlayer dielectric layer on the front side of the silicon wafer; The first metal layer is formed on the upper surface of the interlayer dielectric layer.
7. The method for trench filling and controlling silicon wafer warpage according to claim 6, characterized in that: The thickness of the interlayer dielectric layer is 2-5 microns; the thickness of the first metal layer is 1-3 microns.
8. The method for trench filling and controlling silicon wafer warpage according to claim 1, characterized in that: After forming the second intermetallic dielectric layer, the method further comprises the following steps: The second intermetallic dielectric layer is subjected to chemical mechanical polishing.
9. The method for trench filling and controlling silicon wafer warpage according to claim 8, characterized in that: After the step of chemically mechanically polishing the second intermetallic dielectric layer, the method further comprises the following steps: manufacturing the second metal layer, wherein the second metal layer comprises a second groove; A passivation layer is manufactured, wherein the passivation layer includes a second filling portion, and the second filling portion fills the second trench.
10. A semiconductor device, characterized in that: The semiconductor device is applied to a power device, and comprises a first metal layer, a second metal layer, and an intermetallic dielectric layer, wherein the intermetallic dielectric layer is arranged between the first metal layer and the second metal layer, the first metal layer is provided with a first groove, and the intermetallic dielectric layer comprises a first filling portion, and the first filling portion fills the first groove; The semiconductor device is manufactured using the method for trench filling and controlling silicon wafer warpage as described in any one of claims 1 to 9.