A low-thickness 3D stacked packaging structure and preparation method thereof

Abstract

The present invention discloses a low-thickness 3D stacked packaging structure and a preparation method thereof, the preparation method comprising the following steps: providing a carrier, pasting a conductive layer and a solder resist layer on the carrier, opening a first hole position and a second hole position in the solder resist layer and coating solder paste respectively; pasting a first chip and a conductive block with a double-sided I / O port at the solder paste, and forming a first plastic sealing layer after plastic sealing; removing the key and flipping and fixing, and opening a hole in the conductive layer to form a first redistribution layer; providing a second chip with a single-sided I / O port, pasting the second chip on the side of the first redistribution layer away from the first chip, and forming a second plastic sealing layer after plastic sealing; respectively making a second redistribution layer connecting the I / O port on one side of the first chip and the conductive block and a third redistribution layer connecting the second chip and the first redistribution layer, and plastic sealing the second redistribution layer and the third redistribution layer and electrically leading out. The present invention can reduce the packaging thickness and on-resistance of the low-thickness 3D stacked packaging structure, shorten the physical connection and improve the product yield.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit packaging, and in particular to a low-thickness 3D stacked packaging structure and a preparation method thereof. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a field-effect transistor that can be widely used in analog circuits and digital circuits.

[0003] At present, for MOS chips, when they are stacked and packaged with controller chips, the physical connection lines are long, resulting in slow response speed; the height of the packaging structure is large, resulting in a larger product size, which makes it difficult to meet the needs of miniaturization development of electronic products. Summary of the invention

[0004] The purpose of the present invention is to provide a preparation method of a low-thickness 3D stacked packaging structure and a low-thickness 3D stacked packaging structure. The method can greatly reduce the packaging thickness and on-resistance of the low-thickness 3D stacked packaging structure, shorten the physical connection, and improve the product yield.

[0005] To achieve this object, the present invention adopts the following technical solutions:

[0006] On the one hand, a method for preparing a low-thickness 3D stacked packaging structure is provided, comprising the following steps:

[0007] S10, providing a carrier board, sequentially attaching a conductive layer and a solder resist layer to one side of the carrier board along the thickness direction thereof, and performing hole processing on the solder resist layer to form a first hole position and a second hole position that partially expose the conductive layer;

[0008] S20, applying solder paste to the first hole position and the second hole position respectively; mounting a first chip having a double-sided I / O port on the solder paste position corresponding to the first hole position and mounting a conductive block on the solder paste position corresponding to the second hole position, and plastic-sealing the first chip and the conductive block to form a first plastic-sealing layer;

[0009] S30, debonding and flipping, and performing hole processing on the conductive layer to form a first redistribution layer;

[0010] S40, providing a second chip having a single-sided I / O port, attaching the second chip to a side of the first redistribution layer away from the first chip through an insulating layer, and performing plastic packaging on the second chip to form a second plastic packaging layer;

[0011] S50, respectively make a second redistribution layer connecting the I / O port of the first chip facing away from the solder resist layer and the conductive block, and a third redistribution layer connecting the I / O port of the second chip and the first redistribution layer, plastic-encapsulate the second redistribution layer and the third redistribution layer and electrically lead them out.

[0012] As a preferred solution of the method for preparing a low-thickness 3D stacked packaging structure, in step S20, after the first plastic packaging layer is manufactured, a first copper layer is mounted on the first plastic packaging layer.

[0013] As a preferred solution of the method for preparing a low-thickness 3D stacked packaging structure, in step S40, after the second plastic packaging layer is manufactured, a second copper layer is mounted on the second plastic packaging layer.

[0014] As a preferred solution of the method for preparing a low-thickness 3D stacked packaging structure, step S50 specifically includes the following steps:

[0015] S50a, performing hole processing on the first copper layer and the first plastic encapsulation layer to form a third hole position for exposing the I / O port on one side of the first chip and the conductive block, and performing hole processing on the second copper layer and the second plastic encapsulation layer to form a fourth hole position for exposing the I / O port of the second chip and the first redistribution layer;

[0016] S50b, sequentially forming a first seed layer and a second redistribution layer on the surfaces of the first copper layer and the third hole, and sequentially forming a second seed layer and a third redistribution layer on the surfaces of the second copper layer and the second plastic packaging layer;

[0017] S50c, performing plastic sealing on the second redistribution layer to form a third plastic sealing layer, and performing plastic sealing on the third redistribution layer to form a fourth plastic sealing layer;

[0018] S50d, drilling the third plastic packaging layer to form a fifth hole for partially exposing the second redistribution layer, making a conductive terminal in the fifth hole, and completing the packaging.

[0019] As a preferred solution of the method for preparing a low-thickness 3D stacked packaging structure, the material of the conductive block is Cu, Ag or Au.

[0020] On the other hand, a low-thickness 3D stacked packaging structure prepared by the preparation method is provided, comprising:

[0021] A solder resist layer and a first redistribution layer located on one side of the solder resist layer, wherein the solder resist layer is provided with first holes and second holes extending therethrough along a thickness direction thereof at intervals;

[0022] A first plastic encapsulation layer located on a side of the solder resist layer away from the first redistribution layer, a first chip with a double-sided I / O port encapsulated in the first plastic encapsulation layer and attached to the first hole position through solder paste, and a conductive block attached to the second hole position through solder paste, wherein the first plastic encapsulation layer is provided with a third hole position for exposing the I / O port of the first chip on the side facing away from the solder resist layer and the conductive block;

[0023] A second redistribution layer is located on the first plastic packaging layer and is connected to the conductive block through the conductive pillar in the third hole;

[0024] A second plastic encapsulation layer and a second chip having a single-sided I / O port located on a side of the first redistribution layer away from the first chip, the second chip being encapsulated in the second plastic encapsulation layer with its back facing the first chip and attached to the first redistribution layer through an insulating layer, the second plastic encapsulation layer being provided with a fourth hole for exposing the I / O port of the second chip and the first redistribution layer;

[0025] The third redistribution layer is located on the second plastic packaging layer and is connected to the first redistribution layer through the conductive pillars in the fourth holes.

[0026] As a preferred solution of the low-thickness 3D stacked packaging structure, it also includes a first copper layer and a second copper layer, the first copper layer is located on the first plastic packaging layer, and the first copper layer and the first plastic packaging layer are both provided with the third hole position, the second copper layer is located on the second plastic packaging layer, and the second copper layer and the second plastic packaging layer are both provided with the fourth hole position.

[0027] As a preferred solution for the low-thickness 3D stacked packaging structure, it also includes a first seed layer and a second seed layer, the first seed layer is located at the third hole position and the surface of the first copper layer, and the second seed layer is located at the fourth hole position and the surface of the second copper layer.

[0028] As a preferred solution for a low-thickness 3D stacked packaging structure, it also includes a third plastic packaging layer, a fourth plastic packaging layer and a conductive end. The third plastic packaging layer is located on the first plastic packaging layer and covers the second redistribution layer. The third plastic packaging layer is provided with a fifth hole for partially exposing the second redistribution layer. The conductive end is located in the fifth hole. The fourth plastic packaging layer is located on the second plastic packaging layer and covers the third redistribution layer.

[0029] As a preferred solution of the low-thickness 3D stacked packaging structure, the conductive end includes a copper layer located on the surface of the fifth hole and a tin layer located on the copper layer.

[0030] The beneficial effects of the present invention are as follows: the present invention adopts a two-sided fan-out rewiring technology, which can greatly reduce the package thickness and the on-resistance, shorten the physical connection, and for the problem of through-hole electroplating with a high aspect ratio, a method of pre-implanting a conductive block is adopted, which can reduce the difficulty of electroplating and improve the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 It is a flow chart of a method for preparing a low-thickness 3D stacked packaging structure according to an embodiment of the present invention.

[0033] Figure 2 It is a specific flow chart of step S50 in the method for preparing a low-thickness 3D stacked packaging structure according to an embodiment of the present invention.

[0034] Figure 3 It is a cross-sectional schematic diagram of an intermediate product in which a conductive layer is attached to a carrier according to an embodiment of the present invention.

[0035] Figure 4 It is a cross-sectional schematic diagram of an intermediate product in which a solder resist layer is attached to a conductive layer according to an embodiment of the present invention.

[0036] Figure 5 It is a cross-sectional schematic diagram of an intermediate product after the solder mask layer is opened according to an embodiment of the present invention.

[0037] Figure 6 It is a cross-sectional schematic diagram of an intermediate product after solder paste according to an embodiment of the present invention is affixed to a first hole and a second hole and affixed to a first chip and a conductive block.

[0038] Figure 7 It is a cross-sectional schematic diagram of an intermediate product after plastic packaging of a first chip and a conductive block according to an embodiment of the present invention.

[0039] Figure 8 It is a cross-sectional schematic diagram of an intermediate product after debonding, flipping and mounting a first copper layer on a first plastic packaging layer according to an embodiment of the present invention.

[0040] Fig. 9 It is a cross-sectional schematic diagram of an intermediate product after the second chip according to an embodiment of the present invention is mounted on the first redistribution layer through the insulating layer.

[0041] Fig.10It is a cross-sectional schematic diagram of an intermediate product after the second chip is plastic-sealed and the second copper layer is mounted according to an embodiment of the present invention.

[0042] Fig.11 It is a cross-sectional schematic diagram of an intermediate product after the third hole position and the fourth hole position are formed according to an embodiment of the present invention.

[0043] Fig.12 It is a cross-sectional schematic diagram of an intermediate product after manufacturing a first seed layer and a second seed layer according to an embodiment of the present invention.

[0044] Fig.13 It is a cross-sectional schematic diagram of an intermediate product after manufacturing the second redistribution layer and the third redistribution layer according to an embodiment of the present invention.

[0045] Fig.14 It is a cross-sectional schematic diagram of an intermediate product after manufacturing the third plastic sealing layer and the fourth plastic sealing layer according to an embodiment of the present invention.

[0046] Fig.15 It is a cross-sectional schematic diagram of a product obtained after a fifth hole is opened and a conductive end is manufactured according to an embodiment of the present invention.

[0047] In the figure:

[0048] 1. Carrier; 21. Conductive layer; 22. First redistribution layer; 3. Solder mask layer; 4. Solder paste; 5. First chip; 6. Conductive block; 7. First plastic layer; 8. Second chip; 9. Insulation layer; 10. Second plastic layer; 11. Second redistribution layer; 12. Third redistribution layer; 13. First copper layer; 14. Second copper layer; 15. First seed layer; 16. Second seed layer; 17. Third plastic layer; 18. Fourth plastic layer; 19. Conductive terminal. DETAILED DESCRIPTION

[0049] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0050] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on this patent; in order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0051] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as a limitation on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0052] In the description of the present invention, unless otherwise clearly specified and limited, if the term "connection" or the like appears to indicate the connection relationship between components, the term should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] In this embodiment, the first chip 5 is a chip with a double-sided I / O port, for example, the first chip 51 is a MOS chip but not limited to a MOS chip; the second chip 8 is a chip with a single-sided I / O port, for example, the second chip 8 is a controller chip but not limited to a controller chip; next, taking the MOS chip and the controller chip as an example, the technical solution of the present invention is described in detail.

[0054] like Figure 1 This embodiment discloses a method for preparing a low-thickness 3D stacked packaging structure, comprising the following steps:

[0055] S10, Reference Figure 3-5 , providing a carrier board 1, and sequentially pasting a conductive layer 21 and a solder resist layer 3 on one side of the carrier board 1 along the thickness direction thereof, and performing a hole opening process on the solder resist layer 3 to form a first hole position and a second hole position that partially expose the conductive layer 21; wherein the material of the carrier board 1 may be one of BT (Bismaleimide Triazine Resin), FR4, FR5, PP, EMC, ABF or PI materials, but is not limited thereto; the opening position and number of the first hole position correspond one-to-one with the position and number of the first chip 5 to be installed, and the opening position and number of the second hole position correspond one-to-one with the position and number of the conductive block 6 to be installed; the material of the solder resist layer 3 is green oil, i.e., acrylic oligomer, which is a liquid photoresist, and the solder resist layer 3 is formed after curing, and the first hole position and the second hole position are formed by exposing the opening holes according to the designed positions of the first chip 5 and the conductive block 6;

[0056] S20, Reference Figure 6 , apply solder paste 4 to the first hole and the second hole respectively; mount a first chip 5 with a double-sided I / O port on the solder paste 4 corresponding to the first hole and mount a conductive block 6 on the solder paste 4 corresponding to the second hole, refer to Figure 7 , the first chip 5 and the conductive block 6 are plastic-sealed to form a first plastic-sealing layer 7; the solder paste 4 is used to preliminarily fix the first chip 5 and the conductive block 6, and then further protect and fix them through the first plastic-sealing layer 7, wherein the solder paste 4 has a conductive effect on the first chip 5 and the conductive block 6;

[0057] S30, Reference Figure 8 , debonding and flipping the semi-finished product over to fix it, opening the conductive layer 21 to form a first redistribution layer 22; wherein the conductive layer 21 is opened by etching with a cover hole method, specifically comprising: making a photosensitive film on the conductive layer 21, removing part of the photosensitive film by exposure and development, so that the conductive layer 21 is partially exposed, and then etching the exposed part of the conductive layer 21 to complete the opening and form the first redistribution layer 22; finally removing the remaining photosensitive film;

[0058] S40, Reference Fig. 9 and Fig.10 , providing a second chip 8 with a single-sided I / O port, attaching the second chip 8 to a side of the conductive layer 21 away from the first chip 5 through an insulating layer 9, and performing plastic sealing on the second chip 8 to form a second plastic sealing layer 10;

[0059] S50, Reference Figure 11-15 , respectively make a second redistribution layer 11 connecting the I / O port of the first chip 5 facing away from the solder resist layer 3 and the conductive block 6, and a third redistribution layer 12 connecting the I / O port of the second chip 8 and the first redistribution layer 22, and plastic-encapsulate the second redistribution layer 11 and the third redistribution layer 12 and electrically lead them out.

[0060] In this embodiment, the I / O port of the second chip 8 is connected to the first rewiring layer 22 through the third rewiring layer 12, and the first rewiring layer 22 is connected to the conductive block 6 through the solder paste 4, and the conductive block 6 is connected to the I / O port on one side of the first chip 5 through the second rewiring layer 11, and the I / O port on the other side of the first chip 5 is connected to the first rewiring layer 22 through the solder paste 4. After the second rewiring layer 11 and the third rewiring layer 12 are electrically led out, the 3D stacking package of the first chip 5 and the second chip 8 is realized. This embodiment adopts the two-sided fan-out rewiring technology, which can greatly reduce the package thickness and the on-resistance, shorten the physical connection, and for the problem of through-hole electroplating with a high aspect ratio, the method of pre-implanting the conductive block 6 can reduce the difficulty of electroplating and improve the product yield.

[0061] Furthermore, in order to improve the connection stability between the second redistribution layer 11 and the first chip 5 and the conductive block 6, in step S20 of this embodiment, after the first plastic encapsulation layer 7 is manufactured, the first copper layer 13 is also mounted on the first plastic encapsulation layer 7 ( Figure 8 ).

[0062] Furthermore, in order to improve the connection stability between the third redistribution layer 12 and the second chip 8 and the first redistribution layer 22, in step S40 of this embodiment, after the second plastic encapsulation layer 10 is manufactured, a second copper layer 14 is mounted on the second plastic encapsulation layer 10 ( Fig.10 ).

[0063] like Figure 2 As shown, step S50 specifically includes the following steps:

[0064] S50a, reference Fig.11 , performing a hole-drilling process on the first copper layer 13 and the first plastic encapsulation layer 7 to form a third hole position for exposing the I / O port on one side of the first chip 5 and the conductive block 6, and performing a hole-drilling process on the second copper layer 14 and the second plastic encapsulation layer 10 to form a fourth hole position for exposing the I / O port of the second chip 8 and the first redistribution layer 22; specifically, performing a laser drilling process on the first copper layer 13 and the first plastic encapsulation layer 7 to form the third hole position, and performing a laser drilling process on the second copper layer 14 and the second plastic encapsulation layer 10 to form the fourth hole position;

[0065] S50b, reference Fig.12 and Fig.13 , a first seed layer 15 and a second redistribution layer 11 are sequentially formed on the surfaces of the first copper layer 13 and the third hole, and a second seed layer 16 and a third redistribution layer 12 are sequentially formed on the surfaces of the second copper layer 14 and the fourth hole; first, a first seed layer 15 is formed on the surfaces of the first copper layer 13 and the third hole, and then a conductive column is formed in the third hole, and a second redistribution layer 11 is formed on the surfaces of the first copper layer 13 and the conductive column; and a second seed layer 16 is formed on the surfaces of the second copper layer 14 and the fourth hole, and then a conductive column is formed in the fourth hole, and a third redistribution layer 12 is formed on the surfaces of the second copper layer 14 and the conductive column; wherein the methods for forming the first seed layer 15, the second seed layer 16, the second redistribution layer 11, and the third redistribution layer 12 are all conventional technical means in the art, and will not be described in detail;

[0066] S50c, reference Fig.14, plastic-encapsulating the second redistribution layer 11 to form a third plastic-encapsulation layer 17 to protect the second redistribution layer 11, and plastic-encapsulating the third redistribution layer 12 to form a fourth plastic-encapsulation layer 18 to protect the third redistribution layer 12;

[0067] S50d, reference Fig.15 , the third plastic encapsulation layer 17 is processed with a hole to form a fifth hole that partially exposes the second redistribution layer 11, and a conductive terminal 19 is made in the fifth hole to complete the packaging; specifically, the third plastic encapsulation layer 17 is processed with a laser drilling method to form a fifth hole, and then a copper layer is electroplated on the surface of the fifth hole, and then a tin layer is electroplated on the surface of the copper layer, and the copper layer and the tin layer of the fifth hole are filled to form the conductive terminal 19, which is used to electrically lead out the first chip 5 and the second chip 8. The copper layer can improve the bonding strength between the tin layer and the second redistribution layer 11.

[0068] Optionally, the first plastic sealing layer 7 , the second plastic sealing layer 10 , the third plastic sealing layer 17 and the fourth plastic sealing layer 18 are made of the same material, which may include any one of polyimide, silica gel and EMC (Epoxy Molding Compound), and EMC is preferred in this embodiment.

[0069] Optionally, the material of the conductive block 6 in this embodiment is Cu, Ag or Au.

[0070] like Fig.15 As shown, this embodiment also provides a low-thickness 3D stacked packaging structure prepared by the preparation method of the above embodiment, including:

[0071] A solder resist layer 3 and a first redistribution layer 22 located on one side of the solder resist layer 3, wherein the solder resist layer 3 is provided with first holes and second holes extending therethrough along a thickness direction thereof at intervals;

[0072] A first plastic encapsulation layer 7 located on a side of the solder resist layer 3 away from the first redistribution layer 22, a first chip 5 with a double-sided I / O port encapsulated in the first plastic encapsulation layer 7 and attached to the first hole position through solder paste 4, and a conductive block 6 attached to the second hole position through solder paste 4, wherein the first plastic encapsulation layer 7 is provided with a third hole position for exposing the I / O port of the first chip 5 facing away from the side of the solder resist layer 3 and the conductive block 6;

[0073] A second redistribution layer 11 is located on the first plastic packaging layer 7 and connected to the conductive block 6 through the conductive pillars in the third holes;

[0074] A second plastic encapsulation layer 10 and a second chip 8 having a single-sided I / O port located on a side of the first redistribution layer 22 away from the first chip 5, wherein the second chip 8 is encapsulated in the second plastic encapsulation layer 10 with its back facing the first chip 5 and is attached to the first redistribution layer 22 through an insulating layer 9, and a fourth hole is provided in the second plastic encapsulation layer 10 for exposing the I / O port of the second chip 8 and the first redistribution layer 22;

[0075] The third redistribution layer 12 is located on the second plastic packaging layer 10 and is connected to the first redistribution layer 22 through the conductive pillars in the fourth holes.

[0076] In this embodiment, the first chip 5 is a MOS chip with a double-sided I / O port, and its I / O port on one side is connected to the first redistribution layer 22 through the solder paste 4 in the first hole position on the solder resist layer 3, and the first redistribution layer 22 is connected to the conductive block 6 and the second redistribution layer 11 through the solder paste 4 at the second hole position, and the I / O port on the other side of the first chip 5 is connected to the second redistribution layer 11 through the conductive column at the third hole position; the second chip 8 is a controller chip, which is attached to the first chip 5 through the insulating layer 9, and its I / O port is located on the side away from the first chip 5. The I / O port is connected to the third redistribution layer 12 and the first redistribution layer 22 in sequence through the conductive column at the fourth hole position, so as to be electrically led out to the second redistribution layer 11. The low-thickness 3D stacked packaging structure of this embodiment has a low thickness, which effectively shortens the physical connection between chips, and can effectively solve the problem of deep hole electroplating with a high aspect ratio. By pre-implanting the conductive block 6, the difficulty of electroplating can be greatly reduced, and the product yield can be improved.

[0077] In this embodiment, the number of the first chip 5 , the second chip 8 and the conductive block 6 is not limited, and the specific number depends on the design.

[0078] The low-thickness 3D stacked package structure further includes a first copper layer 13 and a second copper layer 14, wherein the first copper layer 13 is located on the first plastic encapsulation layer 7, and the first copper layer 13 and the first plastic encapsulation layer 7 are both provided with the third hole position, and the second copper layer 14 is located on the second plastic encapsulation layer 10, and the second copper layer 14 and the second plastic encapsulation layer 10 are both provided with the fourth hole position. By providing the first copper layer 13, the bonding force between the second redistribution layer 11 and the conductive pillar at the third hole position can be effectively improved, and the conductivity can be improved; by providing the third redistribution layer 12, the bonding force between the third redistribution layer 12 and the conductive pillar at the fourth hole position can be effectively improved, and the conductivity can be improved.

[0079] The low-thickness 3D stacked package structure further includes a first seed layer 15 and a second seed layer 16, wherein the first seed layer 15 is located on the surface of the third hole and the first copper layer 13, and the second seed layer 16 is located on the surface of the fourth hole and the second copper layer 14. The first seed layer 15 is located on the surface of the first copper layer 13 and the third hole, which can further improve the electrical connection stability between the second redistribution layer 11 and the I / O port of the first chip 5 and the conductive pillar at the third hole; the second seed layer 16 is located on the surface of the second copper layer 14 and the fourth hole, which can further improve the electrical connection stability between the third redistribution layer 12 and the second chip 8 and the conductive pillar at the fourth hole.

[0080] The first seed layer 15 and the second seed layer 16 both include a titanium metal layer and a copper metal layer located on the titanium metal layer.

[0081] Of course, the first seed layer 15 and the second seed layer 16 of the present embodiment are not limited to a two-layer structure (titanium metal layer, copper metal layer), and may also be a single layer, two layers or a multilayer structure of more than two layers. The materials of the first seed layer 15 and the second seed layer 16 are also not limited to a stacked combination of two single metal materials, and may also be a single metal material, or an alloy material, as long as the redistribution layer can be stably attached to the corresponding plastic packaging layer, and the details will not be repeated.

[0082] Furthermore, the low-thickness 3D stacked packaging structure also includes a third plastic encapsulation layer 17, a fourth plastic encapsulation layer 18 and a conductive terminal 19, wherein the third plastic encapsulation layer 17 is located on the first plastic encapsulation layer 7 and covers the second redistribution layer 11, the third plastic encapsulation layer 17 is provided with a fifth hole for partially exposing the second redistribution layer 11, the conductive terminal 19 is located in the fifth hole, and the fourth plastic encapsulation layer 18 is located on the second plastic encapsulation layer 10 and covers the third redistribution layer 12. The conductive terminal 19 connected to the second redistribution layer 11 is electroplated at the fifth hole to achieve electrical lead-out of the first chip 5 and the second chip 8.

[0083] Furthermore, the conductive end 19 includes a copper layer located on the surface of the fifth hole and a tin layer located on the copper layer.

[0084] It should be noted that the above specific implementations are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art should understand that various modifications, equivalent substitutions, changes, etc. can be made to the present invention. However, as long as these changes do not deviate from the spirit of the present invention, they should be within the scope of protection of the present invention. In addition, some terms used in the specification and claims of this application are not restrictive, but are only for the convenience of description.

Claims

1. A method for preparing a low-thickness 3D stacked packaging structure, It is characterized in that The following steps are involved: S10, providing a carrier board, sequentially attaching a conductive layer and a solder resist layer to one side of the carrier board along the thickness direction thereof, and performing hole processing on the solder resist layer to form a first hole position and a second hole position that partially expose the conductive layer; S20, applying solder paste to the first hole position and the second hole position respectively; mounting a first chip having a double-sided I / O port on the solder paste position corresponding to the first hole position and mounting a conductive block on the solder paste position corresponding to the second hole position, plastic-sealing the first chip and the conductive block to form a first plastic-sealing layer, and mounting a first copper layer on the first plastic-sealing layer; S30, debonding and flipping, and performing hole processing on the conductive layer to form a first redistribution layer; S40, providing a second chip having an I / O port, attaching the second chip to a side of the first redistribution layer away from the first chip through an insulating layer, and performing plastic packaging on the second chip to form a second plastic packaging layer; S50, respectively make a second redistribution layer connecting the I / O port of the first chip facing away from the solder resist layer and the conductive block, and a third redistribution layer connecting the I / O port of the second chip and the first redistribution layer, plastic-encapsulate the second redistribution layer and the third redistribution layer and electrically lead them out.

2. The method for preparing the low-thickness 3D stacked packaging structure according to claim 1, It is characterized in that In step S40, after the second plastic packaging layer is manufactured, a second copper layer is mounted on the second plastic packaging layer.

3. The method for preparing the low-thickness 3D stacked packaging structure according to claim 2, It is characterized in that Step S50 specifically includes the following steps: S50a, performing hole processing on the first copper layer and the first plastic encapsulation layer to form a third hole position for exposing the I / O port on one side of the first chip and the conductive block, and performing hole processing on the second copper layer and the second plastic encapsulation layer to form a fourth hole position for exposing the I / O port of the second chip and the first redistribution layer; S50b, sequentially forming a first seed layer and a second redistribution layer on the surfaces of the first copper layer and the third hole, and sequentially forming a second seed layer and a third redistribution layer on the surfaces of the second copper layer and the second plastic packaging layer; S50c, performing plastic sealing on the second redistribution layer to form a third plastic sealing layer, and performing plastic sealing on the third redistribution layer to form a fourth plastic sealing layer; S50d, drilling the third plastic packaging layer to form a fifth hole for partially exposing the second redistribution layer, making a conductive terminal in the fifth hole, and completing the packaging.

4. The method for preparing a low-thickness 3D stacked packaging structure according to claim 1, It is characterized in that The conductive block is made of Cu, Ag or Au.

5. A low-thickness 3D stacked packaging structure prepared by the preparation method according to any one of claims 1 to 4, It is characterized in that include: A solder resist layer and a first redistribution layer located on one side of the solder resist layer, wherein the solder resist layer is provided with first holes and second holes extending therethrough along a thickness direction thereof at intervals; A first plastic encapsulation layer located on a side of the solder resist layer away from the first redistribution layer, a first chip with a double-sided I / O port encapsulated in the first plastic encapsulation layer and attached to the first hole position through solder paste, and a conductive block attached to the second hole position through solder paste, wherein the first plastic encapsulation layer is provided with a third hole position for exposing the I / O port of the first chip on the side facing away from the solder resist layer and the conductive block; A first copper layer, wherein the first copper layer is located on the first plastic sealing layer, and the first copper layer and the first plastic sealing layer are both provided with the third hole; A second redistribution layer is located on the first plastic packaging layer and is connected to the conductive block through the conductive pillar in the third hole; A second plastic encapsulation layer and a second chip having a single-sided I / O port located on a side of the first redistribution layer away from the first chip, the second chip being encapsulated in the second plastic encapsulation layer with its back facing the first chip and attached to the first redistribution layer through an insulating layer, the second plastic encapsulation layer being provided with a fourth hole for exposing the I / O port of the second chip and the first redistribution layer; A third redistribution layer is located on the second plastic packaging layer and is connected to the first redistribution layer through the conductive pillars in the fourth holes; The first plastic sealing layer and the second plastic sealing layer are made of the same material, including any one of polyimide, silicone and EMC.

6. The low-thickness 3D stacked package structure according to claim 5, It is characterized in that It also includes a second copper layer, which is located on the second plastic packaging layer, and the second copper layer and the second plastic packaging layer are both provided with the fourth hole.

7. The low-thickness 3D stacked package structure according to claim 6, It is characterized in that It also includes a first seed layer and a second seed layer, wherein the first seed layer is located at the third hole position and a surface of the first copper layer, and the second seed layer is located at the fourth hole position and a surface of the second copper layer.

8. The low-thickness 3D stacked package structure according to claim 6, It is characterized in that It also includes a third plastic sealing layer, a fourth plastic sealing layer and a conductive end, the third plastic sealing layer is located on the first plastic sealing layer and covers the second redistribution layer, the third plastic sealing layer is provided with a fifth hole for partially exposing the second redistribution layer, the conductive end is located in the fifth hole, and the fourth plastic sealing layer is located on the second plastic sealing layer and covers the third redistribution layer.

9. The low-thickness 3D stacked package structure according to claim 8, It is characterized in that The conductive end includes a copper layer located on the surface of the fifth hole and a tin layer located on the copper layer.

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