Storage devices and storage systems

Abstract

A storage device is provided, comprising: a power management integrated circuit chip; a plurality of non-volatile memories configured to receive power from the power management integrated circuit chip; and a controller configured to control the non-volatile memories, wherein the controller checks the state of power during read operations and write operations of the non-volatile memories, and when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode with respect to read operations and write operations on all non-volatile memories.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2018-0166414 filed on December 20, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a storage device and a storage system. More particularly, the present disclosure relates to a storage device and a storage system including a power detection mode in which hardware and software operate in conjunction with each other. Background Art

[0004] Flash memory is used as a storage device in various fields due to its advantages such as non-volatility, large capacity and low noise. Storage devices based on flash memory are called solid-state drives (SSDs). SSDs include multiple semiconductor components such as controllers and flash memories, and the semiconductor components are mounted on a printed circuit board and constitute a semiconductor package. In storage devices such as SSDs, it is very important for the reliability of products to find defect factors such as power failures and find solutions accordingly. However, with the increase in the integration of storage devices caused by the development of semiconductor manufacturing technology, it is difficult to prevent all possible defects in advance. Summary of the invention

[0005] According to an aspect of the present disclosure, a storage device is provided with a power failure detection mode in which hardware and software are associated with each other to accurately detect a failure factor that may occur during an operation of the storage device.

[0006] According to another aspect of the present disclosure, a storage system implements a power failure detection mode in which hardware and software are associated with each other to accurately detect a failure factor that may occur during an operation of a storage device in the storage system.

[0007] According to another aspect of the present disclosure, a storage device includes a power management integrated circuit chip, a plurality of non-volatile memories, and a controller. The non-volatile memories are configured to receive power from the power management integrated circuit chip. The controller is configured to control the non-volatile memories. The controller checks the state of power during a read operation and a write operation on the non-volatile memories, and when a power failure is detected in at least one of the non-volatile memories, implements a power failure detection mode for the read operation and the write operation on all the non-volatile memories.

[0008] According to another aspect of the present disclosure, a storage system includes a plurality of storage devices and a host. Each storage device includes a power management integrated circuit chip, a nonvolatile memory, and a controller. The nonvolatile memory of each storage device receives power from the power management integrated circuit chip. The controller of each storage device is configured to control the nonvolatile memory of each storage device. The host configures multi-interface communication with the storage device. The host checks the state of power during a read operation and a write operation on the nonvolatile memory included in the storage device, and when a power failure is detected in at least one of the nonvolatile memories, a power failure detection mode is implemented for the read operation and the write operation on all the nonvolatile memories.

[0009] According to another aspect of the present disclosure, a storage system includes multiple storage devices, a contact module and a host. Each storage device includes a power management integrated circuit chip, a non-volatile memory and a controller. The non-volatile memory of each storage device receives power from the power management integrated circuit chip of each storage device. The controller of each storage device is configured to control the non-volatile memory of each storage device. The contact module is capable of installing the storage device. The host is configured to communicate with the storage device. While performing read operations and write operations on the non-volatile memory included in the storage device, the host switches the state of power to a test mode and collects information about whether a power failure detection mode is implemented for read operations and write operations on the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A block diagram of a computing system including a storage device according to an example embodiment is shown;

[0012] Figure 2 It is shown that there is installed Figure 1 Schematic diagram of the printed circuit boards of various hardware;

[0013] Figure 3 shows a block diagram of a storage device according to an example embodiment;

[0014] Figure 4 Shown is a diagram for describing Figure 3 A block diagram of a non-volatile memory of a storage device;

[0015] Figure 5A and Figure 5B A flow chart showing a read / write operation in a storage device according to an example embodiment;

[0016] Figure 6A flow chart illustrating an alarm signal mode in a storage device according to an example embodiment;

[0017] Figure 7 A block diagram of a storage system according to an example embodiment is shown;

[0018] Figure 8 A block diagram of a storage device included in a storage system according to an example embodiment is shown;

[0019] 9A to 9C is a conceptual diagram illustrating a communication channel between a host and a storage device in a storage system according to an example embodiment;

[0020] Fig. 10A and Fig. 10B A flow chart illustrating program code for read / write operations in a storage system according to an example embodiment;

[0021] Fig.11 A flowchart of determining a failure of a storage device by using a storage system according to an example embodiment is shown;

[0022] Fig.12 A block diagram showing a server system to which a storage device according to an example embodiment may be applied;

[0023] Fig.13 A block diagram showing a server cluster to which a storage device according to an example embodiment may be applied; and

[0024] Fig.14 A block diagram of a processing system including a storage device according to an example embodiment is shown. DETAILED DESCRIPTION

[0025] Figure 1 A block diagram of a computing system including a storage device according to an example embodiment is shown.

[0026] refer to Figure 1 , each of the first storage device 110 and the second storage device 120 according to an example embodiment includes a program code for self-diagnosis in firmware and / or software.

[0027] The semiconductor devices included in the first storage device 110 and the second storage device 120 are mounted on the printed circuit board 100 of the computing system 10. After the first storage device 110 and the second storage device 120 are mounted on the printed circuit board 100, the computing system 10 may run the program code to perform self-diagnosis with respect to the first storage device 110 and the second storage device 120. A detailed description of the program code will be described below with reference to Figure 5A and Figure 5B Given.

[0028] For example, the computing system 10 may include at least one of a computer, a portable computer, a tablet computer, a workstation, a server, a mobile phone such as a smart phone, a digital camera, a device capable of sending and receiving information in a wired / wireless environment, and an electronic device constituting a home network system. The computing system 10 may include a printed circuit board 100 on which various hardware devices are mounted, a display device DD, and an input device (ID).

[0029] The first storage device 110, the second storage device 120, the host 101, the memory 102, the chipset 103, the graphics processing unit 104 (GPU), the network module 105, the input / output controller 106 (I / O controller), the connector 104a, the control connector 106a and the control connector 106b, and the power management integrated circuit chip 107 (PMIC) may be mounted in respective dedicated areas provided on the printed circuit board 100. The connector 104a, the control connector 106a and the control connector 106b may each be, for example, an input / output socket.

[0030] Printed circuit board 100 may be a motherboard or mainboard of computing system 10. Various hardware for operating computing system 10 may be mounted on printed circuit board 100. In some embodiments, printed circuit board 100 may include corresponding dedicated areas on which various hardware (e.g., semiconductor packages, semiconductor devices, passive devices, active devices, control circuits, and / or electronic circuits) may be mounted.

[0031] The printed circuit board 100 may include various wires. The various wires may electrically connect various hardware mounted on the printed circuit board 100 to each other. The various hardware mounted on the printed circuit board 100 may communicate with each other through the various wires.

[0032] The first storage device 110 may include a first controller 111 and a first nonvolatile memory 113, and the second storage device 120 may include a second controller 121 and a second nonvolatile memory 123. Of course, the number of storage devices mounted on the printed circuit board 100 is not limited to two storage devices, i.e., not limited to only the first storage device 110 and the second storage device 120.

[0033] The first controller 111 and the second controller 121 may control the first non-volatile memory 113 and the second non-volatile memory 123 according to a command of the host 101. The first controller 111 and the second controller 121 may each be a processor, such as a microprocessor or an application integrated circuit (ASIC). For example, according to a command of the host 101, the first controller 111 and the second controller 121 read or are configured to read data stored in the first non-volatile memory 113 and the second non-volatile memory 123, or program data to the first non-volatile memory 113 and the second non-volatile memory 123. In some embodiments, the first controller 111 and the second controller 121 may communicate with the host 101 via the chipset 103.

[0034] The first nonvolatile memory 113 and the second nonvolatile memory 123 may include various nonvolatile memories, such as flash memory, phase change RAM (PRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM). For ease of explanation, it is assumed that the first nonvolatile memory 113 and the second nonvolatile memory 123 are NAND flash memories. Of course, the number of nonvolatile memories mounted on the printed circuit board 100 is not limited to only two, that is, not limited to the first nonvolatile memory 113 and the second nonvolatile memory 123.

[0035] The first storage device 110 and the second storage device 120 may be used as mass storage media of the computing system 10. In some embodiments, the first non-volatile memory 113 and the second non-volatile memory 123 may constitute a redundant array of independent disks (RAID).

[0036] The first controller 111, the second controller 121, the first nonvolatile memory 113, and the second nonvolatile memory 123 of the first storage device 110 and the second storage device 120 may be mounted on the printed circuit board 100. In other words, each of the first storage device 110 and the second storage device 120 may be configured as an on-board storage medium or an on-board solid state drive (SSD).

[0037] The host 101 may perform some or all operations required for the computing system 10 to operate. For example, the host 101 may interpret commands input by a user, and perform calculations and process data based on the interpreted commands. The host 101 may be referred to as a central processing unit (CPU), and may include one or more processors that execute instructions from the memory 102.

[0038] The memory 102 may be used as a main memory of the computing system 10. The memory 102 may include a volatile memory such as a DRAM, an SRAM, and a double data rate (DDR) DRAM. In some embodiments, the memory 102 may be mounted on the printed circuit board 100 and electrically connected to the host 101 via a line provided on the printed circuit board 100.

[0039] The chipset 103 is a device that controls various hardware included in the computing system 10 according to a command of the host 101. For example, the chipset 103 may control the first storage device 110, the second storage device 120, the graphics processing unit 104, the network module 105, and the input / output controller 106, etc. according to a command of the host 101. The control of the chipset 103 may include: initiating an operation, terminating an operation, coordinating an operation, selecting an operation between multiple operations, or otherwise performing control consistent with the description herein.

[0040] In some embodiments, the chipset 103 may be mounted on the printed circuit board 100 and electrically connected to various hardware via wires provided on the printed circuit board 100. In addition, the chipset 103 may communicate with various hardware via a preset interface. For example, the preset interface may be configured to include at least one of various interfaces such as USB, PCI, ATA, SCSI, ESDI, IDE, Firewire, UFS, and I2C. As long as the host 101 can be configured to communicate with the storage device via multiple interfaces implemented by the chipset 103, it can be said that the host 101 is configured with multiple interface communication (MIC) with the storage device.

[0041] The graphics processing unit 104 may convert the calculation result or data processed by the host 101 into a video signal. The converted video signal may be output via the display device DD. In some embodiments, the graphics processing unit 104 may be mounted on the printed circuit board 100 and connected to the chipset 103 and the connector 104a via a line provided on the printed circuit board 100. In some embodiments, the graphics processing unit 104 may be included in the host 101. In addition, the connector 104a may be directly connected to the display device DD.

[0042] The network module 105 supports wired or wireless communication with the outside of the computing system 10. For example, the network module 105 can support wireless communication such as CDMA, GSM, WCDMA, TDMA, LTE, Bluetooth, and WiFi. In some embodiments, the network module 105 can be mounted on the printed circuit board 100 and connected to the chipset 103 via a line provided on the printed circuit board 100.

[0043] The input / output controller 106 may process information input from an input device (ID) or the control connector 106a and the control connector 106b. The input / output controller 106 may be connected to and manage the control connector 106a and the control connector 106b. In some embodiments, the input / output controller 106 may be mounted on the printed circuit board 100 and connected to the control connector 106a and the control connector 106b via a line provided on the printed circuit board 100. For example, the control connector 106a and the control connector 106b may include at least one of various input / output terminals such as a PS2 port, a PCI slot, a DIMM slot, a USB terminal, an RGB port, a DVI port, and an HDMI port.

[0044] The power management integrated circuit chip 107 can supply power to various hardware of the computing system 10 based on the externally supplied power. For example, the power management integrated circuit chip 107 can supply power to the first storage device 110 and the second storage device 120. In some embodiments, the power management integrated circuit chip 107 can provide dedicated power for the first storage device 110 and the second storage device 120.

[0045] The power management integrated circuit chip 107 according to the present disclosure may include a power failure detection circuit capable of detecting an abnormal output of a power supply rail, and provide the abnormal output state detected by the power failure detection circuit to the first storage device 110 and the second storage device 120 by using a side band protocol. Therefore, a power supply failure (e.g., interruption) may be detected in several ways by including several different elements of the power management integrated circuit chip 107.

[0046] Each of the first storage device 110 and the second storage device 120 according to the present disclosure may include power diagnostic firmware and / or power diagnostic software (hereinafter referred to as program code). The program code may include information or a program for checking the power status of the first storage device 110 and the second storage device 120, or may include information or a program required to supply power normally. In some embodiments, the program code may be stored in the first controller 111 and the second controller 121 in the form of power diagnostic firmware, or in the first non-volatile memory 113 and the second non-volatile memory 123 in the form of power diagnostic software. As explained herein, the program code may be run or otherwise used as a basis for implementing different modes for the first storage device 110 and the second storage device 120. The different modes may include power failure detection modes, test modes, and other types of modes described herein. Therefore, when the read voltage and the write voltage of the first non-volatile memory 113 provided to the first storage device 110 are temporarily interrupted, the first controller 111 may detect a power failure or otherwise determine a power failure. When the read voltage and the write voltage provided to the second nonvolatile memory 123 of the second storage device 120 are temporarily interrupted, the second controller 121 may detect a power failure or otherwise determine a power failure.

[0047] The first storage device 110 and the second storage device 120 can perform self-diagnosis on power failure based on program code. For example, the first controller 111 and the second controller 121 can perform self-diagnosis by running power diagnosis firmware. When the first controller 111 detects a power failure when the read voltage and / or write voltage provided to the non-volatile memory is temporarily interrupted, and / or when the second controller 121 detects a power failure when the read voltage and / or write voltage provided to the non-volatile memory is temporarily interrupted, self-diagnosis can cause the power failure to be detected. On the other hand, when no power failure is detected, read operations and write operations are performed, such as by normal processing.

[0048] The self-diagnosis of the first storage device 110 and the second storage device 120 according to the present disclosure may be performed during a read / write operation of the computing system 10. For example, during a process for reading / writing data from / to the first nonvolatile memory 113 and the second nonvolatile memory 123, the first controller 111 and the second controller 121 may perform self-diagnosis of a power failure based on a program code.

[0049] Finally, according to the present disclosure, it can be determined whether there is a power failure (e.g., has occurred and / or is occurring) in the first storage device 110 and the second storage device 120 during the read / write operation of the computing system 10. As a result, the reliability of the first storage device 110 and the second storage device 120 can be further ensured. Therefore, the first storage device 110 and the second storage device 120 can be provided with improved reliability.

[0050] Figure 2 It is shown that there is installed Figure 1 Schematic diagram of the printed circuit board for the various hardware.

[0051] Reference together Figure 1 and Figure 2 , the computing system 10 may include various hardware mounted on the printed circuit board 100 .

[0052] As described above, various hardware included in the computing system 10 may be respectively mounted on dedicated areas included in the printed circuit board 100. For example, the printed circuit board 100 may include a dedicated area 101R for the host 101, a dedicated area 102R for the memory 102, a dedicated area 103R for the chipset 103, a dedicated area 107R for the power management integrated circuit chip 107, a dedicated area 110R for the first storage device 110, and a dedicated area 120R for the second storage device 120. The dedicated areas may be electrically connected to each other through various lines provided on the printed circuit board 100.

[0053] The first controller 111 and the first non-volatile memory 113 of the first storage device 110 according to the present disclosure may be configured as an integrated package. Similarly, the second controller 121 and the second non-volatile memory 123 of the second storage device 120 may be configured as an integrated package. An integrated package may refer to an integrated package, an overall package, a package with a single housing, a package with elements manufactured or otherwise constructed together with connected or otherwise attached elements, and the like.

[0054] In some embodiments, each of the first storage device 110 and the second storage device 120 may be provided as a ball grid array type solid state drive. The ball grid array may also be referred to as BGA by the acronym. For example, the first storage device 110 may include a solder ball 110B as an external connection terminal, and the first storage device 110 may be mounted on the printed circuit board 100 so that a ball land 110BL located in the dedicated area 110R is connected to the solder ball 110B. Similarly, the second storage device 120 may be mounted on the printed circuit board 100. The first storage device 110 and the second storage device 120 may be mounted on the printed circuit board 100 using surface mounting technology.

[0055] Although not shown, the first storage device 110 and the second storage device 120 may further include other nonvolatile memories in addition to the first nonvolatile memory 113 and the second nonvolatile memory 123. In addition, the first storage device 110 and the second storage device 120 may be respectively mounted on different surfaces of the printed circuit board 100. For example, the first storage device 110 may be mounted on the top surface of the printed circuit board 100, and the second storage device 120 may be mounted on the bottom surface, which is a surface opposite to the top surface.

[0056] The first storage device 110 and the second storage device 120 may transmit the self-diagnosis result performed using the program code to the host 101 by using the sideband protocol. In some embodiments, the sideband protocol may further include communication protocols such as I2C (Inter-Integrated Circuit Protocol), MCTP (Management Component Transport Protocol), and SMBus (System Management Bus Protocol) provided in addition to the communication protocols provided for normal operation.

[0057] In some embodiments, the program code may include information for performing a series of operations for detecting whether there is a power failure (e.g., has occurred or is occurring) of the first storage device 110 and the second storage device 120, or whether there is a power failure (e.g., has occurred or is occurring) in the configuration included in the first storage device 110 and the second storage device 120. The program code may include information for sending the result of the self-diagnosis to the host 101. The first storage device 110 and the second storage device 120 according to the present disclosure may perform a self-diagnosis operation based on the power supplied from the power management integrated circuit chip 107 by using the program code. Therefore, as described above with respect to the power management integrated circuit chip 107, a power supply failure (e.g., interruption) may be detected in several ways by several different elements, including the power management integrated circuit chip 107, and also including program code stored in the first non-volatile memory 113 and the second non-volatile memory 123 and executed or otherwise implemented by the first controller 111 and the second controller 121. Therefore, in the first storage device 110 and the second storage device 120 , the detection may be performed by the first controller 111 and the second controller 121 , respectively.

[0058] Although not shown, the first storage device 110 and the power management integrated circuit chip 107 according to the present disclosure may be configured as an integrated package. Likewise, the second storage device 120 and the power management integrated circuit chip 107 may be configured as an integrated package. As described above, the integrated package may refer to an integrated package, an overall package, a package with a single housing, a package with elements manufactured or otherwise constructed together with connected or otherwise attached elements, and the like.

[0059] In addition, when the first controller 111 and the first non-volatile memory 113 are provided as an integrated package, the power management integrated circuit chip 107 and the integrated package can be on or mounted on one printed circuit board. When the second controller 121 and the second non-volatile memory 123 are provided as an integrated package, the same is or can be so that the power management integrated circuit chip 107 and the integrated package can be on or mounted on one printed circuit board. In addition, the power management integrated circuit chip 107 can be mounted on one printed circuit board with multiple integrated packages such as a first integrated package having the first controller 111 and the first non-volatile memory 113 and a second integrated package having the second controller 121 and the second non-volatile memory 123.

[0060] Figure 3 A block diagram of a storage device according to an example embodiment is shown.

[0061] refer to Figure 3 , the first storage device 110 may include a first controller 111 , a plurality of nonvolatile memories 113 - 1 to 113 -N, and a volatile memory 115 , where N is a positive integer greater than or equal to 2.

[0062] In response to a request from the host 101 connected to the first storage device 110 , the first controller 111 may control a read operation, a write operation, an erase operation, and / or an initialization operation with respect to the nonvolatile memories 113 - 1 to 113 -N.

[0063] The volatile memory 115 may temporarily store data provided from the host 101 or data read from the nonvolatile memories 113-1 to 113-N. The volatile memory 115 may store metadata or cache data to be stored in the nonvolatile memories 113-1 to 113-N. The volatile memory 115 may include, for example, DRAM, SRAM, etc.

[0064] The nonvolatile memories 113-1 to 113-N are used as storage media of the first storage device 110. Each of the nonvolatile memories 113-1 to 113-N may be, for example, a NAND flash memory. The nonvolatile memories 113-1 to 113-N may be connected to the first controller 111 through a channel.

[0065] Each of the nonvolatile memories 113-1 to 113-N may include a memory cell array 113CA and a set register 113SR. The set register 113SR may set initialization information indicating a product specification of a corresponding nonvolatile memory read by an operation for reading the initialization information during a boot time. In addition, the set register 113SR may set control signals and data received from the first controller 111 for operation options, functions, characteristics, and operation modes of the corresponding nonvolatile memory.

[0066] Each of the nonvolatile memories 113-1 to 113-N may store protection information for prohibiting write / erase operations, trimming data for trimming an operation voltage level in an operation mode, column repair information for repairing a failed bit line, and bad block information including bad memory cells in a portion of the memory cell array 113CA as initialization information. The trimming data is data that is used not only to set an operation mode of each of the plurality of nonvolatile memories 113-1 to 113-N, that is, to set voltage adjustment in a read operation, a write operation, and an erase operation, but also to adjust a sense amplifier or a page buffer and optimize a reference cell.

[0067] Each of the non-volatile memories 113-1 to 113-N may store power diagnostic software as a program code in a portion of the storage cell array 113CA, the power diagnostic software including information for performing a series of operations for detecting power failures. The program code may include information for sending the result of the self-diagnosis to the host 101. In other words, the first storage device 110 according to the present disclosure may perform a self-diagnosis operation by using the program code.

[0068] Figure 4 Shown is a diagram for describing Figure 3 A block diagram of a nonvolatile memory of a storage device.

[0069] refer to Figure 4 , the first nonvolatile memory 113 may include a memory cell array 113CA, a control circuit 113CC, an address decoder 113AD, a read circuit 113RC, and a voltage generator 113VG.

[0070] Although not shown, the first nonvolatile memory 113 may further include a write circuit and an input / output circuit. The write circuit may be configured as a write driver that receives data from the first controller 111 (see FIG. 1 ) through an input / output line. Figure 3 ) is provided to the input / output circuit, and the received data is stored in the memory cell array 113CA. The input / output circuit can temporarily store the data received from the first controller 111 (see Figure 3 ) provided by the first controller 111. The input / output circuit can temporarily store the read data of the first nonvolatile memory 113 and output the read data to the first controller 111 through the input / output line at a specified time (see Figure 3 ).

[0071] The memory cell array 113CA may include a plurality of memory cells. For example, the memory cells may be NAND flash memory cells. In some embodiments, the memory cell array 113CA may include a 3-dimensional memory cell array including a plurality of NAND strings NS.

[0072] The 3-dimensional memory cell array 113CA may include a monolithically-formed physical layer of the memory cell array 113CA, which includes an active region arranged on a silicon (Si) substrate and a circuit formed on or in the Si substrate. The memory cell array 113CA is three-dimensional and includes NAND strings NS arranged in a vertical direction such that at least one memory cell is located above another memory cell.

[0073] The memory cell array 113CA may include a plurality of memory blocks BLK1 to BLKn, where n is a positive integer greater than or equal to 2. Each memory block may be connected to a string selection line SSL, a word line WL, a ground selection line GSL, and a bit line BL. Each memory block may be connected to an address decoder 113AD via a string selection line SSL, a word line WL, and a ground selection line GSL, and may be connected to a read circuit 113RC via a bit line BL.

[0074] The first memory block BLK1 may include a plurality of NAND strings NS, and each of the NAND strings NS may include a string selection transistor SST, a plurality of memory cells MC, and a ground selection transistor GST. The string selection transistor SST is connected to a string selection line SSL, the memory cells MC are respectively connected to corresponding word lines WL1 to WL8, and the ground selection transistor GST is connected to a ground selection line GSL. The string selection transistors SST are respectively connected to corresponding bit lines BL1 to BLn, and the ground selection transistor GST is connected to a common source line CSL.

[0075] The number of rows and columns of the NAND string NS in the first storage block BLK1 can be increased or decreased. When the number of rows of the NAND string NS changes, the number of word lines WL can change. When the number of columns of the NAND string NS changes, the number of bit lines BL connected to the columns of the NAND string NS and the number of NAND strings NS connected to one string selection line SSL can change. The height of the NAND string NS can be increased or decreased. For example, the number of storage cells stacked on each NAND string NS can be increased or decreased.

[0076] 1-bit data may be stored in a storage cell of the first storage block BLK1. A storage cell capable of storing 1-bit data per storage cell may be referred to as a single-level cell (SLC) or a unit cell. The first storage block BLK1 may be configured as a block for storing initialization information of the first nonvolatile memory 113. In some embodiments, the storage cell of the first storage block BLK1 may store power supply diagnostic software including information for performing a series of operations for detecting power failures in the form of program code.

[0077] Each of the second to n-th memory blocks BLK2 to BLKn may include a plurality of memory cells and a plurality of selection transistors in the same manner as the first memory block BLK1. The second to n-th memory blocks BLK2 to BLKn may be configured to store the memory cells received from the first controller 111 (see Figure 3 ) The memory cells of the second memory block BLK2 to the nth memory block BLKn may include single-level cells or multi-level cells capable of storing two or more bits of data per memory cell.

[0078] The control circuit 113CC may control all operations of the first nonvolatile memory 113. The control circuit 113CC may control a read operation, a write operation, and / or an erase operation on the memory cell array 113CA based on a command, an address, and a control signal received from the first controller 111.

[0079] The control circuit 113CC may provide a row address to the address decoder 113AD, a column address to the read circuit 113RC, and a voltage control signal Cvol to the voltage generator 113VG.

[0080] The control circuit 113CC may control an operation for reading initialization information stored in the first memory block BLK1 of the memory cell array 113CA. The control circuit 113CC may control a level of a read voltage Vread required to perform an operation for reading initialization information. The control circuit 113CC may control a level of the read voltage Vread to be lower than a level of the power supply voltage VDD during the operation for reading initialization information by using a voltage control signal Cvol.

[0081] The control circuit 113CC may include a setting register 113SR configured to set initialization information read in an operation for reading initialization information. In some embodiments, the setting register 113SR may not be embedded in the control circuit 113CC.

[0082] The address decoder 113AD can select one of the memory blocks BLK1 to BLKn of the memory cell array 113CA, and can pass a word line voltage to the word line WL of the selected memory block. During a write operation, a program voltage Vpgm is supplied to the selected word line, and a pass voltage Vpass is supplied to unselected word lines. During a read operation, a read voltage Vread is supplied to the selected word line, and a pass voltage Vpass is supplied to unselected word lines.

[0083] The read circuit 113RC can read data from the second memory block BLK2 to the nth memory block BLKn of the memory cell array 113CA, and transfer the read data to the data input / output circuit, which outputs the read data to the first controller 111 (see Figure 3 ). In addition, during the operation for reading the initialization information, the read circuit 113RC may read the initialization information stored in the first memory block BLK1 of the memory cell array 113CA, and send the read initialization information to the setting register 113SR of the control circuit 113CC. The read circuit 113RC may include a page buffer or a page register for reading data, a column selection circuit for selecting a bit line BL, and the like.

[0084] The voltage generator 113VG may generate a voltage (i.e., a word line voltage) to be provided to the word line WL of the memory cell array 113CA in response to the control of the control circuit 113CC. The voltage generator 113VG may generate a program voltage Vpgm, a pass voltage Vpass, and a read voltage Vread. The voltage generator 113VG may be generated from the first controller 111 (see Figure 3 ) receives the power supply voltage VDD. In some embodiments, the voltage generator 113VG can be obtained from the power management integrated circuit chip 107 (see Figure 1 ) receives the power supply voltage VDD.

[0085] In a storage device according to the present disclosure, when a voltage glitch of from about several nanoseconds to tens of nanoseconds occurs in a programming voltage Vpgm and / or a read voltage Vread, a power failure that has occurred and / or is occurring can be detected or otherwise determined. Due to a power failure, an uncorrectable error correction code (UECC) failure may occur in a selected storage block of a storage cell array 113CA. The uncorrectable error correction code can be identified by a controller, such as a first controller 111 or a second controller 121 that runs or otherwise implements a program code stored in a first non-volatile memory 113 or a second non-volatile memory 123.

[0086] Figure 5A and Figure 5B A flow chart of a read / write operation in a storage device according to an example embodiment is shown.

[0087] Figure 5A and Figure 5B A program code S100 for a read operation and a program code S200 for a write operation are respectively shown.

[0088] The program code S100 for the read operation includes an operation for starting the read operation (operation S110), an operation for determining whether the power is normal (operation S120), an operation for performing the read operation (operation S130), and an operation for retrying to read the same page (operation S140). In other words, when the power is abnormal while attempting to read the first page or multiple first pages at S130, retry reading the first page or multiple first pages at S140. In addition, although the determination of whether the power is normal at S120 is described here as occurring before the read operation is performed at S130, the determination at S120 may be performed after S130 instead, or additionally performed after S130 and even performed again after S140.

[0089] The program code S200 for the write operation includes an operation for starting the write operation (operation S210), an operation for determining whether the power is normal (operation S220), an operation for performing the write operation (operation S230), and an operation for allocating the write (e.g., dedicating at least one address and space to the next write operation) to the next free block (operation S240). The write can be allocated by dedicating the next free block to the current or future write operation with the current or future write instruction at S240.

[0090] A read operation and a write operation may be performed in a memory cell array of a memory device. The determination of whether power is normal during the read operation and the write operation may be implemented by a power failure detection circuit and a program code.

[0091] In other words, by adopting a combination of hardware (a power failure detection circuit of a power management integrated circuit chip, and / or a controller, and / or a non-volatile memory storing program code) and software (program code), by performing self-diagnosis of power failure detection during read operations and write operations, errors in read operations and write operations caused by power failure of the storage device can be prevented in advance in a manner similar to the implementation of the defense code in the storage device.

[0092] In addition, a power failure detection circuit capable of detecting an abnormal output voltage of a power supply rail may be applied to a power management integrated circuit chip, and the abnormal output detected by the power failure detection circuit may be provided to a storage device by using a sideband protocol. In other words, a nonvolatile memory having a power failure may be identified through a side interface between the power management integrated circuit chip and a plurality of nonvolatile memories.

[0093] The program code S100 for the read operation will be described in detail. When the read operation is being performed in a plurality of non-volatile memories of the storage device, the power management integrated circuit chip detects the abnormal output voltage and determines whether the power is normal, and when the power is normal, the read operation is performed in the same manner as in the normal state. When the power is abnormal, retry reading the same page (power failure detection mode), and make a determination again whether the power is normal. In other words, the read operation can be performed continuously even during the determination of whether the power is normal (operation S120). In other words, when the power cannot be supplied smoothly, there is a high probability that the read operation will not be performed normally. Therefore, by reading the same page again, errors in the read operation caused by power failure can be prevented. In other words, when the power is abnormal while trying to read the first page or multiple first pages, retry reading the first page or multiple first pages during the read operation based on determining that the power is abnormal (S120=no).

[0094] The program code S200 for the write operation will be described in detail. When the write operation is being performed in a plurality of non-volatile memories of the storage device, the power management integrated circuit chip detects the abnormal output voltage and determines whether the power is normal, and when the power is normal, the write operation is performed in the same manner as in the normal state. When the power is abnormal, the next free block is allocated (for example, at least one address and space are dedicated to the next write operation) to write (power failure detection mode), and a determination is made again whether the power is normal. In other words, the write operation can be performed continuously even during the determination of whether the power is normal (operation S220). In other words, when the power cannot be supplied smoothly, there is a high probability that the write operation will not be performed normally. Therefore, by allocating the write (for example, at least one address and space are dedicated to the next write operation) to another block, errors in the write operation caused by power failure can be prevented. In other words, when the power is abnormal while attempting a write operation to write the first page or multiple first pages, the write to the next allocated free block is performed during the write operation based on the determination that the power is abnormal (S220=No).

[0095] In other words, the program code S100 for the read operation and the program code S200 for the write operation can minimize data loss due to external factors such as a sudden interruption of power supplied from the power management integrated circuit chip. In addition, in a state where power is unstable, the program code S100 for the read operation and the program code S200 for the write operation can improve data reliability.

[0096] In some embodiments, when a power failure is detected from at least one of the non-volatile memories, during the read operation and the write operation, the program code S100 for the read operation and the program code S200 for the write operation for the multiple non-volatile memories of the storage device can implement a power failure detection mode on all non-volatile memories. When a power failure is detected from any one of the non-volatile memories, the power failure is likely to occur in other non-volatile memories at the same time point or at adjacent time points. Therefore, in order to prevent errors in the read operation and the write operation caused by the power failure, the power failure detection mode is implemented on all non-volatile memories.

[0097] Figure 6 A flow chart illustrating an alarm signal mode in a storage device according to an example embodiment is shown.

[0098] Figure 6 An alarm signal mode S300 is shown in which, when a power failure is detected, an alarm is sent to a host in communication with a plurality of nonvolatile memories.

[0099] The alarm signal mode S300 includes operation S310 for starting power supply, operation S320 and operation S360 for determining whether the power is normal, operation S330 for performing read / write operation, operation S340 for terminating power supply, operation S350 for sending an alarm signal, and operation S370 for sending an alarm cancel signal.

[0100] As described above, a read operation and a write operation may be performed in a memory cell array of a memory device. The determination of whether power is normal during the read operation and the write operation may be implemented by a power failure detection circuit and a program code.

[0101] The alarm signal mode S300 will be described in detail. When a power failure is detected in at least one of the multiple non-volatile memories, an alarm signal is sent to the host. After sending the alarm signal, when no power failure is detected in all non-volatile memories, an alarm cancellation signal is sent to the host. The host and the non-volatile memory can constitute a multi-interface communication, thereby sharing the alarm signal for any one non-volatile memory with all non-volatile memories. That is, as long as the host can be configured to communicate with the non-volatile memory through multiple interfaces (e.g., interfaces of different types and / or instances), it can be said that the host and the non-volatile memory constitute a multi-interface communication (MIC). The host can communicate with the non-volatile memory simultaneously through multiple interfaces according to the multi-interface communication, in the same time period and / or at different times.

[0102] In addition, when a power failure is not detected in all nonvolatile memories while power is being supplied, power supply to the storage device is terminated after the read operation and the write operation are completed.

[0103] When a power failure is detected in at least one of the nonvolatile memories while read operations and write operations are performed in a plurality of nonvolatile memories of a storage device according to the present disclosure, an alarm signal is sent to a host, and a power failure detection mode regarding the read operations and the write operations can be performed on all nonvolatile memories.

[0104] The host according to the present disclosure can analyze the alarm signal and the alarm cancellation signal and determine the cause of the power failure. Specifically, the cause of the power failure can be determined by analyzing the collected information, such as the characteristics of the non-volatile memory corresponding to the alarm, the alarm occurrence frequency, the start time and end time of the alarm, and the alarm occurrence interval.

[0105] Figure 7 A block diagram of a storage system according to an example embodiment is shown.

[0106] refer to Figure 7The storage system 1000 includes a host 1100, a contact module 1120, and a test substrate 1130, on which a plurality of storage devices 20 are arranged.

[0107] The test substrate 1130 may exchange signals with the host 1100 and receive power through the contact module 1120. The test substrate 1130 includes the storage device 20, a supporter 1131, and a test terminal 1133.

[0108] The host 1100 may perform all operations required for the operation of the storage system 1000. For example, the host 1100 may interpret a command input from a user, perform a computing operation based on the interpreted instruction, or process data. The host 1100 may be referred to as a storage facility.

[0109] The chipset 1110 is a device that controls various hardware included in the storage system 1000 according to a command of the host 1100. For example, the chipset 1110 may test the operation of the storage device 20 through the test terminal 1133 according to a command of the host 1100.

[0110] The storage device 20 is connected to the test substrate 1130 via the support 1131. The test terminal 1133 is connected to a signal line capable of electrically checking each storage device 20 mounted on the test substrate 1130. The support 1131 may be provided with the test terminal 1133 on its surface. Therefore, the test terminal 1133 may be connected to the contact module 1120 to perform a failure analysis on each storage device 20. Figure 7 It is illustrated that the storage device 20 includes eight consecutively arranged M.2 type solid-state drives, but the number of the storage devices 20 arranged on the test substrate 1130 is not limited thereto.

[0111] Therefore, it is not necessary to connect the storage device 20 to the host 1100 separately during the failure analysis of the storage device 20, which can reduce the failure analysis time. In addition, when the connection between the storage device 20 and the support member 1131 is separated after the test is completed, each storage device 20 can be provided as an M.2 type solid-state drive.

[0112] Figure 8 A block diagram of a storage device included in a storage system according to example embodiments is shown.

[0113] refer to Figure 8 , the storage device 20 has a form factor of an M.2 type solid-state drive, and includes a printed circuit board 200 on which various hardware is mounted.

[0114] Generally, the form factor of an M.2 type solid-state drive defines a length 200Y of the printed circuit board 200 in the Y direction as 22 mm, and a length 200X in the X direction as 60 mm, 80 mm, or 110 mm.

[0115] As the size of an electronic device including the storage device 20 becomes smaller and a storage device 20 operating at a higher speed is required, a storage device 20 having a smaller size and supporting a high-speed interface protocol is required. Therefore, a form factor corresponding to a relatively small size has been proposed, for example, an mSATA type using a PCI Express Mini Card layout and an M.2 type having a size more flexible than that defined by the mSATA type. The M.2 type is defined as Figure 8 The small-size solid-state drive is shown, and the small-size solid-state drive may include at least one of the nonvolatile memories 210 mounted on the printed circuit board 200 .

[0116] The M.2 type may define a port 200P. The port 200P may be located on one side of the printed circuit board 200 and may include a plurality of pins for communicating with the host 1100 (see Figure 7 ). The plurality of pins may constitute an exposed pattern and include a conductive material such as copper (Cu).

[0117] In addition, the M.2 type may also define a recessed structure 200E for mounting and fixing the storage device 20 to a motherboard (or mainboard). The M.2 type may include a semicircular recessed structure 200E, and the recessed structure 200E is on the other side of the printed circuit board 200 opposite to the side of the port 200P. An exposed pattern may be formed on the edge of the recessed structure 200E, and may be connected to a conductor of the motherboard when the M.2 type is mounted on the motherboard. For example, a pattern formed on the edge of the recessed structure 200E may be connected to a conductor corresponding to a ground node of the motherboard.

[0118] The controller 201 can be configured according to the host 1100 (see Figure 7 ) to control the first non-volatile memory 211 and the second non-volatile memory 213. For example, the controller 201 may control the first non-volatile memory 211 and the second non-volatile memory 213 according to the command of the host 1100 (see Figure 7 ) command to read the data stored in the first non-volatile memory 211 and the second non-volatile memory 213.

[0119] The memory 202 may include a volatile memory such as DRAM, SRAM, and DDR DRAM. In some embodiments, the memory 202 may be mounted on the printed circuit board 200 and may be electrically connected to the controller 201 via a line provided on the printed circuit board 200 .

[0120] The power management integrated circuit chip 203 can supply power to the storage device 20 based on the externally supplied power. Figure 8 As shown, the power management integrated circuit chip 203 can provide power to the controller 201 .

[0121] 9A to 9C is a conceptual diagram illustrating a communication channel between a host and a storage device in a storage system according to example embodiments.

[0122] exist 9A to 9C In the process, the host 1100 controls the multi-interface communication channel to select Figure 7 Some of the storage devices 20 in the host 1100, and check whether a power failure occurs in the non-volatile memory 210 of the selected storage device 20. That is, the host 1100 can be configured to control the communication channel using and / or through multiple interfaces, and therefore it can be said that the multi-interface communication channel is controlled to select some of the storage devices 20 and check whether a power failure occurs in the non-volatile memory 210 of the selected storage device 20. The ability to communicate through multiple interfaces as described herein can be referred to as multi-interface communication, and the multiple interfaces can be, for example, interfaces of different types and / or instances, such as different types of interfaces implementing different standards and / or protocols. The host 1100 can communicate with the storage device 20 through multiple interfaces in the multi-interface communication in the same time period and / or at different times simultaneously.

[0123] refer to Fig. 9A , the host 1100 selects the chip select channel CS Figure 7 Some of the storage devices 20 directly perform the sending TX of the power status to the power management integrated circuit chip 203 of the selected storage device and the receiving RX of the power status from the power management integrated circuit chip 203 of the selected storage device, and use a bypass to send the power status to the controller and receive the power status from the controller.

[0124] refer to Fig. 9B , the host 1100 may include: a first channel for performing transmission TX' of the power state to the power management integrated circuit chip 203 of the selected storage device 20 and reception RX of the power state from the power management integrated circuit chip 203 of the selected storage device 20; and a second channel for performing transmission Tx of the power state to the controller 201 and reception Rx of the power state from the controller 201. The channels for transmission Tx and transmission Tx' may be selected by a relay or a switch. In other words, the first channel and the second channel may include the same interface communication channel.

[0125] refer to Fig. 9C, the host 1100 may include: a first channel for communicating with the power management integrated circuit chip 203 of the selected storage device 20 according to the I2C interface; and a second channel for performing transmission Tx of the power state to the controller 201 and reception Rx of the power state from the controller 201. The first channel and the second channel may be selected by the chipset 1110. In other words, the first channel and the second channel may include different interface communication channels, and the communication may therefore be characterized as multi-interface communication.

[0126] Fig. 10A and Fig. 10B A flow chart of a program code for read / write operations in a storage system according to an example embodiment is shown.

[0127] Most operations constituting the program code S400 for the read operation and the program code S500 for the write operation described below are similar to those in the above reference. Figure 5A and Figure 5B The operations described are substantially the same or similar. Therefore, for ease of explanation, the description given below will focus on the differences between the program code S400 for the read operation and the program code S500 for the write operation, and the program code S100 for the read operation and the program code S200 for the write operation.

[0128] refer to Fig. 10A and Fig. 10B , a program code S400 for a read operation and a program code S500 for a write operation are shown.

[0129] The program code S400 for the read operation may include an operation S410 for selecting some of the plurality of storage devices, an operation S420 for starting a read operation on the selected storage device, an operation S430 for determining whether the power is normal, an operation S440 for performing a read operation on the selected storage device, and an operation S450 for retrying to read the same page. In other words, when the power is abnormal while the read operation on the first page or multiple first pages is started at S440, the reading of the first page or multiple first pages is retried at S450. Additionally, although the determination of whether the power is normal at S430 is described herein as occurring before the read operation is performed at S440, the determination at S430 may be performed alternatively after S440, or additionally after S440 and even again after S450.

[0130] The program code S500 for a write operation may include an operation S510 for selecting some of a plurality of storage devices, an operation S520 for starting a write operation on the selected storage device, an operation S530 for determining whether power is normal, an operation S540 for performing a write operation on the selected storage device, and an operation S550 for allocating the write (e.g., dedicating at least one address and space to the next write operation) to the next free block.

[0131] Operations S410 and S510 for selecting some of the storage devices may be performed by the storage system 1000 (see Figure 7 ) in the chip select channel CS (see Fig. 9A )implement.

[0132] The read operation and the write operation may be performed in the memory cell array of the selected memory device. Determining whether power is normal during the read operation and the write operation may be implemented by a power failure detection circuit and a program code.

[0133] In other words, the program code S400 for the read operation and the program code S500 for the write operation can minimize the data loss of the selected storage device due to external factors such as the sudden interruption of the power supplied from the power management integrated circuit chip. In addition, in the state of unstable power, the program code S400 for the read operation and the program code S500 for the write operation can improve the data reliability of the selected storage device.

[0134] Fig.11 A flow chart of determining a failure of a storage device by using a storage system according to an example embodiment is shown.

[0135] refer to Figure 7 and Fig.11 , the determination of the failure of the storage device S600 may be performed by using the storage system 1000 .

[0136] In some embodiments, the storage system 1000 may further include a monitoring device 1140 that identifies the storage device 20 .

[0137] Determination S600 of storage device failure may include operation S610 for starting read operations and write operations on the storage device, operation S620 for switching the power state to a test mode, operation S630 for determining whether to implement a power failure detection mode on the storage device, operation S640 for determining whether the storage device is normal or abnormal, operation S650 for generating determination data for the storage device, and operation S660 for terminating read operations and write operations on the storage device.

[0138] In detail, the host 1100 can switch the power state to the test mode while performing a read operation and a write operation on the non-volatile memory included in the storage device 20, and collect information about whether the power failure detection mode for the read operation and the write operation is being normally implemented on the non-volatile memory. The power failure detection mode may be included in the program code of the non-volatile memory. In the test mode, abnormal power with which the read operation and the write operation cannot be performed normally is provided. That is, the power failure detection mode may be implemented by one or more program codes included in each non-volatile memory, such as when they are run or processed by the corresponding controller of the non-volatile memory.

[0139] In addition, the monitoring device 1140 may check the information collected by the host 1100 and determine whether the storage device 20 is normal or abnormal (operation S640), and generate data on whether the storage device 20 is normal or abnormal by analyzing the information on whether the storage device 20 is normal (operation S650). Therefore, the monitoring device 1140 may be configured to analyze information on the failure of the storage device.

[0140] Fig.12 A block diagram of a server system to which a storage device according to example embodiments may be applied is shown.

[0141] refer to Fig.12 , the server system 1200 may include a plurality of servers 1220 - 1 to 1220 -N. The servers 1220 - 1 to 1220 -N may be connected to the manager 1210 .

[0142] Each of the servers 1220-1 to 1220-N may include a storage device according to the present disclosure. The storage device according to the present disclosure performs self-diagnosis of power failure detection during read operations and write operations by adopting a combination of hardware (power failure detection circuit of a power management integrated circuit chip, and / or a controller, and / or a non-volatile memory storing program code) and software (program code), and can prevent errors in read operations and write operations caused by power failure of the storage device in advance in a manner similar to the implementation of the defense code in the storage device.

[0143] Fig.13 A block diagram showing a server cluster to which a storage device according to example embodiments may be applied.

[0144] refer to Fig.13 , the storage cluster 1300 is highlighted as a high-performance computing infrastructure capable of quickly computing large amounts of data in the era of big data and artificial intelligence (AI).

[0145] The storage cluster 1300 can maximize computing performance by configuring a parallel computing environment through large-scale clustering. The storage cluster 1300 can provide storage to a network or a storage area network based on the capacity of storage memory and the flexible arrangement of physical components.

[0146] The storage cluster 1300 may include a data center 1305 implemented as a plurality of server systems 1200-1 to 1200-N. Each of the server systems 1200-1 to 1200-N may be associated with a reference Fig.12 The server system 1200 described is similar or substantially the same.

[0147] The server systems 1200-1 to 1200-N can communicate with the storage nodes 1320-1 to 1320-N through a network 1310 such as a computer network or the Internet. According to an embodiment, the storage nodes 1320-1 to 1320-N do not need to be arranged adjacent to each other. For example, each of the storage nodes 1320-1 to 1320-N can be any one of a client computer, a server, a remote data center, and a storage system.

[0148] Each of the server systems 1200-1 to 1200-N that receives requests from the storage nodes 1320-1 to 1320-N may include a storage device according to the present disclosure. The storage device according to the present disclosure performs self-diagnosis of power failure detection during read operations and write operations by adopting a combination of hardware (power failure detection circuit of a power management integrated circuit chip, and / or a controller, and / or a non-volatile memory storing program code) and software (program code), and can prevent errors in read operations and write operations caused by power failure of the storage device in advance in a manner similar to the implementation of the defense code in the storage device.

[0149] Fig.14 A block diagram of a processing system including a storage device according to an example embodiment is shown.

[0150] refer to Fig.14 , the processing system 1400 may include a processing unit 1410, a volatile memory unit 1420, a resistive memory unit 1430, and a mass storage unit 1440. The processing system 1400 may be a general computing system or a special computing system (such as a mobile device, a personal computer, a server computer, and a programmable electronic device) and a mainframe computer.

[0151] The processing unit 1410 may run an operating system and a plurality of software systems and perform specific calculations or tasks. The processing unit 1410 may be a processor, such as a microprocessor or a central processing unit (CPU). The processing unit 1410 may run instructions stored in a memory and retrieved from a memory to perform some or all aspects of the processing described herein.

[0152] The volatile memory unit 1420 refers to a medium that stores data in a short-term or temporary manner as an operating memory or a cache memory of the processing system 1400. The volatile memory unit 1420 may include one or more memories.

[0153] The resistive memory unit 1430 may be used as a cache memory for the large-capacity storage unit 1440. The resistive memory unit 1430 may store an application of an operating system or some data. The resistive memory unit 1430 may include one or more memories.

[0154] The mass storage unit 1440 refers to a storage medium in which the processing system 1400 stores user data for a long term. The mass storage unit 1440 may store application programs or program data.

[0155] The large-capacity storage unit 1440 may include a storage device according to the present disclosure. The storage device according to the present disclosure performs self-diagnosis of power failure detection during read and write operations by adopting a combination of hardware (power failure detection circuit of a power management integrated circuit chip, and / or a controller, and / or a non-volatile memory storing program code) and software (program code), and can prevent errors in read and write operations caused by power failure of the storage device in advance in a manner similar to the implementation of the defense code in the storage device.

[0156] While the inventive concepts described herein have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: Power management integrated circuit chips; a plurality of non-volatile memories configured to receive power from the power management integrated circuit chip; as well as A controller configured to control the nonvolatile memory, wherein the controller checks the state of power during a read operation and a write operation of the nonvolatile memory, and when a power failure is detected in at least one of the nonvolatile memories, implements a power failure detection mode with respect to the read operation and the write operation for all the nonvolatile memories, Wherein, when a read voltage and a write voltage supplied to a nonvolatile memory are temporarily interrupted, the controller detects a power failure, when a power failure is detected in at least one of the nonvolatile memories, the controller sends an alarm signal to a host, and when a power failure is not detected in all nonvolatile memories after sending the alarm signal, the controller sends an alarm cancel signal to the host.

2. The storage device according to claim 1, wherein: In a power failure detection mode on a read operation, an attempt to read the first page is retried, and In the power failure detection mode regarding write operations, the write is assigned to the next free block.

3. The storage device according to claim 1, wherein: When a power failure is not detected in all nonvolatile memories, the read operation and the write operation are performed.

4. The storage device according to claim 1, wherein: The controller is configured as an integral package with the non-volatile memory.

5. The storage device according to claim 1, wherein: The non-volatile memory forms a redundant array of independent disks.

6. A storage system comprising: a plurality of memory devices, each memory device including a power management integrated circuit chip, a nonvolatile memory receiving power from the power management integrated circuit chip, and a controller configured to control the nonvolatile memory; as well as Host, configure multi-interface communication with storage devices, wherein the host checks the state of power during a read operation and a write operation of nonvolatile memories included in the storage device, and when a power failure is detected in at least one of the nonvolatile memories, implements a power failure detection mode with respect to the read operation and the write operation for all the nonvolatile memories, wherein the host selects some of the storage devices as the selected plurality of storage devices by controlling the channels of the multi-interface communication, and A state of power of a nonvolatile memory with respect to each of the selected plurality of storage devices is checked.

7. The storage system according to claim 6, wherein: In a power failure detection mode on a read operation, an attempt to read the first page is retried, and, In the power failure detection mode regarding write operations, the write is assigned to the next free block.

8. The storage system according to claim 6, wherein: The host directly sends power to the power management integrated circuit chip and receives power from the power management integrated circuit chip, and uses a bypass to send power to the controller of each storage device in the selected multiple storage devices and receives power from the controller of each storage device in the selected multiple storage devices.

9. The storage system according to claim 6, in, The host directly sends and receives the status of power to and from the power management integrated circuit chip and the controller of each of the selected plurality of storage devices.

10. The storage system according to claim 9, wherein: Channels include: A first channel, through which the host and the power management integrated circuit chip communicate; and a second channel through which the host communicates with a controller of each of the selected plurality of storage devices, and The first channel and the second channel have different interfaces.

11. The storage system according to claim 6, wherein: When a power failure is detected in at least one of the storage devices, sending an alarm signal to the host, and When a power failure is not detected in all storage devices after the alarm signal is sent, an alarm cancel signal is sent to the host.

12. The storage system according to claim 11, wherein: The host analyzes the alarm signal and the alarm cancel signal, and determines whether there is a failure in the storage device.

13. The storage system according to claim 6, wherein: The storage device is an M.2 type solid-state drive, and The storage devices are arranged serially.

14. A storage system comprising: a plurality of memory devices, each memory device including a power management integrated circuit chip, a nonvolatile memory receiving power from the power management integrated circuit chip, and a controller configured to control the nonvolatile memory; Access module, capable of installing storage devices; as well as A host, configured to communicate with a storage device, In which, while the host is performing read operations and write operations on the non-volatile memory included in the storage device, it switches the power state to a test mode and collects information about whether a power failure detection mode for read operations and write operations is implemented on the non-volatile memory.

15. The storage system according to claim 14, wherein: The power failure detection mode is implemented by program code stored in each of the plurality of memory devices, In a power failure detection mode on a read operation, an attempt to read the first page is retried, and, In the power failure detection mode regarding write operations, the write is assigned to the next free block.

16. The storage system according to claim 14, wherein: In the test mode, abnormal power with which a read operation and a write operation are not performed is supplied.

17. The storage system according to claim 14, further comprising: A monitoring device configured to check the storage device, The monitoring device determines the failure of the storage device by checking the information collected by the host.

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