A computer task high-speed synchronous control device and control method thereof

Abstract

The present invention provides a computer task high-speed synchronous control device, comprising a PC host and PC slaves 1, PC slaves 2, ... PC slaves N, wherein the PC host comprises a host CPU, a host synchronous board and a host board slot, each PC slave comprises a slave CPU, a slave synchronous board and a slave board slot, one PC host carries N PC slaves, and the host synchronous board of the PC host is electrically connected to the slave synchronous boards of the PC slaves 1, PC slaves 2, ... PC slaves N respectively; the present invention also provides a computer task high-speed synchronous control method, wherein the host synchronous board sends a transmission signal to each slave synchronous board, each slave synchronous board triggers a bus interrupt between the slave CPU and the slave synchronous board to enter an interrupt processing function to realize a synchronous task; the present invention uses a method of transmitting a synchronous signal by hardware, solves the problem of computer task synchronization, improves the system response speed and the transmission rate of the synchronous signal, enhances the stability of the system, and reduces the cost.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and in particular relates to a computer task high-speed synchronous control device and a control method thereof. Background Art

[0002] At present, many technical fields use a one-master-multiple-slave computer control mode, where the PC host transmits control signals to each PC slave, and each PC slave performs synchronous tasks. For example, the visual system of a flight simulator is a PC host that sends visual control signals, and each PC slave updates the visual drawing. However, due to the time difference in the transmission of control signals to each PC slave, the visual update task time of each PC slave will be out of sync, resulting in image tearing, and the visual effect does not meet the actual application requirements.

[0003] In the prior art, a synchronous update signal is set in the host software task, and multiple PC slaves receive the synchronous update signal and execute the update task at the same time. However, due to the slow signal transmission rate of the communication system, the update will be partially delayed and there is a possibility of packet loss. There is also the use of reflective memory cards for network networking and optical fiber high-speed communication. This technical solution can meet most usage environments, but it is costly and not suitable for widespread application. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a computer task high-speed synchronization control device and a control method thereof. A PC host carries multiple PC slaves. The host synchronization board is electrically connected to each slave synchronization board respectively. The host synchronization board sends a transmission signal to each slave synchronization board. Each slave synchronization board triggers a bus interrupt between the slave CPU and the slave synchronization board to enter an interrupt processing function to realize the synchronization task. The method of transmitting synchronization signals by hardware solves the problem of computer task synchronization, improves the system response speed and the transmission rate of the synchronization signal, enhances the stability of the system, and reduces the cost.

[0005] The present invention provides a computer task high-speed synchronous control device, comprising a PC host and PC slaves 1, PC slaves 2, ..., PC slaves N;

[0006] The PC host includes a host CPU, a host synchronization board and a host board slot, the host CPU is electrically connected to the host synchronization board, and the host synchronization board is inserted into the host board slot. Each PC slave includes a slave CPU, a slave synchronization board and a slave board slot, the slave CPU is electrically connected to the slave synchronization board, and the slave synchronization board is inserted into the slave board slot. The host synchronization board of the PC host is electrically connected to the slave synchronization boards of PC slave 1, PC slave 2...PC slave N, respectively, where N is an integer greater than or equal to 3.

[0007] Furthermore, the host synchronization board and each slave synchronization board are provided with a field programmable gate array FPGA.

[0008] Furthermore, the host CPU and the field programmable gate array FPGA on the host synchronization board adopt the PCI-E protocol to perform data transmission, and the slave CPU and the field programmable gate array FPGA on the slave synchronization board adopt the PCI-E protocol to perform data transmission.

[0009] Furthermore, the host board slot and the slave board slot are both PCI-E slots.

[0010] Furthermore, the host synchronization board and each slave synchronization board are provided with two communication connectors, the first communication connector of the host synchronization board is electrically connected to the first communication connector of the slave synchronization board 1 through a signal line, the second communication connector of the slave synchronization board 1 is electrically connected to the first communication connector of the slave synchronization board 2 through a signal line, the second communication connector of the slave synchronization board 2 is electrically connected to the first communication connector of the slave synchronization board 3 through a signal line, and so on until the second communication connector of the slave synchronization board N-1 is electrically connected to the first communication connector of the slave synchronization board N through a signal line.

[0011] Furthermore, the signal cable is an RJ45 network cable.

[0012] The present invention also provides a computer task high-speed synchronous control method using the above-mentioned computer task high-speed synchronous control device, the method comprising the following steps:

[0013] Step S1, after the PC host receives the main task, the host CPU sends a synchronization command to the host synchronization board through the bus;

[0014] Step S2, the host synchronization board receives the synchronization command, and after each PC slave is ready for the task, the host synchronization board transmits a signal to each slave synchronization board;

[0015] Step S3, after the host synchronization board transmits the signal, it enters the delay waiting process, and after receiving the signal, each slave synchronization board triggers the bus interrupt between the slave CPU and the slave synchronization board, and enters the interrupt processing function to realize the synchronization task;

[0016] Step S4, after each PC slave synchronization task is completed, it enters the PC slave task preparation state and sends a command to the PC host, and the host CPU of the PC host sends a synchronization command to the host synchronization board through the bus again;

[0017] Step S5, looping from step S2 to step S4.

[0018] Furthermore, the host synchronization board and each slave synchronization board are equipped with a field programmable gate array FPGA. The host CPU sends a synchronization command to the field programmable gate array FPGA on the host synchronization board through a bus. After receiving the signal, each slave synchronization board triggers a bus interrupt between the slave CPU and the field programmable gate array FPGA through its field programmable gate array FPGA.

[0019] Furthermore, the host CPU and the field programmable gate array FPGA on the host synchronization board adopt the PCI-E protocol to perform data transmission, and the slave CPU and the field programmable gate array FPGA on the slave synchronization board adopt the PCI-E protocol to perform data transmission.

[0020] Furthermore, the field programmable gate array FPGA on the host synchronization board transmits signals to each slave synchronization board by pulling up the interrupt signal line. After receiving the rising edge interrupt signal, the field programmable gate array FPGA on each slave synchronization board triggers the PCI-E bus interrupt between its corresponding slave CPU and field programmable gate array FPGA, and enters the interrupt processing function to realize the synchronization task.

[0021] Beneficial effects of the present invention:

[0022] The present invention provides a computer task high-speed synchronous control device, comprising a PC host and PC slaves 1, PC slaves 2, ... PC slaves N, wherein the PC host comprises a host CPU, a host synchronous board and a host board slot, and each PC slave comprises a slave CPU, a slave synchronous board and a slave board slot, and one PC host carries N PC slaves, and the host synchronous board of the PC host is electrically connected to the slave synchronous boards of the PC slaves 1, PC slaves 2, ... PC slaves N respectively; the present invention also provides a computer task high-speed synchronous control method, wherein the host synchronous board sends a transmission signal to each slave synchronous board, and each slave synchronous board triggers a bus interrupt between the slave CPU and the slave synchronous board to enter an interrupt processing function to realize a synchronous task; the present invention uses a method of transmitting a synchronous signal by hardware, thereby solving the problem of computer task synchronization, improving the system response speed and the transmission rate of the synchronous signal, enhancing the stability of the system, and reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention is further described using the accompanying drawings, but the embodiments in the accompanying drawings do not constitute any limitation to the present invention. A person skilled in the art can obtain other drawings based on the following drawings without creative work.

[0024] Figure 1 The invention provides a schematic block diagram of the principle of a high-speed synchronous control device for computer tasks.

[0025] Figure 2 The invention provides a control logic flow chart of a method for high-speed synchronous control of computer tasks. DETAILED DESCRIPTION

[0026] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0028] Embodiment 1:

[0029] Reference Figure 1 , this embodiment provides a computer task high-speed synchronous control device, including a PC host and PC slaves 1, PC slave 2...PC slave N;

[0030] The PC host includes a host CPU, a host synchronization board and a host board slot. The host synchronization board is provided with a field programmable gate array FPGA. The host CPU is electrically connected to the host synchronization board, and the host CPU and the field programmable gate array FPGA on the host synchronization board adopt the PCI-E protocol for data transmission. The host synchronization board is inserted into the host board slot, and the slot is a PCI-E slot.

[0031] Each of the PC slaves includes a slave CPU, a slave synchronization board and a slave board slot. The slave synchronization board is provided with a field programmable gate array FPGA. The slave CPU is electrically connected to the slave synchronization board, and the slave CPU and the field programmable gate array FPGA on the slave synchronization board use the PCI-E protocol for data transmission. The slave synchronization board is inserted into the slave board slot, and the slot is a PCI-E slot; the host synchronization board of the PC host is electrically connected to the slave synchronization boards of PC slave 1, PC slave 2...PC slave N respectively, where N is an integer greater than or equal to 3.

[0032] The hardware transmission synchronization signal method is adopted to electrically connect the host synchronization board of the PC host with the slave synchronization boards of PC slaves 1, PC slave 2, ... PC slave N, thereby avoiding the possibility of packet loss in high-speed communication situations when using software synchronization, solving the problem of computer task synchronization, and the PCI-E data transmission protocol built on the basis of FPGA, which is faster in communication control, improves the system response speed and the transmission rate of the synchronization signal, and reduces the cost.

[0033] The host synchronization board and each slave synchronization board are provided with two communication connectors, the first communication connector of the host synchronization board is electrically connected to the first communication connector of the slave synchronization board 1 through a signal line, the second communication connector of the slave synchronization board 1 is electrically connected to the first communication connector of the slave synchronization board 2 through a signal line, the second communication connector of the slave synchronization board 2 is electrically connected to the first communication connector of the slave synchronization board 3 through a signal line, and so on until the second communication connector of the slave synchronization board N-1 is electrically connected to the first communication connector of the slave synchronization board N through a signal line. In addition, this signal line is an RJ45 network cable. The connection method using this RJ45 network cable can improve the stability of the system.

[0034] Embodiment 2:

[0035] Reference Figure 2 This embodiment provides a computer task high-speed synchronization control method using the computer task high-speed synchronization control device in embodiment 1, the method comprising the following steps:

[0036] Step S1, after the PC host receives the main task, the host CPU sends a synchronization command to the host synchronization board through the bus;

[0037] Step S2, the host synchronization board receives the synchronization command, and after each PC slave is ready for the task, the host synchronization board transmits a signal to each slave synchronization board;

[0038] Step S3, after the host synchronization board transmits the signal, it enters the delay waiting process, and after receiving the signal, each slave synchronization board triggers the bus interrupt between the slave CPU and the slave synchronization board, and enters the interrupt processing function to realize the synchronization task;

[0039] Step S4, after each PC slave synchronization task is completed, it enters the PC slave task preparation state and sends a command to the PC host, and the host CPU of the PC host sends a synchronization command to the host synchronization board through the bus again;

[0040] Step S5, looping from step S2 to step S4.

[0041] It should be noted that the host CPU of the PC host sends a synchronization command to the host synchronization board, and the host synchronization board is responsible for transmitting signals to each slave synchronization board. Since the communication rate between the host synchronization board and each slave synchronization board is much higher than the rate requirement for updating the synchronization task, experimental tests have shown that the total time from sending the synchronization command to entering the interrupt processing function is about 10 microseconds, which can effectively solve the problem of jamming between the slave synchronization boards. After receiving the signal, each slave synchronization board triggers the bus interrupt between the slave CPU and the slave synchronization board, and enters the interrupt processing function to realize the synchronization task. Realizing a synchronization task is an action.

[0042] In addition, the host synchronization board and each slave synchronization board are equipped with a field programmable gate array FPGA. The host CPU sends a synchronization command to the field programmable gate array FPGA on the host synchronization board through the bus. After receiving the signal, each slave synchronization board triggers a bus interrupt between the slave CPU and the field programmable gate array FPGA through its field programmable gate array FPGA.

[0043] The host CPU and the field programmable gate array FPGA on the host synchronization board use the PCI-E protocol to perform data transmission, and the slave CPU and the field programmable gate array FPGA on the slave synchronization board use the PCI-E protocol to perform data transmission.

[0044] The field programmable gate array FPGA on the host synchronization board transmits signals to each slave synchronization board by pulling up the interrupt signal line. After receiving the rising edge interrupt signal, the field programmable gate array FPGA on each slave synchronization board triggers the PCI-E bus interrupt between its corresponding slave CPU and field programmable gate array FPGA, and enters the interrupt processing function to realize the synchronization task.

[0045] The above embodiment is a PCI-E data transmission protocol built on the basis of FPGA, which improves the system response speed and the transmission rate of the synchronization signal, avoids the communication packet loss problem of the synchronization signal transmitted by software, enhances the stability of the system, and also shortens the product development time and reduces the cost.

[0046] Compared with the prior art, the present invention provides a computer task high-speed synchronous control device, comprising a PC host and PC slaves 1, PC slaves 2...PC slaves N, wherein the PC host comprises a host CPU, a host synchronization board and a host board slot, and each PC slave comprises a slave CPU, a slave synchronization board and a slave board slot, and one PC host carries N PC slaves, and the host synchronization board of the PC host is electrically connected to the slave synchronization boards of PC slaves 1, PC slaves 2...PC slaves N respectively; the present invention also provides a computer task high-speed synchronous control method, wherein the host synchronization board sends a transmission signal to each slave synchronization board, and each slave synchronization board triggers a bus interrupt between the slave CPU and the slave synchronization board to enter an interrupt processing function to realize a synchronous task; the present invention uses a hardware transmission synchronization signal method to solve the computer task synchronization problem, improve the system response speed and the transmission rate of the synchronization signal, enhance the system stability, and reduce the cost.

[0047] Finally, it should be emphasized that the present invention is not limited to the above-mentioned implementation mode. The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for high-speed synchronous control of computer tasks, characterized in that: Applicable to a high-speed synchronous control device for computer tasks, the device comprising a PC host and PC slaves 1, PC slave 2, ... PC slave N; The PC host comprises a host CPU, a host synchronization board and a host board slot, wherein the host CPU is electrically connected to the host synchronization board, and the host synchronization board is inserted into the host board slot; each PC slave comprises a slave CPU, a slave synchronization board and a slave board slot, wherein the slave CPU is electrically connected to the slave synchronization board, and the slave synchronization board is inserted into the slave board slot; the host synchronization board of the PC host is electrically connected to the slave synchronization boards of PC slave 1, PC slave 2, ..., PC slave N, respectively, wherein N is an integer greater than or equal to 3; The host synchronization board and each slave synchronization board are provided with a field programmable gate array FPGA; The host CPU and the field programmable gate array FPGA on the host synchronization board use the PCI-E protocol to perform data transmission, and the slave CPU and the field programmable gate array FPGA on the slave synchronization board use the PCI-E protocol to perform data transmission; The host card slot and the slave card slot are both PCI-E slots; The host synchronization board and each slave synchronization board are each provided with two communication connectors, the first communication connector of the host synchronization board is electrically connected to the first communication connector of the slave synchronization board 1 through a signal line, the second communication connector of the slave synchronization board 1 is electrically connected to the first communication connector of the slave synchronization board 2 through a signal line, the second communication connector of the slave synchronization board 2 is electrically connected to the first communication connector of the slave synchronization board 3 through a signal line, and so on until the second communication connector of the slave synchronization board N-1 is electrically connected to the first communication connector of the slave synchronization board N through a signal line; The signal cable is an RJ45 network cable; The method comprises the following steps: Step S1, after the PC host receives the main task, the host CPU sends a synchronization command to the host synchronization board through the bus; Step S2, the host synchronization board receives the synchronization command, and after each PC slave is ready for the task, the host synchronization board transmits a signal to each slave synchronization board; Step S3, after the host synchronization board transmits the signal, it enters the delay waiting process, and after receiving the signal, each slave synchronization board triggers the bus interrupt between the slave CPU and the slave synchronization board, and enters the interrupt processing function to realize the synchronization task; Step S4, after each PC slave synchronization task is completed, it enters the PC slave task preparation state and sends a command to the PC host, and the host CPU of the PC host sends a synchronization command to the host synchronization board through the bus again; Step S5, looping step S2 to step S4; The host synchronization board and each slave synchronization board are both provided with a field programmable gate array FPGA, the host CPU sends a synchronization command to the field programmable gate array FPGA on the host synchronization board through the bus, and each slave synchronization board triggers a bus interruption between the slave CPU and the field programmable gate array FPGA through its field programmable gate array FPGA after receiving the signal; The host CPU and the field programmable gate array FPGA on the host synchronization board use the PCI-E protocol to perform data transmission, and the slave CPU and the field programmable gate array FPGA on the slave synchronization board use the PCI-E protocol to perform data transmission; The field programmable gate array FPGA on the host synchronization board transmits signals to each slave synchronization board by pulling up the interrupt signal line. After receiving the rising edge interrupt signal, the field programmable gate array FPGA on each slave synchronization board triggers the PCI-E bus interrupt between its corresponding slave CPU and field programmable gate array FPGA, and enters the interrupt processing function to realize the synchronization task.

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