Semiconductor panel, semiconductor package and manufacturing method thereof

Abstract

A method for manufacturing a semiconductor panel includes providing a first prepolymer forming member. The method further includes arranging a plurality of semiconductor chips on the first prepolymer forming member. The method further includes attaching a second prepolymer forming member to the first prepolymer forming member, wherein the semiconductor chips are arranged between the attached prepolymer forming members, and wherein the attached prepolymer forming members form a semiconductor panel encapsulating the semiconductor chips.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor technology. In particular, the present disclosure relates to a semiconductor panel, a semiconductor package and a method for manufacturing the same. Background Art

[0002] Semiconductor devices may be manufactured in the form of semiconductor packages, i.e., metal, plastic, glass or ceramic housings containing one or more semiconductor electronic components. The cost of packaging may be considered one of the main drivers of the semiconductor industry. The design and production of power semiconductor packages may impose special requirements. For example, the conductive paths of a power package may need to be designed to properly handle the high currents present. Manufacturers of semiconductor devices are constantly striving to improve their products and methods of manufacturing them. Therefore, it is desirable to develop methods for manufacturing semiconductor devices that provide improved and cost-effective device production and that may be particularly suitable for the production of power semiconductor packages. Summary of the invention

[0003] Aspects of the present disclosure relate to a method for manufacturing a semiconductor panel. The method includes providing a first prepolymer forming member. The method further includes arranging a plurality of semiconductor chips on the first prepolymer forming member. The method further includes attaching a second prepolymer forming member to the first prepolymer forming member, wherein the semiconductor chips are arranged between the attached prepolymer forming members, and wherein the attached prepolymer forming members form a semiconductor panel encapsulating the semiconductor chips.

[0004] A further aspect of the present disclosure relates to a semiconductor package. The semiconductor package includes a first prepolymer forming member. The semiconductor package further includes a second prepolymer forming member attached to the first prepolymer forming member. The semiconductor package further includes a semiconductor chip arranged between the attached prepolymer forming members, wherein the attached prepolymer forming members form a semiconductor package encapsulating the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings are included to provide a further understanding of the various aspects, and the accompanying drawings are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the various aspects and together with the description explain the principles of the various aspects. As it becomes better understood by reference to the following detailed description, other aspects and many expected advantages of the various aspects will be more easily appreciated. The elements in the accompanying drawings are not necessarily drawn to scale with respect to each other. Like reference numerals indicate corresponding similar parts.

[0006] Figure 1 contains Figures 1A to 1C , schematically illustrates a cross-sectional side view of a method for manufacturing a semiconductor panel 100 according to the present disclosure.

[0007] Figure 2A cross-sectional side view of a semiconductor package 200 according to the present disclosure is schematically shown.

[0008] Figure 3 includes Figures 3A to 3J , schematically illustrates a cross-sectional side view of a method for manufacturing a semiconductor panel and a semiconductor package 300 according to the present disclosure.

[0009] Figure 4 A cross-sectional side view of a semiconductor package 400 according to the present disclosure is schematically shown.

[0010] Figure 5 A cross-sectional side view of a semiconductor package 500 according to the present disclosure is schematically shown.

[0011] Figure 6 A flow chart of a method for manufacturing a semiconductor panel according to the present disclosure is shown. DETAILED DESCRIPTION

[0012] In the following detailed description, reference is made to the accompanying drawings in which specific aspects of the present disclosure may be practiced are shown by way of illustration. In this regard, directional terms such as "top," "bottom," "front," "back," etc. may be used with reference to the orientation of the accompanying drawings being described. Because the elements of the described devices may be placed in many different orientations, directional terms are used for illustration and are by no means limiting. Other aspects may be utilized and structural or logical changes may be made without departing from the concepts of the present disclosure. Therefore, the following detailed description is not restrictive, and the concepts of the present disclosure are defined by the appended claims.

[0013] Figure 1 contains Figures 1A to 1C , schematically illustrates a cross-sectional side view of a method for manufacturing a semiconductor panel 100 according to the present disclosure. The method of FIG. 1 is illustrated in a general manner to qualitatively illustrate aspects of the present disclosure. The method may include other aspects that are not shown for simplicity. For example, the method may be expanded by combining any of the aspects described with other methods and devices according to the present disclosure.

[0014] exist Figure 1A In the embodiment, a first prepolymer forming member 2 is provided. Figure 1A In an example, the first prepolymer forming member 2 may include a plurality of grooves, wherein the semiconductor chip may be subsequently arranged in the grooves. In further examples, the first prepolymer forming member 2 may be of different shapes. For example, the surface of the first prepolymer forming member 2 to which the semiconductor chip is subsequently mounted may be substantially flat. In addition, Figure 1A The number of grooves shown in is exemplary and may be different in further examples.

[0015] exist Figure 1BIn the embodiment, a plurality of semiconductor chips 4 are arranged on the first prepolymer forming member 2. Figure 1B In an example, the semiconductor chip 4 may be arranged in the groove. In a further example, the semiconductor chip 4 may be arranged additionally or alternately on the plane of the first prepolymer forming member 2.

[0016] exist Figure 1C In the embodiment, the second prepolymer formed part 6 is attached to the first prepolymer formed part 2. Figure 1C In an example, the prepolymer forming members 2 and 6 may have similar shapes. In a further example, the shapes of the prepolymer forming members 2 and 6 may be different from each other. The semiconductor chip 4 may be arranged between the attached prepolymer forming members 2 and 6. The attached prepolymer forming members 2 and 6 form a semiconductor panel 100 encapsulating the semiconductor chip 4.

[0017] According to one embodiment, arranging the semiconductor chip 4 may include arranging the semiconductor chip 4 in a plurality of grooves of the first prepolymer forming member 2, such as Figure 1B As shown by way of example. Figure 1C When viewed from the arrow in the figure, the shape of the groove is similar to the shape of the semiconductor chip 4 arranged in the groove. For example, the semiconductor chip 4 is bonded to the bottom of the groove so that the opening of the groove can be selected to be slightly larger than the semiconductor chip 4.

[0018] According to one embodiment, arranging the semiconductor chip 4 may include arranging an electrical contact of the semiconductor chip 4 on a through hole of the first prepolymer formation 2. The electrical contact of the semiconductor chip 4 may be formed as a contact pad (or contact unit, contact terminal, contact electrode), and may provide electrical access to an internal circuit of the semiconductor chip 4. The through hole may extend from a first surface of the first prepolymer formation 2 to a second surface of the first prepolymer formation 2. The through hole may then be filled with a conductive material so that the filled through hole may provide an electrical access, in particular from the opposite side of the first prepolymer formation 2 to the electrical contact of the semiconductor chip 4.

[0019] According to one embodiment, arranging the electrical contact portion may include: arranging a first electrical contact portion of the semiconductor chip 4 on the first through hole; arranging a second electrical contact portion of the semiconductor chip 4 on a second through hole adjacent to the first through hole. The first through hole and the second through hole may be separated by a separation structure. When the separation structure is arranged along the z direction (see Figure 1CThe opening area of ​​these through holes may substantially correspond to the surface area of ​​the electrical contact portion when viewed from the arrows in the figure. For example, the semiconductor chip 4 may be a power transistor chip, the gate electrode and the source electrode of which are arranged on the surface of the semiconductor die 4 facing the first and second through holes. Here, the gate electrode may be arranged above the first through hole, and the source electrode may be arranged above the second through hole. The through holes subsequently filled with the conductive material may provide an electrical path, in particular from the opposite side of the first prepolymer forming part 2 to the gate electrode and the source electrode of the semiconductor chip 4.

[0020] According to one embodiment, attaching the second prepolymer forming member 6 may include arranging a through hole of the second prepolymer forming member 6 over an electrical contact of the semiconductor chip 4. The through hole may extend from a first surface of the second prepolymer forming member 6 to a second surface of the second prepolymer forming member 6. The through hole, which is then filled with a conductive material, may provide an electrical path to the electrical contact, in particular from the opposite face of the second prepolymer forming member 6. For the case of the power transistor chip explained above, the electrical contact may correspond to a drain electrode of the semiconductor chip 4.

[0021] According to one embodiment, the method of FIG1 may further include depositing a metallization material into the through-hole of at least one of the prepolymer formations 2 and 6, wherein the deposited metallization material may be electrically coupled to the electrical contact of the semiconductor chip 4. For example, the metallization material may be deposited by applying at least one of the following techniques: cold gas spraying, plasma dust spraying, plasma induction spraying, electroplating, electroless plating, galvanic plating, vapor deposition, printing, etc.

[0022] According to one embodiment, depositing the metallization material may include cold gas spraying at least one of a metal and a metal alloy in the through hole. Cold gas spraying may refer to a coating deposition method in which a solid powder may be accelerated in a supersonic gas jet to a speed of up to about 500 m / s to about 1000 m / s. The accelerated powder particles have a diameter of about 1 micron to about 50 microns. During collision with a target, the particles may undergo plastic deformation and may adhere to the surface of the target. Typically, metals, polymers, ceramics, composite materials, and nanocrystalline powders may be deposited using cold gas spraying. The powder used in cold gas spraying does not necessarily melt during the spraying process. For example, the metallization material is deposited by cold gas spraying at least one of copper, aluminum, iron, nickel, and alloys thereof. The porosity of the cold gas sprayed metallization material may be less than about 50%, more particularly less than about 40%, more particularly less than about 30%, more particularly less than about 20%, and even more particularly less than about 10%. In one example, the porosity may be in the range of about 10% to about 50%. The porosity may be infinitesimally small and may correspond to the ratio of the void volume to the total volume of the porous material or a body formed of the porous material.For example, a metallized material produced by cold gas spraying may be distinguished from a bulk material layer of the same material.

[0023] According to one embodiment, the method of FIG. 1 may further include partially removing at least one of the prepolymer formations 2 and 6 and the metallization material, wherein after removing the material, the surface of at least one of the prepolymer formations 2 and 6 and the surface of the metallization material may be arranged on a common plane. For example, the surface formed by one of the prepolymer formations 2 and 6 and the metallization material needs to be planarized so that additional material layers can be properly deposited on the flat surface that has been formed. The material may be removed by applying at least one of the following techniques: grinding, chemical mechanical polishing, etching, etc.

[0024] According to one embodiment, the first prepolymer formation 2 may include a first via extending through the first prepolymer formation 2, and the second prepolymer formation 6 may include a second via extending through the second prepolymer formation 6. In addition, attaching the second prepolymer formation 6 may include providing an overlap between the first via and the second via, and the deposited metallization material may form an electrical via connection extending through the semiconductor panel 100. Thus, the electrical contacts on the surface of the semiconductor chip 4 may become accessible from the surface of the semiconductor panel 100 arranged opposite to the chip surface. For example, all electrical contacts (e.g., gate electrodes, source electrodes, drain electrodes) of a power transistor chip may be arranged on the same surface of a semiconductor package obtained by singulating the semiconductor panel 100.

[0025] According to one embodiment, the method of FIG. 1 may further include, before attaching the second prepolymer forming member 6, arranging a conductive layer on the first prepolymer forming member 2, wherein the conductive layer may be arranged between the prepolymer forming members 2 and 6. In particular, the conductive layer may be made of at least one of a metal and a metal alloy, such as, for example, copper, aluminum and alloys thereof. The conductive layer may be made by applying any suitable technique. In one example, the conductive layer may be made by applying at least one of electroless plating, current deposition, vapor deposition, etc. In a further example thereof, the conductive layer may be a preformed metal sheet, such as, for example, a copper sheet or an aluminum sheet, which may be attached to, in particular bonded to, one of the prepolymer forming members 2 and 6 before the prepolymer forming members 2 and 6 are attached to each other. The conductive layer may have the function of a redistribution layer, providing redistribution of electrical signals of the semiconductor chip 4 and other electronic components of the semiconductor package to be manufactured.

[0026] According to one embodiment, the method of FIG. 1 may further include: forming at least one groove in at least one of the prepolymer forming members 2 and 6; arranging an electronic component in the at least one groove, wherein the electronic component may be packaged into the semiconductor panel 100. For example, the electronic component may include at least one of a passive electronic component (e.g., an integrated passive device (IDP)), an active electronic component, a surface mount device (SMD) (e.g., an SMD capacitor), etc. After attaching the prepolymer forming members 2 and 6 to each other, the electronic component may be particularly arranged in the cavity of the semiconductor 100.

[0027] According to an embodiment, the electronic component may be electrically coupled to one of the semiconductor chips 4 via the conductive layer. In particular, the electronic component may be glued or soldered to the conductive layer, wherein an electrical connection between electrical contacts of the electronic component and electrical contacts of the semiconductor chip 4 may be established via the conductive layer.

[0028] According to one embodiment, the semiconductor chip 4 may include a power semiconductor chip. The semiconductor chip (or semiconductor die) 4 may be of similar or different types. Typically, the semiconductor chip 4 may include an integrated circuit, a passive electronic component, an active electronic component, etc. Typically, the integrated circuit is designed as a logic integrated circuit, an analog integrated circuit, a mixed signal integrated circuit, a power integrated circuit, etc. In one example, the semiconductor chip 4 may be manufactured from a basic semiconductor material, such as Si, etc. In a further example, the semiconductor chip 4 may be manufactured from a composite semiconductor material, such as GaN, SiC, SiGe, GaAs, etc. In particular, the semiconductor chip 4 may include one or more power semiconductors. The power semiconductor chip may be configured as a diode, a power MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), a JFET (junction gate field effect transistor), a HEMT (high electron mobility transistor), a super junction device, a power bipolar transistor, etc. The power semiconductor chip may have a vertical structure, that is, the current may flow substantially in a direction perpendicular to the main surface of the semiconductor chip. For example, the source electrode and the gate electrode of the power MOSFET may be arranged on one surface, and the drain electrode of the power MOSFET may be arranged on another surface. The power semiconductor chip may have a lateral structure, ie, current may flow substantially in a direction parallel to a main surface of the semiconductor chip. For example, a gate electrode, a source electrode, and a drain electrode of a power MOSFET may be arranged on one main surface of the power MOSFET.

[0029] According to one embodiment, the method of claim 1 may further include constructing at least one of the prepolymer forms 2 and 6, wherein the constructing includes at least one of molding, milling, grinding, and laser drilling. Molding may include at least one of compression molding, injection molding, powder molding, liquid molding, lamination, printing, etc. In particular, constructing the prepolymer forms 2 and 6 may be performed before performing the operation of FIG. 1 .

[0030] According to one embodiment, the semiconductor panel 100 may be in a rectangular shape, and the surface area of ​​the rectangular semiconductor panel 100 may be greater than or equal to 300 mm×300 mm. The method of FIG. 1 may be regarded as a panel-level packaging (PLP) technology or a fan-out panel-level packaging (FOPLP) technology, which is different from the known wafer-level packaging (WLP) technology and the known fan-out wafer-level packaging (FOWLP) technology. In WLP or FOWLP, the wafer or the reconstructed wafer may be circular with a diameter of 200 mm or 300 mm. Compared to WLP and FOWLP, the size of the semiconductor panel of PLP and FOPLP may be increased so that manufacturers and suppliers can process more semiconductor chips (or semiconductor dies) at the panel level compared to the wafer level. For example, a 500 mm×500 mm panel can process 4.45 times more semiconductor chips than a 300 mm diameter wafer. This can result in lower production costs. In particular, when the wafer is arranged along the z direction (see Figure 1C When viewed from the perspective of the arrow in the figure, the manufactured semiconductor panel 100 may be rectangular in shape. In this way, the semiconductor chips 4 may be arranged, for example, in a periodic and rectangular grid-like structure. In one example, the size of the semiconductor panel 100 may be 510 mm×515 mm. In a further example, the size of the semiconductor panel 100 may be 600 mm×600 mm. In another further example, the size of the semiconductor panel 100 may be 18"×24" (i.e., 457.2 mm×609.6 mm). The number of semiconductor chips 4 embedded in the semiconductor panel 100 may be as high as 8,000 or more.

[0031] Figure 2 A cross-sectional side view of a semiconductor package 200 according to the present disclosure is schematically shown. The semiconductor package 200 is shown in a general manner to qualitatively illustrate aspects of the present disclosure. The semiconductor package 200 may include further elements that are not shown for simplicity. For example, the semiconductor package 200 may be expanded by various aspects described in conjunction with other devices and methods according to the present disclosure.

[0032] The semiconductor package 200 includes a first prepolymer forming member 2. The semiconductor package 200 further includes a second prepolymer forming member 6 attached to the first prepolymer forming member 2. The semiconductor package 200 further includes a semiconductor chip 4 arranged between the attached prepolymer forming members 2 and 6. The attached prepolymer forming members 2 and 6 form the semiconductor package 200 encapsulating the semiconductor chip 4. For example, the semiconductor package 200 may be manufactured according to the method of FIG. 1. In this regard, as shown in FIG. Figures 1A to 1C The semiconductor panel 100 may be manufactured as shown. In a further operation, the semiconductor panel 100 may be singulated into a plurality of semiconductor packages 200. The semiconductor panel 100 may be singulated by applying a cutting process including at least one of plasma cutting, ultrasonic mechanical cutting, laser cutting, and the like.

[0033] According to one embodiment, the semiconductor package 200 may further include a metallization material electrically coupled to the electrical contact portion of the semiconductor chip 4, wherein the metallization material may be manufactured by cold gas spraying. In particular, the metallization material may be made of or may include at least one of copper, aluminum, iron, nickel, and alloys thereof. The porosity of the sprayed metallization material may be less than about 50%, more particularly less than about 40%, more particularly less than about 30%, more particularly less than about 20%, and even more particularly less than about 10%. In one example, the porosity may be in the range of about 10% to about 50%.

[0034] According to one embodiment, the semiconductor package 200 may further include a conductive layer arranged between the prepolymer forms 2 and 6. In particular, the conductive layer may be a preformed metal sheet, such as, for example, a copper sheet or an aluminum sheet.

[0035] According to one embodiment, at least one of the prepolymer formations 2 and 6 may include at least one of a molding compound, a laminate, an epoxy, a filled epoxy, a glass fiber filled epoxy, an imide, a thermoplastic, a thermosetting polymer, a polymer blend. The prepolymer formations 2 and 6 may be made of similar or different materials. In particular, the prepolymer formations 2 and 6 may be prefabricated. That is, the prepolymer formations 2 and 6 may be manufactured and formed in one or more operations before performing the various operations of FIG. 1 .

[0036] Figure 3 contains Figures 3A to 3J , Figures 3A to 3J The cross-sectional side view schematically shows a method for manufacturing a semiconductor panel 100 and a semiconductor package 300 according to the present disclosure. The manufactured semiconductor package 300 can be regarded as Figure 2 In addition, the method of FIG. 3 may be regarded as a more detailed implementation of the method of FIG. 1 .

[0037] exist Figure 3AIn the embodiment, a first prepolymer formed part 2 may be provided, which is shown in a cross-sectional side view. The first prepolymer formed part 2 may include a groove 8, wherein the semiconductor chip 4 may be subsequently arranged in the groove 8. In particular, when viewed along the z-direction (as shown by the arrow), the opening area of ​​the groove 8 is slightly larger than the footprint area of ​​the semiconductor chip 4 to be assembled. The first prepolymer formed part 2 may further include a first through hole 10 and an adjacent second through hole 12, which are separated by a separation structure 14. The through holes 10 and 12 may extend from the bottom surface of the groove 8 to the bottom surface of the first prepolymer formed part 2. The first prepolymer formed part 2 may further include a groove 40 and a via 16. The via 16 may extend from the bottom surface of the groove 40 to the upper surface of the first prepolymer formed part 2. As shown in FIG. Figure 3A As shown by the dashed lines in FIG. 1 , the cross-sectional side view of the first prepolymer formed member 2 may be substantially rectangular before the grooves and through holes are formed.

[0038] For illustration purposes, Figure 3A Only a portion or part of the first prepolymer forming member 2 is shown. The first prepolymer forming member 2 may be formed of a plurality of such parts, and the parts may be periodically arranged in Figure 3A In addition, the component can be arranged periodically on the left and right sides of the component. Figure 3A The periodically arranged components may form a single (or complete) first prepolymer forming part 2, wherein the grooves 8 may in particular form a rectangular and periodic grid structure when viewed along the z direction (see arrow). The following description may only refer to Figure 3A components, but may also be applicable to additional components not shown for simplicity.

[0039] Figure 3B Shows Figure 3A A bottom view of the groove 8, through holes 10, 12 and separation structure 14 of the first prepolymer formed part 2. The outline of the groove 8 is indicated by the dashed rectangle. The separation structure 14 can be arranged so that the opening area of ​​the first through hole 10 and the opening area of ​​the second through hole 12 are similar to the surface area of ​​the electrical contact of the semiconductor chip to be arranged in the groove 8. Figure 3B In the example of FIG. 1 , the separation structure 14 may be arc-shaped. In a further example, the separation structure 14 may be rectangular, polygonal, etc.

[0040] exist Figure 3C In the embodiment, a plurality of semiconductor chips 4 may be provided. The semiconductor chips 4 may have been cut out from a semiconductor wafer in a previous operation. The number of semiconductor chips 4 is arbitrary and may in particular correspond to the number of recesses 8 in the first prepolymer formation 2. Figure 3CIn an example, the semiconductor chip 4 may be a power transistor chip having a vertical structure. Each semiconductor chip 4 may include a gate electrode 18 and a source electrode 20 arranged on the upper surface of the corresponding semiconductor chip 4. In addition, each semiconductor chip 4 may include a drain electrode 22 arranged on the relative bottom surface of the corresponding semiconductor chip 4. In a further example, the semiconductor chip 4 may be of a different type, such as a power transistor chip, a power diode chip, etc. having a lateral structure. An adhesive material 24, such as glue, may be arranged at the outer edge of the upper surface of the semiconductor chip 4 and between the gate electrode 18 and the source electrode 20. For example, the adhesive material 24 may be printed on the upper surface of the semiconductor chip 4.

[0041] exist Figure 3D In Figure 3C The semiconductor chip 4 is turned over and arranged in the groove 8 of the first prepolymer forming part 2. The adhesive material 24 can attach the outer edge of the semiconductor chip 4 to the bottom edge of the groove 8. In addition, the adhesive material 24 can attach the area between the gate electrode 18 and the source electrode 20 to the separation structure 14. The source electrode 20 can be arranged above the first through hole 10, and the gate electrode 18 can be arranged above the second through hole 12. After the semiconductor chip 4 is arranged, the adhesive material 24 can be cross-bonded in an optional further operation, in particular cured.

[0042] exist Figure 3E In the embodiment, the conductive layer 26 may be arranged on the upper surface of the first prepolymer formed part 2. In particular, the area above the semiconductor chip 4 may remain uncovered by the conductive layer 26. Figure 3E In the example of FIG. 1 , the conductive layer 26 may be a preformed metal sheet or a preformed metal alloy sheet, such as a sheet made of or including copper or aluminum. Figure 3D The adhesive material 24 of the adhesive material 24 can bond the metal sheet to the upper surface of the first prepolymer formed part 2. In particular, the adhesive material 24 can be deposited on multiple parts of the first prepolymer formed part 2 in a parallel operation, for example by applying a printing technique.

[0043] exist Figure 3F , a second prepolymer forming member 6 shown in a cross-sectional side view may be provided. Figure 3A The first prepolymer is formed into a member 2, for the purpose of illustration, Figure 3FOnly a part or component of the second prepolymer forming member 6 is shown in FIG. The second prepolymer forming member 6 may include a plurality of components arranged periodically in this manner. The second prepolymer forming member 6 may include a groove 28, a through hole 30, and a via 32. The groove 28 may be formed on the upper surface of the second prepolymer forming member 6. The through hole 30 may extend from the bottom surface of the groove 28 to the bottom surface of the second prepolymer forming member 6. In particular, when viewed along the z direction, the occupied area of ​​the through hole 30 is similar to the surface area of ​​the drain electrode 22 of the semiconductor chip 4. The via 32 may also extend from the bottom surface of the groove 28 to the bottom surface of the second prepolymer forming member 6. When the prepolymer forming members 2 and 6 are stacked on each other, the vias 16 and 32 of the first and second prepolymer forming members 2 and 6 may be substantially consistent. This also applies to the through holes of the prepolymer forming members 2 and 6.

[0044] exist Figure 3G In the embodiment of the present invention, an adhesive material 34, such as glue, can be arranged on the upper surface of the first prepolymer forming member 2 and in particular on the upper surface of the conductive layer 26. The area on the semiconductor chip 4 can remain uncovered by the adhesive material 34. In particular, the adhesive material 34 can be applied to a plurality of periodically arranged components of the first prepolymer forming member 2 in a parallel operation, for example by applying a printing technique. After applying the adhesive material 34, the second prepolymer forming member 6 can be attached to the first prepolymer forming member 2. After attachment, the vias 16 and 32 of the first and second prepolymer forming members 2 and 6 can overlap and can be substantially consistent. This also applies to the through holes of the prepolymer forming members 2 and 6.

[0045] exist Figure 3H In the embodiment of the present invention, metallization material 36 may be deposited into recesses 28, through holes 30, and vias 32. Figure 3H In the example of , the metallization material 36 may be copper, which may be deposited by applying a cold gas spraying technique. Note that the metallization material 36 may be deposited on multiple parts of the second prepolymer formation 6 in a parallel operation. During the spraying process, a hard mask 38 is arranged on the upper surface of the second prepolymer formation 6 so as to structure the deposited metallization material 36, and the upper surface may remain uncovered by the metallization material 36. In particular, the groove 28, the through hole 30, and the via 32 may be completely filled with the metallization material 36. The deposited metallization material 36 may make physical and electrical contact with the drain electrode 22 and the conductive layer 26.

[0046] In a further operation (not shown), material of at least one of the second prepolymer forming member 6 and the metallization material 36 may be removed from the upper surface of the arrangement to obtain a flat upper surface. In particular, after removing the material, the upper surface of the second prepolymer forming member 6 and the upper surface of the metallization material 36 may be arranged on the same plane. For example, the material may be removed by applying at least one technique of grinding, chemical mechanical polishing, etching, milling, etc. The thickness t of the part of the conductive material 36 arranged in the groove 28 between the through hole 30 and the via 32 may be in the range of about 15 microns to about 450 microns. In particular, the thickness t may be greater than about 100 microns, greater than about 200 microns, greater than about 300 microns, or greater than about 400 microns. Increasing the thickness t of the conductive material 36 may improve heat dissipation, and therefore may improve cooling of the semiconductor package to be manufactured.

[0047] exist Fig. 3I In the embodiment of the present invention, metallization material 36 may be deposited into first through hole 10, second through hole 12, via 16 and recess 40. Metallization material 36 and the techniques for applying the material may be similar to those of Figure 3H The bottom surface of the deposited metallization material 36 may correspond to a landing pad 42 of the semiconductor package to be manufactured. The landing pad 42 may be a contact pad configured to subsequently connect the semiconductor package to a circuit board. Note that by selecting the corresponding size and form of the recesses in the first prepolymer formation 2, the size of the landing pad 42, the form of the landing pad 42, and the distance between the landing pads 42 can be adjusted. Fig. 3I In the example of FIG. 4 , the gate electrode 18 , the source electrode 20 , and the drain electrode 22 may be connected by contacting a landing pad 42 disposed on the bottom surface of the arrangement.

[0048] exist Figure 3J In the embodiment of the present invention, an electrically insulating material 44 can be disposed on the upper surface of the arrangement to electrically insulate the conductive material 36 from other electronic or conductive elements. For example, the electrically insulating material 44 can be deposited in the form of a layer. It is noted that the electrically insulating material 44 can be deposited on multiple components of the semiconductor panel in parallel operations.

[0049] The method of FIG. 3 may further include additional operations, which are not described in detail for simplicity. Fig. 3I The semiconductor panel is singulated into a plurality of semiconductor packages 300, such as Figure 3J In addition, the singulated semiconductor package 300 may be arranged on a circuit board, wherein the landing pads 42 face the circuit board and may provide electrical and mechanical connections between the semiconductor package 300 and the circuit board.

[0050] Figure 4 and 5Schematically illustrates a cross-sectional side view of semiconductor packages 400 and 500 according to the present disclosure. The semiconductor packages 400 and 500 may be viewed as Figure 2 3. A more detailed embodiment of the semiconductor package 200 is shown in FIG. 3, and semiconductor packages 400 and 500 may be manufactured according to the method of FIG. 3.

[0051] Figure 4 The semiconductor package 400 may include a first prepolymer formed member 2 and a second prepolymer formed member 6 attached to the first prepolymer formed member 2. The semiconductor chip 4 may be arranged between the prepolymer formed members 2 and 6, and the semiconductor chip 4 may be packaged by the prepolymer formed members 2 and 6. Figure 4 In the example of , the semiconductor chip 4 may be a power transistor chip including a gate electrode 18 and a source electrode 20 arranged on a first surface of the semiconductor chip 4 and a drain electrode 22 arranged on an opposite second surface of the semiconductor chip 4. The electrodes of the semiconductor chip 4 may be redistributed on the bottom surface of the semiconductor package 400 by the conductive material 36 extending through the prepolymer forming members 2 and 6. The conductive layer 26 may be arranged between the prepolymer forming members 2 and 6. In addition, an electrically insulating layer 44 may be arranged on the upper surface of the semiconductor package 400. The semiconductor package 400 may be similar to Figure 3J A semiconductor package 300. Figure 3J In contrast, the landing pad 42 of the semiconductor package 400 has an increased footprint area to connect the semiconductor package 400 to a circuit board.

[0052] Figure 5 The semiconductor package 500 may be similar to Figure 4 A semiconductor package 400. Figure 4 In contrast, the semiconductor package 500 may further include a cavity 46, wherein the electronic component 48 may be arranged in the cavity. It should be understood that other examples of semiconductor packages described herein may also include a semiconductor component 48 arranged in a cavity similar to Figure 5 One or more electronic components in a cavity. Figure 5 In the example of , the cavity 46 can be formed by a groove of the second prepolymer formed part 6. In a further example, the cavity 46 can also be formed by a groove of the first prepolymer formed part 2 or a groove formed in the two prepolymer formed parts 2 and 6. The electronic component 48 can be electrically coupled to the semiconductor chip 4 through the conductive layer 26. In order to provide such electrical coupling, the conductive layer 26 can be structured in an additional operation. Figure 5 In the example of , in particular the electronic component 48 can be electrically coupled to the drain electrode 22 of the semiconductor chip 4 .

[0053] Figure 6 A flow chart of a method for manufacturing a semiconductor panel according to the present disclosure is shown. The method may be similar to the method of FIG. 1 , and may be read in conjunction with the method of FIG. 1 .

[0054] At 50, a first prepolymer forming piece is provided. At 52, a plurality of semiconductor chips are arranged on the first prepolymer forming piece. At 54, a second prepolymer forming piece is attached to the first prepolymer forming piece. The semiconductor chips are arranged between the attached prepolymer forming pieces. The attached prepolymer forming pieces form a semiconductor panel encapsulating the semiconductor chips.

[0055] Example

[0056] Hereinafter, a semiconductor panel, a semiconductor package, and a method of manufacturing the same are explained by way of examples.

[0057] Example 1 is a method for manufacturing a semiconductor panel, the method comprising: providing a first prepolymer formed piece; arranging a plurality of semiconductor chips on the first prepolymer formed piece; attaching a second prepolymer formed piece to the first prepolymer formed piece, wherein the semiconductor chips are arranged between the attached prepolymer formed pieces, and wherein the attached prepolymer formed pieces form a semiconductor panel encapsulating the semiconductor chips.

[0058] Example 2 is the method according to Example 1, wherein arranging the semiconductor chip includes: arranging the semiconductor chip in a plurality of grooves of the first prepolymer formation.

[0059] Example 3 is the method according to Example 1 or 2, wherein arranging the semiconductor chip includes: arranging an electrical contact of the semiconductor chip over the through hole of the first prepolymer formation.

[0060] Example 4 is a method according to Example 3, wherein arranging electrical contacts comprises: arranging a first electrical contact of the semiconductor chip on a first through hole, and arranging a second electrical contact of the semiconductor chip on a second through hole adjacent to the first through hole, wherein the first through hole and the second through hole can be separated by a separation structure.

[0061] Example 5 is the method according to any of the preceding examples, wherein attaching the second pre-polymer form includes arranging the through-holes of the second pre-polymer form over the electrical contacts of the semiconductor chip.

[0062] Example 6 is a method according to any of the preceding examples, further comprising: depositing a metallization material onto the through-hole of at least one of the prepolymer formations, wherein the deposited metallization material is electrically coupled to an electrical contact of the semiconductor chip.

[0063] Example 7 is the method of Example 6, wherein depositing the metallization material comprises cold gas spraying at least one of a metal and a metal alloy into the through hole.

[0064] Example 8 is a method according to Example 6 or 7, further comprising: partially removing at least one of the prepolymer forming piece and the metallization material, wherein after removing the material, the surface of at least one of the prepolymer forming piece and the surface of the metallization material can be arranged on the same plane.

[0065] Example 9 is a method according to one of Examples 6 to 8, wherein the first prepolymer form includes a first via extending through the first prepolymer form, the second prepolymer form includes a second via extending through the second prepolymer form, attaching the second prepolymer form includes providing an overlap between the first via and the second via, and the deposited metallization material forms an electrical via connection extending through the semiconductor panel.

[0066] Example 10 is a method according to any of the preceding examples, further comprising: prior to attaching the second pre-polymer form, disposing a conductive layer over the first pre-polymer form, wherein the conductive layer is disposed between the pre-polymer forms.

[0067] Example 11 is a method according to any of the preceding examples, further comprising: forming at least one groove in at least one of the prepolymer forms; and arranging an electronic component in the at least one groove, wherein the electronic component can be packaged into a semiconductor panel.

[0068] Example 12 is the method of Example 11, wherein the electronic component is electrically coupled to one of the semiconductor chips through a conductive layer.

[0069] Example 13 is a method according to any of the preceding examples, wherein the semiconductor chip comprises a power semiconductor chip.

[0070] Example 14 is a method according to any of the preceding examples, further comprising: constructing at least one of the prepolymer formations, wherein constructing comprises at least one of molding, milling, grinding, and laser drilling.

[0071] Example 15 is a method according to any of the preceding examples, wherein the semiconductor panel is rectangular in shape, and a surface area of ​​the rectangular semiconductor panel is greater than or equal to 300 mm×300 mm.

[0072] Example 16 is a semiconductor package, comprising: a first prepolymer formed piece; a second prepolymer formed piece attached to the first prepolymer formed piece; a semiconductor chip arranged between the attached prepolymer formed pieces, wherein the attached prepolymer formed pieces form a semiconductor package encapsulating the semiconductor chip.

[0073] Example 17 is a semiconductor package according to Example 16, further comprising: a metallization material electrically coupled to the electrical contacts of the semiconductor chip, wherein the metallization material is manufactured by cold gas spraying.

[0074] Example 18 is a semiconductor package according to Example 16 or 17, further comprising: a conductive layer disposed between the prepolymer formations.

[0075] Example 19 is a semiconductor package according to one of Examples 16 to 18, wherein at least one of the prepolymer formed parts includes at least one of a molding compound, a laminate, an epoxy resin, a filled epoxy resin, a glass fiber filled epoxy resin, an imide, a thermoplastic plastic, a thermosetting polymer, and a blended polymer.

[0076] Example 20 is a method for manufacturing a semiconductor package, the method including: manufacturing a semiconductor panel according to one of Examples 1 to 15; and singulating the semiconductor panel into a plurality of semiconductor packages.

[0077] As used in this specification, the terms "connected", "coupled", "electrically connected" and / or "electrically coupled" do not necessarily mean that the elements must be directly connected or coupled together. Intermediate elements may be provided between the elements that are "connected", "coupled", "electrically connected" or "electrically coupled".

[0078] Furthermore, the expression "on" used with respect to, for example, a material layer formed on or located "on" a surface of an object, is used herein to mean that the material layer may be "directly" located (e.g., formed, deposited, etc.) on the implied surface, e.g., in direct contact with the implied surface. The expression "on" used with respect to, for example, a material layer formed on or located "on" a surface, is also used herein to mean that the material layer may be "indirectly" located (e.g., formed, deposited, etc.) on the implied surface, e.g., one or more additional layers are disposed between the implied surface and the material layer.

[0079] Furthermore, to the extent the terms "having," "containing," "including," "comprising," or variations thereof are used in the detailed description or claims, they are intended to be inclusive in a manner similar to the term "comprising." That is, as used herein, the terms "having," "containing," "comprising," "having," "including," and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features.

[0080] In addition, the expression "exemplary" is used herein to mean used as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as superior to other aspects or designs. On the contrary, the use of the word exemplary is intended to present concepts in a concrete way.

[0081] Devices and methods for making the devices are described herein. Comments made in connection with the devices apply to the corresponding methods, and vice versa. For example, if specific elements of a device are described, the corresponding methods for making the device may include operations for providing the elements in a suitable manner, even if such operations are not explicitly described or shown in the drawings.

[0082] Although the present disclosure has been described with reference to illustrative embodiments, this description is not to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present disclosure will be apparent to those skilled in the art with reference to the description. Therefore, the appended claims cover any such modifications or embodiments.

Claims

1. A method for manufacturing a semiconductor panel, the method comprising: providing a first prepolymer forming member; Arranging a plurality of semiconductor chips on the first prepolymer forming member and in a plurality of grooves of the first prepolymer forming member; and attaching a second prepolymer form to the first prepolymer form, wherein the semiconductor chip is arranged between the attached prepolymer forming members, and The attached prepolymer forming member forms the semiconductor panel encapsulating the semiconductor chip.

2. The method according to claim 1, wherein arranging the semiconductor chip comprises: The electrical contacts of the semiconductor chip are arranged over the through holes of the first prepolymer formation.

3. The method of claim 2, wherein arranging the electrical contacts comprises: Arranging a first electrical contact of the semiconductor chip over the first through-hole, and Arranging a second electrical contact of the semiconductor chip over a second through hole adjacent to the first through hole, The first through hole and the second through hole are separated by a separation structure.

4. The method according to claim 1, further comprising: A metallization material is deposited into the through-holes of at least one of the pre-polymer formations, wherein the deposited metallization material is electrically coupled to an electrical contact of the semiconductor chip.

5. The method of claim 4, wherein depositing the metallization material comprises: At least one of a metal and a metal alloy is cold gas sprayed into the through-hole.

6. The method according to claim 4, further comprising: At least one of the prepolymer form and the metallization material is partially removed, wherein after the removing, a surface of at least one of the prepolymer form and a surface of the metallization material are arranged on a common plane.

7. The method according to claim 4, wherein The first prepolymer formed piece includes a first via extending through the first prepolymer formed piece, the second prepolymer formed piece includes a second via extending through the second prepolymer formed piece, Attaching the second prepolymer formation includes providing an overlap between the first via and the second via, and The deposited metallization material forms electrical via connections extending through the semiconductor panel. The method of claim 1 , wherein the semiconductor chip comprises a power semiconductor chip.

9. The method according to claim 1, further comprising: At least one of the prepolymer formations is structured, wherein the structured comprises at least one of molding, milling, grinding, laser drilling.

10. The method of claim 1, wherein the semiconductor panel is rectangular in shape, and a surface area of ​​the rectangular semiconductor panel is greater than or equal to 300 mm x 300 mm.

11. A method for manufacturing a semiconductor package, the method comprising: Manufacturing a semiconductor panel according to claim 1; and The semiconductor panel is singulated into a plurality of semiconductor packages.

12. A method for manufacturing a semiconductor panel, the method comprising: providing a first prepolymer forming member; Arranging a plurality of semiconductor chips on the first prepolymer formation; attaching a second prepolymer form to the first prepolymer form, and prior to attaching the second prepolymer formation, disposing a conductive layer over the first prepolymer formation, wherein the conductive layer is disposed between the prepolymer formations; wherein the semiconductor chip is arranged between the attached prepolymer forming members, and The attached prepolymer forming member forms the semiconductor panel encapsulating the semiconductor chip.

13. The method according to claim 12, further comprising: forming at least one groove in at least one of the prepolymer forms, and An electronic component is arranged in the at least one groove, wherein the electronic component is packaged into the semiconductor panel.

14. The method of claim 13, wherein the electronic component is electrically coupled to one of the semiconductor chips through the conductive layer.

15. A semiconductor package, comprising: a first prepolymer forming member; a second prepolymer form attached to the first prepolymer form; a semiconductor chip disposed between the attached prepolymer forming members, and a conductive layer disposed between the attached prepolymer forms, The attached prepolymer forming member forms a semiconductor package encapsulating the semiconductor chip.

16. The semiconductor package according to claim 15, further comprising: A metallization material electrically coupled to an electrical contact of the semiconductor chip, wherein the metallization material is produced by cold gas spraying.

17. The semiconductor package of claim 15, wherein at least one of the prepolymer formations comprises at least one of a mold compound, a laminate, an epoxy, a filled epoxy, a glass fiber filled epoxy, an imide, a thermoplastic, a thermoset polymer, a polymer blend.

18. A method for manufacturing a semiconductor panel, the method comprising: providing a first prepolymer forming member; Arranging a plurality of semiconductor chips on the first prepolymer formation; and attaching a second prepolymer form to the first prepolymer form, wherein the semiconductor chip is arranged between the attached prepolymer forming members, wherein the attached prepolymer forming member forms the semiconductor panel encapsulating the semiconductor chip, and The attaching of the second prepolymer forming member includes: arranging the through hole of the second prepolymer forming member over the electrical contact portion of the semiconductor chip.

19. The method according to claim 18, further comprising: A metallization material is deposited into the through-hole, wherein the deposited metallization material is electrically coupled to an electrical contact of the semiconductor chip.

20. The method according to claim 18, wherein arranging the semiconductor chip comprises: The semiconductor chips are arranged in the plurality of grooves of the first prepolymer formation.

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