Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof

Abstract

The present application discloses a chip substrate and a manufacturing method thereof, a packaged chip and a packaging method thereof, wherein a plurality of guide holes are provided on the chip substrate, and the spacing of the guide holes at the center position of the chip substrate is smaller than the spacing of the guide holes at the edge position of the chip substrate. The packaged chip comprises a bare chip and the above-mentioned chip substrate, wherein at least one groove is provided on the chip substrate, the bare chip is fixed in the groove, and the bare chip is electrically connected to the chip substrate. The manufacturing method of the chip substrate comprises: providing a chip substrate, forming a plurality of guide holes on the chip substrate, and making the spacing of the guide holes at the center position of the chip substrate smaller than the spacing of the guide holes at the edge position of the chip substrate. In the above manner, the present application can improve the chip packaging yield and reduce the chip packaging cost.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip substrate and a manufacturing method thereof, a packaged chip and a packaging method thereof. Background Art

[0002] With the continuous development of integrated circuit technology, the performance of integrated circuit chips is constantly improving. The heat dissipation problem of high-integration, high-performance, and high-power chips during operation is becoming more and more important. The increase in chip temperature will affect the working performance of the device, shorten the working life of the device, and even directly damage the device due to high temperature. The design of high-performance microprocessor packaging is becoming more and more challenging.

[0003] During the long-term research and development process, the inventors of the present application discovered that due to the different thermal expansion coefficients of the chip material and the chip substrate solder joints, the shrinkage of the chip size is smaller than the shrinkage of the chip substrate during the heating and cooling process after soldering reflow. Therefore, anisotropic stress will be generated on the soldering surface, causing the chip and the chip substrate to warp, which will affect the working performance of the device. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a chip substrate and a manufacturing method thereof, a packaged chip and a packaging method thereof, which can improve the chip packaging yield and reduce the chip packaging cost.

[0005] To solve the above technical problems, a technical solution adopted in the present application is: providing a chip substrate, on which a plurality of guide holes are provided, and the spacing between the guide holes at the center position of the chip substrate is smaller than the spacing between the guide holes at the edge position of the chip substrate.

[0006] To solve the above technical problems, another technical solution adopted in the present application is: to provide a packaged chip, the packaged chip comprising: a bare chip and the above-mentioned chip substrate; wherein, at least one groove is provided on the chip substrate, the bare chip is fixed in the groove, and the bare chip is electrically connected to the chip substrate.

[0007] To solve the above technical problems, another technical solution adopted in the present application is: to provide a method for manufacturing a chip substrate, the manufacturing method comprising: providing a chip substrate; forming a plurality of guide holes on the chip substrate, and making the spacing of the guide holes at the center position of the chip substrate smaller than the spacing of the guide holes at the edge position of the chip substrate.

[0008] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a chip packaging method, which includes: providing a chip substrate; opening at least one groove on the chip substrate; fixing the bare chip in the groove; forming a plurality of guide holes on the chip substrate, and making the spacing of the guide holes at the center position of the chip substrate smaller than the spacing of the guide holes at the edge position of the chip substrate; forming a metal conductive layer in at least a portion of the guide holes, and electrically connecting the bare chip to the metal conductive layer.

[0009] Different from the prior art, the beneficial effect of the present application is that since the maximum stress usually occurs at the solder joint at the edge of the chip substrate, the present application adopts a method in which the spacing of the guide holes at the center of the chip substrate is smaller than the spacing of the guide holes at the edge of the chip substrate, and sets the guide holes on the chip substrate. That is, the guide hole density at the edge of the chip substrate of the present application is smaller than the guide hole density at the center, thereby dispersing the stress between the guide holes at the edge, effectively avoiding chip damage caused by anisotropic stress on the welding surface, and problems such as chip peeling and breaking from the chip substrate, thereby improving product reliability, improving chip packaging yield, and reducing chip packaging costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0011] Figure 1 It is a structural schematic diagram of an embodiment of a chip substrate of the present application;

[0012] Figure 2 It is a structural schematic diagram of another embodiment of a chip substrate of the present application;

[0013] Figure 3 It is a structural schematic diagram of another embodiment of a chip substrate of the present application;

[0014] Figure 4 It is a structural schematic diagram of another embodiment of a chip substrate of the present application;

[0015] Figure 5 yes Figure 1 A schematic diagram of the partial structure of an embodiment of the middle chip substrate at the position of the guide hole 11;

[0016] Figure 6 yes Figure 1 A schematic diagram of the partial structure of another embodiment of the middle chip substrate at the position of the guide hole 11;

[0017] Figure 7 It is a structural schematic diagram of an embodiment of a packaged chip of the present application;

[0018] Figure 8 It is a schematic flow chart of an embodiment of a method for manufacturing a chip substrate of the present application;

[0019] Fig. 9 It is a schematic flow chart of another embodiment of a method for manufacturing a chip substrate of the present application;

[0020] Fig.10 It is a schematic flow chart of another embodiment of a method for manufacturing a chip substrate of the present application;

[0021] Fig.11 It is a flow chart of an embodiment of a chip packaging method of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] In the prior art, because the thermal expansion coefficients of the chip material and the chip substrate solder joints are different, during the heating and cooling process after soldering reflow, the shrinkage of the chip size is smaller than that of the chip substrate. Therefore, anisotropic stress will be generated on the soldering surface, causing the chip and the chip substrate to warp, which will affect the working performance of the device. Among them, the maximum stress usually occurs at the solder joints at the edge of the chip substrate. Therefore, the edge of the chip substrate is prone to damage to the solder joint connection, and even the chip and the chip substrate are peeled off, broken, etc., causing the chip device to fail, resulting in the chip packaging yield being limited and the chip packaging cost increasing sharply.

[0024] In order to solve the above technical problems, the present application proposes a chip substrate. Figure 1 , Figure 1 1 is a schematic diagram of the structure of an embodiment of a chip substrate of the present application. The chip substrate 10 is provided with a plurality of guide holes 11, and the spacing of the guide holes 11 at the center of the chip substrate 10 is smaller than the spacing of the guide holes 11 at the edge of the chip substrate 10. That is to say, in this embodiment, within a unit area, the density of the guide holes 11 at the center of the chip substrate 10 is greater than the density of the guide holes 11 at the edge of the chip substrate 10.

[0025] The shapes of the plurality of guide holes 11 may be triangular, circular, square or irregular shapes, etc. The position, shape, size and depth of the guide holes 11 may be set according to the chip substrate 10 or actual needs, and are not set here. The guide holes 11 may be half-through blind holes or through holes.

[0026] The chip substrate 10 may be in sheet form, with a thickness of >0.001 mm, a flat and smooth surface, preferably a mirror surface; its shape may be various polygons such as square and hexagon, or circular, elliptical, fan-shaped, and the like.

[0027] The chip substrate 10 is at least one of a composite metal chip substrate 10 and a plastic chip substrate 10, and can use various solid materials, such as conductor materials (such as Au, Ag, Al, Cu, stainless steel, AlSiC, SiC, AlSi, NiCu, CuAl, carbon steel, etc.), or semiconductor materials (such as Si, Ge, GaAs, InP, etc.), or insulating materials (such as Al 2 O 3 , ceramics, glass, etc.), and polymer materials (such as rubber, plastic, polytetrafluoroethylene, etc.).

[0028] In the above manner, since the maximum stress usually occurs at the solder joint at the edge of the chip substrate 10 in this embodiment, the spacing of the guide holes 11 at the center of the chip substrate 10 is smaller than the spacing of the guide holes 11 at the edge of the chip substrate 10 in this embodiment, and the guide holes 11 are arranged on the chip substrate 10. That is, the density of the guide holes 11 at the edge of the chip substrate 10 in this embodiment is smaller than the density of the guide holes 11 at the center, thereby dispersing the stress between the guide holes 11 at the edge, effectively avoiding chip damage caused by anisotropic stress on the welding surface, and problems such as separation and fracture of the chip and the chip substrate 10, thereby improving the reliability of the product, improving the chip packaging yield, and reducing the chip packaging cost.

[0029] See also Figure 2 , Figure 2 1 is a schematic diagram of the structure of another embodiment of a chip substrate of the present application. In one embodiment, the spacing between the plurality of guide holes 11 gradually increases from the center position of the chip substrate 10 to the edge position of the chip substrate 10. The spacing between the plurality of guide holes 11 refers to the spacing value between the center of each guide hole 11 and the center of the adjacent guide hole 11. For example. The spacing between the plurality of guide holes 11 at the center position of the chip substrate 10 is smaller, and the spacing between the plurality of guide holes 11 at the edge position of the chip substrate 10 is larger.

[0030] Among them, Figure 2As shown, in one embodiment, a plurality of guide holes at least form a first guide hole group 11A and a second guide hole group 11B. In this embodiment, the first guide hole group 11A and the second guide hole group 11B are both in a straight line shape and are arranged crosswise with each other. It can be understood that in some other embodiments, the first guide hole group 11A and the second guide hole group 11B can also be in a curved shape. From the center position to the edge position of the chip substrate, the spacing between the guide holes of the first guide hole group 11A gradually increases, and the spacing between the guide holes of the second guide hole group 11B gradually increases. For example. At the center position of the chip substrate, the spacing between the plurality of guide holes of the first guide hole group 11A is small, and at the edge position of the chip substrate, the spacing between the plurality of guide holes of the first guide hole group 11A is large. At the center position of the chip substrate, the spacing between the plurality of guide holes of the second guide hole group 11B is small, and at the edge position of the chip substrate, the spacing between the plurality of guide holes of the second guide hole group 11B is large.

[0031] See also Figure 3 , Figure 3 It is a structural schematic diagram of another embodiment of a chip substrate of the present application. A plurality of guide holes can be formed into a plurality of guide hole groups arranged crosswise at equal angles. For example, a plurality of guide holes can be formed into at least four guide hole groups in a cross-shaped structure, which are composed of four guide hole groups arranged crosswise at equal angles, and the angle between the straight line where the center of the guide hole of each guide hole group is located and the straight line where the center of the guide hole of the adjacent guide hole group is located is 45°, and the straight lines where the centers of the guide holes of the four guide hole groups intersect at the same point. For another example, a plurality of guide holes can be formed into at least three guide hole groups, which are composed of three guide hole groups arranged crosswise at equal angles, and the angle between the straight line where the center of the guide hole of each guide hole group is located and the straight line where the center of the guide hole of the adjacent guide hole group is located is 60°, and the straight lines where the centers of the guide holes of the three guide hole groups intersect at the same point.

[0032] Further, see Figure 4 , Figure 4 1 is a schematic diagram of the structure of another embodiment of a chip substrate of the present application. The first guide hole group 11A and the second guide hole group 11B are perpendicular to each other. For example, the two guide hole groups in a cross-shaped structure are perpendicular to each other, and the angle between the straight line where the center of the guide hole of the first guide hole group 11A is located and the straight line where the center of the guide hole of the second guide hole group 11B is located is 90°.

[0033] See also Figure 5 , Figure 5 yes Figure 1 A schematic diagram of a partial structure of an embodiment of a chip substrate at the position of a guide hole 11. A metal conductive layer 12 is provided on the inner wall of at least a portion of the guide hole 11, and the metal conductive layer 12 surrounds a first cavity. The metal conductive layer 12 can be formed by chemical plating or sputtering. The first cavity is filled with a metal conductive material 120, and the metal conductive material 120 is selected from copper, tin, silver, platinum, gold and a combination thereof.

[0034] Specifically, a hot melt process, an electroplating process, or a deposition process may be used to form a metal conductive layer 12 on a portion or all of the inner walls of the guide hole 11. For example, the metal conductive layer 12 may be formed on the hole wall of the guide hole 11 by chemical plating, and the process of forming the metal conductive layer 12 is the hole metallization process. The metal conductive layer 12 completely covers the inner wall of the guide hole 11 and surrounds a first cavity, which may be used to fill the metal conductive material 120.

[0035] See also Figure 6 , Figure 6 yes Figure 1 A schematic diagram of the partial structure of another embodiment of the chip substrate at the position of the guide hole 11. The inner wall of at least a portion of the guide hole 11 may be provided with a metal heat-conducting layer 13, and the metal heat-conducting layer 13 surrounds the second cavity. The metal heat-conducting layer 13 may be formed by chemical plating or sputtering. The second cavity is filled with a metal heat-conducting material 130, and the metal heat-conducting material 130 is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and a combination thereof.

[0036] Specifically, a metal thermal conductive layer 13 can be formed on the inner wall of a part or all of the guide hole 11 by a hot melt process, an electroplating process or a deposition process. For example, a metal layer can be formed on the hole wall of the guide hole 11 by chemical plating, and the process of forming the metal thermal conductive layer 13 is the hole metallization process. The metal thermal conductive layer 13 completely covers the inner wall of the guide hole 11 and encloses a second cavity, which can be used to fill the above-mentioned metal thermal conductive material 130. Among them, graphene material has an extremely high in-plane thermal conductivity coefficient, which can be as high as 5000W / m·K, which is higher than carbon nanotubes and diamonds. At present, graphene is the thermal conductive material with the best performance. Using graphene as a thermal interface material is expected to obtain excellent heat dissipation performance and has great market potential. Due to the physical properties of graphene two-dimensional materials, in order to obtain good heat dissipation performance, it needs to be vertically located between the heat source and the heat sink.

[0037] See also Figure 7 , Figure 7 1 is a schematic diagram of a packaged chip according to an embodiment of the present application. The packaged chip 100 comprises: a bare chip 20 and a chip substrate 10 in any of the above embodiments. The chip substrate 10 is provided with at least one groove, the bare chip 20 is fixed in the groove, and the bare chip 20 is electrically connected to the chip substrate 10.

[0038] Specifically, a groove can be opened on the chip substrate 10 by controlled depth milling, or by etching and laser ablation. A groove is opened on the chip substrate 10 to facilitate the subsequent embedding of the chip. The groove must have a certain depth. In this embodiment, the size of the groove is determined according to the size of the bare chip 20 to be embedded. An adhesive can be used to fix the bare chip 20 in the groove. The adhesive can be a chip-mounting resin or a silver-based resin or other non-conductive adhesive that can fix the bare chip 20 in the groove, so that the bare chip 20 is fixed in the groove. When the chip substrate 10 needs to be embedded with multiple chips of different thicknesses, it is ensured that the chips of different thicknesses remain coplanar after being packaged into the chip substrate 10, and the length and width of the groove are at least larger than the size of the chip to be embedded, so that the groove can be large enough to accommodate the chip to be embedded.

[0039] Furthermore, a filling material may be used to fill the gap between the substrate 10 and the bare chip 20 so that the groove is filled. The filling material is a material used for semiconductor packaging, which is usually a liquid, has heat dissipation and insulation functions, and becomes solid at 120°C-300°C. It should be noted that the filling material may also be a material that is usually a liquid, has heat dissipation and electrical conductivity, and becomes solid at 120°C-300°C. If there is a pad at the bottom of the bare chip 20, this material can be used to make it electrically connected to the bottom of the groove, which is not limited here.

[0040] The bare chip 20 includes a plurality of pins 21, and the plurality of pins 21 are connected to the metal conductive layer 12 or the metal thermal conductive layer 13 in the guide hole 11 on the chip substrate 10 through a conductive adhesive. In other embodiments, the bare chip 20 can be directly electrically connected to the chip substrate 10 through a filled conductive medium, so that no leads or pins 21 are required.

[0041] The packaged chip 100 has a power density of 350W / cm 2 Above or / and hot spot reaches 10KW / cm 2 The above chip 100.

[0042] When the system uses a lot of power density up to 350W / cm 2 Above or / and hot spot reaches 10KW / cm 2For the above chip 100, the maximum junction temperature that can be controlled by the original heat sink and fan of the chip is only about 100°C, and the design requires that the temperature of the chip package shell cannot exceed 65°C. If forced air cooling is used to solve the heat dissipation of the chip, it will cause the electronic product to work unstably. Therefore, the chip 100 often overheats. Furthermore, the shrinkage of the chip 100 size is smaller than the shrinkage of the chip substrate 10. Therefore, anisotropic stress will be generated on the welding surface, causing the chip 100 and the chip substrate 10 to warp, which will affect the working performance of the device. For this type of chip 100, the chip substrate 10 in any of the above embodiments can be used to disperse the stress between the guide holes 11 at the edge position, which can effectively avoid chip damage caused by anisotropic stress on the welding surface and the peeling and breaking of the chip 100 and the chip substrate 10, thereby improving the reliability of the product, improving the packaging yield of the chip 100, and reducing the packaging cost of the chip 100.

[0043] See also Figure 8 , Figure 8 This is a flow chart of an embodiment of a method for manufacturing a chip substrate of the present application. The manufacturing method includes:

[0044] S11: Provide a chip substrate.

[0045] S12: forming a plurality of guide holes on the chip substrate, and making the pitch of the guide holes at the center position of the chip substrate smaller than the pitch of the guide holes at the edge position of the chip substrate.

[0046] Specifically, on one side of the chip substrate, a laser beam can be used to form a half-through blind hole structure at a predetermined processing guide hole position.

[0047] Among them, in step S12, the spacing between the plurality of guide holes is gradually increased from the center position of the chip substrate to the edge position of the chip substrate. That is, the guide hole density at the edge position of the chip substrate of this embodiment is less than the guide hole density at the center position, thereby dispersing the stress between the guide holes at the edge position, and effectively avoiding chip damage caused by anisotropic stress on the welding surface, as well as the peeling and breaking of the chip and the chip substrate, thereby improving the reliability of the product, improving the chip packaging yield, and reducing the chip packaging cost.

[0048] See also Fig. 9 , Fig. 9 FIG. 1 is a flow chart of another embodiment of a method for manufacturing a chip substrate of the present application. In one embodiment, the manufacturing method further includes:

[0049] S21: Provide a chip substrate.

[0050] S22: forming a plurality of guide holes on the chip substrate, and making the pitch of the guide holes at the center of the chip substrate smaller than the pitch of the guide holes at the edge of the chip substrate.

[0051] S23: electroplating a metal conductive layer on the inner wall of at least a portion of the guide hole, wherein the metal conductive layer surrounds a first cavity.

[0052] S24: Filling the first cavity with a metal conductive material.

[0053] Steps S21-S22 in this embodiment are the same as steps S11-S12 in the above embodiment. Please refer to the above embodiment for details, which will not be repeated here.

[0054] The metal conductive material is selected from copper, tin, silver, platinum, gold and combinations thereof. Specifically, a metal conductive layer can be formed on the inner wall of at least a portion of the guide hole by a hot melt process, an electroplating process or a deposition process. For example, a metal conductive layer can be formed on the hole wall of the guide hole by chemical plating, and the process of forming the metal conductive layer is the hole metallization process. The metal conductive layer completely covers the inner wall of the guide hole and surrounds a first cavity, which can be used to fill the above-mentioned metal conductive material.

[0055] See also Fig.10 , Fig.10 FIG. 1 is a flow chart of another embodiment of a method for manufacturing a chip substrate of the present application. In one embodiment, the manufacturing method further includes:

[0056] S31: Provide a chip substrate.

[0057] S32: forming a plurality of guide holes on the chip substrate, and making the pitch of the guide holes at the center of the chip substrate smaller than the pitch of the guide holes at the edge of the chip substrate.

[0058] S33: electroplating a metal heat-conducting layer on the inner wall of at least a portion of the guide hole, wherein the metal heat-conducting layer surrounds a second cavity.

[0059] S34: Filling the second cavity with a metal heat-conducting material.

[0060] Steps S31-S32 in this embodiment are the same as steps S11-S12 in the above embodiment. Please refer to the above embodiment for details, which will not be repeated here.

[0061] The metal thermal conductive material is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and a combination thereof. Specifically, a metal thermal conductive layer can be formed on the inner wall of at least a portion of the guide hole by a hot melt process, an electroplating process or a deposition process. For example, a metal thermal conductive layer can be formed on the hole wall of the guide hole by chemical plating, and the process of forming the metal thermal conductive layer is the hole metallization process. The metal thermal conductive layer completely covers the inner wall of the guide hole and surrounds a first cavity, which can be used to fill the above-mentioned metal thermal conductive material.

[0062] It should be noted that, for the detailed description of the chip substrate in the above-mentioned chip substrate manufacturing method, please refer to the above-mentioned chip substrate part, which will not be repeated here.

[0063] See also Fig.11 , Fig.11 1 is a flow chart of an embodiment of a chip packaging method of the present application. The packaging method includes:

[0064] S41: Provide a chip substrate.

[0065] S42: Open at least one groove on the chip substrate.

[0066] Specifically, at least one groove is formed on the chip substrate to be embedded. The groove can be formed on the chip substrate by controlled depth milling, or by etching and laser ablation, which is not limited here. A groove is formed on the chip substrate to facilitate the subsequent embedding of the chip. The groove must have a certain depth. In this embodiment, the size of the groove is determined according to the size of the chip to be embedded.

[0067] S43: Fix the bare chip in the groove.

[0068] Specifically, the bare chip can be fixed in the groove using adhesive, and the bare chip can be embedded in the groove. The adhesive can be chip attaching resin or silver-based resin or other non-conductive adhesive that can fix the chip in the groove, so that the bare chip is fixed in the groove.

[0069] S44: forming a plurality of guide holes on the chip substrate, wherein the plurality of guide holes are formed on the chip substrate, and a pitch of the guide holes at a center position of the chip substrate is smaller than a pitch of the guide holes at an edge position of the chip substrate;

[0070] S45: forming a metal conductive layer in at least a portion of the guide holes, and electrically connecting the bare chip to the metal conductive layer.

[0071] Specifically, the chip substrate with the bare chip mounted thereon is covered with an insulating resin laminate on one side close to the chip and then hot-pressed by vacuum means. Finally, a blind hole is laser drilled through the metal pad on the surface of the bare chip (i.e., the electrode of the chip, the electrode thickness is generally 0.1μm-0.5μm, for example, 0.1μm, 0.2μm, 0.4μm or 0.5μm), and then a conductive medium (such as a copper electrode) is formed by electroplating the blind hole to achieve electrical connection between the chip and the external circuit.

[0072] The spacing of the guide holes at the center of the chip substrate is smaller than the spacing of the guide holes at the edge of the chip substrate.

[0073] Furthermore, the bare chip includes a plurality of pins, and in step S45, the pins can be connected to the metal conductive layer by means of conductive glue.

[0074] It should be noted that, for the detailed description of the chip in the above chip packaging method, please refer to the above packaged chip part, which will not be repeated here.

[0075] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip substrate, It is characterized in that The chip substrate is provided with a plurality of guide holes, and the spacing of the guide holes at the center position of the chip substrate is smaller than the spacing of the guide holes at the edge position of the chip substrate; wherein the spacing between the plurality of guide holes gradually increases from the center position of the chip substrate to the edge position of the chip substrate; the guide holes are half-through blind holes; at least a portion of the inner walls of the guide holes are provided with a metal heat-conducting layer, the metal heat-conducting layer surrounds a second cavity, and the second cavity is filled with a metal heat-conducting material.

2. The chip substrate according to claim 1, It is characterized in that The plurality of guide holes at least form a first guide hole group and a second guide hole group which are both linear, and the first guide hole group and the second guide hole group are arranged crosswise.

3. The chip substrate according to claim 2, It is characterized in that From the center position to the edge position of the chip substrate, the spacing between the guide holes of the first guide hole group gradually increases, and the spacing between the guide holes of the second guide hole group gradually increases.

4. The chip substrate according to claim 2, It is characterized in that The first guide hole group and the second guide hole group are both in a straight line shape, and the first guide hole group and the second guide hole group are perpendicular to each other.

5. The chip substrate according to claim 1, It is characterized in that At least a portion of the inner walls of the guide holes are provided with a metal conductive layer, and the metal conductive layer surrounds a first cavity.

6. The chip substrate according to claim 5, It is characterized in that The first cavity is filled with a metal material, and the metal material is selected from copper, tin, silver, platinum, gold and a combination thereof.

7. The chip substrate according to claim 1, It is characterized in that The metal thermal conductive material is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and a combination thereof.

8. The chip substrate according to claim 1, It is characterized in that The plurality of guide holes are in a circular or square shape.

9. The chip substrate according to claim 1, It is characterized in that The chip substrate is at least one of a composite metal chip substrate and a plastic chip substrate.

10. A packaged chip, It is characterized in that The packaged chip comprises: a bare chip and a chip substrate as described in any one of claims 1 to 9 above; Wherein, at least one groove is provided on the chip substrate, the bare chip is fixed in the groove, and the bare chip is electrically connected to the chip substrate.

11. The packaged chip according to claim 10, It is characterized in that The bare chip includes a plurality of pins, and the plurality of pins are connected to the metal conductive layer or the metal heat conductive layer in the guide hole on the chip substrate through a conductive adhesive.

12. The packaged chip according to claim 11, It is characterized in that The packaged chip has a power density of 350W / cm 2 Above or / and hot spot reaches 10KW / cm 2 The above chips.

13. A method for manufacturing a chip substrate, It is characterized in that The production method comprises: Providing a chip substrate; A plurality of guide holes are formed on the chip substrate, and the spacing between the guide holes at the center of the chip substrate is smaller than the spacing between the guide holes at the edge of the chip substrate, including: the spacing between the plurality of guide holes gradually increases from the center of the chip substrate to the edge of the chip substrate; the guide holes are half-through blind holes; The manufacturing method further comprises: forming a metal heat-conducting layer on at least a portion of the inner wall of the guide hole, wherein the metal heat-conducting layer surrounds a second cavity; The second cavity is filled with a metal heat-conducting material.

14. The method according to claim 13, It is characterized in that The production method further comprises: forming a metal conductive layer on at least a portion of the inner wall of the guide hole, wherein the metal conductive layer surrounds a first cavity; The first cavity is filled with a metal conductive material, wherein the metal conductive material is selected from copper, tin, silver, platinum, gold and a combination thereof.

15. The method according to claim 13, It is characterized in that The metal thermal conductive material is selected from copper, tin, silver, platinum, gold, carbon powder, artificial graphite, graphene and a combination thereof.

16. A chip packaging method, It is characterized in that The packaging method comprises: Providing a chip substrate; Opening at least one groove on the chip substrate; Fixing the bare chip in the groove; A plurality of guide holes are formed on the chip substrate, and the spacing between the guide holes at the center of the chip substrate is smaller than the spacing between the guide holes at the edge of the chip substrate, including: the spacing between the plurality of guide holes gradually increases from the center of the chip substrate to the edge of the chip substrate; the guide holes are half-through blind holes; forming a metal conductive layer in at least a portion of the guide holes, and electrically connecting the bare chip to the metal conductive layer; forming a metal heat-conducting layer on the inner wall of at least a portion of the guide hole, wherein the metal heat-conducting layer surrounds a second cavity; The second cavity is filled with a metal heat-conducting material.

17. The packaging method according to claim 16, It is characterized in that The bare chip includes a plurality of pins; In the step of forming a metal conductive layer in at least a portion of the guide holes and electrically connecting the bare chip to the metal conductive layer, the pins are connected to the metal conductive layer by means of a conductive adhesive.

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