Vertical memory device

Abstract

A vertical memory device includes a substrate having a cell array region and a stepped region surrounding the cell array region, gate electrodes located on the cell array region and the stepped region, and a channel located on the cell array region. The gate electrodes are spaced apart from each other in a first direction and a third direction and each extends in a second direction. The channel extends through one or more gate electrodes in the first direction. The end of a first gate electrode in the second direction defines a first step in the second direction and a second step in the third direction on the stepped region of the substrate, each second step being connected to a first step at the same horizontal height.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0165825, filed on December 20, 2018, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This invention relates to a vertical memory device. More specifically, this invention relates to a vertical memory device having gate electrodes stacked in a stepped structure. Background Technology

[0004] When manufacturing VNAND flash memory devices, sacrificial layers and insulating layers are stacked alternately and repeatedly. Each sacrificial layer is patterned to form steps in stepped regions where contact plugs for connection to upper wiring are formed. An etching process can be performed using a photoresist pattern that partially covers the steps, thereby forming a molded part with a stepped structure. As the number of steps included in the molded part increases, the area of ​​the molded part may increase, potentially reducing the integration density of the VNAND flash memory device. Summary of the Invention

[0005] An example embodiment provides a vertical memory device with good characteristics.

[0006] According to some example embodiments, a vertical memory device may include a substrate comprising a cell array region and a stepped region surrounding the cell array region. The vertical memory device may include a plurality of gate electrodes located on the cell array region and the stepped region of the substrate. The plurality of gate electrodes may be spaced apart in a first direction to prevent direct contact with each other. Each of the plurality of gate electrodes may extend in a second direction. The plurality of gate electrodes may be further spaced apart in a third direction to prevent direct contact with each other. The first direction may be substantially perpendicular to the upper surface of the substrate. A third direction may be substantially parallel to the upper surface of the substrate. The second direction may be substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction. The vertical memory device may include a channel located on the cell array region of the substrate. The channel may extend through one or more of the plurality of gate electrodes in the first direction. The end of a first gate electrode in the second direction defines a first step in the second direction and a second step in the third direction on the stepped region of the substrate, the second steps respectively connecting to the first step at the same horizontal height.

[0007] According to some example embodiments, a vertical memory device may include a substrate comprising a cell array region and a stepped region surrounding the cell array region. The vertical memory device may include a plurality of gate electrodes located on the cell array region and the stepped region of the substrate. The plurality of gate electrodes may be spaced apart in a first direction to avoid direct contact with each other. Each of the plurality of gate electrodes may extend in a second direction. The plurality of gate electrodes may be further spaced apart in a third direction to avoid direct contact with each other. The first direction may be substantially perpendicular to the upper surface of the substrate. A third direction may be substantially parallel to the upper surface of the substrate. The second direction may be substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction. The vertical memory device may include a channel located on the cell array region of the substrate. The channel may extend through one or more of the plurality of gate electrodes in the first direction. The end of a first gate electrode in the second direction may define a first step in the second direction on the stepped region of the substrate. The end of a second gate electrode above the first gate electrode in the second direction may define a second step in the second direction and / or a second step in the second direction and / or a third direction upward on the stepped region of the substrate. The first step may overlap with the second step in the first direction.

[0008] According to some example embodiments, a vertical memory device may include a substrate comprising a cell array region and a stepped region surrounding the cell array region. The vertical memory device may include a plurality of gate electrodes located on the cell array region and the stepped region of the substrate. The plurality of gate electrodes may be spaced apart in a first direction to avoid direct contact with each other. Each of the plurality of gate electrodes may extend in a second direction. The plurality of gate electrodes may be further spaced apart in a third direction to avoid direct contact with each other. The first direction may be substantially perpendicular to the upper surface of the substrate. The third direction may be substantially parallel to the upper surface of the substrate. The second direction may be substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction. The vertical memory device may include a channel located on the cell array region of the substrate. The channel may extend through one or more of the plurality of gate electrodes in the first direction. The end of the first gate electrode in the second direction may be defined in a plan view as a first step each having an "L" shape.

[0009] Vertical memory devices may not have an increased horizontal area, but they can effectively achieve enhanced integration by using sequentially stacked gate electrodes. Attached Figure Description

[0010] Figures 1 to 64 These are plan views, cross-sectional views, and perspective views illustrating a method of manufacturing a vertical memory device according to some example embodiments.

[0011] Figure 1 , Figures 13A to 13B , Figure 20 , Figure 25 , Figure 28 , Figure 39 , Figure 42 , Figure 51 , Figure 53 , Figures 56 to 57 and Figure 60 This is a plan view illustrating a method of manufacturing a vertical memory device according to some example embodiments. Figure 13. Figure 20 , Figure 25 , Figure 39 , Figure 42 and Figure 56 Based on some example embodiments Figure 1 A plan view of region X. Figure 28 , Figure 51 , Figure 53 , Figure 57 and Figure 60 Based on some example embodiments Figure 1 A planar diagram of region Y.

[0012] Figure 2 , Figure 4 , Figure 6 , Figures 21 to 24 , Figures 26 to 27 , Figures 29 to 31 , Figures 44 to 50 , Figure 52 , Figures 54 to 55 , Figure 58 and Figures 61 to 64 This is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments. Figure 4 , Figure 21 and Figure 44 It is based on some example embodiments along Figure 1 A cross-sectional view taken from line A-A'. Figure 6 , Figure 22 , Figure 24 , Figure 27 , Figures 29 to 31 , Figure 45 , Figure 47 , Figures 49 to 50 and Figure 61 It is based on some example embodiments along Figure 1 A cross-sectional view taken from line B-B'. Figure 26 , Figure 48 and Figure 62 It is based on some example embodiments along Figure 1 The cross-sectional view taken from line C-C'. Figure 52 , Figures 54 to 55 and Figure 58 It is based on some example embodiments along Figure 1 The cross-sectional view taken by line D-D'. Figure 2 and Figure 64 It is based on some example embodiments along Figure 1 The cross-sectional view taken from line E-E'. Figure 23 , Figure 46 and Figure 63 It is based on some example embodiments along Figure 1 The cross-sectional view taken by line F-F'.

[0013] Figure 3 , Figure 5 , Figures 7 to 12 , Figures 14 to 19 , Figures 32 to 38 , Figures 40 to 41 , Figure 43 and Figure 59 This is a perspective view illustrating a method of manufacturing a vertical memory device according to some example embodiments. Detailed Implementation

[0014] The above and other aspects and features of the vertical memory device and the method of manufacturing it, according to some exemplary embodiments, will become readily understood from the following detailed description with reference to the accompanying drawings.

[0015] Figures 1 to 64 These are plan views, cross-sectional views, and perspective views illustrating a method of manufacturing a vertical memory device 1 according to some example embodiments. Specifically, Figure 1 Figure 13 Figure 20 , Figure 25 , Figure 28 , Figure 39 , Figure 42 , Figure 51 , Figure 53 , Figures 56 to 57 and Figure 60 It's a floor plan. Figure 2 , Figure 4 , Figure 6 , Figures 21 to 24 , Figures 26 to 27 , Figures 29 to 31 , Figures 44 to 50 , Figure 52 , Figures 54 to 55 , Figure 58 and Figures 61 to 64 It is a cross-sectional view, and Figure 3 , Figure 5 , Figures 7 to 12 , Figures 14 to 19 , Figures 32 to 38 , Figures 40 to 41 , Figure 43 and 59 It is a perspective view.

[0016] Figure 13 Figure 20 , Figure 25 , Figure 39 , Figure 42 and Figure 56 yes Figure 1 A planar view of region X. Figure 28 , Figure 51 , Figure 53 , Figure 57 and Figure 60 yes Figure 1 A planar diagram of region Y, and Figure 3 , Figure 5 , Figures 7 to 12 , Figures 14 to 19 , Figures 32 to 38 , Figures 40 to 41 , Figure 43 and Figure 59 yes Figure 1 A perspective view of region X.

[0017] Figure 4 , Figure 21 and Figure 44 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 6 , Figure 22 , Figure 24 , Figure 27 , Figures 29 to 31 , Figure 45 , Figure 47 , Figures 49 to 50 and Figure 61 It is along Figure 1 A cross-sectional view taken from line B-B'. Figure 26 , Figure 48 and Figure 62 It is along Figure 1 A cross-sectional view taken from line C-C'. Figure 52 , Figures 54 to 55 and Figure 58 It is along Figure 1 A cross-sectional view taken from line D-D'. Figure 2 and Figure 64 It is along Figure 1 The cross-sectional view taken by line E-E', and Figure 23 , Figure 46 and Figure 63 It is along Figure 1 The cross-sectional view taken by line F-F'.

[0018] In the following description, a direction substantially perpendicular to the upper surface 600a of the substrate 600 (e.g., perpendicular within manufacturing and / or material tolerances) may be defined as a first direction, and two directions substantially parallel to the upper surface 600a of the substrate 600 (e.g., parallel within manufacturing and / or material tolerances) and intersecting each other may be defined as a second direction and a third direction, respectively. In some example embodiments, the second direction and the third direction may be substantially perpendicular to each other (e.g., perpendicular within manufacturing and / or material tolerances).

[0019] Reference Figure 1The substrate 600 may include a first region I and a second region II surrounding the first region I.

[0020] Substrate 600 may include silicon, germanium, silicon-germanium, or III-V composites (such as GaP, GaAs, GaSb). In some embodiments, substrate 600 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some example embodiments (including...) Figures 1 to 64 In the example embodiment shown, the first region I of the substrate 600 may be a cell array region in which memory cells may be formed, and the second region II of the substrate 600 may be a stepped region in which contact plugs connected to the memory cells are formed.

[0021] In some exemplary embodiments, the vertical memory device 1 may have a cell over periphery (COP) structure. That is, the circuit pattern 699 for driving the memory cell may not be formed on the periphery of the memory cell, but may be formed below the memory cell. Therefore, the circuit pattern region and the cell array region can be vertically stacked on the substrate 600, and the circuit pattern 699 may also be referred to as the lower circuit pattern. However, the inventive concept is not limited to this, and even if the vertical memory device 1 has a COP structure, the substrate 600 may also include a peripheral circuit region surrounding the second region II, in which some circuit patterns may be formed.

[0022] It will be understood that, as described herein, an element located "on" another element may be located "above" or "below" that other element. Furthermore, it will be understood that, as described herein, an element located "on" another element may be directly on that other element such that the elements are in direct contact with each other, or an element located "on" another element may be indirectly on that other element such that the elements are separated from each other by one or more insertion structures and / or spaces to prevent direct contact.

[0023] Figure 1 Region X shown is part of the second region II of substrate 600, and region Y includes a portion of region X and a portion of the first region I of substrate 600 adjacent to region X in a second direction. In some example embodiments, multiple regions X may be arranged in a third-direction upward direction, and regions Y may be arranged at each of the opposite sides of regions X in a third-direction upward direction. The portions of regions X and Y of substrate 600 that overlap with each other may be referred to as third region III and fourth region IV, respectively, and the portion of region X located between third region III and fourth region IV may be referred to as fifth region V.

[0024] Reference Figure 2The circuit pattern 699 may be formed on the substrate 600, and the first lower insulating layer 660 and the second lower insulating layer 730 may be formed on the substrate 600 to cover the circuit pattern 699.

[0025] The substrate 600 may include a field-effect region on which an isolation pattern 610 is formed and an active region on which no isolation pattern is formed. The isolation pattern 610 may be formed by, for example, shallow trench isolation (STI) processing and may include, for example, silicon oxide.

[0026] The circuit pattern 699 may include transistors, lower contact plugs, lower wiring, lower vias, etc. For example, a transistor may be formed including a lower gate structure 650 on a substrate 600 and a first impurity region 605 adjacent thereto located at the upper portion of the active region of the substrate 600. The lower gate structure 650 may include a lower gate insulating pattern 620, a lower gate electrode 630, and a lower gate mask 640 stacked in sequence.

[0027] A first lower insulating interlayer 660 may be formed on the substrate 600 to cover the transistor, and a lower contact plug 670 may extend through the first lower insulating interlayer 660 to contact the first impurity region 605. A first lower wiring 680 may be formed on the first lower insulating interlayer 660 to contact the upper surface of the lower contact plug 670. A first lower via 690, a second lower wiring 700, a second lower via 710, and a third lower wiring 720 may be sequentially stacked on the first lower wiring 680. In some example embodiments, a plurality of third lower wirings 720 may be formed in the third-party direction. Each of the first to third lower wirings 680, 700, and 720, and each of the first lower via 690 and the second lower via 710, may be formed by damascene processing or patterning.

[0028] The second lower insulating interlayer 730 may be formed on the first lower insulating interlayer 660 to cover the first to third lower wirings 680, 700 and 720, as well as the first lower via 690 and the second lower via 710.

[0029] In the following description, the circuit pattern 699 on the substrate 600 will not be shown in the accompanying drawings to avoid complicating the drawings.

[0030] Reference Figure 3 and Figure 4 The bottom pattern 100 may be formed on the second lower insulating interlayer 730, and the insulating layer 110 and the sacrificial layer 120 may be sequentially formed on the bottom pattern 100. Therefore, it will be understood that the bottom pattern 100 may be located on the substrate 600.

[0031] The base pattern 100 may include a semiconductor material (e.g., silicon), the insulating layer 110 may include an oxide (e.g., silicon oxide), and the sacrificial layer 120 may include a material that has etch selectivity relative to the insulating layer 110 (e.g., a nitride such as silicon nitride).

[0032] A portion of the sacrificial layer 120 located on the second region II of the substrate 600 can be removed to form a first opening that exposes the insulating layer 110, and a first dividing pattern 130 can be formed to fill the first opening.

[0033] In some example embodiments, a plurality of first partition patterns 130 may be formed on each of the third region III and the fourth region IV of the substrate 600 in a third-party orientation. The first partition patterns 130 may include oxides, such as silicon oxide.

[0034] Reference Figure 5 and Figure 6 The insulating layer 110 and the sacrificial layer 120 may also be formed alternately and repeatedly on the sacrificial layer 120 and the first dividing pattern 130, such that a lower molding layer comprising the insulating layer 110 and the sacrificial layer 120 alternately stacked in the first direction can be formed. In addition, an etch stop layer 190 may be formed on the uppermost insulating layer of the insulating layer 110 in the lower molding layer.

[0035] To avoid complicating the accompanying drawings, the following text will include... Figure 5 In all perspective views, insulating layer 110 will not be shown; only sacrificial layer 120 will be shown. The etching process of sacrificial layer 120 may be performed not only on sacrificial layer 120 but also on insulating layer 110. Each insulating layer 110 may form a pair with a sacrificial layer 120 directly below it. For ease of explanation, insulating layer 110 will not be described when the etching process is described with reference to perspective views.

[0036] Reference Figure 7 A first photoresist (not shown) may be formed on the etch stop layer 190 to cover the edge portion of the first region I and the adjacent second region II, and the first photoresist may be used as an etch mask to etch the uppermost sacrificial layer of the etch stop layer 190 and the sacrificial layer 120 of the lower molding layer to form a first sacrificial pattern 122 having a rectangular ring shape around the uppermost sacrificial layer of the sacrificial layer 120 on the first region I of the substrate 600, and the etch stop layer 190 may remain on the uppermost sacrificial layer of the sacrificial layer 120 and the first sacrificial pattern 122.

[0037] However, Figure 7Only a portion of the second region II of the substrate 600 (i.e., region X) is shown, and therefore only a portion of the first sacrificial pattern 122 with a rectangular ring shape is shown, i.e., the portion with a strip shape extending upward in a third direction. Hereinafter, only the shapes of the various sacrificial patterns in region X will be described, not the entire shapes of the various sacrificial patterns on the second region II of the substrate 600 that can be formed by etching the sacrificial layer 120. During the formation of the lower mold and during the lower mold shown with reference to the perspective view, the portion of the sacrificial layer 120 located on the first region I of the substrate 600 can always be covered to avoid etching, and therefore will not be described.

[0038] After the first sacrificial pattern 122 is formed, the first photoresist pattern can be removed by, for example, ashing and / or stripping processes.

[0039] Reference Figure 8 A second photoresist pattern 131 covering a portion of the second region II of the substrate 600 can be formed on a sacrificial layer at a second horizontal height (hereinafter, the nth horizontal height from the uppermost horizontal height will be simply referred to as the nth horizontal height) in the sacrificial layer 120 of the lower molding layer, and the second photoresist pattern 131 can be used as an etching mask to etch the sacrificial layer at the second horizontal height in the sacrificial layer 120 of the lower molding layer.

[0040] In some example embodiments, the second photoresist pattern 131 may include a first portion 132 and a second portion 134, the first portion 132 covering the first sacrificial pattern 122, having a length in the second direction greater than the length of the first sacrificial pattern 122 in the second direction and having a rectangular shape in a plan view, and the second portion 134 being connected to the first portion 132 to cover a portion of region X and having a rectangular shape in a plan view.

[0041] In some example embodiments, in region X, the width of the second portion 134 of the second photoresist pattern 131 in the third direction may be smaller than the width of the first portion 132 of the second photoresist pattern 131 in the third direction. That is, in region X, the second portion 134 of the second photoresist pattern 131 may not contact the end of the first portion 132 of the second photoresist pattern 131 in the third direction.

[0042] Through etching, a first sacrificial pattern 122 having a rectangular shape in a plan view can be further formed at a second horizontal height, the length of which in the second direction is greater than the length of the first sacrificial pattern 122 at the first horizontal height in the second direction, and a second sacrificial pattern 124 can be formed at the second horizontal height, which can be connected to the first sacrificial pattern 122 at the second horizontal height and has a rectangular shape in a plan view.

[0043] Reference Figure 9 The first trimming process can be performed to reduce the area of ​​the second photoresist pattern 131, and the reduced second photoresist pattern 131 can be used as an etching mask to etch the first sacrificial pattern 122 and the second sacrificial pattern 124 and a sacrificial layer at a third horizontal height in the sacrificial layer 120 of the lower molding layer.

[0044] Specifically, through the first trimming process, the first portion 132 of the second photoresist pattern 131 may have a reduced length in the second direction, and the second portion 134 of the second photoresist pattern 131 may have a reduced width in the third direction.

[0045] Therefore, the length of the first sacrificial pattern 122 at the second horizontal height in the second direction can be reduced, and the first sacrificial pattern 122 can be further formed at the third horizontal height. In addition, the width of the second sacrificial pattern 124 at the second horizontal height can be reduced, and the second sacrificial pattern 124 can be further formed at the third horizontal height.

[0046] In some example embodiments, the first trimming process can be performed by exposing the second photoresist pattern 131 and developing the unexposed portions of the second photoresist pattern 131.

[0047] Reference Figure 10 A second trimming process can be performed. That is, after reducing the area of ​​the second photoresist pattern 131 by reducing the length of the first portion 132 of the second photoresist pattern 131 in the second direction and the width of the second portion 134 of the second photoresist pattern 131 in the third direction, the reduced second photoresist pattern 131 can be used as an etching mask to etch the first sacrificial pattern 122, the second sacrificial pattern 124, and one of the sacrificial layers in the lower molding layer 120 at the fourth horizontal height.

[0048] Therefore, the length of the first sacrificial pattern 122 at the second and third horizontal heights in the second direction can be reduced, and the first sacrificial pattern 122 can be further formed at the fourth horizontal height. In addition, the width of the second sacrificial pattern 124 at the second and third horizontal heights in the third direction can be reduced, and the second sacrificial pattern 124 can be further formed at the fourth horizontal height.

[0049] Reference Figure 11 A third trimming process can be performed. That is, after reducing the area of ​​the second photoresist pattern 131 by means of substantially the same method as the first trimming process and the second trimming process, the reduced second photoresist pattern 131 can be used as an etching mask to etch the first sacrificial pattern 122 and the second sacrificial pattern 124 and one of the sacrificial layers 120 of the lower molding layer at the fifth horizontal height.

[0050] Therefore, the length of the first sacrificial pattern 122 at the second to fourth horizontal heights in the second direction can be reduced, and the first sacrificial pattern 122 can be further formed at the fifth horizontal height. In addition, the width of the second sacrificial pattern 124 at the second to fourth horizontal heights in the third direction can be reduced, and the second sacrificial pattern 124 can be further formed at the fifth horizontal height.

[0051] Reference Figure 12 and Figure 13A A fourth trimming process can be performed. That is, after reducing the area of ​​the second photoresist pattern 131 by means of substantially the same method as the first to third trimming processes, the first portion 132 and the second portion 134 of the second photoresist pattern 131 can be used as etching masks to etch the first sacrificial pattern 122 and the second sacrificial pattern 124 and a sacrificial layer at a sixth horizontal height in the sacrificial layer 120 of the lower molding layer.

[0052] Therefore, the length of the first sacrificial pattern 122 at the second to fifth horizontal heights in the second direction can be reduced, and the first sacrificial pattern 122 can be further formed at the sixth horizontal height. In addition, the width of the second sacrificial pattern 124 at the second to fifth horizontal heights in the third direction can be reduced, and the second sacrificial pattern 124 can be further formed at the sixth horizontal height.

[0053] The second photoresist pattern 131 can be removed.

[0054] Therefore, the first sacrificial pattern 122 can be stacked in a stepped shape at six horizontal heights on a sacrificial layer at a seventh horizontal height in the sacrificial layer 120 of the lower molding layer, and the second sacrificial pattern 124 can be stacked in a stepped shape at five horizontal heights on the same sacrificial layer at a seventh horizontal height in the lower molding layer to be connected to the first sacrificial pattern 122 respectively.

[0055] A structure such as a first sacrificial pattern 122 or a second sacrificial pattern 124 stacked in a stepped shape in a first direction can be referred to as a "stepped structure". The layers forming the stepped structure can be referred to as "step layers", and the portion of each step layer that is not covered by the upper step layer but exposed can be referred to as a "step". The step may include a sacrificial layer or sacrificial pattern and an insulating layer thereon, which may be formed as a pair.

[0056] In some example embodiments, a first step structure may be formed on the third to fifth regions III, IV and V of the substrate 600 and may include a first step, a second step, a third step, a fourth step, a fifth step, a sixth step and a seventh step. The first step structure is composed of a sacrificial layer at a seventh horizontal height in the sacrificial layer 120 of the lower molding layer and first sacrificial patterns 122 stacked on the sacrificial layer at six horizontal heights respectively.

[0057] Furthermore, a second stepped structure may be formed on the third region III of the substrate 600, and may include an eighth step, a ninth step, a tenth step, an eleventh step, a twelfth step, and a thirteenth step, whose lengths in the third direction may be a first length L1, a second length L2, a third length L3, a fourth length L4, a fifth length L5, and a sixth length L6, respectively. The second stepped structure is composed of a sacrificial layer at a seventh horizontal height in the sacrificial layer 120 of the lower molding layer and second sacrificial patterns 124 stacked on the sacrificial layer at five horizontal heights. In some example embodiments, the fifth length L5 may be greater than the fourth length L4 and the sixth length L6, and the fourth length L4 and the sixth length L6 may be greater than the first to third lengths L1, L2, and L3. Furthermore, the fourth length L4 and the sixth length L6 may be substantially the same as each other, and the first to third lengths L1, L2, and L3 may be substantially the same as each other.

[0058] The first to sixth lengths L1 to L6 of the eighth to thirteenth steps in the third direction can be achieved by controlling the reduction ratio of the second photoresist pattern 131 during the trimming process.

[0059] The third step structure can be formed on the fourth region IV of the substrate 600, and the second and third step structures can be symmetrical to each other with respect to the straight line 1201 extending in the second direction between them. That is, the third step structure can be composed of a sacrificial layer located at a seventh horizontal height in the sacrificial layer 120 in the fourth region IV of the substrate 600 and second sacrificial patterns 124 stacked on the sacrificial layer at five horizontal heights respectively, and may include a fourteenth step, a fifteenth step, a sixteenth step, a seventeenth step, an eighteenth step, and a nineteenth step, whose lengths in the third direction can be a first length L1, a second length L2, a third length L3, a fourth length L4, a fifth length L5, and a sixth length L6 respectively.

[0060] In some example embodiments, each of the second and third step structures may be connected to the first step structure. For example, the eighth step included in the second step structure may be substantially the same as the first step included in the first step structure, and the ninth to thirteenth steps included in the second step structure may be connected to the second to sixth steps included in the first step structure, respectively.

[0061] Figure 13A The second to sixth steps of the first stepped structure are shown to have substantially equal lengths in the second direction; however, the inventive concept is not limited thereto.

[0062] That is, refer to Figure 13B The lengths of the second to sixth steps of the first-step structure can be equal to the lengths L2, L3, L4, L5, and L6 of the second to thirteenth steps of the second-step structure, respectively, and therefore can be different from each other. For ease of explanation, only examples will be provided below. Figure 13A The first stepped structure shown in the figure, however... Figure 13B The first stepped structure shown in the figure can also be included within the scope of the inventive concept.

[0063] Reference Figure 14 The third photoresist pattern 140 may be formed on a sacrificial layer at a seventh horizontal height in the sacrificial layer 120 of the lower molding layer to cover portions of the first sacrificial pattern 122 and the adjacent second sacrificial pattern 124.

[0064] Reference Figure 15 The third photoresist pattern 140 can be used as an etching mask to etch the second sacrificial pattern 124 and the sacrificial layers 120 of the lower molding layer at the seventh to twelfth horizontal heights, respectively.

[0065] Therefore, third sacrificial patterns 126 can be formed at the seventh to twelfth horizontal heights, respectively, with a length in the second direction greater than that of the first sacrificial pattern 122 in the second direction. The portion of the second sacrificial pattern 124 not covered by the third photoresist pattern 140 can be moved from the second to sixth horizontal heights to the eighth to twelfth horizontal heights, respectively. The portion of the second sacrificial pattern 124 covered by the third photoresist pattern 140 can be transformed into a fourth sacrificial pattern 128 on a third sacrificial pattern at the seventh horizontal height of the third sacrificial pattern 126 in the lower molding layer.

[0066] Reference Figure 16 A fifth trimming process can be performed to reduce the length of the third photoresist pattern 140 in the second direction, so that a portion of the fourth sacrificial pattern 128 can be exposed.

[0067] Reference Figure 17 The third photoresist pattern 140 can be used as an etching mask to etch the exposed fourth sacrificial pattern 128, second sacrificial pattern 124 and third sacrificial pattern 126 and the sacrificial layer 120 of the lower molding layer at the thirteenth to eighteenth horizontal heights, respectively.

[0068] Therefore, the third sacrificial pattern 126 located at the seventh to twelfth horizontal heights can be reduced to have the same length as before, and the third sacrificial pattern 126 can be further formed at the thirteenth to eighteenth horizontal heights to have the same length as the third sacrificial pattern 126 at the seventh to twelfth horizontal heights. The exposed portion of the fourth sacrificial pattern 128 can be moved from the second to sixth horizontal heights to the eighth to twelfth horizontal heights, and it can be referred to hereinafter as the fifth sacrificial pattern 129. The portion of the second sacrificial pattern 124 not covered by the third photoresist pattern 140 can be moved from the eighth to twelfth horizontal heights to the fourteenth to eighteenth horizontal heights, respectively.

[0069] Repeatable execution and reference Figure 16 and Figure 17 The processes shown are substantially the same or similar, and their figures are omitted herein.

[0070] Reference Figure 18 After removing the third photoresist pattern 140, it can be performed in conjunction with the reference. Figure 14 The processes shown are substantially the same or similar.

[0071] That is, the fourth photoresist pattern 142 can be formed on a sacrificial layer at a given horizontal height in the sacrificial layer 120 of the lower molding layer to cover a portion of the first sacrificial pattern 122, the third to fifth sacrificial patterns 126, 128 and 129, and the adjacent second sacrificial pattern 124.

[0072] Reference Figures 19 to 23 Repeatable execution and reference Figures 15 to 17 The illustrated process is substantially the same or similar, allowing a fifth sacrificial pattern 129 to be further formed at a desired horizontal height, and allowing stepped structures, each including the first to fifth sacrificial patterns 122, 124, 126, 128, and 129, to be formed on the second region II of the substrate 600. The stepped structures, along with the insulating layer 110 and sacrificial layer 120 retained on the first region I of the substrate 600, can together form a lower molded part 800.

[0073] In some example embodiments, each first sacrificial pattern 122 may form a first stepped structure on the third to fifth regions III, IV and V of the substrate 600, wherein the length of each stepped layer in the second direction gradually decreases from the lowest horizontal height to the highest horizontal height, and each fourth sacrificial pattern 128 may form a second stepped structure and a third stepped structure on the third region III and the fourth region IV of the substrate 600, respectively, wherein the length of each stepped layer in the second direction gradually decreases from the lowest horizontal height to the highest horizontal height.

[0074] Furthermore, each third sacrificial pattern 126 can form a fourth step structure, wherein the length of each step layer in the second direction gradually decreases by a number of horizontal heights (e.g., six horizontal heights) units from the lowest horizontal height to the highest horizontal height; each second sacrificial pattern 124 can form a fifth step structure, wherein the length of each step layer in each of the second and third directions gradually decreases from the lowest horizontal height to the highest horizontal height; and each fifth sacrificial pattern 129 can form a sixth step structure and a seventh step structure on the third region III and the fourth region IV of the substrate 600, respectively, wherein the length of each step layer in the third direction gradually decreases from the lowest horizontal height to the highest horizontal height.

[0075] The sixth-step structure may include the twentieth to twenty-fifth steps stacked sequentially from the lowest horizontal level to the highest horizontal level in the first direction, which may be arranged sequentially in the third direction. The lengths of the twentieth to twenty-fifth steps in the third direction may be the first to sixth lengths L1, L2, L3, L4, L5, and L6, respectively.

[0076] The sixth and seventh step structures may be spaced apart from each other in the third direction ("separated to avoid direct contact") and may be symmetrical with respect to the straight line 1201 extending between them in the second direction. Therefore, the seventh step structure may include the twenty-sixth to thirty-first steps stacked sequentially from the lowest horizontal height to the highest horizontal height in the first direction, and their lengths in the third direction may be the first to sixth lengths L1, L2, L3, L4, L5, and L6, respectively.

[0077] Reference Figure 24 This can increase the thickness of the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 on the second region II of the substrate 600 at their respective ends in the second direction or the third direction.

[0078] In some example embodiments, portions of the insulating layer 110 located on the steps of the stepped structure can be removed to expose the ends of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 of the steps. A material substantially the same as that of the sacrificial layer 120 can be deposited on the exposed ends of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129, thereby increasing the thickness of each end of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129. Therefore, the top surface of each end of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 can be higher than the top surfaces of their other portions, and the thickness of each end can be greater than the thickness of their other portions.

[0079] Reference Figure 25 and Figure 26A first etch mask 170 can be formed on a first region I and a second region II of the substrate 600, having a second opening 180 that exposes a fifth region V of the substrate 600 and the next-most sacrificial layer in the sacrificial layer 120, and can reduce the thickness of the respective ends of the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 of the lower mold 800 located on the fifth region V of the substrate 600 and the next-most sacrificial layer in the sacrificial layer 120 of the lower mold 800.

[0080] In some example embodiments, on the fifth region V of the substrate 600 and the next lowest sacrificial layer of the sacrificial layer 120, reference is made. Figure 24 The increased thickness at the ends of the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 shown can be reduced to the original thickness.

[0081] Reference Figure 27 A first insulating interlayer 200 may be formed on the substrate 600 to cover the lower molded part 800, and may be planarized until the upper surface of the uppermost insulating layer in the insulating layers 110 of the lower molded part 800 is exposed. The planarization process may include chemical mechanical polishing (CMP) and / or etch-back processing.

[0082] A second interlayer insulating layer 210 may be formed on the lower molded part 800 and the first interlayer insulating layer 200. Both the first interlayer insulating layer 200 and the second interlayer insulating layer 210 may comprise oxides, such as silicon oxide. In some example embodiments, the first interlayer insulating layer 200 and the second interlayer insulating layer 210 may be incorporated into the insulating layer 110.

[0083] Reference Figure 28 and Figure 29 A second etch mask (not shown) may be formed on the second interlayer insulating layer 210, and the second etch mask may be used to etch the second interlayer insulating layer 210 and the insulating layer 110 and sacrificial layer 120 of the lower mold 800 to form a first channel hole 230 therethrough, thereby exposing the upper surface of the bottom pattern 100 on the first region I of the substrate 600. A barrier pattern 240 may be formed on the sidewalls and bottom of the first channel hole 230. In some example embodiments, a plurality of first channel holes 230 may be formed in each of the second and third directions.

[0084] The barrier pattern 240 can be formed by forming a barrier layer on the sidewalls and bottom of the first channel hole 230, on the uppermost insulating layer of the insulating layer 110 of the lower mold part 800, and on the second insulating interlayer 210, and removing the portion of the barrier layer on the second insulating interlayer 210 by an anisotropic etching process. The barrier pattern 240 may include nitrides (e.g., metal nitrides or silicon nitride) or polysilicon.

[0085] Reference Figure 30 The connecting layer 250 may be formed on the second insulating interlayer 210, and the upper portion of the connecting layer 250 may be planarized.

[0086] In some example embodiments, the connecting layer 250 may include a material with low gap-filling properties or low-step coverage, such as TEOS, HDP, oxides, etc. Therefore, the first channel hole 230 may not be completely filled by the connecting layer 250, and a space may be formed in the first channel hole 230 to which it is connected. Hereinafter, the first channel hole 230 and the space may be referred to as the first gap 260.

[0087] Reference Figure 31 and Figure 32 The insulating layer 110 and the sacrificial layer 120 may also be formed alternately and repeatedly on the connecting layer 250, such that an upper molding layer comprising the insulating layer 110 and the sacrificial layer 120 alternately stacked in the first direction can be formed. In addition, an etch stop layer 190 may also be formed on the uppermost insulating layer of the insulating layer 110 in the upper molding layer.

[0088] In the following text, except Figure 43 In all perspective views except those shown, the processes used to form the upper mold part will be shown, and the lower mold part 800 will not be shown.

[0089] Reference Figure 33 Executable and reference Figure 7 The processes shown are substantially the same or similar.

[0090] Therefore, a fifth photoresist (not shown) can be used to perform an etching process to form a first sacrificial pattern 122 having a rectangular ring shape surrounding the uppermost sacrificial layer of the upper molded layer 120 located on a first region I of the substrate 600, and an etch stop layer 190 can be formed on the uppermost sacrificial layer of the upper molded layer 120 and the first sacrificial pattern 122. However, Figure 33 The length of the first sacrificial pattern 122 from the edge of the first region I 600 from the substrate in the second direction may be less than Figure 7 The length of the first sacrifice pattern 122 in the second direction.

[0091] Reference Figure 34 Executable and reference Figure 8 The processes shown are substantially the same or similar. However, unlike the second photoresist pattern 131, which includes a first portion 132 and a second portion 134 connected to each other, a sixth photoresist pattern 136 and a seventh photoresist pattern 138 that are spaced apart from each other in a second direction ("separated from each other to avoid direct contact") can be used in the etching process.

[0092] The sixth photoresist pattern 136 may cover the first sacrificial pattern 122, and its length in the second direction may be greater than the length of the first sacrificial pattern 122 in the second direction. The seventh photoresist pattern 138 may cover the portion of the sacrificial layer 120 located in region X, and may have a rectangular shape in the plan view.

[0093] Due to the etching process, a first sacrificial pattern 122 can be further formed at a second horizontal height, the length of which in the second direction is greater than the length of the first sacrificial pattern 122 at the first horizontal height in the second direction, and a second sacrificial pattern 124 having a rectangular shape in the plan view can be formed to be spaced apart from the first sacrificial pattern 122 at the second horizontal height.

[0094] Reference Figure 35 Executable and reference Figure 9 The processes shown are substantially the same or similar.

[0095] Therefore, the first sacrificial pattern 122 at the second horizontal height may have a reduced length in the second direction, and the first sacrificial pattern 122 may be further formed at the third horizontal height. Furthermore, the second sacrificial pattern 124 at the second horizontal height may have a reduced area, and the second sacrificial pattern 124 may be further formed at the third horizontal height.

[0096] Reference Figure 36 Executable and reference Figure 10 The processes shown are substantially the same or similar.

[0097] Therefore, the length of the first sacrificial pattern 122 at the second and third horizontal heights can be reduced in the second direction, and the first sacrificial pattern 122 can be further formed at the fourth horizontal height. In addition, the area of ​​the second sacrificial pattern 124 at the second and third horizontal heights can be reduced, and the second sacrificial pattern 124 can be further formed at the fourth horizontal height.

[0098] Reference Figure 37 Executable and reference Figure 11 The processes shown are substantially the same or similar.

[0099] Therefore, the length of the first sacrificial pattern 122 at the second to fourth horizontal heights can be reduced in the second direction, and the first sacrificial pattern 122 can be further formed at the fifth horizontal height. In addition, the area of ​​the second sacrificial pattern 124 at the second to fourth horizontal heights can be reduced, and the second sacrificial pattern 124 can be further formed at the fifth horizontal height.

[0100] Reference Figure 38 and Figure 39 Executable and reference Figure 12The process is substantially the same as or similar to the process shown in Figure 13.

[0101] Therefore, the length of the first sacrificial pattern 122 at the second to fifth horizontal heights can be reduced in the second direction, and the first sacrificial pattern 122 can be further formed at the sixth horizontal height. In addition, the area of ​​the second sacrificial pattern 124 at the second to fifth horizontal heights can be reduced, and the second sacrificial pattern 124 can be further formed at the sixth horizontal height.

[0102] The sixth photoresist pattern 136 and the seventh photoresist pattern 138 can be removed.

[0103] Therefore, the first sacrificial pattern 122 can be stacked in a stepped shape at six horizontal heights on a sacrificial layer at a seventh horizontal height in the upper molding layer 120, and the second sacrificial pattern 124 can be stacked in a stepped shape at five horizontal heights on the same sacrificial layer at a seventh horizontal height in the upper molding layer 120, spaced apart from the first sacrificial pattern 122.

[0104] In some example embodiments, each first sacrificial pattern 122 may form an eighth step structure, and each second sacrificial pattern 124 may form a ninth and tenth step structure. However, with Figure 12 Unlike the stepped structures in Figure 13, the ninth and tenth stepped structures may be spaced apart from the eighth stepped structure rather than connected to it. The ninth stepped structure may include steps thirty-two to thirty-seven, which have lengths L1, L2, L3, L4, L5, and L6 respectively in the third direction. Furthermore, the tenth stepped structure, symmetrical to the ninth stepped structure, may include steps thirty-eighth to forty-third, which have lengths L1, L2, L3, L4, L5, and L6 respectively in the third direction.

[0105] Reference Figure 40 Executable and reference Figure 14 The processes shown are substantially the same or similar.

[0106] Therefore, the eighth photoresist pattern 145 can be formed on a sacrificial layer at a seventh horizontal height in the sacrificial layer 120 of the upper molding layer to cover portions of the first sacrificial pattern 122 and the adjacent second sacrificial pattern 124.

[0107] Reference Figure 41 and Figure 42 Executable and reference Figures 15 to 23 The processes shown are substantially the same or similar.

[0108] Therefore, a stepped structure can be formed on the second region II of the substrate 600, each stepped structure including first to fifth sacrificial patterns 122, 124, 126, 128 and 129. The stepped structure, along with the insulating layer 110 and sacrificial layer 120 retained on the first region I of the substrate 600, can be used together to form an upper molded part 850.

[0109] In some example embodiments, each first sacrificial pattern 122 may form an eighth step structure on the third to fifth regions III, IV, and V of the substrate 600, wherein the length of each step layer in the second direction gradually decreases from the lowest horizontal height to the highest horizontal height, and each fourth sacrificial pattern 128 may form a ninth step structure and a tenth step structure on the third region III and the fourth region IV of the substrate 600, respectively, wherein the length of each step layer in the second direction gradually decreases from the lowest horizontal height to the highest horizontal height. The ninth and tenth step structures may be spaced apart from the eighth step structure rather than connected to it.

[0110] Furthermore, each third sacrificial pattern 126 can form an eleventh step structure, wherein the length of each step layer in the second direction gradually decreases by a number of horizontal heights (e.g., six horizontal heights) units from the lowest horizontal height to the highest horizontal height; each second sacrificial pattern 124 can form a twelfth step structure, wherein the length of each step layer in each of the second and third directions gradually decreases from the lowest horizontal height to the highest horizontal height; and each fifth sacrificial pattern 129 can form a thirteenth step structure and a fourteenth step structure on the third region III and the fourth region IV of the substrate 600, respectively, wherein the length of each step layer in the third direction gradually decreases from the lowest horizontal height to the highest horizontal height.

[0111] The thirteenth-step structure may include forty-fourth to forty-ninth steps stacked sequentially from the lowest to the highest horizontal level in a first direction, which may be arranged sequentially in a third direction. The lengths of the forty-fourth to forty-ninth steps in the third direction may be the first to sixth lengths L1, L2, L3, L4, L5, and L6, respectively. The fourteenth-step structure, symmetrical to the thirteenth-step structure, may include fiftieth to fifty-fifth steps stacked sequentially from the lowest to the highest horizontal level in a first direction, and their lengths in the third direction may be the first to sixth lengths L1, L2, L3, L4, L5, and L6, respectively.

[0112] The lower mold part 800 and the upper mold part 850 are shown in the reference diagram. Figures 43 to 46The end of the last second sacrificial pattern 124 in the upper mold part 850 in the second direction may overlap with the center portion of the fourth sacrificial pattern 128 in the lower mold part 800 in the second direction. Therefore, the end of the last second sacrificial pattern 124 in the upper mold part 850 in the second direction may be arranged above and partially overlapped with the second and third stepped structures of the lower mold part 800 in the first direction, and the first stepped structure of the lower mold part 800 may overlap with the upper mold part 850 in the first direction.

[0113] Reference Figure 47 Executable and reference Figure 24 The processes shown are substantially the same or similar.

[0114] Therefore, the thickness of the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 on the second region II of the substrate 600 of the upper mold 850 can be increased at their respective ends in the second direction or the third direction.

[0115] Reference Figure 48 Executable and reference Figure 25 and Figure 26 The processes shown are substantially the same or similar.

[0116] Therefore, the thickness of the ends of the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 of the upper mold 850 on the fifth region V of the substrate 600 and the lowest sacrificial layer 120 of the upper mold 850 can be reduced.

[0117] Reference Figure 49 Executable and reference Figures 27 to 29 The processes shown are substantially the same or similar.

[0118] Therefore, a third insulating interlayer 270 may be formed on the connecting layer 250 to cover the upper molded part 850, and may be planarized until the upper surface of the uppermost insulating layer in the insulating layer 110 of the upper molded part 850 is exposed. The etch stop layer 190 may be removed by the planarization process.

[0119] A fourth interlayer insulating layer 280 may be formed on the upper mold 850 and the third interlayer insulating layer 270, and the fourth interlayer insulating layer 280, the insulating layer 110 and the sacrificial layer 120 of the upper mold 850, and the connecting layer 250 may be etched to form a second channel hole 290 through which the first gap 260 is exposed. In some example embodiments, a plurality of second channel holes 290 may be formed in each of the second and third directions, each corresponding to the first gap 260 (i.e., the first channel hole 230).

[0120] Reference Figure 50 The barrier pattern 240 can be removed to expose the sidewalls of the first gap 260 and the upper surface of the bottom pattern 100. A charge storage structure layer and a first spacer layer (not shown) can be sequentially stacked on the exposed upper surface of the bottom pattern 100, the sidewalls of the first gap 260 and the second channel hole 290, and the upper surface of the fourth insulating interlayer 280. The first spacer layer can be anisotropically etched to form a first spacer (not shown) on the sidewalls of the first gap 260 and the second channel hole 290. The first spacer can be used as an etching mask to etch the charge storage structure layer to form a charge storage structure 300 with an open-bottomed cup shape on the upper surface of the bottom pattern 100 and the sidewalls of the first gap 260 and the second channel hole 290. The charge storage structure 300 may include a first barrier pattern, a charge storage pattern, and a tunnel insulating pattern sequentially stacked.

[0121] The first spacer and charge storage pattern may include nitrides (e.g., silicon nitride), and the tunnel insulation pattern and the first barrier pattern may include oxides (e.g., silicon oxide).

[0122] After the first spacer is removed, a channel layer may be formed on the exposed bottom pattern 100, charge storage structure 300, and fourth insulating interlayer 280, and a fill layer may be formed on the channel layer to fill the remaining portion of the first gap 260 and the second channel via 290. The fill layer and channel layer may be planarized until the upper surface of the fourth insulating interlayer 280 is exposed to form a fill pattern 320, and the channel layer may be transformed into a channel 310. The fill pattern 320 may include an oxide, such as silicon oxide.

[0123] The upper portion of the first structure, including the fill pattern 320, the channel 310, and the charge storage structure 300, can be removed to form a trench, and a capping pattern 330 can be formed to fill the trench. The channel 310 and the capping pattern 330 may comprise polycrystalline silicon or monocrystalline silicon that is undoped or lightly doped with impurities.

[0124] In some example embodiments, a plurality of channels 310 may be formed in each of the second and third directions to form a channel array. The channel array may include a plurality of channel groups spaced apart from each other in the third direction (“isolated to avoid direct contact with each other”), and each channel group may include a plurality of channel columns spaced apart from each other in the third direction (“isolated to avoid direct contact with each other”). Each channel column may include a plurality of channels 310 arranged in the second direction. Figure 51 The diagram shows a channel array comprising four channel groups in region Y.

[0125] Reference Figure 51 and Figure 52The second dividing pattern 340 can be formed through the sacrificial layer 120 and insulating layer 110 located in the first region I of the substrate 600 through the upper mold 850 and a portion of the second region II of the substrate 600 adjacent thereto.

[0126] The second dividing pattern 340 can be formed by the following steps: forming a third etch mask (not shown) on the fourth interlayer insulating layer 280; etching the fourth interlayer insulating layer 280, the insulating layer 110 of the upper mold 850, and the sacrificial layer 120 using the third etch mask to form a third opening through them; and filling the third opening with an insulating material. In some example embodiments, the second dividing pattern 340 may extend through the upper portion of the channel 310 included in the channel column that may be arranged in the third direction at the central portion of each channel group.

[0127] In some example embodiments, the second dividing pattern 340 may extend not only through the upper portion of the channel 310, but also through the fourth interlayer insulating layer 280, the sacrificial layer at the upper two horizontal heights of the sacrificial layer 120, and the insulating layer at the upper two horizontal heights of the insulating layer 110, and also through a portion of the insulating layer 110 of the upper molded member 850 at the third horizontal height from the top. The second dividing pattern 340 may extend not only in the first region I of the substrate 600 in the second direction, but also in the second region II of the substrate 600, to extend through the upper two step layers of the eighth step structure. Therefore, the sacrificial layer 120 and the first sacrificial pattern 122 at the upper two horizontal heights of the upper molded member 850 may be divided by the second dividing pattern 340 in the third direction.

[0128] Reference Figure 53 and Figure 54 The fifth interlayer insulating layer 350 may be formed on the fourth interlayer insulating layer 280, the capping pattern 330 and the second dividing pattern 340. The fourth etch mask (not shown) may be formed on the fifth interlayer insulating layer 350, and the fourth etch mask may be used to etch the fourth interlayer insulating layer 280, the fifth interlayer insulating layer 350, the lower mold 800 and the upper mold 850, each of the insulating layers 110 and each of the sacrificial layers 120, to form the fourth opening 360 and the fifth opening 370 through them, thereby exposing the upper surface of the bottom pattern 100.

[0129] In some example embodiments, each of the fourth opening 360 and the fifth opening 370 may extend in a second direction between channel groups on the first region I and the second region II of the substrate 600, and a plurality of fourth openings 360 and fifth openings 370 may be formed in a third direction. That is, a channel group may be arranged between adjacent fourth openings 360 and fifth openings 370 in the third direction.

[0130] As the fourth opening 360 and the fifth opening 370 are formed, the sacrificial layer 120 can be divided into multiple pieces, each extending in the second direction, and the insulating layer 110 can be transformed into an insulating pattern 115, each insulating pattern 115 extending in the second direction.

[0131] In some example embodiments, the fourth opening 360 may extend continuously on the first region I and the second region II of the substrate 600; however, the fifth opening 370 may be sealed on the second region II of the substrate 600. Therefore, each of the sacrificial layers 120 extending in the second direction on the opposite third-direction sides of the fifth opening 370 may be connected to each other on the second region II of the substrate 600. In some example embodiments, the connection portion connecting the sacrificial layers 120 may overlap with a sacrificial pattern at a third horizontal height in the first sacrificial pattern 122 included in the eighth stepped structure and the first dividing pattern 130 in the first direction.

[0132] In some example embodiments, the fourth opening 360 may overlap with each of the opposite edges of region X, and thus four channel groups may be arranged between the fourth openings in the third-direction upward adjacent area of ​​the fourth opening 360. Furthermore, a fifth opening 370 may be formed between the channel groups in region X, and thus a channel group may be formed between the fifth openings in the third-direction upward adjacent area of ​​the fifth opening 370. As a result, the four sacrificial layers 120 extending in the second direction in region X can be connected to each other by connecting portions. However, the sacrificial layers at the lowest horizontal level of the sacrificial layers 120 may be separated from each other by a first dividing pattern 130.

[0133] In some example embodiments, when the fourth opening 360 and the fifth opening 370 are formed, a sixth opening 380 may also be formed to extend through the fourth interlayer insulating layer 280 and the fifth interlayer insulating layer 350, the insulating layers 110 of the lower mold part 800 and the upper mold part 850, and the first to fifth sacrificial patterns 122, 124, 126, 128 and 129, thereby exposing the upper surface of the bottom pattern 100.

[0134] The sixth opening 380 may extend in the second region II of the substrate 600 in the second direction, thereby dividing each of the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 in the third direction. In a plan view, the sixth opening 380 may extend from one of the first sacrificial patterns 122 included in the eighth step structure toward the end of the second region II of the substrate 600.

[0135] Reference Figure 55 and Figure 56After removing the fourth etch mask, the sacrificial layers 120 and the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 of the lower mold 800 and upper mold 850 exposed by the fourth to sixth openings 360, 370 and 380 can be removed, thereby forming a second gap between adjacent insulating patterns in the insulating patterns 115 of the lower mold 800 and upper mold 850 in the first direction, and exposing a portion of the sidewall of the second dividing pattern 340 and a portion of the outer sidewall of the charge storage structure 300.

[0136] The second barrier layer 400 may be formed on the exposed portion of the sidewall of the second dividing pattern 340, the exposed portion of the outer sidewall of the charge storage structure 300, the inner wall of the second gap, the surface of the insulating pattern 115, the upper surface of the bottom pattern 100, and the upper surface of the fifth insulating interlayer 350, and a gate conductive layer may be formed on the second barrier layer 400 to fill the remaining portion of the second gap. A gate barrier layer (not shown) may be further formed between the second barrier layer 400 and the gate conductive layer.

[0137] The second barrier layer 400 may include a metal oxide (e.g., aluminum oxide), the gate conductive layer may include a metal (e.g., tungsten), and the gate barrier layer may include a metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0138] The gate conductive layer can be partially removed to form a gate conductive pattern in the second gap, and when the gate barrier layer is formed, the gate barrier layer can be partially removed to form a gate barrier pattern (not shown). The gate conductive pattern and the gate barrier pattern can form a gate electrode.

[0139] In some example embodiments, the gate electrode may extend in a second direction, and multiple gate electrodes may be formed in the first direction. Furthermore, multiple gate electrodes may also be formed in a third direction. That is, the gate electrodes may be spaced apart from each other in the third direction by a fourth opening 360 ("separated to avoid direct contact with each other"). Additionally, each gate electrode may be divided into multiple pieces in the third direction by a fifth opening 370, which can be connected to each other via connection portions that may be formed on a second region II of the substrate 600 to overlap with the first dividing pattern 130. Each gate electrode extending in the second direction on the second region II of the substrate 600 (except for the gate electrodes at the two horizontal heights above) may also be divided in the third direction by a sixth opening 380.

[0140] Gate electrodes (e.g., multiple gate electrodes of the vertical memory device 1) may include first to third gate electrodes 412, 414, and 416 stacked sequentially in a first direction. In some example embodiments, the first gate electrode 412 may be formed at the lowest horizontal height, the third gate electrode 416 may be formed at the upper two horizontal heights, and the second gate electrode 414 may be formed at multiple horizontal heights between the first gate electrode 412 and the third gate electrode 416.

[0141] Each gate electrode can be formed by replacing the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 of the first to fourth stepped structures on the second region II of the substrate 600. Therefore, hereinafter, the first to fourth stepped structures may include gate electrodes that replace the sacrificial patterns. That is, the stepped structure may be referred to as a structure including stepped layers, each stepped layer may be composed of a pair of gate electrodes and an insulating pattern 115 thereon. The end of the gate electrode (e.g., any one of gate electrodes 412, 414, 416) in the second direction and a portion of the insulating pattern 115 thereon may be referred to together as a step, which may have the same name as the previously shown sacrificial pattern. The lower mold 800 and upper mold 850 including the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 may be converted into a lower mold 900 and an upper mold 950 including gate electrodes, respectively.

[0142] As shown above, the thickness of the ends of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 located in the fifth region V of the substrate 600 can be less than the thickness of the ends of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 located in the third region III and the fourth region IV of the substrate 600. Therefore, when a second gap is formed by removing the sacrificial layer 120 and the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 exposed by the fourth to sixth openings 360, 370, and 380, the removal ratio of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 located in the fifth region V of the substrate 600 that are not completely removed but remain can be less than the removal ratio of the first to fifth sacrificial patterns 122, 124, 126, 128, and 129 located in the third region III and the fourth region IV of the substrate 600. Figure 56 As shown, the two edge portions of the first to fifth sacrificial patterns 122, 124, 126, 128 and 129 located on the fifth region V of the substrate 600 can be removed to be replaced by gate electrodes, but their middle portions are not removed to be retained as the lower mold 800 and the upper mold 850.

[0143] Reference Figure 57 and Figure 58Impurities can be implanted into the upper part of the base pattern 100 exposed by the fourth opening 360 and the fifth opening 370, thereby forming the second impurity region 105.

[0144] The second spacer layer may be formed on the upper surface of the bottom pattern 100 exposed by the fourth to sixth openings 360, 370 and 380, the sidewalls of the fourth to sixth openings 360, 370 and 380 and the upper surface of the fifth insulating interlayer 350, and may be anisotropically etched to form a second spacer 420 on each of the sidewalls of the fourth to sixth openings 360, 370 and 380.

[0145] The first common source line (CSL) 430 and the second common source line 440 may be formed in the fourth opening 360 and the fifth opening 370 respectively on the second impurity region 105, and the third dividing pattern 450 may be formed in the sixth opening 380 on the bottom pattern 100.

[0146] In some example embodiments, a conductive layer may be formed on the exposed upper surface of the base pattern 100, the second spacer 420, and the fifth interlayer insulating layer 350 to fill the fourth to sixth openings 360, 370, and 380, and may be planarized until the upper surface of the fifth interlayer insulating layer 350 is exposed, thereby forming a first CSL 430 and a second CSL 440, as well as a third dividing pattern 450. During the planarization process, a portion of the second barrier layer 400 on the fifth interlayer insulating layer 350 may also be removed. The first CSL 430 and the second CSL 440 may be formed in the fourth opening 360 and the fifth opening 370, respectively, to contact the upper surface of the second impurity region 105.

[0147] Reference Figures 59 to 64 The sixth insulating interlayer 460 is formed in the fifth insulating interlayer 350, the first CSL 430 and the second CSL. After passing through the third dividing pattern 450, the second spacer 420, and the second barrier layer 400, a contact plug 470 may be formed through one or more of the first to sixth interlayer insulating layers 200, 210, 270, 280, 350, and 460 and the connection layer 250, the insulating pattern 115, and the second barrier layer 400 located on the third region III and the fourth region IV of the substrate 600, thereby contacting the upper surfaces of the first to third gate electrodes 412, 414, and 416. And through the via 480, a contact plug 470 may be formed through one or more of the first to sixth interlayer insulating layers 200, 210, 270, 280, 350, and 460 and the connection layer 250, the insulating pattern 115, the sacrificial layer 120, the bottom pattern 100, and the second lower interlayer insulating layer 730, thereby contacting the upper surface of the third lower wiring 720 located on the fifth region V of the substrate 600.

[0148] Figure 59Only some of the contact plugs 470 are shown to avoid complicating the figures. In some example embodiments, the contact plugs 470 may contact the upper surface of one or more steps included in the first through fourteenth step structures (excluding the first, ninth, and tenth step structures).

[0149] The ninth and tenth step structures included in the upper mold part 950 can be formed at the same horizontal height as the eighth step structure but spaced apart from it. Therefore, the contact plug 470 can not contact the upper surface of the steps of the ninth and tenth step structures, but can contact the step of the eighth step structure to be electrically connected to the gate electrode at their respective horizontal heights.

[0150] The first stepped structure included in the lower mold member 900 may overlap with, for example, the eleventh to fourteenth stepped structures of the upper mold member 950 in a first direction. Therefore, the contact plug 470 may not contact the step of the first stepped structure. However, in some example embodiments, the second and third stepped structures included in the lower mold member 900 may be formed at the same horizontal level as the first stepped structure for connection thereto. Therefore, even if the contact plug 470 does not directly contact the step of the first stepped structure included in the lower mold member 900, the contact plug 470 may contact the steps in the second and third stepped structures that do not overlap with the eleventh to fourteenth stepped structures of the upper mold member 950 to electrically connect to the gate electrode at their respective horizontal levels.

[0151] That is, when the upper mold part 850 is formed on the lower mold part 800, the upper mold part 850 may not overlap integrally with the second and third stepped structures in the first direction, but the edge of the upper mold part 850 may overlap with the central portion of the second and third stepped structures in the second direction in the first direction. Therefore, the contact plug 470 can contact the upper surface of the steps of the second and third stepped structures, and the gate electrode of the first stepped structure connected to the second and third stepped structures can be used.

[0152] When the upper mold component 850 is arranged such that its edge does not even overlap with the first stepped structure of the lower mold component 800, the horizontal area of ​​the vertical memory device 1 can be increased, thereby degrading its integration density. Therefore, in the present invention, to avoid increasing the horizontal area, unlike the ninth and tenth stepped structures of the upper mold component 850 which are spaced apart from the eighth stepped structure, the upper mold component 850 can be arranged to overlap with the first stepped structure of the lower mold component 800, and the second and third stepped structures can be connected to the first stepped structure, so that the gate electrode at the relevant horizontal height can be used.

[0153] As a result, the vertical memory device 1 may not have an increased horizontal area, but it can effectively have enhanced integration by using sequentially stacked gate electrodes.

[0154] Through-holes 480 may be formed between the sixth and seventh step structures or between the thirteenth and fourteenth step structures arranged in a third-direction orientation. In some example embodiments, six through-holes 480 may be formed therebetween.

[0155] The contact plug 470 and through-hole 480 may comprise metal and / or metal nitride. Upper wiring and vias may be further formed to complete the fabrication of the vertical memory device 1.

[0156] The vertical memory device 1 may have the following structural features.

[0157] In some example embodiments, the vertical memory device 1 may include a circuit pattern 699 on a substrate 600 and a bottom pattern 100 above the circuit pattern 699, such that the circuit pattern 699 is located between the substrate 600 and the bottom pattern 100, and gate electrodes 412, 414, and 416, a channel 310, and a lower mold member 800 and an upper mold member 850 may be formed on the bottom pattern 100. As shown, the channel 310 may extend in a first direction over a first region I (e.g., a cell array region) of the substrate 600 and may extend through one or more of the gate electrodes 412, 414, and 416. Through-holes 480 may extend through the lower mold member 800, the upper mold member 850, and the bottom pattern 100 to be electrically connected to the circuit pattern 699, and a plurality of through-holes 480 may be formed in a third direction.

[0158] In some example embodiments, each of the first CSL 430 and the second CSL 440 may extend on the substrate 600 in a second direction, such that each of the gate electrodes 412, 414, and 416 may be spaced apart from each other in a third direction (“isolated to avoid direct contact with each other”). The first CSL 430 may extend continuously in the second direction on a first region I and a second region II of the substrate 600, while the second CSL 440 may extend in the second direction on the first region I and the second region II of the substrate 600, however, the second CSL 440 may be partially cut off in the second region II of the substrate 600. Thus, it will be understood that each of the gate electrodes 412, 414, and 416 may be isolated from each other in each of the first and third directions in the first region I (e.g., a cell array region) and the second region II (e.g., a stepped region) of the substrate 600 to avoid direct contact with each other, wherein each gate electrode extends in the second direction.

[0159] In some example embodiments, the vertical memory device 1 may further include a third partition pattern 450, each of the third partition patterns 450 extending in a second direction between the first CSL 430 and the second CSL 440 that are adjacent in the third-third upward direction, to partition each of the gate electrodes 412, 414 and 416 in the third-third upward direction.

[0160] In some example embodiments, the gate electrode (e.g., gate electrodes 412, 414, 416) (hereinafter referred to as the fourth gate electrode), which may replace the sacrificial pattern of the first and second stepped structures in the lower molded part 800, may form (“defined”) first to seventh steps arranged sequentially in the second direction and eighth to thirteenth steps arranged sequentially in the third direction, and the eighth to thirteenth steps may be connected to the first to sixth steps at the same horizontal height, respectively. Reiterating, and as shown, the end of the first gate electrode 6200-1 in the second direction may define a first step 6401 in the second direction and a second step 6402 in the third direction on the second region II (e.g., the stepped region) of the substrate 600, wherein each second step 6402 is connected to a first step at the same horizontal height, respectively. Therefore, the first gate electrode 6200-1 may define a first step, each having an “L” shape in the plan view.

[0161] Therefore, the first to sixth steps and the eighth to thirteenth steps connected thereto can form (“defined”) steps each having an “L” shape in the plan view (e.g., the first step).

[0162] In some example embodiments, the end of the gate electrode (hereinafter referred to as the fifth gate electrode) at the same horizontal height as the fourth gate electrode may form (“defined”) a 56th to 62nd step arranged sequentially in the second direction and a 14th to 19th step arranged sequentially in the third direction, and the 14th to 19th steps and the 8th to 13th steps may be symmetrical with respect to the straight line 1201 extending in the second direction. The 14th to 19th steps may be connected to the 56th to 62nd steps respectively formed at the same horizontal height. Therefore, the 56th to 62nd steps and the 14th to 19th steps connected thereto may form an “L” shape in plan view. The “L” shape formed by the 56th to 62nd steps and the 14th to 19th steps and the “L” shape formed by the first to sixth steps and the 8th to 13th steps may be symmetrical with respect to the straight line 1201 extending in the second direction. To reiterate, and as shown, the end of the second gate electrode 6200-2 in the second direction may be defined by a third step 6403 arranged in the second direction and a fourth step 6404 arranged in the third direction, the second gate electrode 6200-2 being at the same horizontal height as the first gate electrode 6200-1, wherein the fourth step 6404 and the second step 6402 are symmetrical with respect to the straight line 1201 extending in the second direction, and the fourth step 6404 is connected to the third step 6403 at the same horizontal height. Therefore, the second gate electrode 6200-2 at the same horizontal height as each corresponding first gate electrode 6200-1 may be defined by a second step having an "L" shape in the plan view. It will be understood that the L-shape of the end of the second gate electrode 6200-2 and the L-shape of the end of the first gate electrode 6200-1 may be symmetrical with respect to the straight line 1201 extending in the second direction.

[0163] The lower mold part 800 (e.g., an insulating mold part) may be located between the eighth to thirteenth steps (e.g., the second step) and the corresponding fourteenth to nineteenth steps (e.g., the fourth step).

[0164] In some example embodiments, the length of one or more of the eighth to thirteenth steps in the third direction may differ from the lengths of the other multiple third-direction steps in the eighth to thirteenth steps (see [link to example embodiment]). Figures 13A to 13B For example, as shown, at least two steps in the second step 6402 may have different lengths in the third direction. In some example embodiments, the lengths of the eighth to thirteenth steps in the third direction may be substantially equal to the lengths of the first to sixth steps in the second direction (see [reference]). Figure 13B For example, as shown, the length of the second step 6402 in the third direction may be equal to the length of the corresponding first step 6401 in the second direction, which is located at the same horizontal height as the second step 6402.

[0165] In some example embodiments, a step formed at the end of a gate electrode (hereinafter referred to as the sixth gate electrode) in the second direction, which may be a sacrificial pattern replacing the eighth to fourteenth step structures in the upper mold 850, may overlap with the first to seventh steps in the first direction, and also partially overlap with the eighth to thirteenth steps in the first direction. However, the step may not overlap with other portions of the eighth to thirteenth steps (specifically, portions of the eighth to thirteenth steps away from the edge of the first region I of the substrate 600) in the first direction. Reiterating, and as shown, the end of the third gate electrode 6200-3 above the first gate electrode 6200-1 (e.g., with respect to the first gate electrode 6200-1 away from the substrate 600) in the second direction may define a fifth step 6405 on the second region II (e.g., the stepped region) of the substrate 600, and the fifth step 6405 may not overlap with at least a portion of each of the second steps 6402 in the first direction (e.g., at least a portion of each of the second steps 6402 may be exposed in the first direction). As further illustrated, the fifth step 6405 may not overlap with a portion of each step in the second step 6402 in a first direction, wherein said portion is remote from the edge of the first region I (e.g., the cell array region) of the substrate 600. As shown, the fifth step 6405 may overlap with the first step 6401 in the first direction.

[0166] In some example embodiments (including at least) Figure 63 (As shown in the example embodiment), the channel 310 may have a width that gradually decreases from its bottom to its top in a first direction between the lower mold part 900 and the upper mold part 950 (i.e., between the uppermost gate electrode (e.g., the first gate electrode 6200-1) in the fourth gate electrode and the lowermost gate electrode (e.g., the third gate electrode 6200-3) in the sixth gate electrode).

[0167] In some example embodiments, the eighth to thirteenth steps may have first to sixth lengths L1, L2, L3, L4, L5, and L6 in a third-party direction, and contact plugs 470 may be formed on the eighth to thirteenth steps respectively. To reiterate, and as at least... Figure 64 As shown, a plurality of contact plugs 470 may contact the upper surface of each corresponding step in the second step 6402. The contact plugs 470 may not be formed on the upper surface of the first to seventh steps; however, the eighth to thirteenth steps may be connected to the first to sixth steps respectively, so that electrical signals can be applied to the first to sixth steps via the contact plugs 470 on the corresponding eighth to thirteenth steps. To reiterate, and as at least... Figure 63As shown, the contact plug 470 may not contact the upper surface of each step in the first step 6401, so that the contact plug 470 does not directly contact the first step 6401, but the contact plug 470 may be electrically connected to each corresponding step in the first step 6401 via, for example, each corresponding second step 6402.

[0168] The distances between adjacent contact plugs 470 on the eighth to thirteenth steps can be a first distance D1, a second distance D2, a third distance D3, a fourth distance D4, and a fifth distance D5, respectively, and the fourth distance D4 and the fifth distance D5 can be greater than the first to third distances D1, D2, and D3. In some example embodiments, the fourth distance D4 and the fifth distance D5 can be equal, and the first to third distances D1, D2, and D3 can be equal.

[0169] While exemplary embodiments have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A vertical memory device, comprising: A substrate comprising a cell array region and a stepped region surrounding the cell array region; A plurality of gate electrodes are located on the cell array region and the stepped region of the substrate. The plurality of gate electrodes are separated from each other in a first direction to avoid direct contact with each other. Each of the plurality of gate electrodes extends in a second direction. The plurality of gate electrodes are also separated from each other in a third direction to avoid direct contact with each other. The first direction is substantially perpendicular to the upper surface of the substrate. The third direction is substantially parallel to the upper surface of the substrate. The second direction is substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction. and A channel located on the cell array region of the substrate, the channel extending in the first direction through one or more of the plurality of gate electrodes. Wherein, the end of the first gate electrode of the plurality of gate electrodes in the second direction defines a first step in the second direction and a second step in the third direction on the stepped region of the substrate, the second steps being connected to corresponding first steps of the same horizontal height, to define a plurality of steps each having an "L" shape in the plan view, and The "L" shape has a width that gradually increases from bottom to top in the third direction and the second direction, respectively.

2. The vertical memory device according to claim 1, wherein The second gate electrode among the plurality of gate electrodes defines a third step in the second direction and a fourth step in the third direction at its end. The second gate electrode is at the same horizontal height as the first gate electrode. The fourth step and the second step are symmetrical with respect to the line extending in the second direction, and the fourth step is connected to the third step at the same horizontal height.

3. The vertical storage device according to claim 2, further comprising: An insulating molded part, located between the second step and the fourth step at the same horizontal height.

4. The vertical storage device according to claim 3, further comprising: A base pattern, which is located on the substrate. The gate electrode, the channel, and the insulating molding are located on the base pattern.

5. The vertical memory device according to claim 4, further comprising: A circuit pattern located between the substrate and the bottom pattern; and A through-hole extends through the insulating molding and the base pattern, and the through-hole is electrically connected to the circuit pattern.

6. The vertical memory device of claim 1, wherein, At least two steps in the second step have different lengths in the third direction.

7. The vertical memory device of claim 1, wherein, The length of the second step in the third direction is equal to the length of the corresponding first step at the same horizontal height in the second direction.

8. The vertical memory device according to claim 1, wherein The third gate electrode, which is higher than the first gate electrode among the plurality of gate electrodes, defines a fifth step on the stepped region of the substrate at its end in the second direction, and The fifth step does not overlap with at least a portion of each of the second steps in the first direction.

9. The vertical memory device of claim 8, wherein, The fifth step does not overlap with the portion of the cell array region of each step in the second step that is away from the substrate in the first direction.

10. The vertical memory device of claim 8, wherein, The fifth step overlaps with the first step in the first direction.

11. The vertical memory device of claim 8, wherein, The width of the channel gradually decreases from the bottom to the top of the channel in the first direction between the uppermost gate electrode in the first gate electrode and the lowermost gate electrode in the third gate electrode.

12. The vertical storage device according to claim 1, further comprising: Multiple contact plugs contact the upper surface of each corresponding step in the second step.

13. A vertical memory device, comprising: A substrate comprising a cell array region and a stepped region surrounding the cell array region; A plurality of gate electrodes are located on the cell array region and the stepped region of the substrate. The plurality of gate electrodes are separated from each other in a first direction to avoid direct contact with each other. Each of the plurality of gate electrodes extends in a second direction. The plurality of gate electrodes are also separated from each other in a third direction to avoid direct contact with each other. The first direction is substantially perpendicular to the upper surface of the substrate. The third direction is substantially parallel to the upper surface of the substrate. The second direction is substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction. and A channel located on the cell array region of the substrate, the channel extending in the first direction through one or more of the plurality of gate electrodes. Wherein, the first gate electrode in the gate electrode defines a plurality of sequential first steps in the second direction at its end in the second direction on the stepped region of the substrate, and each of the plurality of sequential first steps has an "L" shape in a plan view. Wherein, the end of the second gate electrode, which is higher than the first gate electrode among the plurality of gate electrodes, defines a second step in the second direction and / or the third direction on the stepped region of the substrate, and The plurality of sequential first steps overlap with the second step in the first direction, and The "L" shape has a width that gradually increases from bottom to top in the third direction and the second direction, respectively.

14. The vertical memory device according to claim 13, further comprising: Multiple contact plugs are electrically connected to each corresponding step in the first step.

15. The vertical memory device according to claim 14, wherein, The plurality of contact plugs do not directly contact the first step.

16. The vertical memory device according to claim 14, wherein The end of the first gate electrode in the second direction further defines the third step in the third direction, and The third step is connected to the first step at the same horizontal level.

17. The vertical memory device according to claim 16, wherein, The plurality of contact plugs directly contact the upper surface of each corresponding step in the third step.

18. The vertical memory device according to claim 16, wherein, The second step does not overlap with at least a portion of each of the third steps in the first direction.

19. The vertical memory device according to claim 16, wherein The third gate electrode among the plurality of gate electrodes defines a fourth step in the second direction and a fifth step in the third direction at its end in the second direction. The third gate electrode is at the same horizontal height as the first gate electrode, and The fifth step and the third step are symmetrical with respect to the line extending in the second direction, and the fifth step is connected to the fourth step at the same horizontal height.

20. The vertical memory device according to claim 19, further comprising: An insulating molded part, located at the same horizontal height between the third step and the fifth step.

21. The vertical memory device according to claim 16, wherein, At least two of the third steps have different lengths in the third direction.

22. A vertical memory device, comprising: A substrate comprising a cell array region and a stepped region surrounding the cell array region; A plurality of gate electrodes are located on the cell array region and the stepped region of the substrate. The plurality of gate electrodes are separated from each other in a first direction to avoid direct contact with each other. Each of the plurality of gate electrodes extends in a second direction. The plurality of gate electrodes are also separated from each other in a third direction to avoid direct contact with each other. The first direction is substantially perpendicular to the upper surface of the substrate. The third direction is substantially parallel to the upper surface of the substrate. The second direction is substantially parallel to the upper surface of the substrate and substantially perpendicular to the third direction. and A channel located on the cell array region of the substrate, the channel extending in the first direction through one or more of the plurality of gate electrodes. Wherein, the end of the first gate electrode among the plurality of gate electrodes in the second direction is defined by a plurality of sequential first steps, each having an L-shape in the plan view, and The "L" shape has a width that gradually increases from bottom to top in the third direction and the second direction, respectively.

23. The vertical memory device according to claim 22, wherein... The second gate electrode in the second direction has an L-shaped second step formed at its end in the plan view. The second gate electrode and its corresponding first gate electrode are at the same horizontal height. The L-shape of the end of the second gate electrode and the L-shape of the end of the first gate electrode are symmetrical with respect to a line extending in the second direction.

24. The vertical memory device according to claim 22, wherein... The third gate electrode, which is higher than the first gate electrode among the plurality of gate electrodes, defines a third step at its end in the second direction, and The third step does not overlap with at least a portion of each of the first steps in the first direction.

25. The vertical memory device according to claim 24, further comprising: Multiple contact plugs contact the upper surface of each corresponding step in the first step.

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