Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. The characteristics of a semiconductor device having a back electrode including an Au-Sb alloy are improved. The semiconductor device has a semiconductor substrate and a back electrode including an Au-Sb alloy layer. The back electrode is formed on the semiconductor substrate. The Sb concentration in the Au-Sb alloy layer is equal to or greater than 15wt% and equal to or less than 37wt%. The thickness of the Au-Sb alloy layer is equal to or greater than 20nm and equal to or less than 45nm.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2018-239968 filed on December 21, 2018 including its specification, drawings and abstract are incorporated herein by reference in their entirety. Background Art

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same. For example, the present invention relates to a semiconductor device having a back electrode including an Au-Sb alloy layer and a method for manufacturing the same.

[0004] A semiconductor device having a silicon substrate and a back electrode is known, the back electrode including a gold antimony (AuSb) alloy layer formed on the back surface of the silicon substrate. The gold antimony alloy layer can be formed on a semiconductor wafer by a vapor deposition method or a sputtering method (for example, see Japanese Unexamined Patent Application Publication No. 61-220344). Japanese Unexamined Patent Application Publication No. 61-220344 discloses an embodiment of forming a gold antimony alloy layer on a semiconductor wafer by vapor deposition. Summary of the invention

[0005] According to the research of the present inventors, it is found that as the size of the semiconductor wafer increases, it becomes difficult to form a uniform gold-antimony alloy layer on the semiconductor wafer by a vapor deposition method. Therefore, the present inventors have studied the formation of the gold-antimony alloy layer by a sputtering method. However, if the gold-antimony alloy layer is formed by a sputtering method, the ohmic contact between the gold-antimony alloy layer and the semiconductor wafer cannot be formed, or the back electrode is likely to be peeled off from the semiconductor wafer, resulting in insufficient characteristics of the semiconductor device. Therefore, there is a problem that the characteristics of a semiconductor device having a back electrode including a gold-antimony alloy layer formed by a sputtering method are to be enhanced. Other objects and novel features will become clear from the description of the specification and the accompanying drawings.

[0006] A semiconductor device according to an embodiment has a semiconductor substrate and an electrode including a gold-antimony (Au-Sb) alloy layer. The electrode is formed on the semiconductor substrate. The antimony (Sb) concentration in the Au-Sb alloy layer is equal to or greater than 15wt% and equal to or less than 37wt%. The thickness of the gold-antimony alloy layer is equal to or greater than 20nm and equal to or less than 45nm.

[0007] In addition, a method for manufacturing a semiconductor device according to an embodiment includes the following steps: preparing a semiconductor wafer, and forming an electrode on the semiconductor wafer by a sputtering method, the electrode including a gold-antimony (Au-Sb) alloy layer. In the step for forming the electrode, the Au-Sb alloy layer is formed by using a target made of an Au-Sb alloy having an antimony (Sb) concentration of 22 wt % or more and 37 wt % or less.

[0008] According to one embodiment, characteristics of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a main portion cross-sectional view illustrating an exemplary configuration of a semiconductor device according to an embodiment;

[0010] Figure 2 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0011] Figure 3 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0012] Figure 4 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0013] Figure 5 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0014] Figure 6 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0015] Figure 7 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0016] Figure 8 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0017] Fig. 9 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0018] Fig.10 is a main part cross-sectional view showing an exemplary process included in a method for manufacturing a semiconductor device according to an embodiment;

[0019] Fig.11 is the state diagram of Au-Sb alloy;

[0020] Fig.12 is a table showing the relationship between the Sb concentration of the target and the Sb concentration in the Au-Sb alloy layer; and

[0021] Fig.13 The graph shows the Sb concentration of the Au-Sb alloy layer, the thickness of the Au-Sb alloy layer, the evaluation results of adhesion, the measured V CE(sat) A table of the results and the corresponding classification of semiconductor devices is shown. DETAILED DESCRIPTION

[0022] Hereinafter, a semiconductor device and a method for manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings. In the specification and the accompanying drawings, the same or corresponding components are represented by the same reference numerals, and their repeated description is omitted. In the accompanying drawings, for the convenience of description, the configuration may be omitted or simplified.

[0023] <Configuration of semiconductor device>

[0024] Figure 1 : is a main part cross-sectional view showing an exemplary configuration of the semiconductor device SD according to the present embodiment.

[0025] like Figure 1 As shown, the semiconductor device SD includes a semiconductor substrate SUB, an insulating layer IL, a first electrode EL1, a second electrode EL2 and a back electrode BE. The first electrode EL1 and the second electrode EL2 are also referred to as surface electrodes.

[0026] The semiconductor substrate SUB includes a first surface (front surface) SF1 and a second surface (back surface) SF2 in a front-to-back relationship with each other. Examples of the type of the semiconductor substrate SUB include a silicon substrate. The second surface SF2 of the semiconductor substrate SUB contacts the back electrode BE. The thickness of the semiconductor substrate SUB is, for example, equal to or greater than 150 μm and equal to or less than 300 μm.

[0027] like Figure 1 As shown, the semiconductor substrate SUB has a base portion BASE, and an epitaxial layer EPI formed on the base portion BASE. The thickness of the epitaxial layer EPI of the semiconductor substrate SUB is 10 μm or more and 130 μm or less.

[0028] A diffusion layer constituting a so-called vertical transistor is formed inside the semiconductor substrate SUB. Here, a vertical transistor refers to a transistor in which a channel is formed along the relative directions of a first surface SF1 and a second surface SF2 of the semiconductor substrate SUB. Examples of transistors include bipolar transistors such as npn and pnp transistors, and IGBTs. In the present embodiment, the bipolar transistor is an npn transistor. As an npn transistor, a structure called a bipolar transistor can be adopted. In the present embodiment, the semiconductor substrate SUB includes a first n-type semiconductor region SRn1, a p-type semiconductor region SRp, and a second n-type semiconductor region SRn2.

[0029] The first n-type semiconductor region SRn1 is adjacent to the p-type semiconductor region SRp in the semiconductor substrate SUB, the first surface SF1 of the semiconductor substrate SUB, and the second surface SF2 of the semiconductor substrate SUB. The first n-type semiconductor region SRn1 is formed on the base portion BASE and the epitaxial layer EPI of the semiconductor substrate SUB. The first n-type semiconductor region SRn1 includes a first portion SRn1 (BASE) located on the base portion BASE, and a second portion SRn1 (EPI) located on the epitaxial layer EPI. At least one region (the first portion SRn1 (BASE)) of the semiconductor substrate SUB on the back electrode BE side contains n-type impurities (dopants). In the present embodiment, the epitaxial layer EPI of the first n-type semiconductor region SRn1 is formed so as to cover the p-type semiconductor region SRp. Examples of n-type impurities include antimony atoms (Sb), phosphorus atoms (P), and arsenic atoms (As). In the first n-type semiconductor region SRn1, the concentration of n-type impurities in the first portion SRn1 (BASE) located on the base portion BASE is, for example, 1.5×10 18 cm -3 or greater, and the concentration of n-type impurities is 1.2×10 19 cm -3 In the first n-type semiconductor region SRn1, the concentration of the n-type impurity in the second portion SRn1 (EPI) located in the epitaxial layer EPI is, for example, 4.7×10 13 cm -3 or larger, and 3.7×10 15 cm -3 or smaller.

[0030] The p-type semiconductor region SRp is formed inside the semiconductor substrate SUB so as to be sandwiched between the first n-type semiconductor region SRn1 and the second n-type semiconductor region SRn2. The p-type impurity contains, for example, boron (B). The concentration of the p-type impurity is, for example, 1.0×10 15 cm -3 or larger, and 2.0×10 18 cm-3 or smaller.

[0031] The second n-type semiconductor region SRn2 is formed inside the semiconductor substrate SUB so as not to be in contact with the first n-type semiconductor region SRn1 and so as to be adjacent to the p-type semiconductor region SRp. The second n-type semiconductor region SRn2 is formed in the surface electrode side region of the semiconductor substrate SUB. Examples of n-type impurities are the same as those of n-type impurities included in the first n-type semiconductor region SRn1. The concentration of the n-type impurity is, for example, 1.0×10 18 cm -3 or larger, and 2.0×10 18 cm -3 or smaller.

[0032] The insulating layer IL is formed on the first surface SF1 of the semiconductor substrate SUB. In the insulating layer IL, a first opening OP1 exposing a portion of the p-type semiconductor region SRp in the semiconductor substrate SUB and a second opening OP2 exposing a portion of the second n-type semiconductor region SRn2 are formed. The insulating layer IL is made of, for example, silicon oxide (SiO2).

[0033] The first electrode EL1 is an emitter electrode electrically connected to the second n-type semiconductor region SRn2. The first electrode EL1 is formed on the insulating layer IL to fill the first opening OP1 formed in the insulating layer IL. The first electrode EL1 is, for example, a metal film containing aluminum as a main component.

[0034] The second electrode EL2 is a base electrode, which is electrically connected to the p-type semiconductor region SRp. The second electrode EL2 is formed on the insulating layer IL to fill the second opening OP2 formed in the insulating layer IL. The second electrode EL2 is, for example, a metal film containing aluminum as a main component.

[0035] The back electrode BE is a collector electrode, which is electrically connected to the first n-type semiconductor region SRn1. The back electrode BE is formed on the second surface SF2 of the semiconductor substrate SUB. The back electrode BE includes a first titanium layer TiL1, a gold-antimony alloy layer AuSbL, a second titanium layer TiL2, a nickel layer NiL, and a silver layer AgL.

[0036] The first titanium layer TiL1 is a layer for improving adhesion between the semiconductor substrate SUB and the gold-antimony alloy layer AuSbL. The first titanium layer TiL1 is formed on the second surface SF2 of the semiconductor substrate SUB. In other words, the first titanium layer TiL1 is formed between the semiconductor substrate SUB and the gold-antimony alloy layer AuSbL.

[0037] The thickness of the first titanium layer TiL1 is not particularly limited as long as the first titanium layer can exhibit the above-mentioned function. However, if the thickness of the first titanium layer TiL1 is too small, the above-mentioned function is insufficient, and the ohmic contact of the semiconductor substrate SUB and the back electrode BE tends not to be formed. In addition, if the thickness of the first titanium layer TiL1 is too large, antimony atoms do not diffuse from the gold-antimony alloy layer AuSbL into the semiconductor substrate SUB, and it tends to be difficult to form an ohmic contact between the semiconductor substrate SUB and the back electrode BE. For example, the thickness of the first titanium layer TiL1 is preferably equal to or greater than 15 nm, and equal to or less than 30 nm.

[0038] The gold-antimony alloy layer AuSbL is formed on the first titanium layer TiL1. In the semiconductor device SD according to the present embodiment, antimony atoms diffused from the gold-antimony alloy layer AuSbL into the semiconductor substrate SUB can reduce the resistivity of the semiconductor substrate SUB.

[0039] The antimony concentration in the gold-antimony alloy layer AuSbL is, for example, equal to or greater than 15 wt % and equal to or less than 37 wt %. As will be described in detail later, the gold-antimony alloy layer AuSbL having an antimony concentration of less than 15 wt % and greater than 37 wt % is difficult to form by a sputtering method because it is difficult to produce a target for sputtering.

[0040] The thickness of the gold-antimony alloy layer AuSbL is equal to or greater than 20 nm, and equal to or less than 45 nm. If the thickness of the gold-antimony alloy layer AuSbL is less than 20 nm, the amount of antimony atoms diffused into the semiconductor substrate SUB becomes insufficient, and as a result, the resistivity of the semiconductor substrate SUB cannot be sufficiently reduced. When the thickness of the gold-antimony alloy layer AuSbL is greater than 45 nm, the amount of antimony atoms diffused into the semiconductor substrate SUB becomes excessive, and as a result, the adhesion between the back electrode BE and the semiconductor substrate SUB becomes insufficient. In view of the above, the thickness of the gold-antimony alloy layer AuSbL is preferably equal to or greater than 25 nm, and equal to or less than 35 nm, and more preferably about 30 nm.

[0041] The second titanium layer TiL2 is a layer used as a stopper when the nickel layer NiL is formed on the gold-antimony alloy layer AuSbL. The second titanium layer TiL2 is formed on the gold-antimony alloy layer AuSbL. As a result, silicon atoms (Si) diffused into the gold-antimony alloy layer AuSbL and nickel atoms (Ni) included in the nickel layer NiL react with each other to suppress an increase in the resistivity of the back electrode BE.

[0042] The thickness of the second titanium layer TiL2 is not particularly limited as long as the second titanium layer can exhibit the above-mentioned function. For example, the thickness of the second titanium layer TiL2 is about 200 nm.

[0043] The nickel layer NiL is a layer used as a barrier film for the silver layer AgL. The nickel layer NiL is formed on the second titanium layer TiL2. The thickness of the nickel layer NiL is not particularly limited as long as it can exhibit the above-mentioned functions. For example, the thickness of the nickel layer NiL is about 400 nm.

[0044] The silver layer AgL is a layer for enhancing wettability with solder. The silver layer AgL is formed on the nickel layer NiL. The thickness of the silver layer AgL is not particularly limited as long as it can exhibit the above-mentioned functions. For example, the thickness of the silver layer AgL is about 1000 nm.

[0045] <Method of Manufacturing Semiconductor Device>

[0046] Next, a method for manufacturing the semiconductor device SD according to the present embodiment will be described. Figures 2 to 10 2 is a main portion cross-sectional view showing an example of steps included in the manufacturing method of the semiconductor device SD.

[0047] The manufacturing method of the semiconductor device SD includes the following steps: 1) a step of preparing a semiconductor wafer SW; 2) a step of forming a diffusion layer; 3) a step of forming an insulating layer IL; 4) a step of forming a positive electrode (a first electrode EL1 and a second electrode EL2), 5) a step of forming a back electrode BE, and 6) an annealing step. Except for the step of forming the back electrode BE, the manufacturing method of the semiconductor device SD according to the present embodiment can be appropriately selected from the methods referred to as the manufacturing methods of the vertical transistor.

[0048] 1) Preparation of semiconductor wafer SW

[0049] First, if Figure 2 As shown, a semiconductor wafer SW is prepared. The semiconductor wafer SW has a first surface SF1 and a second surface SF2 that are in a front-to-back relationship with each other. The semiconductor wafer SW includes a base portion BASE and an epitaxial layer EPI. The first surface SF1 is the surface of the base portion BASE, and the second surface SF2 is the surface of the epitaxial layer EPI. In this embodiment, the semiconductor wafer SW is an n-type silicon substrate containing n-type impurities.

[0050] 2) Formation of diffusion layer

[0051] Next, if Figure 3 As shown, a diffusion layer is formed inside the semiconductor wafer SW. In the present embodiment, the first n-type semiconductor region SRn1, the p-type semiconductor region SRp, and the second n-type semiconductor region SRn2 are formed as diffusion layers inside the semiconductor wafer SW. For example, each of the diffusion layers can be formed by known photolithography and ion implantation techniques.

[0052] 3) Formation of insulating layer

[0053] Next, if Figure 4 As shown, the insulating layer IL is formed on the first surface SF1 of the semiconductor wafer SW, and the first opening OP1 and the second opening OP2 are formed in the insulating layer IL. For example, after the insulating layer IL is formed on the first surface SF1 of the semiconductor wafer SW by the CVD method, the first opening OP1 and the second opening OP2 can be formed in the insulating layer IL by the photolithography technology and the etching technology. At this time, the first opening OP1 is formed at a position corresponding to the second n-type semiconductor region SRn2, and the second opening OP2 is formed at a position corresponding to the p-type semiconductor region SRp. Examples of materials constituting the insulating layer IL include silicon oxide (SiO2).

[0054] 4) Formation of positive surface electrode

[0055] Next, if Figure 5 As shown, the first electrode EL1 and the second electrode EL2 are formed on the insulating layer IL. For example, after a conductive film is formed on the insulating layer IL by a sputtering method to fill the first opening OP1 and the second opening OP2, the first electrode EL1 and the second electrode EL2 can be formed by processing the conductive film into a desired pattern by a photolithography technique and an etching technique. Examples of materials constituting the first electrode EL1 and the second electrode EL2 include aluminum.

[0056] 5) Formation of back surface electrode

[0057] Next, a back electrode BE is formed on the second surface SF2 of the wafer SW. In the present embodiment, the process of forming the back electrode BE includes the following processes: 5-1) forming a first titanium layer TiL1, 5-2) forming a gold-antimony alloy layer AuSbL, 5-3) forming a second titanium layer TiL2, 5-4) forming a nickel layer NiL, and 5-5) forming a silver layer AgL. Except for the step of forming the gold-antimony alloy layer AuSbL, the method of forming the back electrode BE according to the present embodiment can be appropriately selected from known methods for forming the back electrode BE of a vertical transistor.

[0058] 5-1) Formation of the first Ti layer TiL1

[0059] First, if Figure 6 As shown, a first titanium (Ti) layer TiL1 is formed on the second surface SF2 of the semiconductor wafer SW. For example, the first titanium layer TiL1 may be formed by a sputtering method.

[0060] 5-2) Formation of Au-Sb alloy layer AuSbL

[0061] Next, if Figure 7As shown, a gold-antimony (Au-Sb) alloy layer AuSbL is formed on the first titanium layer TiL1. The gold-antimony alloy layer AuSbL can be formed by a sputtering method. In this embodiment, a target made of a gold-antimony alloy is used, and the gold-antimony alloy has an antimony concentration of 22 wt% or more and 37 wt% or less. In other words, in this embodiment, a target made of a gold-antimony alloy with a melting point of 360 °C or higher and 430 °C or lower is used. Details of the reason for using this target will be described later.

[0062] Except that it is the mixing ratio of gold atoms and antimony atoms of the contained components, the target can be manufactured by a process called the manufacturing method for sputtering targets. Sputtering conditions such as the output power of a DC power supply and the sputtering time can be appropriately adjusted according to the thickness of the gold-antimony alloy layer AuSbL. For example, the output power of the DC power supply is about 2 kW, and the sputtering time is about 10 seconds.

[0063] 5-3) Formation of the second Ti layer TiL2

[0064] Next, as Figure 8 shown, a second titanium (Ti) layer TiL2 is formed on the Au-Sb alloy layer AuSbL. For example, the second titanium layer TiL2 can also be formed by a sputtering method.

[0065] 5-4) Formation of the Ni layer NiL

[0066] Next, as Fig. 9 shown, a nickel (Ni) layer NiL is formed on the second titanium layer TiL2. For example, the nickel layer NiL can also be formed by a sputtering method.

[0067] 5-5) Formation of the Ag layer AgL

[0068] Next, as Fig.10 shown, a silver (Ag) layer AgL is formed on the nickel layer NiL. For example, the silver layer AgL can also be formed by a sputtering method.

[0069] 6) Annealing treatment

[0070] Next, the semiconductor wafer SW on which the back electrode BE is formed is annealed. From the viewpoint of causing the antimony atoms in the gold-antimony alloy layer AuSbL to diffuse into the semiconductor substrate SUB and reducing the resistivity of the semiconductor substrate SUB, the annealing treatment is preferred. The annealing treatment can be performed in a nitrogen atmosphere. The annealing temperature of the semiconductor wafer SW is, for example, 340 °C or higher and 360 °C or lower.

[0071] Finally, a plurality of separated semiconductor devices SD are obtained by cutting the semiconductor wafer SW into pieces.

[0072] <Au-Sb alloy target>

[0073] Here, the reason for using the above-mentioned target will be described. Fig.11 is the phase diagram of gold-antimony alloy. Fig.11 In the graph, the horizontal axis represents the antimony concentration (wt%) and the vertical axis represents the melting point (°C) of the gold-antimony alloy. Fig.11 As shown in FIG. 1 , when the antimony concentration is about 25 wt %, the melting point of the gold-antimony alloy is minimum. When the antimony concentration is less than 22 wt %, and greater than 27 wt %, the melting point of the gold-antimony alloy is greater than 430° C. When the melting point of the gold-antimony alloy constituting the target exceeds 430° C., cracks caused by the alloy mixture are generated when manufacturing the target, and the target becomes difficult to manufacture.

[0074] like Fig.11 As shown, when the antimony concentration is 1 wt % or less, the melting point of the gold-antimony alloy becomes 430° C. or less, and a target can be manufactured. However, in this example, as described below, the characteristics of the semiconductor device SD become insufficient.

[0075] When the gold-antimony alloy layer AuSbL is formed using a gold-antimony alloy target having different antimony concentrations, the antimony concentration of the gold-antimony alloy layer AuSbL is studied. For comparison, the result of forming the gold-antimony alloy layer by vapor deposition is also shown. Fig.12 : is a graph showing the relationship between the antimony concentration of the target and the antimony concentration of the gold-antimony alloy AuSbL.

[0076] like Fig.12 As shown in FIG. 1 , when the antimony concentration is 0.6 wt %, although a target having the same antimony concentration is used, the antimony concentration of the gold-antimony alloy layer formed by the sputtering method is very small compared to the case where the gold-antimony alloy layer is formed by the evaporation method. This means that the antimony atoms are not sufficient to sufficiently reduce the resistivity of the semiconductor substrate SUB. On the other hand, when the antimony concentration is 26.0 wt %, a gold-antimony alloy layer AuSbL having a satisfactory antimony concentration can be formed. This means that antimony atoms that contribute to reducing the resistivity of the semiconductor substrate SUB are sufficiently present in the gold-antimony AuSbL.

[0077] Experiments have shown that if the melting point of the gold-antimony alloy used as a material is too high, it is difficult to properly manufacture a target for sputtering. In addition, when the antimony concentration is too small (1.0 wt% or less), although the target can be produced, the antimony concentration contained in the gold-antimony alloy layer AuSbL becomes insufficient. From the above viewpoint, in this embodiment, a target composed of a gold-antimony alloy having an antimony concentration of 22 wt% or more and 37 wt% or less is used as a target for sputtering.

[0078] like Fig.12As shown, it can be understood that the antimony concentration of the gold-antimony alloy layer is approximately the same as or less than the antimony concentration of the target. For example, when a target composed of a gold-antimony alloy having an antimony concentration of 22 wt % or more and 37 wt % or less is used, the antimony concentration can be adjusted according to the sputtering conditions, and a gold-antimony alloy having an antimony concentration of 15 wt % or more and 37 wt % or less can be formed.

[0079] According to the above manufacturing method, the semiconductor device SD according to the embodiment can be manufactured. Before the process of forming the back electrode BE, the semiconductor wafer SW can be ground from the second surface SF2 to adjust the thickness of the semiconductor wafer SW to a desired value. In addition, from the viewpoint of removing the oxide film on the front surface of the semiconductor wafer SW to reduce the contact resistance, before the process of forming the back electrode BE, the second surface SF2 of the semiconductor wafer SW, which is the formation surface of the back electrode, is preferably cleaned. This cleaning step can be performed, for example, by immersing the semiconductor wafer SW in a cleaning solution (hydrofluoric acid, HF:H2O=1:9) for 20 seconds.

[0080] <Effect>

[0081] As described above, in the manufacturing method of the semiconductor device SD related to the present embodiment, the gold-antimony alloy layer AuSbL having a thickness of 20 nm or more and 45 nm or less is formed by using a target composed of a gold-antimony alloy having an antimony concentration of 22 wt % or more and 37 wt % or less. The semiconductor device SD has a gold-antimony alloy layer AuSbL in which the antimony concentration is 15 wt % or more and 37 wt % or less, and the thickness of the gold-antimony alloy layer is 20 nm or more and 45 nm or less. An appropriate amount of antimony atoms diffuses from the gold-antimony AuSbL into the semiconductor substrate SUB. This makes it possible to achieve high adhesion of the semiconductor substrate SUB and the back electrode BE, and low resistivity of the semiconductor substrate SUB. As a result, the characteristics of the semiconductor device SD can be enhanced.

[0082] <Implementation Method>

[0083] Hereinafter, the present embodiment will be described in detail with respect to the implementation mode, but the present embodiment is not limited to the following implementation mode. Hereinafter, the gold-antimony alloy layer corresponds to the gold-antimony alloy layer AuSbL of the present embodiment. The semiconductor substrate corresponds to the semiconductor substrate SUB of the present embodiment. The back electrode corresponds to the back electrode BE of the present embodiment. The insulating layer corresponds to the insulating layer IL of the present embodiment.

[0084] In this embodiment, a plurality of semiconductor devices are prepared, each having a gold-antimony alloy layer of different thickness. From the viewpoint of evaluating the resistivity of the semiconductor substrate, the collector-emitter saturation voltage (V CE(sat)) can be measured. In addition, from the viewpoint of evaluating the adhesion of the semiconductor substrate to the back electrode, a peel test is performed.

[0085] 1. Semiconductor devices

[0086] (1) Preparation of silicon wafer

[0087] First, in the preparation of a silicon wafer, the silicon wafer was prepared to have a thickness of 725 μm as a semiconductor wafer. The silicon wafer had a base portion and an epitaxial layer formed on the base portion. The concentration of antimony atoms contained in the base portion was 5.0×10 18 cm -3 The concentration of antimony atoms contained in the epitaxial layer is 5.0×10 14 cm -3 The resistivity of the silicon wafer (base portion) is 0.018 Ω·cm. A portion of the semiconductor wafer constitutes a first n-type semiconductor region.

[0088] (2) Formation of diffusion layer

[0089] Next, boron is implanted into the silicon wafer to form an impurity concentration of 1.0×10 18 cm -3 Then, n-type impurity phosphorus is injected into the p-type semiconductor region to form an n-type impurity concentration of 5.0×10 20 cm -3 A second n-type semiconductor region.

[0090] (3) Formation of insulating layer

[0091] Next, after a silicon oxide film having a thickness of 0.7 μm was formed on the surface of the silicon wafer, a first opening for exposing the p-type semiconductor region, and a second opening for exposing the second n-type semiconductor region were formed.

[0092] (4) Formation of positive surface electrode

[0093] Next, an aluminum film is formed on the silicon oxide film by a sputtering method so as to fill the first opening and the second opening. Next, a photomask is formed on the aluminum film by photolithography, and then the aluminum film is processed into a desired pattern by dry etching to form an emitter and a base.

[0094] (5) Formation of protective film

[0095] Next, after a protective film made of polyimide is formed on the silicon oxide film, an opening for exposing the emitter electrode, and an opening for exposing the base electrode are formed in the protective film by photolithography and dry etching.

[0096] (6) Back surface grinding

[0097] The back side of the silicon wafer was then ground to a thickness of 200 μm.

[0098] (7) Formation of back surface electrode

[0099] Next, a first titanium layer, a gold-antimony alloy layer, a second titanium layer, a nickel layer, and a silver layer are formed in this order on the back surface of the silicon wafer by using a sputtering device. The thickness of the first titanium layer is 20 nm, the thickness of the second titanium layer is 20 nm, the thickness of the nickel layer is 400 nm, and the thickness of the silver layer is 1000 nm. In the present embodiment, a gold-antimony alloy layer having a thickness of 9 nm, 20 nm, 45 nm, or 75 nm is formed using a target made of a gold-antimony alloy having an antimony content of 26.0 wt%. At this time, gold-antimony alloy layers having different thicknesses are formed by adjusting the sputtering time. For example, in the case of forming a gold-antimony alloy layer having a thickness of 75 nm, the output power of the DC power supply is set to 2 kW, and the sputtering time is set to 10 seconds.

[0100] After the gold antimony alloy layer was formed on the silicon wafer, the antimony concentration of the gold antimony alloy layer was measured on the silicon wafer by using a dielectrically coupled plasma mass spectrometer. For each silicon wafer, the antimony concentration of the gold antimony alloy layer was 23.0 wt %.

[0101] (8) Annealing

[0102] Next, for each of the four types of silicon wafers including back electrodes having thicknesses different from each other, annealing treatment was performed at 350° C. in a nitrogen atmosphere.

[0103] 2. Evaluation

[0104] (1) Adhesion evaluation

[0105] The peeling test was performed on four types of silicon wafers, each of which included back electrodes with different thicknesses from each other. Specifically, a 2.5 mm square grid cut reaching the silicon wafer was formed on the front surface of the back electrode. Next, a polyester film tape (610S#25, adhesion strength (width: 25 mm); 9.3N (950 gf)) was attached to the back electrode and then peeled off from the back electrode. At this time, the adhesion of the silicon wafer to the back electrode was evaluated based on whether the back electrode was peeled off from the silicon wafer. For each silicon wafer, the case where peeling of the back electrode was not observed was evaluated as "0", and the case where peeling of the back electrode was observed was evaluated as "x".

[0106] (2) Collector-emitter saturation voltage (V CE(sat) )

[0107] The silicon wafer is cut into pieces to obtain semiconductor devices. For each semiconductor device obtained from each silicon wafer, the collector-to-emitter saturation voltage (V CE(sat) ) is measured. As the measurement condition, the collector current I C is set to 1.5A, and the base current I B Set to 150mA. From a practical point of view, a V CE(sat) is considered acceptable.

[0108] (3) Conclusion

[0109] Fig.13 The antimony concentration of the gold-antimony alloy layer, the thickness of the gold-antimony alloy layer, the result of evaluating the adhesion, V CE(sat) The following is a graph showing the measurement results and the classification of each semiconductor device.

[0110] like Fig.13 As shown in the figure, when the thickness of the gold-antimony alloy layer is 9 nm, the V CE(sat) is high. The thickness of the gold-antimony alloy is considered to be small, and the number of antimony atoms diffused into the silicon substrate is insufficient, and as a result, the resistivity of the silicon substrate cannot be sufficiently reduced. When the thickness of the gold-antimony alloy layer is 75 nm, the adhesion between the silicon substrate and the back electrode of the gold-antimony alloy layer is insufficient. The thickness of the gold-antimony alloy layer is considered to be large, and the number of antimony atoms diffused into the silicon substrate is excessive, and as a result, the back electrode is separated from the silicon substrate.

[0111] On the other hand, Fig.13 As shown, when the antimony content of the gold-antimony alloy layer is 15 wt % or more and 37 wt % or less, and the thickness of the gold-antimony alloy layer is 20 nm or more and 45 nm or less, V CE(sat) is low, and the adhesion between the silicon substrate and the back electrode is excellent. That is, according to this embodiment, a semiconductor device that can simultaneously satisfy the reduction of the resistivity of the silicon substrate and the adhesion between the silicon substrate and the back surface electrode can be provided.

[0112] It should be noted that the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist thereof.

[0113] In addition, even when describing a specific numerical value example, it may be a value exceeding the specific numerical value, or may be a value less than the specific numerical value, unless it is theoretically obvious that it is limited to the numerical value. In addition, the component means "B contains A as a main component" and the like, and does not exclude a mode containing other components.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; as well as an electrode formed on the semiconductor substrate and comprising an Au-Sb alloy layer, wherein the concentration of Sb in the Au-Sb alloy layer is equal to or greater than 15 wt % and equal to or less than 26 wt %, wherein the thickness of the Au-Sb alloy layer is equal to or greater than 20 nm and equal to or less than 45 nm, wherein the electrode further comprises a Ti layer between the semiconductor substrate and the Au-Sb alloy layer, and The thickness of the Ti layer is equal to or greater than 15 nm and equal to or less than 30 nm. 2 . The semiconductor device according to claim 1 , wherein the thickness of the Au—Sb alloy layer is equal to or greater than 25 nm and equal to or less than 35 nm.

3. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon, and The electrode is a back surface electrode in contact with the back surface of the semiconductor substrate.

4. The semiconductor device according to claim 1, A region of the semiconductor substrate on one side of the electrode contains n-type impurities. 5 . The semiconductor device according to claim 4 , wherein the n-type impurity is one of an antimony atom, a phosphorus atom, and an arsenic atom.

6. A method for manufacturing a semiconductor device, comprising the following steps: preparing semiconductor wafers; as well as forming an electrode on the semiconductor wafer by a sputtering method, wherein the electrode includes an Au-Sb alloy layer, wherein in the step for forming the electrode, the Au-Sb alloy layer is formed by using a target made of an Au-Sb alloy having an Sb concentration of 22 wt % or more and 26 wt % or less, wherein in the step for forming the electrode, a Ti layer is formed on the semiconductor wafer before forming the Au-Sb alloy layer, and The thickness of the Ti layer is equal to or greater than 15 nm and equal to or less than 30 nm.

7. The method according to claim 6, wherein the electrode is a back surface electrode in contact with the back surface of the semiconductor wafer, and wherein in the step for forming the back surface electrode, the back surface of the semiconductor wafer is cleaned.

8. The method according to claim 7, wherein in the step for cleaning the back surface of the semiconductor wafer, the semiconductor wafer is immersed in hydrofluoric acid.

9. The method according to claim 6, wherein after the step for forming the electrode, an annealing process of the semiconductor wafer is performed. 10 . The method according to claim 9 , wherein in the step for performing the annealing treatment, a temperature of the annealing treatment is set at 340° C. or higher and 360° C. or lower.

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