Si-passivated Ge gate stack

Abstract

In a first aspect, the present invention relates to a method for forming a gate stack of a field effect transistor, the method comprising the following steps: (a) depositing a Si capping layer (200) on a Ge channel material (100); and (b) depositing an oxide layer (300) on the Si capping layer (200) by a plasma enhanced deposition technique at a temperature of 200° C. or less and a plasma power of 100 W or less, preferably 90 W or less.

Description

Technical Field

[0001] The present invention relates to a Ge gate stack for a field effect transistor, and more particularly to a Ge gate stack using a Si capping layer to passivate the Ge channel material. Background Art

[0002] Ge is a promising high-mobility channel material for complementary metal-oxide-semiconductor (CMOS) devices. However, several challenges still need to be overcome before its potential can be fully unlocked.

[0003] Groeseneken et al. disclosed: x Si passivation of the Ge gate can lead to improved bias temperature instability (BTI) reliability compared to passivation of the Ge gate (GROESENEKEN, Guido, et al., BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities, in Electron Devices Meeting (IEDM) 2014 IEEE International. IEEE, 2014, pp. 34.4.1-34.4.4).

[0004] However, for Si-passivated Gen n-channel oxide semiconductor field effect transistors (NMOS), a trade-off between electron mobility and positive BTI (PBTI) was found, which is sensitive to Si capping thickness. In order to overcome this trade-off, Arimura et al. found that electron mobility was improved by optimizing Si thickness, while PBTI reliability was significantly improved by band engineering using La-induced interface dipoles and defect passivation using laser annealing (ARIMURA, Hiroaki et al., "GenFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipoleformation. ", in Electron Devices Meeting (IEDM), IEEE International (IEEE International.) IEEE, 2015. Pages 21.6.1-21.6.4).

[0005] Ren et al. revealed that two different types of electron traps can be identified in Ge nMOS: type A controlled by the thickness of the HfO2 layer and type B controlled by Ge segregation induced by Si growth (REN, Pengpeng et al., "Understanding charge traps for optimizing Si-passivated Ge nMOSFETs," in VLSI Technology, IEEE Symposium on. IEEE, 2016, pp. 1-2). It was found that only type B caused a decrease in mobility, which did not saturate with increasing stress time, while the opposite was true for type A.

[0006] Therefore, there is a need in the art to develop further improved Si-passivated Ge gate stacks. Summary of the invention

[0007] One object of the present invention is to provide a good method for forming a field effect transistor gate stack. Another object of the present invention is to provide a good gate stack associated with the method. This object is achieved by the method and structure of the present invention.

[0008] One advantage of embodiments of the present invention is that Ge inclusions in the oxide layer may be reduced or even completely prevented.

[0009] One advantage of embodiments of the present invention is that the characteristics of the gate stack (eg, electron mobility and / or PBTI) may be improved.

[0010] One advantage of embodiments of the present invention is that the size of the gate stack can be relatively small (eg, the thickness of the Si capping layer therein is about 1 nm and below).

[0011] One advantage of embodiments of the present invention is that the thermal budget used by the method may be low. Another advantage of embodiments of the present invention is that the method is therefore compatible with many other materials and structures that may be integrated on the same substrate.

[0012] An advantage of embodiments of the present invention is that the method is relatively straightforward.

[0013] In a first aspect, the present invention relates to a method for forming a gate stack of a field effect transistor, the method comprising the following steps: (a) depositing a Si capping layer on a Ge channel material; and (b) depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature of 200°C or less and a plasma power of 100 W or less, preferably 90 W or less.

[0014] In a second aspect, the present invention relates to a semiconductor device obtainable by a method according to any embodiment of the first aspect.

[0015] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features in the dependent claims may be combined with features in the independent claim and with features in other dependent claims as appropriate and not limited to those explicitly stated in the claims.

[0016] While improvements, changes and developments in apparatus are ongoing in the art, the concepts of the present invention are believed to represent substantially new and novel improvements involving changes in existing practice resulting in the provision of a more efficient, more stable and more reliable apparatus of this nature.

[0017] The above and other characteristics, features and advantages of the present invention will become apparent in the following detailed description in conjunction with the accompanying drawings, which illustrate the principles of the present invention by way of example. This description is for illustrative purposes only and does not limit the scope of the present invention. The reference figures cited below refer to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1The schematic shows the top portion of the Si capping layer being oxidized to form an oxide layer, as is known in the art.

[0019] Figure 2 The deposition of an oxide layer on a Si capping layer according to the present invention is schematically shown.

[0020] In different drawings, the same reference signs identify the same or similar elements. DETAILED DESCRIPTION

[0021] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the invention is not limited thereto, only by the claims. The drawings described are illustrative only and non-limiting. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. The dimensions and relative dimensions do not correspond to actual reductions in the practice of the invention.

[0022] In addition, the terms first, second, etc. in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a sequence in time, space, hierarchy, or any other manner. It should be understood that the terms used in this manner are interchangeable where appropriate, and the embodiments of the present invention are capable of operating in other sequences than those described or illustrated herein.

[0023] In addition, in the specification and claims, the terms top, above, below, etc. are used for descriptive purposes and not necessarily for describing relative positions. It should be understood that the terms so used are interchangeable with their antonyms where appropriate, and that the embodiments described in the present invention are capable of operating in other orientations than those described or illustrated herein.

[0024] It should be noted that the term "comprising" used in the claims should not be interpreted as being limited to the parts listed thereafter, and it does not exclude other elements or steps. Therefore, it should be understood to indicate the presence of the features, integers, steps or components, but this does not exclude the presence or addition of one or more other features, integers, steps or components or their combination. Therefore, the term "comprising" covers the case where only the features are present and the case where these features and one or more other features are present. Therefore, the scope of the expression "a device comprising components A and B" should not be understood to limit the device to be composed only of components A and B. It means that for the present invention, the relevant components of the device are only A and B.

[0025] References to "one embodiment" or "an embodiment" in the specification mean that the specific features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in the specification do not necessarily all refer to the same embodiment, but may all refer to the same embodiment. In addition, specific features, structures, or characteristics may be combined in one or more embodiments in any suitable manner, which will be apparent to those of ordinary skill in the art.

[0026] Similarly, it should be understood that in the description of exemplary embodiments of the invention, different features of the invention are sometimes combined into a single embodiment, feature, or description thereof in order to simplify the disclosure and aid in understanding one or more different aspects of the invention. However, the methods in the present disclosure should not be understood to reflect an invention that the claimed invention requires more features than those expressly recited in the claims. And, as reflected in the appended claims, inventive aspects may include fewer features than all of the features of a single embodiment disclosed above. Therefore, the claims that follow the detailed description are expressly incorporated into the detailed description, and each claim is itself based on an independent embodiment of the invention.

[0027] In addition, when some embodiments described herein include some but not other features included in other embodiments, the combination of features of different embodiments should be intended to be included within the scope of the present invention and form different embodiments, which should be understood by those skilled in the art. For example, in the claims below, any embodiment claimed for protection can be used in any combination.

[0028] Numerous specific details are set forth in the description herein. However, it should be understood that embodiments of the present invention may be implemented without these specific details. In other cases, well-known methods, procedures, and techniques are not described in detail in order not to obscure the understanding of this specification.

[0029] Reference transistors. These transistors are devices having a first main electrode (eg, drain), a second main electrode (eg, source), and a control electrode (eg, gate) for controlling the flow of charge between the first and second main electrodes.

[0030] The following terms are provided solely to aid in the understanding of the present invention.

[0031] As used herein, and unless otherwise specified, a Ge gate stack is a gate stack used on a Ge channel material. The gate stack may alternatively be referred to as a gate region or a control electrode.

[0032] In a first aspect, the present invention relates to a method for forming a gate stack of a field effect transistor, the method comprising the following steps: (a) depositing a Si capping layer on a Ge channel material; and (b) depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature of 200°C or less and a plasma power of 100 W or less, preferably 90 W or less.

[0033] In the present invention, it is surprisingly recognized that Ge inclusions in isolated Ge channel materials (i.e., B-type electron traps, see Background) are most problematic when they are incorporated into an oxide layer on a Si capping layer. Therefore, it is contemplated to deposit a pristine (i.e., Ge-inclusion-free) oxide layer on a Si capping layer using deposition conditions that minimize oxidation of the Si capping layer and its consumption.

[0034] To achieve this, the oxide layer deposition is carried out at a relatively low deposition temperature (preferably as low as the deposition allows) to reduce the oxygen diffusion rate through the oxide layer. In order to obtain a sufficiently high-quality oxide layer at this relatively low temperature, a plasma (e.g., oxygen plasma) enhanced deposition technique is used. The oxidation of the Si capping layer is further reduced by minimizing the amount and kinetic energy of ions and / or free radicals (e.g., oxygen ions and / or free radicals) originating from the plasma. The kinetic energy of these ions and / or free radicals increases with the increase of the plasma power (i.e., the power generated by the plasma). Therefore, the plasma power is kept as low as possible.

[0035] In some embodiments, a Si capping layer may be epitaxially grown on the Ge channel material.

[0036] In some embodiments, the thickness of the Si capping layer obtained after step a and before step b may be 0.1 nm to 2 nm, preferably 0.2 nm to 1 nm, more preferably 0.3 nm to 0.7 nm, for example 0.5 nm.

[0037] In some embodiments, the thickness of the Si capping layer obtained after step b can be 0.1nm to 2nm, preferably 0.2nm to 1nm, more preferably 0.3nm to 0.5nm, for example 0.4nm. Since Ge inclusions are related to the isolation of Ge channel materials in the Si capping layer, the negative impact of Ge inclusions in the oxide layer increases as the thickness of the Si capping layer decreases; another reason is that the concentration of Ge inclusions is highest at the interface between the Si capping layer and the Ge channel material. Therefore, a thick Si capping layer can be used as a buffer layer for these Ge inclusions, while a thin Si capping layer is not. However, since most of the charge carriers travel in the Si capping layer rather than in the higher mobility Ge channel, a thick Si capping layer has an adverse effect on electron mobility. The thickness range of this embodiment attempts to reach a compromise between limiting Ge inclusions and ensuring high electron mobility. Thus, the present invention generally provides greater advantages when the Si capping layer is relatively thin.

[0038] In a preferred embodiment, the oxide layer may be a SiO2 layer. In other embodiments, the oxide layer may be made of another oxide, such as an Al2O3 oxide layer. Trimethylaluminum is a possible precursor for forming Al2O3 by PECVD or PEALD. However, a SiO2 layer is preferred because it provides particularly good passivation for the Si capping layer.

[0039] In some embodiments, the plasma enhanced deposition technique in step b may be plasma enhanced chemical vapor deposition (PECVD). In these embodiments using PECVD, deposition may be performed at a temperature of 180°C or less. In embodiments using PECVD, deposition may be performed at a plasma power of 90W or less. In embodiments using PECVD, deposition may be performed at a pressure of 10Torr or less, for example 1torr or less. In some embodiments, a pressure of 1Torr to 10Torr may be used. In some embodiments, step b may include co-depositing a precursor substance and an oxygen substance. It may be performed until the desired layer thickness is obtained. In some embodiments, the precursor substance may be a plasma dissociated form (e.g., free radicals and / or ions) of a metalloid or metal precursor. Preferably, the precursor substance may be a plasma dissociated form of a silicon precursor (e.g., SiH4, octamethylcyclotetrasiloxane, dichlorosilane, tetraethoxysilane, and / or other precursors listed below). In some embodiments, the oxygen species may be a plasma dissociated form (eg, free radicals and / or ions) of an oxidant (eg, O 2 , N 2 O, or CO 2 ).

[0040] In other embodiments, the plasma enhanced deposition technique in step b may be plasma enhanced atomic layer deposition (PEALD). In embodiments using PEALD, deposition may be performed at a temperature of 75°C or less. For this purpose, the temperature of the substrate may be maintained at a temperature of 75°C or less during the entire step b. In embodiments using PEALD, deposition may be performed at a plasma power of 45W or less. In embodiments using PEALD, deposition may be performed at a pressure of 200Pa (Pascals) or less. In some embodiments, step b may include: (b1) depositing an atomically thick layer of precursor, (b2) oxidizing the precursor in an oxygen plasma. Steps (b1) and (b2) may be implemented one or more times. In some embodiments, step b may include step (b3): ​​repeating steps (b1) and (b2) until the desired layer thickness is obtained. The precursor (for PEALD or PECVD) is typically a metalloid or metal precursor, for example, a Si precursor. For example, suitable Si precursors that can be used in the process are described in US2013115763A1, specifically [0130–144], which is incorporated herein by reference. In some embodiments, the silicon precursor may be SiH4. In some embodiments, the silicon precursor may be an aminosilane or an amine silane. In some embodiments, the silicon precursor may include an aminosilane, wherein silicon is combined with one nitrogen atom and three hydrogen atoms. For example, the silicon precursor may include dialkylaminosilane (R2N)SiH3. In some embodiments, the silicon precursor may include silanamine, wherein silicon is combined with two nitrogen atoms and two hydrogen atoms. For example, the silicon precursor may include bis(dialkylamine)silane (R2N)2SiH2. In some embodiments, the silicon precursor may include bis(diethylamino)silane. In some embodiments, the silicon precursor may include silanamine, wherein silicon is combined with three nitrogen atoms and one hydrogen atom. For example, the silicon precursor may include tris(dialkylamine)silane (R2N)3SiH. In some embodiments, the silicon precursor may include a silanamine, wherein silicon is bonded to four nitrogen atoms. For example, the silicon precursor may include tetra(dialkylamine)silane (R2N)4Si. In some embodiments, an organic compound having a Si-Si bond and an NHx group is used, wherein the Si-Si bond and the NHx group are either attached to silicon (one or more silicon atoms) or to a carbon chain, which is attached to silicon. In some embodiments, the silicon precursor may include an aminodisilane, for example, hexa(ethylamino)disilane. In some embodiments, the silicon compound may have the formula: R III 3-x (R II R I N) x Si-Si(NR I R II) y RIII 3-y , wherein x is selected from 1 to 3; y is selected from 1 to 3; RI is selected from the group consisting of hydrogen, alkyl and substituted alkyl; R II is selected from alkyl and substituted alkyl; R III is selected from the group consisting of hydrogen, hydroxyl (-OH), amino (-NH2), alkoxy, alkyl, and substituted alkyl; and wherein x, y, R III and R I Can be selected independently of each other. In some embodiments, the silicon compound can be hexa(monoalkylamino)disilane:

[0041] (R II -NH)3Si-Si(NH-R II )3.

[0042] In other embodiments, the silicide may be (CH3O)3Si-Si(O-CH3)3. Other possible precursors have the formula Si(OR)3OH, and R is C 1-4 Alkyl group.

[0043] To implement step (b2), O2 and a carrier gas (e.g., AR) may be exposed to a plasma in the presence of a Si precursor. In some embodiments, the atomic ratio of O2 and Ar may be 0.5:2 to 2:0.5, such as 0.8:1.2 to 1.2:0.8, preferably a ratio of 1:1. In some embodiments, step (b) may include: (i) allowing O2 and Ar to flow continuously into the chamber; (ii) injecting a Si precursor flow into O2 and Ar (e.g., a Si precursor pulse of 0.1 to 0.3 seconds, such as 0.2 seconds); (iii) interrupting the Si precursor flow (e.g., 0.2 seconds to 0.4 seconds, such as 0.3 seconds); and (iv) generating a plasma at a plasma power of 45 W or less (e.g., 45 W) and a pressure of 200 Pa or less for 0.05 seconds to 0.2 seconds (e.g., 0.2 seconds). Steps (ii) to (iv) may be repeated one or more times.

[0044] In some embodiments, the method may further include a step b' after step b and before step c: annealing the oxide layer (at a temperature of 300°C to 800°C for 3 minutes to 5 hours) or nitriding the top surface of the oxide layer. For example, the top surface of the oxide layer may be nitrided by exposing it to a nitrogen source (e.g., NH3) at a temperature of 400°C to 800°C for a period of 1 minute to 5 hours. Since the melting point of Ge is about 900°C, the annealing temperature must be lower than 900°C. In order to avoid GeO deposition, it is preferred to use a relatively low temperature. Therefore, in some embodiments, step b' may include nitriding the top surface of the oxide by exposing the top surface to a nitrogen source (e.g., NH3) at a temperature of 400°C to 500°C, for example, 400°C to 470°C.

[0045] To help introduce nitrogen into the oxide layer, pressures greater than 1 atm may be used. For example, pressures greater than 10 atm may be used.

[0046] In some embodiments, the method may further include step c: forming a high-k dielectric layer on the layer. In some embodiments, the high-k dielectric layer may include HfO2 (e.g., consist of HfO2). In some embodiments, the high-k node layer has a thickness of 1 nm to 5 nm, such as 2 nm.

[0047] In some embodiments, the method may further include a step c' after step c and before step d: annealing the oxide layer (at a temperature of 350°C to 800°C for 30 seconds to 5 hours) or nitriding the top surface of the high-k dielectric layer. For example, nitridation may be performed by exposing the top surface to a nitrogen source (e.g., NH3) at a temperature of 400°C to 800°C for a period of 1 minute to 5 hours. In some embodiments, step c' may include exposing the surface of the high-k dielectric material to a nitrogen source (e.g., NH3) at a temperature of 400°C to 500°C, for example, 400°C to 470°C.

[0048] To help introduce nitrogen into the high-k layer, a pressure greater than 1 atm may be used. For example, a pressure greater than 10 atm may be used.

[0049] In some embodiments, the method may further include step d: forming a barrier layer on the high-k dielectric material. In some embodiments, the barrier layer may include (or consist of) TiN, TaN, or a combination thereof. For example, the barrier layer may be TaN, or may include a TiN layer on the high-k dielectric material and a TaN layer on the TiN layer.

[0050] In some embodiments, the method may further include step e: forming a gate metal on the barrier layer if there is a barrier layer, or forming a gate metal on the high-k dielectric material if there is no barrier layer. In some embodiments, the gate metal may include W (eg, consist of W).

[0051] In some embodiments, the gate stack can be used for a field effect transistor (FET). In some embodiments, the field effect transistor can be an n-channel metal oxide semiconductor field effect transistor (NMOS). In some embodiments, the field effect transistor can also include a source region and a drain region. In some embodiments, the source region and the drain region can define a channel region therebetween, and the channel region is present in the Ge channel material.

[0052] In a second aspect, the invention relates to a semiconductor device obtainable by a method according to any embodiment of the first aspect. The Ge content of the oxide layer contained in the gate stack obtainable by some embodiments of the invention is typically based on that obtainable by oxidation of a Si capping layer.

[0053] In some embodiments, any feature of any embodiment of the second aspect may be independently described in any embodiment of any other aspect.

[0054] The present invention is now described by a detailed description of several embodiments of the present invention. It is obvious that other embodiments of the present invention can be constructed according to the knowledge of those skilled in the art without departing from the true technical teachings of the present invention, and the present invention is limited only by the appended claims. Comparative Example: Forming a Gate Stack of a FET According to Prior Art

[0055] See now Figure 1. This is carried out according to the embodiment of Arimura et al. (2015) (see Background). To this end, a thin Si capping layer (200) is epitaxially grown on the Ge channel material (100). Subsequently, a top portion of the Si capping layer is oxidized using dry O3 oxidation to form a SiO2 oxide layer (300), thereby leaving a minimum required Si capping layer (200) thereunder. The optimal remaining Si capping layer thickness was found to be about 0.4 nm. Therefore, a 0.9 nm thick Si capping layer is initially grown, which leaves a Si capping layer of about 0.4 nm after dry O3 oxidation, with a SiO2 interface layer of about 1.1 nm thereon. However, by oxidizing the top portion (210) of the Si capping layer (200), the Ge inclusions (110) in the Si capping layer (200) that are separated from the Ge channel material (100) are incorporated into the SiO2 oxide layer (300). It was found that such Ge (or GeO2) inclusions (110) in the oxide layer (300) have a negative impact on the properties of the final FET device (eg, forward bias temperature instability and / or electron mobility).

[0056] Example 1: Formation of a gate stack of a FET according to the present invention

[0057] We now see Figure 2 Different from the prior art (see Comparative Examples and Figure 1 ), the gate stack of the present invention is formed by depositing an original oxide layer (400) on the deposited Si capping layer (200). When doing so, ideally, the Si capping layer (200) is completely free of oxidation and Ge inclusions are not incorporated into the oxide layer (400); see Figure 2 a. Alternatively, a small amount of the top surface (210) of the Si capping layer (200) is still oxidized to form a thin SiO2 oxide layer (300) with Ge (or) ; see Figure 2 b. Regardless, the original oxide layer (400) remains free of inclusions, and the concentration of these inclusions (110) decreases throughout the oxide layer (300+400).

[0058] To this end, a thin Si capping layer is first epitaxially grown on the Ge channel material, for example, as described by Loo et al. (LOO, R. et al., Editors' Choice—EpitaxialCVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structure, ECS Journal of Solid State Science and Technology, 2018, 7.2: 66-P72), which is incorporated herein by reference. Considering the limited consumption of the Si capping layer during the deposition of the oxide layer in the present invention, an initial Si capping layer of about 0.5 nm thickness may be sufficient to obtain a remaining Si capping layer in a final gate stack of about 0.4 nm thickness.

[0059] Then, a SiO2 oxide layer is deposited on the Si capping layer by one of the two plasma-assisted deposition methods listed above. Alternatively, the oxide layer can be made of another oxide material, such as Al2O3.

[0060] Subsequently, a high-k dielectric material (e.g., HfO2) is deposited on the oxide layer to reduce gate leakage current. To improve the high-k / SiO2 layer quality and thermal stability, such a SiO2 surface or high-k / SiO2 stack can be nitrided and / or the high-k dielectric layer can be annealed after deposition. A barrier layer (e.g., TiN or TaN, or a combination thereof) and a gate metal (e.g., W) can be further deposited thereon using processes known in the art.

[0061] Example 1a: Deposition of an oxide layer by plasma enhanced chemical vapor deposition

[0062] The SiO2 oxide layer is deposited by plasma enhanced chemical vapor deposition (PECVD), in which a silicon precursor (e.g., SiH4) and an oxidant (e.g., O2, N2O, or CO2) are simultaneously dissociated in a plasma. The radicals and ions of silicon and oxygen then continue to combine to form a SiO2 film. The typical process parameters used are a pressure of 1-10 Torr, a plasma power of 90 W, and a temperature of 180°C.

[0063] Example 1b: Deposition of an oxide layer by plasma enhanced atomic layer deposition

[0064] Alternatively, a SiO2 oxide layer can be deposited using plasma enhanced atomic layer deposition (PEALD). Thus, a self-limiting atomically thick silicon precursor layer is first deposited; then oxidized in an oxygen plasma. In this latter step, not only is the plasma power low, but the plasma duration is also short. The two steps of layer deposition followed by plasma exposure are then repeated until the desired thickness is obtained. During this cycle, the substrate temperature is maintained at 75°C. O2 and Ar in a ratio of 1:2 flow continuously, wherein the Si precursor is injected with the Ar flow for 0.2 seconds (i.e., Si precursor pulse). Next, the Si precursor flow is stopped for 0.3 seconds (i.e., Si precursor removal), and then the plasma is opened for 0.1 seconds at a plasma power of 45W. The chamber pressure is typically maintained at 200 Pa. For example, suitable Si precursors that can be used in this process are described in US2013115763A1, specifically [0130–144], which is incorporated herein by reference. For example, the silicon precursor can be bis(diethylamino)silane (BDEAS).

[0065] It should be understood that although the preferred embodiments, specific configurations and configurations, and materials of the device of the present invention have been discussed herein, various changes or modifications may be made to the form and details without departing from the scope and technical teachings of the present invention. For example, any of the schemes given above represent only processes that may be used. Functions may be added or deleted from the block diagram, and operations may be exchanged between functional blocks. Steps may be added or reduced to the methods within the scope of the present invention.

Claims

1. A method for forming a gate stack of a field effect transistor, the method comprising: a. Depositing a Si capping layer (200) on the Ge channel material (100); as well as b. Depositing an oxide layer (300) on the Si capping layer (200) obtained in step a by plasma enhanced deposition technology at a temperature of 200°C or lower and a plasma power of 100 W or lower, so that the thickness range of the Si capping layer (200) reaches a compromise between limiting Ge inclusions and ensuring high electron mobility.

2. The method of claim 1, wherein: The plasma power is 90W or less.

3. The method of claim 1, wherein: The oxide layer (300) is a SiO2 layer (300).

4. The method of claim 1, wherein: The thickness of the Si capping layer (200) obtained after step b is 0.1 nm to 2 nm.

5. The method of claim 1, wherein: The thickness of the Si capping layer (200) obtained after step b is 0.2 nm to 1 nm.

6. The method of claim 1, wherein: The plasma enhanced deposition technique in step b is plasma enhanced chemical vapor deposition or plasma enhanced atomic layer deposition.

7. The method of claim 6, wherein: The plasma enhanced deposition technique in step b is plasma enhanced atomic layer deposition performed at a temperature of 75° C. or lower.

8. The method of claim 6 or claim 7, wherein: Step b is performed at a plasma power of 45 W or less.

9. The method of claim 6 or claim 7, wherein: Step b is carried out at a pressure of 200 Pa or less.

10. The method of claim 1, wherein: The step b comprises: b1. Deposition of atomically thick precursor layers, b2. oxidizing the precursor in an oxygen plasma; and b3. Repeat steps b1 and b2 until the desired thickness of the oxide layer (300) is obtained.

11. The method according to claim 1, further comprising step c: forming a high-k dielectric layer on the oxide layer (300).

12. The method of claim 11, wherein: The high-k dielectric layer includes HfO2.

13. The method according to claim 11 or claim 12, further comprising step d: forming a barrier layer on the high-k dielectric layer.

14. The method of claim 13, wherein: The barrier layer includes TaN.

15. The method of claim 11 or claim 12, further comprising step e: forming a gate metal on the barrier layer if there is a barrier layer, or forming a gate metal on the high-k dielectric layer if there is no barrier layer.

16. The method of claim 15, wherein: The gate metal includes W. 17 . A gate stack obtainable by the method according to claim 1 .

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