Comparator circuit and mobile device

Abstract

A comparator circuit and a mobile device are provided. The comparator circuit includes a differential input circuit, a load circuit, a first current source, a first bias voltage supply circuit, a third connection circuit, and a fourth connection circuit. The differential input circuit includes a first transistor and a second transistor, a first input signal is supplied to the first transistor, and a second input signal is supplied to the second transistor. The load circuit includes a third transistor and a fourth transistor, the third transistor is connected to the first transistor and the first connection circuit is inserted between the third transistor and the first transistor, the fourth transistor is connected to the second transistor and the second connection circuit is inserted between the fourth transistor and the second transistor, and a gate of the third transistor and a gate of the fourth transistor are connected to the first connection circuit through a third capacitor. The first bias voltage supply circuit supplies a first bias voltage to the gate of the third transistor and the gate of the fourth transistor and the third capacitor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Japanese Patent Application No. 2018-237883 filed with the Japan Patent Office on December 20, 2018, and Korean Patent Application No. 10-2019-0088302 filed with the Korean Intellectual Property Office on July 22, 2019, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the inventive concepts described herein relate to a comparator circuit, an analog-to-digital converter (ADC) circuit, a semiconductor device, and a mobile device. Background Art

[0004] Currently, there is a strong demand for low-power image sensors manufactured using large-scale integration (LSI) technology for use in mobile devices such as smartphones. The analog-to-digital converter (ADC) embedded in LSI image sensors is a major consumer of power in LSI image sensors. Therefore, the implementation of a low-power ADC can lead to the realization of low-power LSI image sensors.

[0005] To this end, various ADC-related technologies have been proposed. For example, Japanese Patent Document (JP2011-166278A) proposes a differential amplifier circuit that suppresses variations in the output operating point caused by variations in the common-mode input voltage. This differential amplifier circuit comprises two pairs of complementary metal oxide semiconductor (CMOS) inverting amplifiers. Summary of the Invention

[0006] At least one embodiment of the inventive concept provides a comparator circuit that can be driven with a low power supply voltage.

[0007] A comparator circuit according to an exemplary embodiment of the inventive concept includes a differential amplifier comparing a first input signal and a second input signal to output a comparison result, and an output amplifier configured to output an amplified signal based on the comparison result. The differential amplifier includes a differential input circuit, a load circuit, a first current source, a first bias voltage supply circuit, a third connection circuit, and a fourth connection circuit. The differential input circuit includes a first transistor and a second transistor. A first input signal is applied to a gate of the first transistor through a first capacitor, and a second input signal is supplied to a gate of the second transistor through a second capacitor. The load circuit is provided at the differential input circuit. The load circuit includes a third transistor connected to the first transistor with the first connection circuit interposed therebetween, and a fourth transistor connected to the second transistor with the second connection circuit interposed therebetween. Gates of the third transistor and the fourth transistor are connected to the first connection circuit through a third capacitor. The first current source is a current source of the differential input circuit, and is connected to the first transistor and the second transistor. The first bias voltage supply circuit supplies a first bias voltage to the gates of the third transistor and the fourth transistor, and the third capacitor. The third connection circuit connects the gate of the first transistor and the first connection circuit. The fourth connection circuit connects the gate of the second transistor and the second connection circuit. The output amplifier includes a fifth transistor, a second current source, and a sixth connection circuit. A signal based on the comparison result is supplied to a gate of the fifth transistor through a fourth capacitor. The second current source is connected to the fifth transistor with the fifth connection circuit interposed therebetween. The sixth connection circuit connects the gate of the fifth transistor and the fifth connection circuit. A node of the fifth connection circuit outputs the amplified signal.

[0008] In an exemplary embodiment of the comparator circuit, the first bias voltage supply circuit includes a first switch adjusting timing of supplying the first bias voltage, and the third connection circuit includes a second switch adjusting timing of connecting the gate of the first transistor and the first connection circuit.

[0009] In an exemplary embodiment of the comparator circuit, the fourth connection circuit includes a third switch adjusting timing of connecting the gate of the second transistor and the second connection circuit, and the sixth connection circuit includes a fourth switch adjusting timing of connecting the gate of the fifth transistor and the fifth connection circuit. With this configuration, the comparator circuit can set an operating point of each transistor.

[0010] In the exemplary embodiment of the comparator circuit, the differential amplifier further includes a second bias voltage supply circuit that supplies a second bias voltage to the first connection circuit, and a fifth switch that adjusts timing of the supply of the second bias voltage to the first connection circuit. With this configuration, the comparator circuit can supply a bias voltage more suitable for the load circuit.

[0011] In the exemplary embodiment of the comparator circuit, the first switch is turned on before the second switch, the third switch, the fourth switch, and the fifth switch are turned on, wherein the fifth switch and the second switch, the third switch, and the fourth switch are turned on at the same time, and the second switch, the third switch, and the fourth switch are turned off after the first switch and the fifth switch are turned off. With this configuration, the operating point can be more appropriately set with respect to each transistor.

[0012] In the exemplary embodiment of the comparator circuit, the differential amplifier further includes a buffer circuit between the first capacitor and the gate of the first transistor. Further, in the exemplary embodiment, the buffer circuit includes a constant current supply circuit, a buffer transistor, a second bias voltage supply circuit, and a sixth switch. Further, in the exemplary embodiment, the constant current supply circuit supplies a given current. Further, in the exemplary embodiment, one of the source and the drain of the buffer transistor is connected to the constant current supply circuit, the other of the source and the drain of the buffer transistor is grounded, and the first input signal and the second bias voltage are supplied to the gate of the buffer transistor. Further, in the exemplary embodiment, the second bias voltage supply circuit supplies the second bias voltage. Further, in the exemplary embodiment, the sixth switch adjusts timing of the supply of the second bias voltage to the gate of the buffer transistor. With this configuration, the load of the second bias voltage supply circuit can be reduced.

[0013] In the exemplary embodiment of the comparator circuit, the second switch, the third switch, and the fourth switch can be turned on after the first switch and the sixth switch are turned on, and can be turned off after the first switch and the sixth switch are turned off. With this configuration, the comparator circuit including the buffer circuit can more appropriately set the operating point with respect to each transistor.

[0014] In the exemplary embodiment of the comparator circuit, each of the first current source and the second current source includes a current source transistor, the gate of the current source transistor being supplied with a third bias voltage. In this case, each of the first current source and the second current source further includes a current source switch that adjusts timing of the supply of the third bias voltage. Further, the current source switch can be turned off at the same time as the first switch is turned off. With this configuration, the influence of the comparator circuit on the peripheral configuration can be reduced.

[0015] The ADC circuit according to at least one embodiment of the inventive concept includes a plurality of comparator circuits.

[0016] A semiconductor circuit according to at least one embodiment of the present inventive concept includes the ADC circuit and a plurality of photoelectric conversion elements arranged in a matrix shape. The ADC circuit can perform a discrete process on an analog signal generated by the photoelectric conversion elements. Further, a mobile device according to an exemplary embodiment of the present inventive concept can include a semiconductor device and a lens for imaging an image of an object. The semiconductor device can generate and process image data imaged through the lens. With this configuration, the ADC circuit, the semiconductor device, and the mobile device can reduce power consumption.

[0017] According to an exemplary embodiment of the present inventive concept, a comparator circuit includes a differential amplifier and an output amplifier. The differential amplifier is configured to compare a first input signal and a second input signal to output a comparison result. The output amplifier is configured to output an amplified signal based on the comparison result. The differential amplifier includes a differential input circuit, a load circuit, a first current source, a first bias voltage supply circuit, a third connection circuit, a fourth connection circuit, and a buffer circuit. The differential input circuit includes a first transistor and a second transistor, the first input signal is applied to a gate of the first transistor through a first capacitor, and the second input signal is supplied to a gate of the second transistor through a second capacitor. The load circuit provides a load to the differential input circuit, and includes a third transistor connected to the first transistor with a first connection circuit interposed therebetween, and a fourth transistor connected to the second transistor with a second connection circuit interposed therebetween, wherein a gate of the third transistor and a gate of the fourth transistor are connected to the first connection circuit through a third capacitor. The first current source is a current source of the differential input circuit, and is connected to the first transistor and the second transistor. The first bias voltage supply circuit supplies a first bias voltage. The third connection circuit connects the gate of the first transistor and the first connection circuit. The fourth connection circuit connects the gate of the second transistor and the second connection circuit. The buffer circuit is connected between the first capacitor and the gate of the first transistor. BRIEF DESCRIPTION OF DRAWINGS

[0018] Exemplary embodiments of the present inventive concept will become apparent by reference to the accompanying drawings.

[0019] Figure 1 is a circuit diagram of a comparator circuit according to an exemplary embodiment of the present inventive concept.

[0020] Figure 2 is a timing diagram of a switch in the comparator circuit of Figure 1

[0021] Figure 3 is a circuit diagram of a comparator circuit according to an exemplary embodiment. ​

[0022] Figure 4 is a timing chart of a switch in a comparator circuit according to an exemplary embodiment of the inventive concept. Figure 3

[0023] Figure 5 is a circuit diagram of a comparator circuit according to an exemplary embodiment of the inventive concept.

[0024] Figure 6 is a timing chart of a switch in a comparator circuit according to an exemplary embodiment of the inventive concept. Figure 5 DETAILED DESCRIPTION

[0025] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings. In the following description, details of well-known technical features are not described in detail in order to help the reader understand the exemplary embodiments of the inventive concept. Therefore, the embodiments described herein can have various changes or improvements without departing from the scope of the inventive concept. In the drawings, like reference numerals refer to like parts throughout the several views.

[0026] Figure 1 is a circuit diagram of a comparator circuit according to an exemplary embodiment of the inventive concept. For example, Figure 1 The comparator circuit 10 shown in FIG. 1 can be used in an analog-to-digital converter (ADC).

[0027] The comparator circuit 10 includes a differential amplifier 11 that compares first and second input signals IN1 and IN2 provided in the form of a differential signal and outputs a result of the comparison (i.e., a comparison result), and an output amplifier 12 that outputs an output signal VOUT in response to the comparison result. The output signal VOUT is referred to as an "amplified signal".

[0028] Hereinafter, the differential amplifier 11 will be described. The differential amplifier 11 includes a differential input circuit 111, a load circuit 112, a first current source 113, a first bias voltage supply circuit 114, a second bias voltage supply circuit 115, a third connection circuit W3, and a fourth connection circuit W4.

[0029] The differential input circuit 111 includes a first transistor T1 and a second transistor T2, and the first input signal IN1 is supplied to a gate of the first transistor T1 through a first capacitor C1, and the second input signal IN2 is supplied to a gate of the second transistor T2 through a second capacitor C2. In an exemplary embodiment, the first and second transistors T1 and T2 are N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). The N-type MOSFETs are referred to as "NMOS transistors".

[0030] ​​The load circuit 112 corresponds to the differential input circuit 111, and forms a load differential transistor stage. The load circuit 112 includes a third transistor T3 and a fourth transistor T4. In the exemplary embodiment, the third transistor T3 and the fourth transistor T4 are P-type MOSFETs. P-type MOSFETs are referred to as "PMOS transistors".

[0031] The source of the third transistor T3 is connected to the first power supply VI, and the drain of the third transistor T3 is connected to the drain of the first transistor Tl through a first connection circuit Wl interposed between the drain of the third transistor T3 and the drain of the first transistor Tl. The source of the fourth transistor T4 is connected to the second power supply V2, and the drain of the fourth transistor T4 is connected to the drain of the second transistor T2 through a second connection circuit W2 interposed between the drain of the fourth transistor T4 and the drain of the second transistor T2. The gate of the third transistor T3 and the gate of the fourth transistor T4 are connected to each other. Also, the gate of the third transistor T3 and the gate of the fourth transistor T4 are connected to the first connection circuit Wl through a third capacitor C3 interposed between the gate of the third transistor T3 and the gate of the fourth transistor T4 and the first connection circuit Wl. The third transistor T3 and the fourth transistor T4 of the load circuit 112 constitute a current mirror circuit, which is connected in diode form to one side of the first transistor Tl. However, the third capacitor C3 is added to this diode connection configuration.

[0032] Also, the load circuit 112 is connected to a first bias voltage supply circuit 114. The first bias voltage supply circuit 114 supplies a first bias voltage Vbl to a node between the gate of the third transistor T3 and the gate of the fourth transistor T4 and the third capacitor C3. The first bias voltage supply circuit 114 includes a first switch SWl that adjusts the timing at which the first bias voltage Vbl is supplied. By adjustment of the first switch SWl, the load circuit 112 receives the first bias voltage Vbl, and sets the operating point in accordance with the received bias voltage. For example, the first switch SWl can be controlled (turned on and off) by a first control signal (not shown). For example, the first switch SWl can be implemented by a transistor having a gate that receives the first control signal.

[0033] The first current source 113 is a current source of the differential input circuit 111, and is connected to the first transistor Tl and the second transistor T2. The first current source 113 includes a sixth transistor T6. In the exemplary embodiment, the sixth transistor T6 is an NMOS transistor. The drain of the sixth transistor T6 is connected to the source of the first transistor Tl and the source of the second transistor T2, and the source of the sixth transistor T6 is connected to the ground GND. A third bias voltage Vb3 is supplied to the gate of the sixth transistor T6.

[0034] The third connection circuit W3 connects the gate of the first transistor T1 and the first connection circuit W1. That is, the gate and the drain of the first transistor T1 are short-circuited through the third connection circuit W3.

[0035] The third connection circuit W3 includes a second switch SW2. The second switch SW2 adjusts timing of connecting the gate of the first transistor T1 and the first connection circuit W1. The operating point of the first transistor T1 is set by the adjustment of the second switch SW2. For example, the second switch SW2 can be controlled (turned on and off) by a second control signal (not shown). For example, the second switch SW2 can be realized by a transistor having a gate that receives the second control signal.

[0036] The fourth connection circuit W4 connects the gate of the second transistor T2 and the second connection circuit W2. That is, the gate and the drain of the second transistor T2 are short-circuited through the fourth connection circuit W4.

[0037] The fourth connection circuit W4 includes a third switch SW3. The third switch SW3 adjusts timing of connecting the gate of the second transistor T2 and the second connection circuit W2. The operating point of the second transistor T2 is set by the adjustment of the third switch SW3. For example, the third switch SW3 can be controlled (turned on and off) by a third control signal (not shown). For example, the third switch SW3 can be realized by a transistor having a gate that receives the third control signal.

[0038] The second bias voltage supply circuit 115 is connected to the first connection circuit W1 and supplies the first connection circuit W1 with the second bias voltage Vb2. The second bias voltage supply circuit 115 includes a fifth switch SW5. The fifth switch SW5 adjusts timing of supplying the first connection circuit W1 with the second bias voltage Vb2. The drain-source voltage Vds of the third transistor T3 is set by the adjustment of the fifth switch SW5. For example, the fifth switch SW5 can be controlled (turned on and off) by a fifth control signal (not shown). For example, the fifth switch SW5 can be realized by a transistor having a gate that receives the fifth control signal.

[0039] According to the above configuration, the differential amplifier 11 is supplied with the first input signal IN1 and the second input signal IN2, generates a signal indicating a result of comparing the two signals IN1 and IN2, and supplies the output amplifier 12 with the generated signal.

[0040] Next, the output amplifier 12 will be described. The output amplifier 12 receives a signal supplied by the differential amplifier 11 and outputs an output signal VOUT in response to the received signal. The main configuration of the output amplifier 12 includes a fifth transistor T5, a second current source 121, a sixth connection circuit W6, and an output section 122.

[0041] In the exemplary embodiment, the fifth transistor T5 is a PMOS transistor. The source of the fifth transistor T5 is connected to the power supply V3. The signal of the comparison result output by the differential amplifier 11 is supplied to the gate of the fifth transistor T5 through the fourth capacitor C4. The drain of the fifth transistor T5 is connected to the second current source 121 through the fifth connection circuit W5. Since the output of the differential amplifier 11 is supplied to the fifth transistor T5 through the fourth capacitor C4, voltage separation is caused between the differential amplifier 11 and the output amplifier 12, thereby preventing the differential amplifier 11 from affecting the output amplifier 12.

[0042] The second current source 121 is connected to the fifth transistor T5 through the fifth connection circuit W5 interposed between the second current source 121 and the fifth transistor T5.

[0043] The second current source 121 includes a seventh transistor T7. In the exemplary embodiment, the seventh transistor T7 is an NMOS transistor. The drain of the seventh transistor T7 is connected to the drain of the fifth transistor T5 through the fifth connection circuit W5 interposed between the drain of the seventh transistor T7 and the drain of the fifth transistor T5. The source of the seventh transistor T7 is connected to the ground GND. The gate of the seventh transistor T7 is supplied with the third bias voltage Vb3. In addition, as shown in FIG. 1, the gate of the seventh transistor T7 and the gate of the sixth transistor T6 are supplied with the third bias voltage Vb3. The gate of the seventh transistor T7 and the gate of the sixth transistor T6 can receive the third bias voltage Vb3 from the same power supply. Figure 1

[0044] The sixth connection circuit W6 connects the gate of the fifth transistor T5 and the fifth connection circuit W5. That is, the gate and the drain of the fifth transistor T5 are short-circuited through the sixth connection circuit W6.

[0045] The sixth connection circuit W6 includes a fourth switch SW4. The fourth switch SW4 adjusts the timing of connecting the gate of the fifth transistor T5 and the fifth connection circuit W5. The operating point of the fifth transistor T5 is set by the adjustment of the fourth switch SW4. For example, the fourth switch SW4 can be controlled (turned on and off) by a fourth control signal (not shown). For example, the fourth switch SW4 can be implemented by a transistor having a gate that receives the fourth control signal.

[0046] The output section 122 is provided in the fifth connection circuit W5, and outputs the output signal VOUT generated by the output amplifier 12.

[0047] Hereinafter, the operation timing of the switches in the comparator circuit 10 according to the exemplary embodiment of the inventive concept will be described with reference to Figure 2 Figure 2 Figure 1 the timing table of the switches in the comparator circuit 10 shown in FIG. 2.​​​Figure 2 In the graph, the horizontal axis represents time "t", and the vertical axis represents the switching state (on or off). For example, the first switch SW1 is on before time tO, and changes from the on state to the off state at time tl. The fifth switch SW5 changes from the off state to the on state at time tO, and changes from the on state to the off state at time tl. The second switch SW2, the third switch SW3, and the fourth switch SW4 change from the off state to the on state at time tO, and change from the on state to the off state at time t2.

[0048] As shown in FIG. 10, in the comparator circuit 10, the first switch SW1 is on before the second switch SW2, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 are on. Also, the fifth switch SW5 is on at the same time as the second switch SW2, the third switch SW3, and the fourth switch SW4, and the fifth switch SW5 is off at the same time as the first switch SW1. After the first switch SW1 and the fifth switch SW5 are off, the second switch SW2, the third switch SW3, and the fourth switch SW4 are off. The comparator circuit 10 sets the operating point of each transistor by adjusting each switch according to the above timing. Figure 2 The comparator circuit 10 according to the exemplary embodiment of the present inventive concept is described above. As described above, the comparator circuit 10 according to the exemplary embodiment of the present inventive concept is configured to set the operating point of each transistor independently of each other. Also, since the capacitor is provided at the gate of each transistor in the comparator circuit 10 described above, each direct current (DC) component is separated while the alternating current component propagates. As such, for example, the first bias voltage Vbl supplied to the gate of the third transistor T3 and the second bias voltage Vb2 supplied to the drain of the third transistor T3 are set to different values. Accordingly, the first bias voltage Vbl is set in such a way that the gate-source voltage Vgs of the third transistor T3 is greater than the threshold voltage Vth of the third transistor T3. The second bias voltage Vb2 can be different from the first bias voltage Vbl, and the drain-source voltage Vds that allows the third transistor T3 to normally operate in the saturation region can be set based on the second bias voltage Vb2.

[0049] Figure 1 In the exemplary embodiment, the comparator circuit 10 sets the second bias voltage Vb2 to be higher than the first bias voltage Vbl. Accordingly, the transistor of the comparator circuit 10 can set the drain-source voltage Vds to a value suitable for a constant voltage driving method. As such, the comparator circuit 10 can reduce the driving voltage. Figure 1

[0050] In the exemplary embodiment, the comparator circuit 10 sets the second bias voltage Vb2 to be higher than the first bias voltage Vbl. Accordingly, the transistor of the comparator circuit 10 can set the drain-source voltage Vds to a value suitable for a constant voltage driving method. As such, the comparator circuit 10 can reduce the driving voltage.

[0051] ​​The comparator circuit 10 can be used in a device requiring low power consumption. For example, the comparator circuit 10 can be used in a mobile device having a camera function. The mobile device includes an image sensor that generates picture data by imaging an object using a lens. In the image sensor, a plurality of photoelectric conversion elements (e.g., imaging elements) can be arranged in a matrix form and generate an analog signal, and a single slope type ADC performs discrete processing on the analog signal. Accordingly, the mobile device including the comparator circuit 10 can reduce power consumption.

[0052] According to an exemplary embodiment, the comparator circuit 10 can be driven with a low voltage. Power consumption of an ADC circuit, a semiconductor device, or a mobile device including the comparator circuit 10 according to an exemplary embodiment can be reduced.

[0053] The comparator circuit 10 according to an exemplary embodiment of the present inventive concept is described below, which is different from the comparator circuit 10 of Figure 1 For example, unlike the comparator circuit 10 of Figure 1 The comparator circuit 10 according to an exemplary embodiment of the present inventive concept is described below, which is different from the comparator circuit 10 of Figure 3 The comparator circuit 10 according to an exemplary embodiment of the present inventive concept is described below, which is different from the comparator circuit 10 of

[0054] Figure 3 is a circuit diagram of the comparator circuit 10 according to an exemplary embodiment of the present inventive concept. Additional description is omitted with respect to the above-described components / elements to avoid redundancy.

[0055] Figure 3 The comparator circuit 20 shown in FIG. 20 includes a buffer circuit 21 connected to a node receiving the first input signal IN1 and an input stage of the second bias voltage. In other words, the differential amplifier 11 further includes the buffer circuit between the first capacitor C1 and the gate of the first transistor T1. The buffer circuit 21 includes a constant current supply circuit A1 and a buffer transistor T8.

[0056] The constant current supply circuit A1 is a constant current source capable of supplying a given current, and is connected to the power supply V4 and the source of the buffer transistor T8. Also, the constant current supply circuit A1 is connected to the gate of the first transistor T1, and supplies a given signal to the first transistor T1 according to the switching operation of the buffer transistor T8.

[0057] In the embodiment, the buffer transistor T8 is a PMOS transistor. The buffer transistor T8 includes a source connected to the constant current supply circuit Al and a drain connected to the ground GND. A gate of the buffer transistor T8 is connected to the first capacitor Cl and the second bias voltage supply circuit 211. The second bias voltage supply circuit 211 supplies the second bias voltage Vb4 to the gate of the buffer transistor T8. The second bias voltage supply circuit 211 includes a sixth switch SW6. The sixth switch SW6 adjusts the timing for supplying the second bias voltage Vb4 to the gate of the buffer transistor T8.

[0058] Hereinafter, the operation timing of the switches in the comparator circuit 20 according to the exemplary embodiment of the present inventive concept will be described with reference to Figure 4 Figure 4 is a timing chart of the switches in the comparator circuit 20 according to the exemplary embodiment of the present inventive concept. Figure 3

[0059] The comparator circuit 20 according to the exemplary embodiment is different from the comparator circuit 10 of Figure 1 in that the sixth switch SW6 is included. The sixth switch SW6 is turned on before the time tO, and is turned from the on state to the off state at the time t21.

[0060] As shown in Figure 4 , the second switch SW2, the third switch SW3, and the fourth switch SW4 are turned on after the first switch SW1 and the sixth switch SW6 are turned on, and are turned off after the first switch SW1 and the sixth switch SW6 are turned off. Also, the sixth switch SW6 is turned off before the first switch SW1 is turned off.

[0061] The comparator circuit 20 sets the operating point of each transistor by adjusting each switch according to the above timing.

[0062] In the comparator circuit 20 according to the exemplary embodiment of the present inventive concept, a signal can be supplied from the constant current supply circuit Al to the first connection circuit Wl by the above configuration. Accordingly, the comparator circuit 20 can receive the second bias voltage Vb4 with a small impedance. The second bias voltage supply circuit 211 can be configured to operate as a small load.

[0063] According to the exemplary embodiment of the present inventive concept, the comparator circuit 20 can be driven with a low voltage. Also, the comparator circuit 20 according to the exemplary embodiment can reduce a load current related to the bias voltage generation circuit in self-biasing. Accordingly, the comparator circuit 20 according to the exemplary embodiment can reduce power consumption of the bias voltage generation circuit. Accordingly, power consumption of an ADC circuit, a semiconductor device, or a mobile device including the comparator circuit 20 can be reduced.

[0064] Hereinafter, the operation timing of the switches in the comparator circuit 20 according to the exemplary embodiment of the present inventive concept will be described with reference to​​Figure 5 to describe exemplary embodiments of the inventive concept. Figure 5 The structure and Figure 1 The difference in the configuration is that the first current source 113 includes a first current source switch SW31, and the second current source 121 includes a second current source switch SW32. Figure 1 and Figure 5 The differences between the structures.

[0065] In the comparator circuit 30 according to an exemplary embodiment of the present inventive concept, the first current source 113 includes a sixth transistor T6, the second current source 121 includes a seventh transistor T7, and a third bias voltage Vb3 is applied to the gates of the sixth transistor T6 and the seventh transistor T7. Furthermore, the first current source 113 further includes a first current source switch SW31, and the second current source 121 further includes a second current source switch SW32.

[0066] The first current source switch SW31 is connected to the gate of the sixth transistor T6 and adjusts the timing of supplying the third bias voltage Vb3 to the gate of the sixth transistor T6. The second current source switch SW32 is connected to the gate of the seventh transistor T7 and adjusts the timing of supplying the third bias voltage Vb3 to the gate of the seventh transistor T7.

[0067] Below, we will refer to Figure 6 Operation timings of switches of the comparator circuit 30 according to an exemplary embodiment of the inventive concept are described. Figure 6 is a timing diagram of switches in the comparator circuit 30 according to an exemplary embodiment of the inventive concept.

[0068] Figure 6 The timing diagram shown is the same as Figure 2 The difference in the timing diagram shown is that the timing related to the current source switches SW31 and SW32 is added. The current source switches SW31 and SW32 are turned on before time t0 and change from the on state to the off state at time t1. In other words, the current source switches SW31 and SW32 are turned off at the same time as the first switch SW1 is turned off.

[0069] According to the above configuration, the comparator circuit 30 can reduce the mutual influence between the comparator circuit 30 and adjacent circuits by turning off the switch of the current source after determining the bias voltage. The above configuration makes it difficult for the comparator circuit 30 including multiple switches to be affected by the noise caused by the switching operation. Therefore, abnormal operation caused by noise can be reduced in the circuit including the comparator circuit 30. Moreover, the comparator circuit 30 can be driven at a low voltage.

[0070] In an exemplary embodiment, there is additional control circuitry (not shown) to control the Figure 2、 Figure 4 or Figure 6 The described timing provides control signals to one or more of the above-mentioned switches (e.g., SW1-SW6, SW31-SW32, etc.). In exemplary embodiments, the control circuit is provided within a given one of the described comparators. When the given one of the comparators is present in an ADC circuit, the control circuit can also be present in the ADC circuit.

[0071] According to exemplary embodiments of the inventive concept, one or more comparator circuits are provided that are capable of being driven at low voltages.

[0072] While the inventive concept has been illustrated and described with reference to exemplary embodiments, it will be readily apparent to a person of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept.

Claims

1. A comparator circuit comprising: a differential amplifier configured to compare a first input signal and a second input signal to output a comparison result; and an output amplifier configured to output an amplified signal based on the comparison result, wherein the differential amplifier includes: a differential input circuit including a first transistor and a second transistor, the first input signal being applied to a gate of the first transistor through a first capacitor, and the second input signal being supplied to a gate of the second transistor through a second capacitor; a load circuit providing a load to the differential input circuit, and including a third transistor and a fourth transistor, the third transistor being connected to the first transistor with a first connection circuit interposed therebetween, the fourth transistor being connected to the second transistor with a second connection circuit interposed therebetween, gates of the third transistor and the fourth transistor being connected to the first connection circuit through a third capacitor; a first current source being a current source for the differential input circuit, and connected to the first transistor and the second transistor; a first bias voltage supply circuit supplying a first bias voltage to the gates of the third transistor and the fourth transistor, and the third capacitor; a second bias voltage supply circuit supplying a second bias voltage to the first connection circuit; a fifth switch for adjusting timing of supplying the second bias voltage to the first connection circuit; a third connection circuit connecting the gate of the first transistor and the first connection circuit; and a fourth connection circuit connecting the gate of the second transistor and the second connection circuit, wherein the output amplifier includes: a fifth transistor including a gate, the gate of the fifth transistor being supplied with a signal based on the comparison result through a fourth capacitor; a second current source connected to the fifth transistor with a fifth connection circuit interposed therebetween; a sixth connection circuit connecting the gate of the fifth transistor and the fifth connection circuit; and an output portion provided in the fifth connection circuit, and outputting the amplified signal.

2. The comparator circuit according to claim 1, wherein the first bias voltage supply circuit includes a first switch for adjusting timing of supplying the first bias voltage, wherein the third connection circuit includes a second switch for adjusting timing of connecting the gate of the first transistor and the first connection circuit, wherein the fourth connection circuit includes a third switch for adjusting timing of connecting the gate of the second transistor and the second connection circuit, and wherein the sixth connection circuit includes a fourth switch for adjusting timing of connecting the gate of the fifth transistor and the fifth connection circuit.

3. The comparator circuit according to claim 2, wherein the first switch is turned on before the second switch, the third switch, the fourth switch, and the fifth switch are turned on. wherein the fifth switch, the second switch, the third switch, and the fourth switch are simultaneously turned on, and wherein the second switch, the third switch, and the fourth switch are turned off after the first switch and the fifth switch are turned off.

4. The comparator circuit according to claim 2, wherein the differential amplifier further comprises: a buffer circuit connected between the first capacitor and a gate of the first transistor, wherein the buffer circuit comprises: a constant current supply circuit that supplies a given current; a buffer transistor having a source, a drain, and a gate, one of the source and the drain being connected to the constant current supply circuit, the other of the source and the drain being grounded, and the first input signal and a second bias voltage being supplied to the gate of the buffer transistor; a second bias voltage supply circuit that supplies the second bias voltage; and a sixth switch for adjusting timing of supplying the second bias voltage to the gate of the buffer transistor.

5. The comparator circuit according to claim 4, wherein the second switch, the third switch, and the fourth switch are turned on after the first switch and the sixth switch are turned on, and are turned off after the first switch and the sixth switch are turned off.

6. The comparator circuit according to claim 2, wherein each of the first current source and the second current source includes a current source transistor, a gate of the current source transistor being supplied with a third bias voltage.

7. The comparator circuit according to claim 6, wherein each of the first current source and the second current source further includes a current source switch for adjusting timing of supplying the third bias voltage.

8. The comparator circuit according to claim 7, wherein the current source switch is turned off when the first switch is turned off.

9. A mobile device including an analog-to-digital converter circuit, the analog-to-digital converter circuit including a plurality of comparator circuits, wherein each of the plurality of comparator circuits including: a differential amplifier configured to compare a first input signal and a second input signal to output a comparison result; and an output amplifier configured to output an amplified signal based on the comparison result, wherein the differential amplifier includes: a differential input circuit including a first transistor and a second transistor, the first input signal being applied to a gate of the first transistor through a first capacitor, and the second input signal being supplied to a gate of the second transistor through a second capacitor; a load circuit that provides a load to the differential input circuit, and includes a third transistor and a fourth transistor, the third transistor being connected to the first transistor with a first connection circuit interposed therebetween, the fourth transistor being connected to the second transistor with a second connection circuit interposed therebetween, a gate of the third transistor and a gate of the fourth transistor being connected to the first connection circuit through a third capacitor; a first current source connected to the third transistor and the fourth transistor, and configured to supply a first current to the third transistor and the fourth transistor; and a second current source connected to the third transistor and the fourth transistor, and configured to supply a second current to the third transistor and the fourth transistor. a first current source that is a current source of the differential input circuit and is connected to the first transistor and the second transistor; a first bias voltage supply circuit that supplies a first bias voltage to a gate of the third transistor and a gate of the fourth transistor and the third capacitor; a second bias voltage supply circuit that supplies a second bias voltage to the first connection circuit; a fifth switch for adjusting timing of supply of the second bias voltage to the first connection circuit; a third connection circuit that connects the gate of the first transistor and the first connection circuit; and a fourth connection circuit that connects the gate of the second transistor and the second connection circuit, wherein the output amplifier includes: a fifth transistor including a gate to which a signal based on the comparison result is supplied through a fourth capacitor; a second current source connected to the fifth transistor with a fifth connection circuit interposed between the second current source and the fifth transistor; a sixth connection circuit that connects the gate of the fifth transistor and the fifth connection circuit; and an output portion provided in the fifth connection circuit and outputting the amplified signal.

10. The mobile device according to claim 9, comprising a semiconductor device, wherein the semiconductor device includes: the analog-digital converter circuit; and a plurality of photoelectric conversion elements arranged in a matrix shape, wherein the analog-digital converter circuit performs discrete processing on an analog signal generated by the photoelectric conversion elements.

11. The mobile device according to claim 10, further comprising a lens for imaging an image of an object, wherein the semiconductor device generates and processes image data imaged by the lens.

12. A comparator circuit, comprising: a differential amplifier configured to compare a first input signal and a second input signal to output a comparison result; and an output amplifier configured to output an amplified signal based on the comparison result, wherein the differential amplifier includes: a differential input circuit including a first transistor and a second transistor, the first input signal being applied to a gate of the first transistor through a first capacitor, and the second input signal being supplied to a gate of the second transistor through a second capacitor; a load circuit that provides a load to the differential input circuit and includes a third transistor and a fourth transistor, the third transistor being connected to the first transistor with a first connection circuit interposed between the third transistor and the first transistor, the fourth transistor being connected to the second transistor with a second connection circuit interposed between the fourth transistor and the second transistor, a gate of the third transistor and a gate of the fourth transistor being connected to the first connection circuit through a third capacitor; a first current source that is a current source of the differential input circuit and is connected to the first transistor and the second transistor; a first bias voltage supply circuit that supplies a first bias voltage to a gate of the third transistor and a gate of the fourth transistor and the third capacitor; a second bias voltage supply circuit that supplies a second bias voltage to the first connection circuit; ​ a third connection circuit connecting the gate of the first transistor and the first connection circuit; a fourth connection circuit connecting the gate of the second transistor and the second connection circuit; and a buffer circuit connected between the first capacitor and the gate of the first transistor, wherein the buffer circuit includes: a constant current supply circuit supplying a given current; a buffer transistor having a source, a drain, and a gate, one of the source and the drain being connected to the constant current supply circuit, the other of the source and the drain being grounded, and the first input signal and a second bias voltage being supplied to the gate of the buffer transistor; and a second bias voltage supply circuit supplying the second bias voltage.

13. The comparator circuit according to claim 12, wherein the output amplifier includes: a fifth transistor including a gate to which a signal based on the comparison result is supplied through a fourth capacitor; a second current source connected to the fifth transistor with a fifth connection circuit interposed between the second current source and the fifth transistor; a sixth connection circuit connecting the gate of the fifth transistor and the fifth connection circuit; and an output portion provided in the fifth connection circuit and outputting the amplified signal.

14. The comparator circuit according to claim 13, wherein the first bias voltage supply circuit includes a first switch for adjusting timing of supplying the first bias voltage, wherein the third connection circuit includes a second switch for adjusting timing of connecting the gate of the first transistor and the first connection circuit, wherein the fourth connection circuit includes a third switch for adjusting timing of connecting the gate of the second transistor and the second connection circuit, and wherein the sixth connection circuit includes a fourth switch for adjusting timing of connecting the gate of the fifth transistor and the fifth connection circuit.

15. The comparator circuit according to claim 14, wherein the differential amplifier further includes: a fifth switch for adjusting timing of supplying the voltage of the gate of the first transistor to the first connection circuit.

16. The comparator circuit according to claim 15, wherein the second bias voltage supply circuit further includes a sixth switch for adjusting timing of supplying the second bias voltage to the gate of the buffer transistor.

17. The comparator circuit according to claim 16, wherein the second switch, the third switch, and the fourth switch are turned on after the first switch and the sixth switch are turned on, and are turned off after the first switch and the sixth switch are turned off.

18. The comparator circuit according to claim 13, wherein each of the first current source and the second current source includes a current source transistor, the gate of the current source transistor being supplied with a third bias voltage. ​

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