Resistive memory device and method of operating a resistive memory device

Abstract

A resistive memory device and a method of operating a resistive memory device are disclosed. In an embodiment, the resistive memory device may include a memory cell, the memory cell including at least two transistors and a resistive element. The resistive memory device may also include: a bit line through which data is exchanged with the memory cell, wherein the bit line is electronically interconnected with the memory cell; and a bit line regulator connected to the bit line. The bit line regulator is capable of regulating the bit line based on the state of the resistive element. Forming signals and voltage settings can be transmitted to the memory cell through the bit line regulator and across the bit line.

Description

Technical Field

[0001] The present invention relates to a resistive memory device and a method of operating a resistive memory device. Background Art

[0002] Nonvolatile memory can be used in a wide variety of commercial and military electronic devices and equipment. RRAM (resistive random access memory) is a promising candidate for the next generation of nonvolatile memory technology due to its simple structure and CMOS (complementary metal oxide semiconductor) logic compatible process technology involved in the formation and operation of RRAM.

[0003] RRAM, also known as ReRAM, is a form of non-volatile memory device that can be operated by changing the resistance of a specially formulated solid dielectric material. An RRAM cell may include a metal oxide material sandwiched between a top electrode and a bottom electrode. This metal oxide material may possess a variable resistance, and its resistance level may correspond to the data state stored in the RRAM cell. Summary of the invention

[0004] Embodiments of a resistive memory device and a method of operating a resistive memory device are disclosed. In an embodiment, the resistive memory device may include a memory cell, the memory cell may include at least two transistors and a resistive element. The resistive memory device may also include a bit line through which data may be exchanged with the memory cell, wherein the bit line is electronically interconnected with the memory cell. The resistive memory device may also include a bit line regulator connected to the bit line, wherein the bit line regulator regulates the bit line based on the state of the resistive element. Formation signals and voltage settings may be transmitted to the memory cell through the bit line regulator and across the bit line.

[0005] In an embodiment, the resistive element may include a variable resistor.

[0006] In an embodiment, the bit line regulator may be directed to the memory cell during a forming operation and the forming signal may be transmitted to the memory cell during the forming operation.

[0007] In an embodiment, the resistive memory device may further include a word line, a source line, and an intermediate sense line interconnecting the memory cells.

[0008] In an embodiment, the bit line regulator may include a capacitive voltage divider connected to the intermediate sense line during a write operation involving writing data to the memory cell at the bit line.

[0009] In an embodiment, the intermediate sense line may be connected to the source line in a reset write mode to increase the transistor strength of at least one of the at least two transistors of the memory cell.

[0010] In an embodiment, the resistive memory device further includes a RRAM (resistive random access memory), which may include a memory cell, a bit line, and a bit line regulator.

[0011] In an embodiment, the resistive element may include a resistive memory element.

[0012] In another embodiment, a resistive memory device may include a plurality of memory cells, wherein each memory cell among the plurality of memory cells includes at least two transistors and a resistive element. Such a resistive memory device may also include a plurality of bit lines through which data may be exchanged with the plurality of memory cells, wherein the plurality of bit lines are electronically interconnected with the plurality of memory cells. The resistive memory device may also include at least one bit line regulator connected to the plurality of bit lines, wherein the at least one bit line regulator regulates the plurality of bit lines based on a state of a resistive element. Forming signals and voltage settings may be transmitted to the plurality of memory cells through the at least one bit line regulator and across the plurality of bit lines.

[0013] In an embodiment of a resistive memory device, the resistive element may include a variable resistor.

[0014] In an embodiment of the resistive memory device, the resistive memory device may further include a plurality of word lines, a plurality of source lines, and a plurality of intermediate sense lines interconnecting the plurality of memory cells.

[0015] In an embodiment of the resistive memory device, each of the plurality of memory cells may be respectively connected to a word line among the plurality of word lines, a bit line among the plurality of bit lines, a source line among the plurality of source lines, and an intermediate sensing line.

[0016] In an embodiment of the resistive memory device for which protection is applied, the at least one bit line regulator may include a plurality of capacitors connected to a plurality of transistors, wherein at least one transistor among the plurality of transistors is connected to an intermediate sensing line, and at least one other transistor among the plurality of transistors is connected to a bit line among the plurality of bit lines.

[0017] In another embodiment, a method of operating a resistive memory device may involve regulating a bit line via a bit line regulator connected to a bit line based on a state of a resistive element of a memory cell, the memory cell comprising at least two transistors and the resistive element, wherein the bit line is electronically interconnected to the memory cell, and signals and voltage settings are transmitted through the bit line regulator and across the bit line to the memory cell.

[0018] In an embodiment of a method of operating a resistive memory device, the resistive element may include a variable resistor.

[0019] In an embodiment, the method of operating a resistive memory device may further involve directing a bit line regulator to a memory cell during a formation operation of transmitting a formation signal to the memory cell.

[0020] In an embodiment of a method of operating a resistive memory device, memory cells may be interconnected with a word line, a source line, and an intermediate sense line.

[0021] In an embodiment of a method of operating a resistive memory device, a bit line regulator may include a capacitive voltage divider connected to the intermediate sense line during a write operation involving writing data to a memory cell at the bit line.

[0022] In an embodiment of a method of operating a resistive memory device, an intermediate sense line may be connected to a source line in a reset write mode to increase the transistor strength of at least one of the at least two transistors of the memory cell.

[0023] In an embodiment of a method of operating a resistive memory device, the resistive memory device may include an RRAM (Resistive Random Access Memory), which may include a memory cell, a bit line, and a bit line regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A circuit diagram depicting a resistive memory device.

[0025] Figure 2 Describe the circuit diagram of the bit line regulator.

[0026] Figure 3 a circuit diagram depicting a resistive memory device including voltage and bit parameters applicable during a form / set operation;

[0027] Figure 4 depicts a table showing selected and unselected bits in a form / set operation of a resistive memory device;

[0028] Figure 5 A circuit diagram depicting a resistive memory device including voltage and bit parameters applicable during a reset operation or a read operation;

[0029] Figure 6 depicts a table showing selected and unselected bits in a reset operation of a resistive memory device;

[0030] Figure 7 depicts a table showing selected and unselected bits in a read operation of a resistive memory device; and

[0031] Figure 8 A flow chart showing logical operational steps of a method of operating a resistive memory device is depicted. DETAILED DESCRIPTION

[0032] It can be readily appreciated that the components of the embodiments generally described herein and illustrated in the accompanying drawings may be arranged and designed in a wide variety of different configurations. Therefore, the following more detailed description of the various embodiments represented in the figures is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. Although various aspects of the embodiments are presented in the figures, the figures are not necessarily drawn to scale unless specifically indicated.

[0033] The present invention may be implemented in other specific forms without departing from the spirit or characteristics of the present invention. The described embodiments are to be considered in all respects as merely illustrative and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than by the specific embodiments thereof. All changes within the equivalent meaning and scope of the claims are encompassed within the scope of the claims.

[0034] Reference throughout this specification to features, advantages, or similar language does not imply that all features and advantages that may be achieved with the present invention should be or are present in any single embodiment of the present invention. Language referring to features and advantages may be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Therefore, discussion of features and advantages and similar language throughout this specification may refer to the same embodiment.

[0035] Furthermore, the described features, advantages, and characteristics of the present invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art may recognize, in light of the description herein, that the present invention may be practiced without one or more of the particular features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present invention.

[0036] Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may refer to the same embodiment.

[0037] Several aspects of the disclosed embodiments are presented with reference to various systems, methods, and devices. These systems, methods, and devices are described in the detailed description below and are illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, operations, methods, algorithms, engines, applications, etc. (which may be individually or collectively referred to as an "element" or "element"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0038] Figure 1A circuit diagram depicting a resistive memory device 100 includes an array of one or more memory cells 202, 204, 206, 208, 210, 212, 214, 216, and 218 and one or more bit line regulators, including bit line regulator 102, bit line regulator 104, and bit line regulator 106. The resistive memory device 100 may be formed as an array including the memory cells 202, 204, 206, 208, 210, 212, 214, 216, and 218. It should be noted that the resistive memory device 100 may be an RRAM (resistive random access memory).

[0039] The resistive memory device 100 may also include one or more word lines, including word line 108, word line 110, and word line 112. It should be noted that as used herein, the acronym WL may refer to "word line." Thus, "WL1" may refer to a first word line, "WL2" may refer to a second word line, "WL3" may refer to a third word line, and so on. Word line 108 (also referred to as "word line") may be a word line. Figure 1 Word line 110 (indicated as "WL1" in FIG. 1 ) may interact with and be connected to memory cell 202, memory cell 208, and memory cell 214. Figure 1 Word line 112 (also shown as "WL2") may interact with and be connected to memory cell 204, memory cell 210, and memory cell 216. Figure 1 2. The memory cell 206, the memory cell 212, and the memory cell 218 may interact with and be connected to the memory cell 206, the memory cell 212, and the memory cell 218.

[0040] The resistive memory device 100 may also include one or more bit lines, including a bit line 114, a bit line 116, and a bit line 118. It should be noted that as used herein, the acronym "BL" may refer to a bit line. Thus, "BL1" may refer to a first bit line, "BL2" may refer to a second bit line, "BL3" may refer to a third bit line, and so on.

[0041] Bit line 114 (also labeled "BL1") may electronically interact and interconnect memory cell 202, memory cell 204, and memory cell 206. Bit line 114 may also be connected to bit line regulator 102. Bit line 116 (also labeled "BL2") may electronically interact and interconnect memory cell 208, memory cell 210, and memory cell 212.

[0042] In addition, bit line 116 may also be connected to bit line regulator 104. Bit line 118 (also labeled as "BL3") may electronically interact and interconnect memory cell 214, memory cell 216, and memory cell 218, and may also be connected to bit line regulator 106. It should be noted that the acronyms "BL" and "bl" as used herein refer to "Bit Line or bitline". Therefore, data may be exchanged with memory cell 202, 204, 206, 208, 210, 212, 214, 216, or 218 using the corresponding bit line.

[0043] The bit line regulator 102 can regulate the bit line 114 (i.e., "BL1") based on the states of the corresponding resistance elements in the memory cell 202, the memory cell 204, and the memory cell 206. For example, the bit line regulator 102 can specifically regulate the bit line 114 based on the state of the resistance element 138 of the memory cell 202, and so on.

[0044] The bit line regulator 104 may similarly regulate the bit line 116 based on the state of one or more of the corresponding resistance elements of the memory cells 208, 210, and 212. It should be noted that the disclosed resistance elements may include resistance storage elements, such as variable resistors. The bit line regulator 106 may regulate the bit line 118 based on the state of the corresponding resistance elements of the memory cells 214, 216, and 218. As will be discussed in more detail herein, the formation signals and voltage settings may be transmitted through the bit line regulator 102, the bit line regulator 104, or the bit line regulator 106 and across the bit line 114, the bit line 116, or the bit line 118 to the memory cells 202, 204, 206 and the memory cells 208, 210, 212 and the memory cells 214, 216, 218, respectively.

[0045] It should be noted that the term "formation" as used herein may relate to the "formation" or "formation" process of the resistive memory device 100, which may be performed to initiate the resistive switching properties of the memory cell (e.g., of the resistive storage element of the memory cell). The formation process may be an electroforming process, which may include the formation of an initial conductive filament that may serve as a switching element of the memory cell. Such a formation process may be performed on a new memory cell (e.g., to initialize a memory cell that may not have undergone a set / reset operation), and / or on a "tail bit" associated with a formation-free memory cell (e.g., a resistive memory cell that may not require a formation process to initialize a bistable switching capability). The terms "reset" and "set" as used herein may relate to a high resistance (reset) state and a low resistance (set) state, respectively.

[0046] The resistive memory device 100 may also include one or more source lines, including source line 120, source line 122, and source line 124. It should be noted that, as used herein, the acronym "SL" may refer to "source line." Thus, "SL1" may refer to a first source line, "SL2" may refer to a second source line, "SL3" may refer to a third source line, and so on.

[0047] Source line 120 (also labeled "SL1") may interact and connect with memory cell 202, memory cell 204, and memory cell 206. Source line 122 (also labeled "SL2") may interact and connect with memory cell 208, memory cell 210, and memory cell 212. Additionally, source line 124 (also labeled "SL3") may interact and connect with memory cell 214, memory cell 216, and memory cell 218.

[0048] The resistive memory device 100 may also include one or more intermediate sense lines, including an intermediate sense line 126, an intermediate sense line 128, and an intermediate sense line 130. The intermediate sense line 126 (also labeled “INTsense1”) may also interact and connect with the memory cell 202, the memory cell 204, the memory cell 206, and the bit line regulator 102. The intermediate sense line 128 (also labeled “INTsense2”) may interact and connect with the memory cell 208, the memory cell 210, the memory cell 212, and the bit line regulator 104. The intermediate sense line 130 (also labeled “INTsense3”) may interact and connect with the memory cell 214, the memory cell 216, the memory cell 218, and the bit line regulator 106. Thus, each memory cell may be interconnected with a word line, a source line, and an intermediate sense line.

[0049] like Figure 1 As shown in FIG. 1 , each memory cell 202, 204, 206, 208, 210, 212, 214, 216, and 218 in the array may include two or more transistors and a resistive element. An example of a memory cell including two or more transistors and a resistive element is memory cell 202, which may include transistor 134, transistor 136, and resistive element 138, which may be a variable resistor. Note that for the sake of simplicity, the detailed description of the memory cell 202 and the memory cell 202 is not provided. Figure 1 Thus, each memory cell 202, 204, 206, 208, 210, 212, 214, 216, and 218 may include two or more transistors and a resistive element that may be a variable resistor.

[0050] The resistive element, such as the resistive element 138, may be a conductive filament or may be formed by a group of conductive filaments. The applied voltage may respectively form and disconnect the conductive filaments in the resistive switching layer of the resistive memory device 100, thereby switching the resistive memory device 100 between a low resistance state (LRS) and a high resistance state (HRS).

[0051] It should be noted that LRS and HRS may be states of individual resistive elements rather than the entire array. Since the RRAM may be EEPROM (Electrically Erasable Programmable Read Only Memory) bytes, a user may perform operations relative to the memory rather than performing bulk operations such as may occur in flash memory (i.e., it should be noted, however, that "forming" may be implemented as a one-time operation performed by the device manufacturer). A forming operation may be required to form the conductive filaments in order to operate the resistive memory device 100. A set operation and a reset operation may be used to switch the resistance of the resistive memory device 100 between LRS and HRS, respectively.

[0052] Figure 2 A circuit diagram of a bit line regulator, such as bit line regulator 102, is depicted. It can be appreciated that although Figure 2 , but similar circuit diagrams with similar electronic components may also be implemented for bit line regulators 104 and 106. For ease of explanation, reference is made to Figure 2 The bit line regulator 102 in FIG.

[0053] Figure 2 1 may include a capacitor 142 (also labeled "C1") that may be electronically connected to a capacitor 144 (also labeled "C2"). Capacitor 144 may be electronically connected to transistor 148 and transistor 146. Capacitor 142 may be electronically connected to transistor 146 and transistor 148. Capacitor 142 may also be electronically connected to transistor 140, which in turn may be connected to intermediate sense line 126. Capacitor 142 and capacitor 144 may also be electronically connected to transistor 150, which in turn may be connected to bit line 114. Transistor 146 and transistor 148 are connected to each other at their respective gates.

[0054] like Figure 2 As further shown in FIG. 1 , the bit line regulator 102 may include a Figure 2 When the resistor element 138 or the resistor elements of memory cells 204 and 206 are reset or manufactured with a "high resistance" in the "factory", the middle sense line 126 (at Figure 2The voltage at the middle sense line 126 (also labeled as "INTsense" in FIG. 1 ), where "INT" means "middle") may be approximately 0 V. It should be noted that the voltage at the middle sense line 126 may be referred to as the INTsense voltage or the middle sense voltage, and "INTsense" may also be referred to as the "INTsense node".

[0055] As one or more of the resistive elements, such as resistive element 138 or the resistive elements of memory cells 204 and 206, become increasingly conductive, the voltage of bit line 114 may increase, and the voltage at node B may also increase. As the voltage at node B increases, the voltage of bit line 114 may increase due to transistor 150 (at Figure 2 The transistor 150 can also be connected to a write voltage Vwrite, such as Figure 2 The voltage Vwrite may be a write voltage.

[0056] Capacitors 142 and 144 may depend on the behavior of transistor 150 and one or more resistive elements, such as resistive element 138 of memory cell 202 or resistive elements associated with memory cells 204 and 206. Capacitors 142 and 144 may form a capacitive voltage divider that may be used to load intermediate sense line 126 with DC (direct current) during a write operation.

[0057] It should be noted that the terms "write" and "read" as used herein may refer to reading data from or writing data to a memory such as a disclosed memory cell. In other words, data may be accessed (read) or written (written) to individual storage locations within the resistive memory device 100, such as the disclosed memory cells 202, 204, 206, 208, 210, 212, 214, 216, and 218. Such data exchange may occur through a read operation or a write operation. The selection of a read operation ("read") or a write operation ("write") may be determined by a read / write signal (e.g., a voltage pulse) applied to the resistive memory device 100.

[0058] Transistor 140 may act as a write transistor, which may be used to isolate intermediate sense line 126 from reset circuitry (not shown) for the capacitive voltage divider. Figure 2 ) can be input to transistor 146 and transistor 148, which are in Figure 2 A reset signal 149 may be applied to the bit line regulator 102 prior to the set operation, reset operation, and read operation so that the node B may be set to ground (0 volts).

[0059] exist Figure 2In the embodiment, transistor 140 may be introduced to connect the rest of the bit line regulator 102 to the middle sense line 126 ( Figure 2 Thus, the gate electrode of transistor 140 can be isolated by a “write” signal (i.e., Figure 2 Transistors 146 and 148 may be included to zero the charge on the plates of capacitors 142 and 144 (i.e., C1 and C2, respectively). Transistors 146 and 148 may include a circuit coupled together and coupled to a reset signal 149 (in Figure 2 Once reset, capacitors 142 and 144 can also enable node B (i.e., Figure 2 'B' in FIG. 1 is at ground potential before rising in response to the INTsense voltage.

[0060] Figure 3 A circuit diagram of a resistive memory device 100 is depicted including voltage and bit parameters applicable during a formation / set operation. Figures 1 to 7 , like parts or elements may be indicated by like reference numerals. It should be noted that the acronym "CSC" as used herein may refer to "control sense circuit." Thus, "CSC1" may refer to a first control sense circuit, "CSC2" may refer to a second control sense circuit, and "CSC3" may refer to a third control circuit. CSC1 may refer to bit line regulator 102, and CSC2 may refer to bit line regulator 104. Additionally, CSC3 may refer to bit line regulator 106. Additionally, in Figure 3 , “Vbl1” may refer to a first bit line voltage, “Vbl2” may refer to a second bit line voltage, and “Vbl3” may refer to a third bit line voltage.

[0061] The acronym “AG” may refer to “Assist Gate”. Thus, “AG1” may refer to a first assist gate, “AG2” may refer to a second assist gate, and so on. Additionally, the acronym “SG” may refer to “Sense Gate”. Thus, “SG1” may refer to a first sense gate, “SG2” may refer to a second sense gate, and so on.

[0062] Figure 4 Describes table 160, which is shown in Figure 3 1 and 2. The selected and unselected bits in the forming / setting operation of the resistive memory device 100 shown in FIG.

[0063] It should be noted that A1, A1', A2, A2', A3, A3', and A4, A4' may refer to nodes within the resistive memory device 100, and R1, R2, R3, and R4 may refer to resistance values ​​or resistors of the resistive memory device 100. Therefore, VA1 may refer to the voltage at node A1, and VA1A1' may refer to the voltages at nodes A1 and A1'. VA2 may refer to the voltage at node A2, and VA2A2' may refer to the voltages at nodes A2 and A2'. Similarly, VA3 may refer to the voltage at node A3, and VA3A3' may refer to the voltages at nodes A3 and A3'. VA4 may refer to the voltage at node A4, and VA4A4' may refer to the voltages at nodes A4 and A4'.

[0064] In table 160, Bit1, Bit2, Bit3, and Bit4 are labeled 1 (select), 2 (row), 3 (column), and 4 (diagonal) at corresponding table headers 161, 163, 165, and 167, respectively. Bit1 can be a selected cell, and Bit2 can represent an unselected cell in the same row. Bit3 can represent an unselected cell in the same column. Bit4 can represent an unselected cell that is neither in the same row nor in the same column. Prior to the formation / set operation, a separate voltage pulse Vrs (e.g., a reset voltage) can be applied to set node B of the bit line regulator 102 to 0V.

[0065] At the start of a formation or setup operation, Figure 4 The resistor element marked as R1 in FIG. Figure 1 The resistor element 138 shown may be in HRS (high resistance state). The voltage Vbl1 (ie, the "BL1" voltage) may be applied to the resistor element 138 via P1 (which corresponds to Figure 2 The transistor 150 shown in FIG. 1 is passed to the node A1, and the node A1' may be 0V, while the voltage V A1A1' It may be approximately voltage Vbl1 (voltage Vbl1 may be a first bit line voltage, also referred to as “BL1 voltage”).

[0066] When the filaments in the resistive layer begin to form / set, R1 can decrease and V A1 Can be raised and passed through SC1 (SC1 corresponds to Figure 1 transistor 136), CSC1 and the capacitor divider shown to node B, and transistor P1 may become less conductive, and the voltage V A1A1' can be further reduced to constrain the continued formation of the filament. It should be noted that the voltage V A2A2' , voltage V A3A3' and voltage V A4A4' It may be approximately 0V, where Vbl=0V or Vwl=0V. The voltage Vset may refer to a set voltage, and Vform may refer to a forming voltage. It should be noted that the voltage Vrs may refer to a reset voltage, and this reset voltage may involve a reset of the capacitive voltage divider.

[0067] Figure 5 A circuit diagram of a resistive memory device 100 is depicted including voltage and bit parameters applicable during a reset operation or a read operation. Figure 5 The circuit diagram of the resistive memory device 100 shown in FIG. Figure 4 , in which labels such as R2, R3, and R4 are added to represent other resistance elements (eg, resistance storage elements) of the resistance memory device 100.

[0068] Figure 6 Depicting table 170, which shows the available Figure 5 1 and 2. The selected and unselected bits of the reset operation of the resistive memory device 100 are shown in FIG. Figure 5 As shown in Table 160, Figure 6 The table 170 depicted in includes Bit1, Bit2, Bit3 and Bit4 marked as 1 (selection), 2 (row), 3 (column) and 4 (diagonal) at corresponding table headers 171, 173, 175 and 177, respectively.

[0069] In table 170, Vbl may refer to the bit line voltage (where "bl" may refer to "bit line"). Note that a ground path may exist on either side of the bit line because the bit line may be completely at ground ("GND") in the reset write mode, where the bit line may be completely connected to GND during reset (and therefore may not require decoding). Additionally, Vsl may refer to the source line voltage (where "sl" may refer to source line), and Vwl may refer to the word line voltage (where "wl" refers to word line).

[0070] Vsc may refer to the stack capacitor voltage, and Vrs may refer to the reset voltage. During reset, the bit line regulator may not be needed, so Vrs may be used as a reset for capacitors 142 and 144, and Vsc for the connection of INTsense (i.e., the middle sense line) to the stack capacitor may be at GND, so the bit line regulator may be disabled. In the reset write mode, INTsense may be connected to the source line to increase (e.g., double) the transistor strength of the memory cell transistor. In other words, the middle sense line may be connected to the sense line in the reset write mode to increase the transistor strength of one or more of the transistors of the memory cell. Finally, Vreset may also refer to the reset voltage, and Vwlrs may refer to the word line reset voltage. The acronyms "NW" or "nw" may refer to "N-well". Therefore, NW (N-well), NW1 (N-Well1), etc. refer to the NW of the p-channel of the bit line regulator. For example, Vnw may refer to the NW voltage of the p-channel of transistor 140.

[0071] In a reset operation, the Vrs voltage pulse prior to the reset may be optional, as the potential associated with node B may not modulate the reset behavior. Additionally, during a reset operation (i.e., "reset"), the memory cell may change from an LRS (low resistance state) to an HRS. Note that, as discussed earlier, the BL ("bit line") may be pulled down to GND ("ground") not through a well diode but through a transistor (N-channel). Note that at least one n-channel device may be connected to each BL of the array to provide a connection to the GND signal. The bit line regulator 102 may be disconnected when CSC1 is in the off state. Additionally, when Vwl2 is in the off state, current does not flow through R3. When Vsl2 is at 0V, current also does not flow through R2 and R4.

[0072] Figure 7 A table showing selected and unselected bits in a read operation of the resistive memory device 100 is depicted. Similar to the previously discussed Figure 5 The table 160 and Figure 6 As depicted in Table 170, Figure 7 The table 180 shown in includes Bit1, Bit2, Bit3 and Bit4 marked as 1 (selection), 2 (row), 3 (column) and 4 (diagonal) at the corresponding table headers 181, 183, 185 and 187, respectively.

[0073] Figure 7 Table 180 shown in indicates that the Vrs voltage pulse is optional because the node B potential does not modulate the read behavior. The read operation of the resistive memory device 100 is similar to the reset operation in some aspects, but may be different from the reset operation in other aspects. For example, a Vread ("read" voltage) signal can be applied through SL, and the bit line regulator 102 can be disconnected from the resistive memory device 100 when CSC is in the off state. It should be noted that whenever there is a read operation or a reset write operation, the n-channel transistor can connect all bit lines to GND. For Bit2 and Bit 4, the current with Vsl2 may not be approximately at 0V. For Bit3, there may be almost no current when Vwl2 is at 0V.

[0074] Figure 8A flow chart showing the logical operational steps of a method 300 of operating a resistive memory device (e.g., resistive memory device 100) is depicted. As indicated at block 302, the process may be initiated. As shown at block 304, a bit line regulator may be directed to a memory cell during a forming operation, and a forming signal may be transmitted to the memory cell during the forming operation. Next, as shown at block 306, a bit line may be adjusted by the bit line regulator based on the state of a resistive element of the memory cell (i.e., as previously discussed—a memory cell may include at least two transistors and a resistive element, and a bit line may be electronically interconnected to the memory cell). Thereafter, as depicted at block 308, a forming signal and a voltage setting may be transmitted to the memory cell by the bit line regulator and across the bit line. As shown at block 310, the process may then end.

[0075] Although the operations of the methods herein are shown and described in a particular order, the order of operations may be changed so that some operations may be performed in reverse order or some operations may be performed at least partially simultaneously with other operations. In another embodiment, instructions or sub-operations of different operations may be implemented in an intermittent and / or alternating manner.

[0076] At least some operations of the methods described herein may be implemented using software instructions stored on a computer usable storage medium executed by a computer. For example, an embodiment of a computer program product includes a computer usable storage medium for storing a computer readable program.

[0077] The computer usable or computer readable storage medium may be an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system (or device or apparatus). Examples of non-transitory computer usable and computer readable storage media include semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk and optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), digital video disk (DVD), flash memory, etc.

[0078] Alternatively, the embodiments of the present invention may be implemented in hardware or in an implementation scheme containing hardware elements and software elements. In an embodiment that does utilize software, the software may include firmware, resident software, microcode, etc.

[0079] In some alternative embodiments, the functions mentioned in the blocks may not occur in the order mentioned in the figure. For example, two blocks shown in succession may actually be executed simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that the blocks in the block diagram and / or flow chart illustrations and the combination of blocks in the block diagram and / or flow chart illustrations may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or implements a combination of dedicated hardware and computer instructions.

[0080] Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.

Claims

1. A resistance memory device, characterized in that: include: a memory cell, the memory cell comprising at least two transistors and a resistance element; a bit line through which data is exchanged with the memory cell, wherein the bit line is electronically interconnected with the memory cell; as well as a bit line regulator connected to the bit line, wherein the bit line regulator regulates the bit line based on a state of the resistive element, wherein a forming signal and a voltage setting are transmitted through the bit line regulator and across the bit line to the memory cell, wherein the resistive memory device further comprises a word line, a source line and an intermediate sensing line interconnected with the memory cell, Wherein the bit line regulator includes a capacitive voltage divider connected to the intermediate sense line during a write operation involving writing data to the memory cell at the bit line.

2. The resistive memory device according to claim 1, wherein: The resistance element includes a variable resistor.

3. The resistive memory device according to claim 1, wherein: The bit line regulator is directed to the memory cell during a forming operation in which the forming signal is transmitted to the memory cell.

4. The resistive memory device according to claim 1, wherein: The intermediate sense line is connected to the source line in a reset write mode to increase the transistor strength of at least one of the at least two transistors of the memory cell.

5. The resistive memory device according to claim 1, wherein: Further included is an RRAM (resistive random access memory) including the memory cell, the bit line and the bit line regulator.

6. The resistive memory device according to claim 1, wherein: The resistance element includes a resistance memory element.

7. A method of operating a resistive memory device, characterized in that: include: regulating a bit line via a bit line regulator connected to a bit line based on a state of a resistive element of a memory cell, the memory cell comprising at least two transistors and the resistive element, wherein the bit line is electronically interconnected to the memory cell; as well as transmitting a forming signal and a voltage setting to the memory cell through the bit line regulator and across the bit line, wherein the memory cells are interconnected with word lines, source lines and intermediate sense lines, Wherein the bit line regulator includes a capacitive voltage divider connected to the intermediate sense line during a write operation involving writing data to the memory cell at the bit line.

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