Array substrate motherboard and preparation method thereof, array substrate and display device

Abstract

The present application provides an array substrate motherboard and a preparation method thereof, an array substrate and a display device, which relate to the field of display technology and can detect the gate drive circuit in the array substrate in advance. The array substrate motherboard includes: a substrate motherboard. A plurality of display units are arranged on the substrate motherboard, and a display unit has a display area and a non-display area, and the non-display area at least partially surrounds the display area. The display unit includes: a gate drive circuit, a detection line and a detection unit arranged in the non-display area, and at least one output end of the gate drive circuit is electrically connected to the detection unit through the detection line.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate motherboard and a preparation method thereof, an array substrate and a display device. Background Art

[0002] In recent years, display devices have developed in the direction of high integration and low cost. One of the important measures is the mass production of array substrate row driving technology (Gate Driver on Array, GOA). The array substrate row driving technology can integrate the gate driving circuit on the array substrate of the display device, thereby improving the integration of the display device and reducing the production cost, and can make the display device have a narrower border. Summary of the invention

[0003] The embodiments of the present invention provide an array substrate motherboard and a manufacturing method thereof, an array substrate and a display device, which can detect the gate driving circuit in the array substrate in advance and reduce the production cost.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0005] In one aspect, an array substrate motherboard is provided, comprising:

[0006] Substrate motherboard.

[0007] A plurality of display units are arranged on the substrate motherboard, and one display unit has a display area and a non-display area, wherein the non-display area at least partially surrounds the display area.

[0008] The display unit includes: a gate driving circuit, a detection line and a detection part arranged in the non-display area, and at least one output end of the gate driving circuit is electrically connected to the detection part through the detection line.

[0009] Optionally, the array substrate motherboard further includes: an insulating layer covering the gate driving circuit.

[0010] The detection line is located on a side of the insulating layer away from the substrate motherboard, and the detection line is electrically connected to at least one output terminal of the gate driving circuit through a first via hole on the insulating layer.

[0011] The detection part includes a first detection pattern, which is connected to the detection line and is provided in the same layer and material.

[0012] Optionally, the gate drive circuit includes a plurality of interconnected thin film transistors, and the detection unit also includes a second detection pattern, the second detection pattern is arranged in the same layer and material as the source and drain of the thin film transistor, and the first detection pattern is electrically connected to the second detection pattern through a second via hole on the insulating layer.

[0013] Optionally, the display unit further includes an anode layer located in the display area, the anode layer is used to form a plurality of anode patterns, and the anode layer, the detection line, and the first detection pattern are provided in the same layer and with the same material.

[0014] Optionally, the display unit includes two gate driving circuits, and the two gate driving circuits are located on opposite sides of the non-display area.

[0015] In another aspect, an array substrate is provided, comprising:

[0016] The substrate has a display area and a non-display area, wherein the non-display area at least partially surrounds the display area.

[0017] A gate driving circuit is disposed on one side of the substrate and located in the non-display area;

[0018] The insulating layer covers the gate driving circuit and is provided with a plurality of first via holes penetrating the insulating layer.

[0019] The detection part is arranged on one side of the substrate and located in the non-display area.

[0020] Optionally, the gate driving circuit includes a plurality of interconnected thin film transistors.

[0021] The detection portion includes a second detection pattern, and the second detection pattern is provided in the same layer and material as the source and drain of the thin film transistor.

[0022] A second via hole is disposed on the insulating layer at a position covering the second detection pattern.

[0023] Optionally, there are two gate driving circuits, which are respectively located on two opposite sides of the non-display area.

[0024] In yet another aspect, a display device is provided, comprising the array substrate as described above.

[0025] In another aspect, a method for preparing an array substrate motherboard is provided, comprising:

[0026] A plurality of display units are formed on the substrate mother board, and one display unit has a display area and a non-display area, wherein the non-display area at least partially surrounds the display area.

[0027] The display unit includes:

[0028] A gate driving circuit is formed in a non-display area of ​​the display unit on a substrate motherboard, and the gate driving circuit includes a plurality of interconnected thin film transistors; forming the gate driving circuit includes: forming a first conductive film on the substrate motherboard, and the first conductive film is used to form a source, a drain and a second detection pattern of the thin film transistor.

[0029] An insulating layer is formed on the substrate motherboard on which the gate driving circuit is formed. The insulating layer includes a first via hole located in a non-display area and covers the gate driving circuit.

[0030] A second conductive film is formed on the insulating layer, and a detection line and a first detection pattern are formed in the non-display area through a composition process; the first detection pattern, the second detection pattern, and a portion of the insulating layer located between the first detection pattern and the second detection pattern constitute a detection part.

[0031] Wherein, at least one output terminal of the gate driving circuit is electrically connected to the first detection pattern through the detection line.

[0032] Optionally, the second conductive film is also used to form an anode layer in a display area of ​​the display unit, and the anode layer is used to form a plurality of anode patterns.

[0033] Optionally, forming the detection line, the first detection pattern and the anode pattern by using the second conductive film includes:

[0034] A photoresist is coated on the second conductive film to form a photoresist layer; a half-exposure pattern and a full-exposure pattern are formed in the photoresist layer corresponding to an area where a detection line is to be formed in the second conductive film by mask exposure; an unexposed pattern and the half-exposure pattern are formed in an area corresponding to a first detection pattern to be formed; and the unexposed pattern and the half-exposure pattern are formed in an area corresponding to anode layer to be formed.

[0035] The full exposure pattern is removed by development to expose a portion of the second conductive film in the area where the detection line is to be formed; and a portion of the photoresist in the half exposure pattern is removed by development.

[0036] The portion of the area where the inspection line is to be formed and exposed by the full exposure pattern is removed through an etching process to form the inspection line.

[0037] The remaining part of the photoresist in the half-exposure pattern is removed by an ashing process to expose the detection line, a part of the first detection pattern, a part of the anode layer, and remove part of the photoresist in the full-exposure pattern.

[0038] The detection line, the exposed portion of the first detection pattern, and the exposed portion of the anode layer are removed by an etching process to form a plurality of anode patterns.

[0039] The present application provides an array substrate motherboard and a preparation method thereof, an array substrate and a display device. The array substrate motherboard includes a plurality of display units, and the display unit includes a gate drive circuit, a detection line and a detection unit arranged in a non-display area, so that the gate drive circuit can transmit the detection signal to the detection unit through the detection line, and then by electrically connecting the detection unit to an external instrument, the waveform of the actual output signal of the gate drive circuit can be obtained; finally, by comparing the actual output signal with the ideal output signal, it can be determined whether the working state of the gate drive circuit is normal. If there is an abnormality in the gate drive circuit, the abnormality can be discovered in time, and the subsequent process can be stopped to avoid wasting the process and manufacturing materials, thereby reducing the production cost. Therefore, compared with the related art, the present application can detect the gate drive circuit in advance, which is conducive to intercepting the abnormal gate drive circuit in advance, saving subsequent processes and materials, and reducing the production cost and the defective rate of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1a A schematic top view of an array substrate motherboard provided in an embodiment of the present application;

[0042] Figure 1b A schematic top view of an array substrate provided in an embodiment of the present application;

[0043] Figure 1c for Figure 1b Schematic cross-sectional view of AA′;

[0044] Figure 1d A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application;

[0045] Figure 1e A comparison diagram of an ideal output signal and an actual output signal of a gate drive circuit provided in an embodiment of the present application;

[0046] Figure 2a A schematic top view of another array substrate provided in an embodiment of the present application;

[0047] Figure 2b for Figure 2a Schematic cross-sectional view of BB′;

[0048] Figure 3a A schematic diagram of a process for preparing an array substrate motherboard provided in an embodiment of the present application;

[0049] Figure 3b-Figure 3c A schematic diagram of a manufacturing process of a display unit provided in an embodiment of the present application;

[0050] Figure 4a A schematic flow chart of a method for preparing a detection line, a first detection pattern and an anode pattern by using a second conductive film provided in an embodiment of the present application;

[0051] Figure 4b-4g A schematic diagram of a preparation process of preparing a detection line, a first detection pattern and an anode pattern by using a second conductive film is provided in an embodiment of the present application.

[0052] Reference numerals:

[0053] 1-array substrate motherboard; 10-substrate motherboard; 100-display unit; 101-display area; 102-non-display area; 103-substrate; 2-array substrate; 21-gate drive circuit; 210-shift register; 211-thin film transistor; 2110-active layer; 2111-gate insulating layer; 2112-gate metal layer; 2113-interlayer insulating layer; 2114-source and drain metal layers; 212-output end; 22-detection line; 23-detection unit; 231-first detection pattern; 232-second detection pattern; 24-insulating layer; 241-first via hole; 242-second via hole; 25-second conductive film; 251-anode layer; 2510-anode pattern; 26-photoresist layer; 261-full exposure pattern; 262-half exposure pattern; 263-unexposed pattern; 27-gate line. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] The present application provides a display device, which may be, for example, a liquid crystal display device (Liquid Crystal Display), an organic light-emitting diode display device (Organic Light-Emitting Diode, OLED), such as an OLED TV (television); the display device at least includes a display panel, and the display panel includes, for example, an array substrate and an opposing substrate. In some embodiments, the opposing substrate may be a color filter substrate, and the color filter substrate is used for light filtering.

[0056] The above array substrate can be obtained by cutting the display unit in the array substrate motherboard, and one display unit corresponds to one array substrate. Figure 1a As shown, the present application proposes an array substrate motherboard 1, comprising:

[0057] The substrate motherboard 10; the material of the substrate motherboard 10 is, for example, glass or polyimide (PI).

[0058] A plurality of display units 100 are disposed on the substrate mother board 10 . Each display unit 100 has a display area 101 and a non-display area 102 . The non-display area 102 at least partially surrounds the display area 101 .

[0059] For example, Figure 1a As shown, the non-display area 102 is, for example, arranged around the display area 101 .

[0060] Or, if Figure 1b As shown, the non-display area 102 is arranged around a portion of the display area 101 .

[0061] Among them, Figure 1b As shown, the display unit 100 includes: a gate driving circuit 21, a detection line 22 and a detection unit 23 arranged in the non-display area 102, and at least one output terminal 212 of the gate driving circuit 21 is electrically connected to the detection unit 23 through the detection line 22.

[0062] The output terminal 212 of the gate driving circuit 21 is also electrically connected to the gate line 27 , and the gate driving circuit 21 is used to transmit a gate driving signal to the gate line 27 .

[0063] For example, Figure 1dAs shown, the gate drive circuit 21 includes n cascaded shift registers 210, each shift register 210 includes, for example, an input signal terminal STVP, a reset signal terminal Rst, a first output signal terminal Out1 and a second output signal terminal Out2; wherein the input signal terminal STVP is used to receive and transmit an input signal stvp to the shift register 210, the reset signal terminal Rst is used to receive and transmit a reset signal to the shift register 210, the first output signal terminal Out1 is used to receive and transmit a gate drive signal to the gate line 27, and the second output signal terminal Out2 is used to receive and transmit a second output signal to the shift register 210.

[0064] In the plurality of cascaded shift registers 210 of the gate driving circuit 21 , the second output signal terminal Out2 of the first stage shift register N1 is electrically connected to the input signal terminal STVP of the second stage shift register N2 .

[0065] The nth stage shift register N n The second output signal terminal Out2 is connected to the n-1th stage shift register N n-1 The reset signal terminal Rst is electrically connected.

[0066] In addition to the first stage shift register N1 and the nth stage shift register N n In addition, the second output signal terminal Out2 of the remaining shift registers 210 is electrically connected to the reset signal terminal Rst of the previous stage shift register 210 and the input signal terminal STVP of the next stage shift register 210.

[0067] The first output signal terminal Out1 of each stage of the shift register 210 is used to be electrically connected to a gate line 27 to provide a gate driving signal for the gate line 27 . Therefore, the gate driving circuit 21 includes a plurality of output terminals 212 .

[0068] like Figure 1b As shown, there are multiple detection units 23, some of which are electrically connected to the input end of the gate drive circuit 21, and can provide detection signals for the gate drive circuit 21, and some of the detection units 23 are electrically connected to the detection line 22, and can receive signals transmitted from the detection line 22. By judging whether the signal received by the detection unit 23 is the same as the detection signal received at the input end of the gate drive circuit 21, it can be judged whether the gate drive circuit 21 can work normally.

[0069] It can be understood by those skilled in the art that the input signal stvp received by the input signal terminal STVP of the first shift register N1 is also a kind of detection signal, and the detection signal in the present application also includes a signal that can detect the gate drive circuit 21 in different regions, for example, a signal that can detect a certain unit in the shift register 210. The detection signal can be, for example, a current signal.

[0070] For example, Figure 1b As shown, a detection signal is input to the detection unit 23 electrically connected to the gate drive circuit 21, and the detection signal is transmitted to the gate drive circuit 21. Each stage of the shift register 210 in the gate drive circuit 21 is opened in turn, and a signal is output from the first output terminal Out1 to the detection line 22. The signal received by the detection unit 23 electrically connected to the detection line 22 is the actual output signal of the gate drive circuit 21.

[0071] The output terminal 212 of the gate drive circuit 21 is electrically connected to the detection unit 23 through the detection line 22, so that the detection unit 23 can receive the signal output by the gate drive circuit 21; and by electrically connecting the detection unit 23 to an external instrument such as an oscilloscope, the waveform of the signal output by the gate drive circuit 21 can be obtained. When inputting the detection signal to the gate drive circuit 21, different detection signals can be input according to different units in the shift register 210 to detect whether the same unit in each shift register 210 can work normally. The shift register 210 includes, for example, input units, pull-up units, pull-down units, reset units, and output units.

[0072] For example, a detection signal for detecting whether the pull-up unit can work normally is input to the gate driving circuit 21, and the detection signal is sequentially transmitted from the first stage shift register N1 to the nth stage shift register N n Then, according to the difference between the actual output signal and the ideal output signal of each stage of the shift register 210, it can be determined whether the pull-up unit in the corresponding shift register 210 can work normally.

[0073] It should be noted that when the detection signal is the input signal stvp when the gate drive circuit 21 is working normally, it can be used to detect the overall performance of the shift register 210. When the detection signal is a signal for detecting a certain unit in the gate drive circuit 21, it can realize regional detection of the gate drive circuit, that is, the working status of each unit in the shift register 210 can be detected in batches.

[0074] For example, Figure 1e As shown, after the first stage shift register N1 receives the detection signal, the ideal output signals outputted by each stage shift register 210 are, for example, N1 to N n The actual output signal detected by the detection unit 23 is, for example, N1′ to N n ', the number of actual output signals and the ideal output signals are the same and correspond one to one. In the case where there are two gate drive circuits 21, that is, two shift registers of the same level are electrically connected to the same gate line, if the actual output signals of the two first-stage shift registers N1 detected by the detection unit 23 are respectively N 11 ′ and N 12′, and N 11 ′ and N 12 ' is the same as the ideal output signal N1 of the first-stage shift register N1, so the working state of the first-stage shift register N1 is normal.

[0075] If the gate drive circuit 21 is abnormal, it will cause Mura (abnormal brightness area) to appear on the display panel during display, and even some areas cannot be displayed normally. In the related art, the gate drive circuit 21 is not tested after the array substrate 2 is prepared, but after the display panel is prepared. At this time, if the gate drive circuit 21 is abnormal, many processes in the display panel preparation process (such as the preparation process of the light-emitting layer, the preparation process of the color film substrate, etc.) will be wasted, resulting in high production costs and a high defect rate of the display panel.

[0076] The present application provides an array substrate motherboard 1, including a plurality of display units 100, the display unit 100 includes a gate drive circuit 21, a detection line 22 and a detection unit 23 arranged in a non-display area 102, so that the gate drive circuit 21 can transmit the detection signal to the detection unit 23 through the detection line 22, and then by electrically connecting the detection unit 23 to an external instrument, the waveform of the actual output signal of the gate drive circuit 21 can be obtained; finally, by comparing the actual output signal with the ideal output signal, it can be determined whether the working state of the gate drive circuit 21 is normal. If there is an abnormality in the gate drive circuit 21, the abnormality can be discovered in time, and the subsequent process can be stopped to avoid wasting the process and manufacturing materials, thereby reducing the production cost. Therefore, compared with the related art, the present application can detect the gate drive circuit 21 in advance, which is conducive to intercepting the abnormal gate drive circuit 21 in advance, saving subsequent processes and materials, and reducing the production cost and the defective rate of the display panel.

[0077] Optional, such as Figure 1c As shown, the array substrate motherboard 1 also includes: an insulating layer 24 covering the gate drive circuit 21. The insulating layer 24 plays a protective and flat role, protecting the gate drive circuit 21 located thereunder and providing a relatively flat surface for the film layer prepared subsequently. For example, the insulating layer 24 can be a flat layer or a passivation layer; the material of the flat layer is, for example, organic matter, and the material of the passivation layer is, for example, at least one of silicon oxide and silicon nitride.

[0078] The detection line 22 is located on a side of the insulating layer 24 away from the substrate motherboard 10, and the detection line 22 is electrically connected to at least one output terminal 212 of the gate drive circuit 21 through a first via hole 241 on the insulating layer 24. The detection line 22 is electrically connected to the gate drive circuit 21 through the first via hole 241, and the first via hole 241 is filled with the material used to make the detection line 22.

[0079] The detection part 23 includes a first detection pattern 231, which is connected to the detection line 22 and is provided in the same layer and the same material. That is, the first detection pattern 231 and the detection line 22 are based on the same film and are prepared by the same composition process. For example, the material of the detection line 22 and the first detection pattern 231 is ITO (Indium tin oxide).

[0080] The detection line 22 and the first detection pattern 231 are provided in the same layer and the same material, the manufacturing process is simple, and the connection between the detection line 22 and the first detection pattern 231 is more stable. The detection line 22 and the first detection pattern 231 are both located on the insulating layer 24, which can avoid the influence of the etching process performed when manufacturing the detection line 22 and the first detection pattern 231 on the gate driving circuit 21 located under the insulating layer 24.

[0081] Optional, such as Figure 1c As shown, the gate driving circuit 21 includes a plurality of interconnected thin film transistors 211, and the detection unit 23 also includes a second detection pattern 232, the second detection pattern 232 is arranged in the same layer and material as the source and drain of the thin film transistor 211, and the first detection pattern 231 is electrically connected to the second detection pattern 232 through a second via 242 on the insulating layer 24.

[0082] like Figure 1c As shown, along the side direction away from the substrate 103, the thin film transistor 211 includes: an active layer 2110, a gate insulating layer 2111, a gate metal layer 2112, an interlayer insulating layer 2113, and a source and drain metal layer 2114 in sequence; wherein the source and drain metal layer 2114 includes a source and a drain, and the source and the drain are in contact with the active layer 2110 through a via hole penetrating the interlayer insulating layer 2113 and the gate insulating layer 2111. In the gate driving circuit 21, the drains of some thin film transistors 211 serve as the output terminal 212 of the shift register 210, that is, as the output terminal 212 of the gate driving circuit 21.

[0083] The detection unit 23 also includes a second detection pattern 232, which is arranged in the same layer and material as the source and drain of the thin film transistor 211, that is, the second detection pattern 232 and the source and drain metal layer 2114 are based on the same conductive film and are formed by the same patterning process. For example, the material of the second detection pattern 232 is a conductive metal such as silver or aluminum.

[0084] The first sensing pattern 231 is electrically connected to the second sensing pattern 232 through the second via hole 242 on the insulating layer 24. In some embodiments, the second via hole 242 and the first via hole 241 are prepared at the same time, and the sizes of the second via hole 242 and the first via hole 241 are the same.

[0085] The detection unit 23 includes a first detection pattern 231 and a second detection pattern 232 , and the first detection pattern 231 and the second detection pattern 232 are connected in parallel, so that the resistance of the detection unit 23 can be reduced and the strength and accuracy of the actual output signal obtained at the detection unit 23 can be improved.

[0086] like Figure 1c As shown, when the detection signal is received by the detection unit 23, the gate line 27 electrically connected to the output terminal 212 of the gate drive circuit 21 can also receive the detection signal, but because the gate line 27 is located at the lower side of the source and the output terminal 212, the gate drive circuit 21 cannot be detected through the gate line 27. The present application realizes the detection of the gate drive circuit 21 by setting the detection line 22 and the first detection pattern 231, and the structure is simple.

[0087] Optional, reference Figure 1c Combination Figure 1b As shown, the display unit 100 further includes an anode layer 251 located in the display area 101 . The anode layer 251 is used to form a plurality of anode patterns. The anode layer 251 , the detection line 22 , and the first detection pattern 231 are provided in the same layer and with the same material.

[0088] exist Figure 1c In the embodiment, the anode layer 251 is used to form a plurality of anode patterns, and the anode layer 251 covers the display area 101 in its entirety, and has not yet been fabricated into a plurality of anode patterns disposed at intervals. An anode pattern fabricated subsequently is electrically connected to the drain of a thin film transistor 211 in a sub-pixel located in the display area 101. The anode pattern is electrically connected to the drain of the thin film transistor 211 through a via hole penetrating the insulating layer 24, and the via hole may be, for example, a first via hole 241.

[0089] The anode layer 251, the detection line 22, and the first detection pattern 231 are of the same layer and the same material, so the anode layer 251, the detection line 22, and the first detection pattern 231 are based on the same thin film and are prepared by the same composition process, and the preparation process is simple. At the same time, when making the anode pattern 2510, the detection line 22 and the first detection pattern 231 can be made by the same mask plate, and the detection line 22 and the first detection pattern 231 for detection can be made without adding a mask plate. That is to say, the present application can detect the gate drive signal in the process of making the anode pattern 2510 without increasing the cost, and the preparation method and the detection method are simple, which can effectively screen out abnormal gate drive circuits 21 in advance, reduce production costs, and facilitate the analysis of abnormal gate drive circuits 21.

[0090] Optional, such as Figure 1b As shown, the display unit 100 includes two gate driving circuits 21 , and the two gate driving circuits 21 are located at opposite sides of the non-display area 102 .

[0091] The gate driving circuit 21 is located in the non-display area 102. Figure 1b As shown, the gate driving circuit 21 is also symmetrical along the center line of the display area 101 .

[0092] The two gate driving circuits 21 include an equal number of shift registers 210 , and the two shift registers 210 at the same level are electrically connected to two ends of the same gate line 27 .

[0093] By providing gate driving signals to the gate lines 27 through two gate driving circuits 21 , attenuation of the gate driving signals can be reduced, the strength of the gate driving signals can be guaranteed, and the accuracy of the gate lines 27 controlling the thin film transistors 211 can be improved.

[0094] Based on the above, if Figure 2a and Figure 2b As shown, the present application provides an array substrate 2 , which includes: a substrate 103 , the substrate 103 having a display area 101 and a non-display area 102 , and the non-display area 102 at least partially surrounds the display area 101 .

[0095] The gate driving circuit 21 is disposed on one side of the substrate 103 and located in the non-display area 102 . The output terminal 212 of the gate driving circuit 21 is electrically connected to the gate line 27 .

[0096] The insulating layer 24 covers the gate driving circuit 21 and is provided with a plurality of first via holes 241 penetrating the insulating layer 24 .

[0097] For example, Figure 2b As shown, the first via hole 241 is located at the intersection of the output terminal 212 of the gate driving circuit 21 and the gate line 27 , and the first via hole 241 is not filled with the same material as the anode layer 251 in the display area 101 , while the output terminal 212 of the gate driving circuit 21 is electrically connected to the gate 27 .

[0098] It should be noted that the position of the first via 241 is not limited to the intersection of the output terminal 212 of the gate driving circuit 21 and the gate line 27 , as long as the orthographic projection of the output terminal 212 of the gate driving circuit 21 on the substrate 103 covers the orthographic projection of the first via 241 .

[0099] The detection part 23 is disposed on one side of the substrate 103 and located in the non-display area 102 . There are a plurality of detection parts 23 , and some of the detection parts 23 are electrically connected to the input end of the gate driving circuit 21 .

[0100] During the preparation of the array substrate 2 , the gate driving circuit 21 can be tested. Therefore, the array substrate 2 has the same beneficial effects as the above-mentioned array substrate motherboard 1 , and thus will not be described in detail.

[0101] Optional, such as Figure 2b As shown, the gate driving circuit 21 includes a plurality of interconnected thin film transistors 211. The drain of the thin film transistor 211 is electrically connected to the gate line 27 to provide the gate line 27 with a gate driving signal.

[0102] The detection portion 23 further includes a second detection pattern 232 . The second detection pattern 232 is provided in the same layer and material as the source and drain of the thin film transistor 211 .

[0103] A second via hole 242 is disposed on the insulating layer 24 at a position covering the second sensing pattern 232 . There is at least one second via hole 242 , and the second via hole 242 whose upper side is not covered with the first sensing pattern 231 is not filled with the material of the anode layer 251 .

[0104] like Figure 2b As described above, the first detection pattern 231 covers a portion of the insulating layer 24 , and the first detection pattern can be used to detect the thin film transistor 211 located in the display area 101 of the array substrate 2 .

[0105] A plurality of anode patterns 2510 are also provided in the display area 101 of the substrate. Each anode pattern 2510 is electrically connected to a thin film transistor 211 located in the display area 101. The thin film transistor 211 in the display area 101 is used to form a pixel driving circuit, which is electrically connected to the gate line 27 and the data line.

[0106] The second detection pattern 232 is connected in parallel with the first detection pattern 231 in the detection portion 23 to reduce the resistance of the detection portion 23 .

[0107] Optional, such as Figure 2a As shown, there are two gate driving circuits 21 , which are respectively located at two opposite sides of the non-display area 102 .

[0108] The shift registers 210 at the same level in the gate driving circuit 21 are electrically connected to the same gate line 27 , which is beneficial to reducing the attenuation of the gate driving signal.

[0109] like Figure 3a As shown, the present application also provides a method for preparing an array substrate motherboard 1, comprising:

[0110] S1. A plurality of display units 100 are formed on a substrate motherboard 10. One display unit 100 has a display area 101 and a non-display area 102. The non-display area 102 at least partially surrounds the display area 101.

[0111] The same film layers in a plurality of display units 100 are formed simultaneously.

[0112] S2, such as Figure 3bAs shown, forming the display unit 100 includes: forming a gate driving circuit 21 in the non-display area 102 of the display unit 100 on the substrate motherboard 10, and the gate driving circuit 21 includes a plurality of interconnected thin film transistors 211; forming the gate driving circuit 21 includes: forming a first conductive film on the substrate motherboard 10, and the first conductive film is used to form the source, drain and second detection pattern 232 of the thin film transistor 211.

[0113] The drain of the thin film transistor 211 can directly serve as the output terminal 212 of the gate driving circuit 21, or the drain of the thin film transistor 211 can be electrically connected to the output terminal 212 of the gate driving circuit 21, and the output terminal 212 of the gate driving circuit 21 and the drain of the thin film transistor 211 are arranged in the same layer and material.

[0114] S3, such as Figure 3c As shown, an insulating layer 24 is formed on the substrate motherboard 10 on which the gate driving circuit 21 is formed. The insulating layer 24 includes a first via hole 241 located in the non-display area 102 and covers the gate driving circuit 21 .

[0115] In some embodiments, the insulating layer 24 further includes at least one second via hole 242 located on an upper side of the second sensing pattern 232 .

[0116] It should be noted that in Figure 3b and Figure 3c Although the entire substrate motherboard 10 is not illustrated, but the substrate 103 is illustrated, those skilled in the art can understand that the part of the substrate motherboard 10 corresponding to each display unit 100 is the substrate 103.

[0117] S4, such as Figure 1c As shown, a second conductive film 25 is formed on the insulating layer 24, and a detection line 22 and a first detection pattern 231 are formed in the non-display area 102 through a composition process; the first detection pattern 231, the second detection pattern 232, and a portion of the insulating layer 24 located between the first detection pattern 231 and the second detection pattern 232 constitute the detection part 23.

[0118] For example, the second conductive film 25 is an ITO film.

[0119] At least one output terminal 212 of the gate driving circuit 21 is electrically connected to the first detection pattern 231 through the detection line 22 , that is, at least one output terminal 212 of the gate driving circuit 21 is electrically connected to the detection unit 23 through the detection line 22 .

[0120] Those skilled in the art should understand that in the process of manufacturing the array substrate motherboard 1, when manufacturing thin films corresponding to the active layer 2110, the gate insulating layer 2111, the gate metal layer 2112, the interlayer insulating layer 2113, the source and drain metal layer 2114, the insulating layer 24 and the like, the thin film will cover the display unit 100 in its entirety. For example, the first conductive film used to form the source and drain metal layer 2114 will cover the display unit 100 in its entirety, and then the required pattern will be manufactured in the corresponding area through a patterning process. Therefore, in some embodiments, the detection unit 23 further includes the interlayer insulating layer 2113, the gate metal layer 2112, the gate insulating layer 2111 and the active layer 2110 located on the side of the second detection pattern 232 close to the substrate.

[0121] The method for preparing the array substrate motherboard 1 has the same beneficial effects as the array substrate motherboard 1 , and thus will not be described in detail.

[0122] Optional, such as Figure 2a As shown, the second conductive film 25 is also used to form an anode layer 251 located in the display area 101 of the display unit 100 , and the anode layer 251 is used to form a plurality of anode patterns 2510 .

[0123] Then, the second conductive film 25 can be used to form the detection line 22 , the first detection pattern 231 and the anode pattern 2510 , which can be formed by the same half-tone mask and the same patterning process, without increasing the preparation cost of the array substrate motherboard 1 .

[0124] Based on the above, if Figure 4a As shown, forming the detection line 22, the first detection pattern 231 and the anode pattern 2510 by the second conductive film 25 includes:

[0125] S10, such as Figure 4b As shown, a photoresist is coated on the second conductive film 25 to form a photoresist layer 26 .

[0126] Illustratively, the photoresist in the photoresist layer 26 is a positive photoresist.

[0127] like Figure 4c As shown, through mask exposure, a half-exposure pattern 262 and a full-exposure pattern 261 are formed in the photoresist layer 26 corresponding to the area A1 where the detection line is to be formed in the second conductive film 25; an unexposed pattern 263 and a half-exposure pattern 262 are formed in the area A2 corresponding to where the first detection pattern is to be formed; and an unexposed pattern 263 and a half-exposure pattern 262 are formed in the area A3 corresponding to where the anode layer is to be formed.

[0128] The photoresist layer 26 is subjected to mask exposure using a half-tone mask to form a full-exposure pattern 261 , a half-exposure pattern 262 , and an unexposed pattern 263 .

[0129] The exposure depths of the photoresist layer 26 in the half-exposure pattern 262 and the full-exposure pattern 261 are different. For example, the exposure depth of the half-exposure pattern 262 is half of the exposure depth of the full-exposure pattern 261 .

[0130] S11, such as Figure 4d As shown, the full exposure pattern 261 is removed by development to expose a portion of the area A1 of the second conductive film 25 where the detection line is to be formed; and part of the photoresist in the half exposure pattern 262 is removed by development.

[0131] When the photoresist layer 26 is developed, the fully exposed pattern 261 is completely removed, and part of the photoresist in the half-exposed pattern 262 (the exposed part) is removed, for example, half of the photoresist in the half-exposed pattern 262 along the thickness direction is removed, and all the photoresist in the unexposed pattern 263 is retained.

[0132] S12, such as Figure 4e As shown, the portion of the area A1 where the inspection line is to be formed and exposed by the full exposure pattern 261 is removed through an etching process to form the inspection line 22 .

[0133] However, at this time, the detection line 22 is still covered with the remaining part of the photoresist of the half-exposure pattern 262 .

[0134] S13, such as Figure 4f As shown, the remaining portion of the photoresist in the half-exposure pattern 262 is removed by an ashing process to expose the inspection line 22 , a portion of the first inspection pattern 231 , a portion of the anode layer 251 , and remove a portion of the photoresist in the full-exposure pattern 261 .

[0135] The photoresist covering the detection line 22 , the photoresist on the first detection pattern 231 corresponding to the half-exposure pattern 262 , and the photoresist on the anode layer 251 corresponding to the half-exposure pattern 262 may be removed by the ashing process.

[0136] S14, such as Figure 4g As shown, the detection line 22 is removed, the exposed portion of the first detection pattern 231 is removed, and the exposed portion of the anode layer 251 is removed through an etching process to form a plurality of anode patterns 2510 .

[0137] like Figure 4g As shown, the first detection pattern 231 still has a remaining part, which is used for subsequent detection of other structures of the array substrate 2, such as detecting the performance of the thin film transistor 211 located in the display area 101. The detection line 22 has been completely etched, so that the output end 212 of the gate drive circuit 21 is only electrically connected to the gate line 27, and the structure is simple.

[0138] The above-mentioned mask exposure, development, ashing and etching all belong to the same patterning process.

[0139] After forming the first sensing pattern 231 and the anode pattern 2510 , the remaining photoresist on the first sensing pattern 231 and the anode pattern 2510 may be removed by ashing.

[0140] The detection line 22, the first detection pattern 231 and the anode pattern 2510 are formed by the second conductive film 25, and only one half-tone mask plate is needed. Therefore, the present application can realize the detection of the gate drive circuit 21 without increasing the number of mask plates, which is beneficial to reducing production costs and the defective rate of the display panel; at the same time, after the detection of the gate drive circuit 21 is completed, the detection line 22 will be etched away, which is also beneficial to simplify the structure of the array substrate 1.

[0141] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for preparing an array substrate motherboard, characterized in that: include: A plurality of display units are formed on the substrate motherboard, wherein one display unit has a display area and a non-display area, and the non-display area at least partially surrounds the display area; The display unit includes: A gate driving circuit is formed in a non-display area of ​​the display unit on a substrate motherboard, wherein the gate driving circuit includes a plurality of interconnected thin film transistors; forming the gate driving circuit includes: forming a first conductive film on the substrate motherboard, wherein the first conductive film is used to form a source electrode, a drain electrode, and a second detection pattern of the thin film transistor; An insulating layer is formed on the substrate motherboard on which the gate driving circuit is formed, wherein the insulating layer includes a first via hole located in the non-display area and covers the gate driving circuit; A second conductive film is formed on the insulating layer, and a detection line and a first detection pattern are formed in the non-display area through a patterning process; the first detection pattern, the second detection pattern, and a portion of the insulating layer between the first detection pattern and the second detection pattern constitute a detection portion; Wherein, at least one output end of the gate driving circuit is electrically connected to the first detection pattern through the detection line, the output end of the gate driving circuit is used to be electrically connected to the gate line, and the gate driving circuit is used to transmit a gate driving signal to the gate line; There are multiple detection parts, some of which are electrically connected to the input end of the gate driving circuit and are configured to: provide a detection signal to the gate driving circuit; some of which are electrically connected to the detection line and are configured to: receive a signal transmitted from the detection line; The second conductive film is also used to form an anode layer in a display area of ​​the display unit, and the anode layer is used to form a plurality of anode patterns; Forming the detection line, the first detection pattern and the anode pattern by using the second conductive film includes: Coating a photoresist on the second conductive film to form a photoresist layer; exposing through a mask to form a half-exposure pattern and a full-exposure pattern in the photoresist layer corresponding to a region where a detection line is to be formed in the second conductive film; forming an unexposed pattern and the half-exposure pattern in a region where a first detection pattern is to be formed; and forming the unexposed pattern and the half-exposure pattern in a region where an anode layer is to be formed; Removing the full exposure pattern by developing to expose a portion of the second conductive film in the area where the detection line is to be formed; removing a portion of the photoresist in the half exposure pattern by developing; By means of an etching process, a portion of the area where the detection line is to be formed and exposed by the full exposure pattern is removed to form the detection line; Removing a portion of the photoresist remaining in the half-exposure pattern through an ashing process to expose the detection line, a portion of the first detection pattern, a portion of the anode layer, and removing a portion of the photoresist in the full-exposure pattern; The detection line, the exposed portion of the first detection pattern, and the exposed portion of the anode layer are removed by an etching process to form a plurality of anode patterns.

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