Real-time jitter impairment insertion of signal sources

Abstract

The present disclosure relates to systems and methods for synthesizing waveforms with jitter and other timing-related impairments in a test and measurement instrument. A test and measurement device having a signal source includes a waveform synthesizer and an impairment generator configured to output impairments. The waveform synthesizer receives an input digital signal to be synthesized, receives impairments, and synthesizes a synthesized digital signal based on the input digital signal and the impairments. The test and measurement instrument also includes a fixed sampling rate digital-to-analog converter configured to receive a clock signal and the synthesized digital signal and output an analog signal.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 787,210, filed on December 31, 2018, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to systems and methods for synthesizing waveforms with jitter and other timing-related impairments in test and measurement instruments. Background Art

[0004] Many communications standards outline a series of stress test scenarios to determine whether the device under test (DUT) passes all performance tests with specified compliance margins. Test and measurement instruments with signal sources, such as arbitrary waveform or function generators and bit error rate testers (BERTs), can be used to generate waveforms for stress testing to measure the performance margin of the DUT in response to the received signals.

[0005] Communications standards may require that jitter impairments be added to the desired data waveform, and the jitter impairments appear in many forms, including but not limited to random, bounded / unbounded, sinusoidal, high / low frequency jitter, clock drift, etc. In view of this, test and measurement instruments with signal sources should have the ability to insert jitter impairments with properties specified by a given communications standard. However, conventional test and measurement instruments typically do not have a large enough baud rate range and / or flexible enough impairment generation capabilities to effectively cover multiple standards.

[0006] Embodiments of the present disclosure address these and other deficiencies of the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects, features, and advantages of embodiments of the present disclosure will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of a test and measurement instrument with a waveform synthesizer according to some embodiments of the present disclosure;

[0009] Figure 2 is a block diagram of an example of a waveform synthesizer according to some embodiments of the present disclosure;

[0010] Figure 3 is a block diagram of an example of a waveform synthesizer according to some embodiments of the present disclosure;

[0011] Figure 4 is a block diagram of a test and measurement instrument according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure may add impairments such as nonlinearity, jitter, noise, crosstalk, inter-symbol interference (ISI), channel frequency response, etc. to a desired data waveform to be synthesized to determine the margin required for a receiver DUT to correctly record the desired data waveform with an acceptable bit error rate (BER) based on the impaired data waveform. As will be discussed in more detail below, embodiments of the present disclosure may add impairments such as jitter or spread spectrum clocking to the desired data waveform using digital signal processing (DSP) or analog components by real-time modulating the signal source DAC sampling clock.

[0013] The embodiments disclosed herein may be implemented in real-time DSP hardware such as a field programmable gate array (FPGA) or application specific integrated circuit (ASIC) or by pre-calculation if the replication / interpolation of the waveform is done in advance and loaded into a waveform pattern memory in a signal source used to generate a real-time output waveform at the DAC sampling rate.

[0014] Figure 1 1 is a block diagram of a test and measurement instrument 100 having a waveform synthesizer according to some embodiments of the present disclosure. An input waveform 102 (x[n]) is a digital representation of the symbol value of the desired output waveform to be generated. The input waveform 102 (x[n]) may be a waveform at the baud rate (F s，符号 ) is sampled. The input waveform 102 may be received at the waveform synthesizer 104, which may be sampled according to the sampling rate (F s，DAC ) synthesized waveform y[m].

[0015] The synthesized waveform y[m] is received at the DAC 106 and converted to an analog signal. The DAC 106 may also receive a reference clock 108 from another component of the test and measurement instrument. In some embodiments, after the synthesized waveform is converted to an analog signal by the DAC 106, the analog waveform may be filtered by an analog low pass filter, which may be used to remove signal content above the first Nyquist zone of the DAC 106 output. This may remove the zero-order hold effect of conventional DACs in higher Nyquist zones, which causes the waveform spectrum in the first Nyquist zone to be spread across higher Nyquist zones. The simulated waveform can be output to a port which can be connected to the device under test via a cable.

[0016] The DAC 106 sampling rate (F s，DAC ) is the waveform baud rate (F s，符号), the analog low pass filter can be removed or bypassed and the output from the DAC 106 can be sent directly to the port because the zero-order hold response of the DAC 106 is consistent with the waveform being synthesized and can enhance the desired symbol transitions in the output waveform for waveform signaling methods in which the symbol value remains constant across the entire symbol period, such as non-return-to-zero (NRZ) methods and pulse amplitude modulation (PAM) methods.

[0017] The impairment 114 added to the synthesized waveform y[m] can be sent to the waveform synthesizer 104 before being sent to the DAC 106. As mentioned above, the impairment 114 can be used to test the DUT connected to the port. That is, the DUT receives the impaired waveform and can be tested to determine whether the DUT properly recovers the expected data waveform (x[n]). As will be discussed in more detail below, the impairment 114 can be jitter, spread spectrum clock (SSC) impairment, and / or other timing or phase impairments. The impairment 114 can come from an impairment generator 116, which can be a memory that stores multiple different impairments required by the test standard, or a processor that can generate impairments based on the test standard stored in the memory or the impairments received from the user input.

[0018] In some embodiments, lesion generator 116 may receive an input signal provided by a user (not shown). Lesion generator 116 may use the input signal to generate lesions 114. In some embodiments, lesions 114 are received input signals, while in other embodiments, lesions 114 are generated using the input signals.

[0019] The waveform synthesizer 104 can synthesize the waveform in a number of different ways, including but not limited to: fractional replication and linear edge interpolation, fractional replication and edge zero insertion, fractional replication with data sample replication to a high oversampling rate followed by a fractional decimation filter, fractional replication with a pre-computed lookup table for edge value interpolation, etc.

[0020] Using a direct linear interpolation method as an example, the DAC input sample y[m] can be calculated from the input waveform 102 (x[n]) using equations (1), (2), and (3):

[0021]

[0022]

[0023]

[0024] in, That is, r is the ratio of the DAC 106 output sample rate to the input waveform 102 baud rate. According to the above equation, The value of will change dynamically for each DAC 106 sampling cycle to achieve the waveform baud rate (F s，符号 ) and the DAC 106 output sampling rate (F s，DAC ). Thus, for the transition between successive x[n] and x[n+1] input symbols, the variable will reflect the placement of symbol edge transitions with sub-sampling resolution relative to the DAC 106 output sampling rate. Edges in waveform y[m] occur only when x[n+1] is not equal to x[n]. A change in the value of from its nominal value calculated in equation (2) will translate into shifting edge transitions earlier or later in time relative to the nominally resampled output data waveform. This modulation of the edge position in the output waveform is equivalent to phase modulation or jitter insertion, which is effective in the case of The equation (4) is shown as:

[0025]

[0026] in corresponds to the amount of jitter phase modulation for a given symbol transition, and corresponds to the phase modulation for a given symbol transition used to simulate the spread spectrum clock (SSC) in the output waveform. Other timing and phase impairments can be added to equation (4) in a similar manner.

[0027] Phase modulation due to jitter, SSC, and / or other timing or phase impairments may cause the symbol transition edges to move to different DAC 106 output sampling periods relative to the sampling period in which the transitions normally occurred before the phase modulation was added. Thus, it may be beneficial to correct the output symbol transition positions, as shown in equations (5) and (6):

[0028]

[0029]

[0030] in, Determine an integer input sample index correction value to adjust the input samples 102 used in the linear interpolation process to account for jitter, SSC, and / or other phase modulation caused by the input samples 102. The cases where is less than zero or greater than or equal to 1, ie, wrap between consecutive input sampling periods.

[0031] The equation of the resulting waveform y[m] with input sample index correction is shown in equation (7):

[0032]

[0033] Figure 2 Another example embodiment for modifying the synthesized waveform y[m] with jitter, SSC, and / or other timing or phase impairments is illustrated. The waveform synthesizer 202 may include, for example, a waveform symbol clock generator 204 and a waveform synthesis interpolator 206. The waveform symbol clock generator 204 also receives impairments 114 and a DAC reference clock 108 from another component of the test and measurement instrument 100. The impairments may come from, for example, the impairment generator 116.

[0034] The waveform symbol clock generator 204 outputs the symbol transition event and the symbol transition sub-sampling phase to the waveform synthesis interpolator 206, which also receives the input signal 102 (x[n]). The waveform synthesis edge interpolator 206 outputs a digital signal (y[m]) to be converted into an analog signal by the DAC 106. Similar to Figure 1 , Figure 2 Embodiments may also include an analog filter to filter the analog signal before the analog signal is output to the port.

[0035] The waveform symbol clock generator 204 outputs a symbol transition event and a symbol transition sub-sampling phase based on the DAC reference clock 108 and the impairment 114. That is, the symbol transition event and the symbol transition sub-sampling phase can be modified based on the impairment 114. The waveform synthesis interpolator 206 can convert the input waveform 102 (x[n]) at the baud rate into an output waveform (y[m]) at the DAC 106 sampling rate by using DSP fractional interpolation and / or replication operations. The symbol transition time phase modulation can include both integer and fractional sampling period phase modulation components relative to the DAC 106 sampling period. Therefore, the phase modulation range can be expanded by multiple DAC 106 sampling periods relative to the normal symbol transition time before applying jitter, SSC and / or other timing or phase impairments.

[0036] Figure 1 and Figure 2 Embodiments advance or delay the transition timing between symbol values ​​in the baud rate input waveform to apply phase modulation by manipulating the output waveform y[m] values ​​through the DSP. On the other hand, Figure 3 is an example embodiment of a simulation operation for inserting impairments into a generated waveform.

[0037] Similar to Figure 1 and Figure 2, the input waveform 102 is received at the waveform synthesizer 302 and output to the DAC 106. The output of the DAC 106 may be further filtered through an analog filter before being output to a port, which may be connected to a device under test.

[0038] The waveform synthesizer 302 includes a waveform generator 304 that can generate an output waveform y[m] at the sampling rate of the DAC 106 using any of the operations discussed above, such as, but not limited to: fractional replication and linear edge interpolation, fractional replication and edge zero insertion, fractional replication with data sample replication to a high oversampling rate followed by a fractional or integer decimation filter, fractional replication with a pre-computed lookup table for edge value interpolation, etc.

[0039] The waveform synthesizer 302 receives impairments 114 from an impairment generator 306, which in this example embodiment outputs a digital codeword that specifies the amount of phase modulation of jitter, SSC, and / or other timing or phase impairments to be inserted for a given output sample. The digital codeword may, for example, come from jitter, SSC, and / or other timing or phase impairment generation operations that create jitter, SSC, and / or other timing or phase impairments of the type indicated by the desired test. For example, if the user wants to perform a sinusoidal jitter tolerance test, the impairment generator 306 may be a numerically controlled oscillator (NCO). As mentioned above, in some embodiments, the memory may store multiple different types of jitter or SSC required for different tests, and the impairment generator 306 may generate these codewords based on the test type selected by the user. In other embodiments, the user may input a specific type of impairment to be used through a user interface of the test and measurement instrument, and the impairment generator 306 outputs a digital codeword based on that information. The codeword output by the impairment generator 306 may be updated for each symbol period of the input waveform 102.

[0040] The digital codeword is sent to an analog phase adjuster 308, which may be, for example, a phase interpolator (PI) or an analog delay line (ADL). Figure 3304 receives the output from the analog phase adjuster 308 and the waveform generator 304. The buffer 310 allows the waveform generator 304 to run at a fixed clock rate. The buffer 310 can also handle situations where the phase modulation wraps around between successive sampling periods, because jitter, SSC, and / or other timing or phase impairments of the phase modulation can cause a scenario where the next input sample value maps to the DAC 106 symbol value one sampling period earlier or later than would otherwise occur without the addition of the phase modulation. The output from the analog phase adjuster 308 is also sent to the DAC 106 as a jittered clock signal, rather than as in Figure 1 and Figure 2 A fixed rate reference clock signal is received as shown in .

[0041] When the buffer 310 is close to being full, flow control may be used to throttle the input data to the buffer 310 and delay the start of the output waveform generation by the DAC 106 until the buffer 310 has accumulated enough valid samples for a buffer to accommodate dynamic changes in the sampling period in the DAC 106. Throttling the input data to the buffer 310 may accommodate dynamic changes in the DAC 106 output sampling rate for situations where it is desirable to implement the digital feed path 312 feeding the DAC 106 with a fixed rate clock rather than a continuously varying clock rate that changes synchronously with the phase modulated DAC 106 effective output sampling rate. In such a situation, the digital data path 312 feeding the buffer 310 may run faster than the highest possible instantaneous DAC 106 output sampling rate.

[0042] If a phase interpolator is used for the analog phase adjuster 308, the analog phase adjuster 308 can rotate within a range (relative to the DAC 106) up to one output sampling period without rollover glitches. If an analog delay line is used for the analog phase adjuster 308, the full output sampling period range can also be supported, but this will be done using a series of analog delay elements, i.e., inverter chains, passive delay lines, etc.

[0043] Figure 4 An example test and measurement instrument 400 is illustrated having a waveform synthesizer 402 and a DAC 106. The waveform synthesizer 402 may be any of the waveform synthesizers 104, 202, and 302 discussed above. The test and measurement instrument 400 may be, for example, an arbitrary waveform generator, an arbitrary function generator, a bit error rate tester (BERT), or any test and measurement instrument that outputs a signal source.

[0044] The test and measurement instrument 400 includes one or more ports 404, which may be any electrical signaling medium or optical signaling medium. The ports 404 may include receivers, transmitters, and / or transceivers and potentially electrical-to-optical and / or optical-to-electrical converters. The ports 404 are coupled to the waveform synthesizer 402 via the DAC 106. The waveform synthesizer 402 is connected to one or more processors 406. Although for ease of illustration, Figure 4 Only one processor 406 is shown in FIG. 4 , but as will be appreciated by those skilled in the art, multiple processors 406 of different types may also be used in combination rather than using a single processor 406. In some embodiments, the waveform synthesizer 402 may be part of one or more processors 406.

[0045] One or more processors 406 may be configured to execute instructions from memory 408, and may execute any method and / or associated steps indicated by such instructions. Memory 408 may be implemented as a processor cache, random access memory (RAM), read-only memory (ROM), solid-state memory, (multiple) hard disk drives, or any other memory type. Memory 408 serves as a medium for storing data, computer program products, and other instructions. For example, one or more processors 406 may output a digital signal to waveform synthesizer 402, such as described above, and the digital signal is to be output as an analog signal, which is output to the device under test through port 404.

[0046] A user input 410 is coupled to the one or more processors 406. The user input 410 may include a keyboard, a mouse, a trackball, a touch screen, and / or any other controls that may be utilized by a user for use with a GUI on a display 412. The display 412 may be a digital screen, a cathode ray tube-based display, or any other monitor that displays waveforms, measurements, and other data to a user. Although the components of the test instrument 400 are depicted as being integrated within the test and measurement instrument 400, it will be appreciated by those of ordinary skill in the art that any of these components may be external to the test instrument 400 and may be coupled to the test instrument 400 in any conventional manner (e.g., wired and / or wireless communication media and / or mechanisms). For example, in some embodiments, the display 412 may be remote from the test and measurement instrument 400.

[0047] Aspects of the present disclosure may operate on specially created hardware, firmware, digital signal processors, or on specially programmed computers including processors that operate according to programming instructions. The terms "controller" or "processor" as used herein are intended to include microprocessors, microcomputers, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and dedicated hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions, such as in one or more program modules, executed by one or more computers (including monitoring modules) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device. Computer executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, random access memory (RAM), etc. As should be appreciated by those skilled in the art, the functions of the program modules may be combined or distributed as desired in various aspects. In addition, the functions may be embodied in firmware or hardware equivalents such as integrated circuits and FPGAs in whole or in part. Certain data structures may be used to more efficiently implement one or more aspects of the present disclosure, and such data structures are contemplated to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0048] In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by one or more computer-readable storage media or stored on one or more computer-readable storage media, which instructions may be read and executed by one or more processors. Such instructions may be referred to as computer program products. As discussed herein, computer-readable media refers to any medium that can be accessed by a computing device. As an example and not limitation, computer-readable media may include computer storage media and communication media.

[0049] Computer storage media refers to any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media does not include the signal itself and the temporary form of signal transmission.

[0050] Communication media refers to any medium that can be used for communication of computer-readable information. By way of example and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic or other types of signals.

[0051] Example

[0052] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below and any combination thereof.

[0053] Example 1, a test and measurement device with a signal source, comprising: an impairment generator, which is configured to output impairments; a waveform synthesizer, which is configured to: receive an input digital signal to be synthesized, receive impairments, and synthesize a synthesized digital signal based on the input digital signal and the impairments; and a fixed sampling rate digital-to-analog converter, which is configured to receive a clock signal and the synthesized digital signal, and output an analog signal.

[0054] Example 2 is the test and measurement equipment of Example 1, wherein the waveform synthesizer includes: a waveform symbol clock generator, which is configured to receive impairments and a reference clock, and output a transition event signal based on the impairments and the reference clock; and a waveform synthesis interpolator, which is configured to receive the transition event signal and the input signal, and output the synthesized digital signal at a fixed sampling rate of the digital-to-analog converter.

[0055] Example 3 is the test and measurement device of Example 2, wherein the transition event signal indicates a timing of the transition event, and the timing of the transition event is advanced or delayed based on the impairment.

[0056] Example 4 is the test and measurement device of any one of Examples 1 to 3, wherein the waveform synthesizer includes: a waveform generator configured to output a synthesized digital signal; an analog phase adjuster configured to receive impairments and output a clock signal as a jittered clock signal based on the impairments; and a buffer configured to store the synthesized digital signal and output a portion of the synthesized digital signal in response to the clock signal.

[0057] Example 5 is the test and measurement device of Example 4, wherein the analog phase adjuster is a phase interpolator.

[0058] Example 6 is the test and measurement device of Example 4, wherein the analog phase adjuster includes an analog delay line.

[0059] Example 7 is the test and measurement device of any one of Examples 4 to 6, wherein the buffer is a first-in-first-out buffer.

[0060] Example 8 is the test and measurement device of any one of Examples 1 to 7, wherein the impairment includes at least one of jitter or spread spectrum clock impairment.

[0061] Example 9 is the test and measurement device of any one of Examples 1 to 8, wherein the waveform synthesizer is further configured to correct the synthesized digital waveform if an impairment causes samples of the synthesized digital signal to be in different sampling periods.

[0062] Example 10 is a method for synthesizing a waveform, comprising: receiving an input digital signal to be synthesized; generating impairments; synthesizing the synthesized digital signal based on the input digital signal and the impairments; and converting the synthesized digital signal into an analog signal with impairments through a fixed sampling rate digital-to-analog converter.

[0063] Example 11 is the method of Example 10, wherein synthesizing the synthesized digital signal includes generating a transition event signal based on impairments and a reference clock; and generating the synthesized digital signal with impairments at a fixed sampling rate of a digital-to-analog converter.

[0064] Example 12 is the method of Example 11, wherein the transition event signal indicates a timing of the transition event, and the timing of the transition event is advanced or delayed based on the impairment.

[0065] Example 13 is a method of any one of Examples 10 to 12, wherein synthesizing the synthesized digital signal includes: storing the synthesized digital signal in a buffer, and outputting the synthesized digital signal to a digital-to-analog converter based on damage; generating a jittered clock signal through an analog phase adjuster; and transmitting the jittered clock signal to the digital-to-analog converter.

[0066] Example 14 is the method of Example 13, wherein the analog phase adjuster is a phase interpolator.

[0067] Example 15 is the method of Example 13, wherein the analog phase adjuster includes an analog delay line.

[0068] Example 16 is the method of any one of Examples 13 to 16, wherein the buffer is a first-in-first-out buffer.

[0069] Example 17 is the method of any one of Examples 10 to 16, wherein the impairment comprises at least one of jitter or spread spectrum clock impairment.

[0070] Example 18 is the method of any one of Examples 10 to 17, further comprising correcting the synthesized digital waveform if the impairment causes samples of the synthesized digital signal to be in different sampling periods.

[0071] Example 19 is one or more computer-readable storage media comprising instructions that, when executed by one or more processors of a test and measurement instrument, cause the test and measurement instrument to generate a digital signal to be synthesized; generate impairments; synthesize the synthesized digital signal based on an input digital signal and the impairments; and convert the synthesized digital signal into an analog signal with impairments through a fixed sampling rate digital-to-analog converter.

[0072] Example 20 is one or more computer-readable storage media of Example 19, wherein synthesizing the synthesized digital signal includes: generating a transition event signal based on impairments and a reference clock; and generating the synthesized digital signal with impairments at a fixed sampling rate of a digital-to-analog converter.

[0073] The previously described versions of the disclosed subject matter have many advantages that are described or will be apparent to those of ordinary skill in the art. Even so, not all versions of the disclosed apparatus, system, or method require these advantages or features.

[0074] Additionally, this written description is referenced to specific features. It is to be understood that the disclosure in this specification includes all possible combinations of those specific features. Where a specific feature is disclosed in the context of a specific aspect or example, the feature may also be used in the context of other aspects and examples to the extent possible.

[0075] Additionally, when reference is made in the present application to a method having two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes those possibilities.

[0076] Although specific examples of the present invention have been illustrated and described for purposes of illustration, it will be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be limited except as limited by the appended claims.

Claims

1. A test and measurement device, the test and measurement device having a signal source, the test and measurement device comprising: a lesion generator configured to output lesions; A waveform synthesizer, the waveform synthesizer being configured to: receiving an input digital signal to be synthesized, receiving damage, and synthesizing a synthesized digital signal based on the input digital signal and the impairment; as well as a fixed sampling rate digital-to-analog converter configured to receive a reference clock signal and the synthesized digital signal and output an analog signal; The waveform synthesizers include: a waveform-symbol clock generator configured to receive an impairment and a reference clock signal and to output a transition event signal based on the impairment and the reference clock signal; as well as A waveform synthesis interpolator is configured to receive the transition event signal and an input signal and output a synthesized digital signal at a fixed sampling rate of a digital-to-analog converter. 2 . The test and measurement device of claim 1 , wherein the transition event signal indicates a timing of a transition event, and the timing of the transition event is advanced or delayed based on the damage.

3. The test and measurement device of claim 1, wherein the impairment comprises at least one of jitter or spread spectrum clock impairment.

4. The test and measurement device of claim 1, wherein the waveform synthesizer is further configured to correct the synthesized digital waveform if an impairment causes samples of the synthesized digital signal to be in different sampling periods.

5. A test and measurement device, the test and measurement device having a signal source, the test and measurement device comprising: a lesion generator configured to output lesions; A waveform synthesizer, the waveform synthesizer being configured to: receiving an input digital signal to be synthesized, receiving damage, and synthesizing a synthesized digital signal based on the input digital signal and the impairment; as well as a fixed sampling rate digital-to-analog converter configured to receive a reference clock signal and the synthesized digital signal and output an analog signal; The waveform synthesizers include: a waveform generator configured to output the synthesized digital signal; an analog phase adjuster configured to receive the impairments and output the reference clock signal as a jittered clock signal based on the impairments; and A buffer is configured to store the synthesized digital signal and output a portion of the synthesized digital signal in response to the reference clock signal.

6. The test and measurement device of claim 5, wherein the analog phase adjuster is a phase interpolator.

7. The test and measurement device of claim 5, wherein the analog phase adjuster comprises an analog delay line.

8. The test and measurement device of claim 5, wherein the buffer is a first-in-first-out buffer.

9. The test and measurement device of claim 5, wherein the impairment comprises at least one of jitter or spread spectrum clock impairment.

10. The test and measurement device of claim 5, wherein the waveform synthesizer is further configured to correct the synthesized digital waveform if an impairment causes samples of the synthesized digital signal to be in different sampling periods.

11. A method for synthesizing a waveform, comprising: receiving an input digital signal to be synthesized; Generate damage; synthesizing a synthesized digital signal based on the input digital signal and the impairment; as well as The synthesized digital signal is converted into an analog signal with impairments by a fixed sampling rate digital-to-analog converter. The digital signals synthesized include: generating a transition event signal based on the impairment and the reference clock signal; as well as The synthesized digital signal with impairments is generated at a fixed sampling rate of the digital-to-analog converter. 12 . The method of claim 11 , wherein the transition event signal indicates a timing of the transition event, and the timing of the transition event is advanced or delayed based on the damage.

13. The method of claim 11, wherein the impairment comprises at least one of jitter or spread spectrum clock impairment.

14. The method according to claim 11, further comprising: If the impairment causes samples of the synthesized digital signal to be in different sampling periods, the synthesized digital waveform is corrected.

15. A method for synthesizing a waveform, comprising: receiving an input digital signal to be synthesized; Generate damage; synthesizing a synthesized digital signal based on the input digital signal and the impairment; as well as The synthesized digital signal is converted into an analog signal with impairments by a fixed sampling rate digital-to-analog converter. The digital signals synthesized include: storing the synthesized digital signal in a buffer and outputting the synthesized digital signal to a digital-to-analog converter based on the impairment; generating a jittered clock signal by an analog phase adjuster; and The jittered clock signal is transmitted to the digital-to-analog converter. The method of claim 15 , wherein the analog phase adjuster is a phase interpolator.

17. The method of claim 15, wherein the analog phase adjuster comprises an analog delay line. The method of claim 15 , wherein the buffer is a first-in-first-out buffer.

19. The method of claim 15, wherein the impairment comprises at least one of jitter or spread spectrum clock impairment.

20. The method of claim 15, further comprising correcting the synthesized digital waveform if impairments cause samples of the synthesized digital signal to be in different sampling periods.

21. One or more computer-readable storage media comprising instructions that, when executed by one or more processors of a test and measurement instrument, cause the test and measurement instrument to: generating a digital signal to be synthesized; Generate damage; synthesizing a synthesized digital signal based on the digital signal and the impairment; and The synthesized digital signal is converted into an analog signal with impairments by a fixed sampling rate digital-to-analog converter. The digital signals synthesized include: generating a transition event signal based on the impairment and the reference clock signal; as well as The synthesized digital signal with impairments is generated at a fixed sampling rate of the digital-to-analog converter.

Images