Semiconductor packaging structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor package structure comprising a conductive trace layer, a semiconductor die disposed above the conductive trace layer, a structural reinforcement layer surrounding the semiconductor die, and an encapsulant covering the semiconductor die and the structural reinforcement layer. The structural reinforcement layer coincides with a center-of-mass plane of the semiconductor package structure. The center-of-mass plane is parallel to the top surface of the semiconductor die. A method for manufacturing the semiconductor package structure is also provided.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging structure with a structural reinforcement layer. Background Art

[0002] Chip-to-Final Fan-Out (FFL) is a packaging technology that reconstructs the I / O pads on a semiconductor chip by laying out RDLs to form a conductive pattern layer with wider line spacing. RDLs are typically made of metal and dielectric layers on the surface of the semiconductor chip. In wafer-level packaging, a relatively thick mold compound is applied to the surface of the semiconductor chip supported by a glass carrier. Due to the different coefficients of thermal expansion (CTE) of the mold compound and RDLs or the fact that the structural mass is unbalanced, the semiconductor package may warp or deform.

[0003] In current technology, the RDL in the last fan-out of the chip is supported by a glass carrier, and the CTE of the glass carrier and the RDL are 3ppm / C and 60ppm / C, respectively. After the RDL is formed on the glass carrier, the package bends in a concave manner. In order to balance the structural quality, a molding compound with a CTE of approximately 8ppm / C, which is close to the CTE of the glass carrier, is selected to be formed on the RDL. However, after the carrier removal operation, since the CTE of the RDL is substantially greater than the CTE of the molding compound, the package bends in a concave manner, which prevents the subsequent packaging process. In order to solve the aforementioned problem, a molding compound with a larger CTE (e.g., 60ppm / C) or a CTE close to that of the RDL is selected. Nevertheless, the application of such a molding compound will exacerbate the concave behavior of the package before the carrier removal operation. The wafer may crack and abnormal handling problems may occur, increasing the difficulty of the carrier removal operation. Summary of the Invention

[0004] The present invention provides a structural reinforcement layer in a semiconductor package structure. The structural reinforcement layer surrounds a semiconductor chip. The geometric center of the final package structure is first identified from a cross-sectional view, and the position of the structural reinforcement layer is calculated accordingly, such that the center of mass of the final package structure including the structural reinforcement layer coincides with the previously identified geometric center. The position of the structural reinforcement layer is then determined from the cross-sectional view. The introduction of such a structural reinforcement layer can simultaneously suppress bending behavior of both concave and convex surfaces and effectively enhance the strength and rigidity of the semiconductor package, thereby achieving structural mass balance.

[0005] Some embodiments of the present invention provide a semiconductor package structure comprising a conductive trace layer, a semiconductor chip on the conductive trace layer, a structural reinforcement layer surrounding the semiconductor chip, and an encapsulant covering the semiconductor chip and the structural reinforcement layer. The top surface of the structural reinforcement layer is lower than the top surface of the semiconductor chip.

[0006] Some embodiments of the present invention provide a semiconductor package structure comprising a conductive trace layer, a first semiconductor chip electrically coupled to the conductive trace layer, a first structural reinforcement layer surrounding a sidewall of the first semiconductor chip, and an encapsulant covering the first semiconductor chip and the first structural reinforcement layer. A top surface of the first semiconductor chip is exposed from the encapsulant.

[0007] Some embodiments of the present invention provide a method for manufacturing a semiconductor package structure, comprising providing a conductive trace layer, placing a semiconductor chip on the conductive trace layer, and placing a structural reinforcement layer at a mass center plane of the semiconductor package structure and surrounding the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present invention.

[0009] Figure 2 is analyzed along plane AA according to some embodiments of the present invention Figure 1 A top view of a semiconductor package structure.

[0010] Figure 3 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present invention.

[0011] Figure 4A According to some embodiments of the present invention Figure 3 An enlarged view of a portion of a semiconductor package structure in FIG.

[0012] Figure 4B According to some embodiments of the present invention Figure 3 An enlarged view of a portion of a semiconductor package structure in FIG.

[0013] Figures 5A to 5J are cross-sectional views of semiconductor package structures during various intermediate manufacturing operations according to some embodiments of the present invention.

[0014] Figure 6 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present invention.

[0015] Figure 7A According to some embodiments of the present invention Figure 6 An enlarged view of a portion of a semiconductor package structure in FIG.

[0016] Figure 7B According to some embodiments of the present invention Figure 6 An enlarged view of a portion of a semiconductor package structure in FIG.

[0017] Figures 8A to 8Kare cross-sectional views of semiconductor package structures during various intermediate manufacturing operations according to some embodiments of the present invention.

[0018] Figure 9 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present invention.

[0019] Figure 10A According to some embodiments of the present invention Figure 9 An enlarged view of a portion of a semiconductor package structure in FIG.

[0020] Figure 10B According to some embodiments of the present invention Figure 9 An enlarged view of a portion of a semiconductor package structure in FIG.

[0021] Figures 11A to 11K are cross-sectional views of semiconductor package structures during various intermediate manufacturing operations according to some embodiments of the present invention.

[0022] Figure 12 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present invention.

[0023] Figure 13A According to some embodiments of the present invention Figure 12 An enlarged view of a portion of a semiconductor package structure in FIG.

[0024] Figure 13B According to some embodiments of the present invention Figure 12 An enlarged view of a portion of a semiconductor package structure in FIG.

[0025] Figure 13C According to some embodiments of the present invention Figure 12 An enlarged view of a portion of a semiconductor package structure in FIG.

[0026] Figures 14A to 14L are cross-sectional views of semiconductor package structures during various intermediate manufacturing operations according to some embodiments of the present invention.

[0027] Figure 15 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present invention.

[0028] Figure 16A According to some embodiments of the present invention Figure 15 An enlarged view of a portion of a semiconductor package structure in FIG.

[0029] Figure 16B According to some embodiments of the present invention Figure 15 An enlarged view of a portion of a semiconductor package structure in FIG.

[0030] Figures 17A to 17J are cross-sectional views of semiconductor package structures during various intermediate manufacturing operations according to some embodiments of the present invention.

[0031] Figure 18 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present invention.

[0032] Figure 19A According to some embodiments of the present invention Figure 18 An enlarged view of a portion of a semiconductor package structure in FIG.

[0033] Figure 19B According to some embodiments of the present invention Figure 18 An enlarged view of a portion of a semiconductor package structure in FIG.

[0034] FIG. 20A to FIG. 20L are cross-sectional views of semiconductor package structures during various intermediate manufacturing operations according to some embodiments of the present invention.

[0035] Figure 21 is a flow chart of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0036] Figure 22 is a flow chart of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention.

[0037] Figure 23 and Figure 24A are cross-sectional views of semiconductor package structures according to some comparative embodiments of the present invention.

[0038] Figure 24B and Figure 25 is a cross-sectional view of a semiconductor package structure according to some embodiments of the present invention. DETAILED DESCRIPTION

[0039] Common reference numerals are used throughout the drawings and detailed description to refer to the same or similar components. Embodiments of the present invention will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0040] Spatial descriptors such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc., are designated relative to a component or group of components or a plane of a component or group of components to orient one or more components as shown in the associated figures. It should be understood that the spatial descriptors used herein are for illustrative purposes only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner without deviating from the advantages of the embodiments of the present invention.

[0041] refer to Figure 1 , Figure 1 is a cross-sectional view of a semiconductor package structure 10 according to some embodiments of the present invention. The semiconductor package structure 10 includes a semiconductor chip 103 placed on a conductive trace layer 101. The semiconductor chip 103 is surrounded by a structural reinforcement layer 105 from the sidewalls 103S of the semiconductor chip 103. The encapsulant 107 covers the semiconductor chip 103 and the structural reinforcement layer 105, as well as the conductive trace layer 101. In some embodiments, the conductive trace layer 101 is composed of a dielectric material, a polymer material, a conductive material and / or a passivation material. The conductive material can be arranged and embedded in the dielectric material, the polymer material or the passivation material. In some embodiments, the conductive trace layer 101 can be a redistribution layer (RDL), one side of which is connected to the conductive terminal 106, for example, a solder bump, and the opposite side is electrically coupled to the semiconductor chip 103.

[0042] In some embodiments, semiconductor chip 103 is connected to the top surface of conductive trace layer 101 through one or more conductive bumps 102. Underfill material 104 surrounds conductive bumps 102 and is placed between the bottom of semiconductor chip 103 and the top of conductive trace layer 101.

[0043] In some embodiments, the encapsulant 107 includes a first portion 107A below the structural reinforcement layer 105 and a second portion 107B above the structural reinforcement layer 105. The bottom surface 105b of the structural reinforcement layer 105 contacts the top surface of the first portion 107A of the encapsulant 107. The structural reinforcement layer 105 includes a top surface 105t, which may be covered by the second portion 107B of the encapsulant 107. Figure 1 As shown in FIG, a top surface 103 t of the semiconductor chip 103 is exposed from the second portion 107B of the encapsulant 107. In some embodiments, the top surface 103 t of the semiconductor chip 103 is coplanar with the top surface of the second portion 107B of the encapsulant 107. The top surface 103 t of the semiconductor chip 103 is exposed from the top surface of the second portion 107B of the encapsulant 107. In the current embodiment, because the structural reinforcement layer 105 is embedded between the first portion 107A and the second portion 107B, the top surface 105 t of the structural reinforcement layer 105 is lower than the top surface 103 t of the semiconductor chip 103.

[0044] In some embodiments, the structural reinforcement layer 105 is a pre-cut film of the desired size and thickness. The structural reinforcement layer 105 can be composed of a metal such as stainless steel or a fiber-reinforced plastic such as glass fiber. The selection of the structural reinforcement layer 105 can be considered at least from the perspective of material hardness and from the perspective of manufacturing applicability. For example, the hardness of the structural reinforcement layer 105 will be greater than the hardness of any major component in the semiconductor package structure 10, thereby enhancing the mechanical strength of the semiconductor package. For example, the hardness of the structural reinforcement layer 105 is greater than the hardness of the conductive trace layer 101, the encapsulant 107 and the semiconductor chip 103. In some embodiments, the structural reinforcement layer 105 can be a patterned flexible film that can be easily applied on the conductive trace layer 101 through a lamination operation without contacting the semiconductor chip 103. The patterned flexible film may have a plurality of openings adapted to the planar topography of the semiconductor chip 103, so that when the structural reinforcement layer 105 is applied to surround the semiconductor chip 103, the structural reinforcement layer 105 may not contact the sidewalls 103s or the top surface 103t of the semiconductor chip 103, and a space may remain between the sidewalls 103s and the structural reinforcement layer 105. Such space may be filled with the encapsulant 107 in a subsequent operation. For example, Figure 1 As illustrated in FIG, the structural reinforcement layer 105 is placed on the first portion 107A of the encapsulant 107, and the space between the sidewall 103s of the semiconductor chip 103 and the structural reinforcement layer 105 is filled with the second portion 107B of the encapsulant 107. In some embodiments, the structural reinforcement layer can be placed directly on the conductive trace layer, as will be described in detail in the present invention. Figure 25 As discussed in .

[0045] The semiconductor package structure 10 has a geometric center plane, which is a plane parallel to the top surface 103t of the semiconductor chip 103 from the perspective of the cross-sectional view and located at the geometric center of the package structure. Typically, the geometric center plane is located at half the height of the package. The semiconductor package structure 10 has a mass center plane, which is also a plane parallel to the top surface 103t of the semiconductor chip 103 from the perspective of the cross-sectional view and located at the mass center of the package structure. Typically, the mass center plane can be determined by considering the density of the main components in the package structure and can be located anywhere between the top and bottom of the package structure. In some embodiments, the geometric center plane of the semiconductor package structure 10 coincides with the mass center plane so as to effectively enhance the mechanical strength of the semiconductor package and alleviate the bending problem as previously described.

[0046] refer to Figure 2 , Figure 2 is analyzed along plane AA according to some embodiments of the present invention Figure 1FIG1 is a top view of a semiconductor package structure 10 of FIG1. ​​From a top view perspective, a first semiconductor chip 103A, a second semiconductor chip 103B, a third semiconductor chip 103C, and a fourth semiconductor chip 103D (hereinafter referred to as “semiconductor chips”) are surrounded by a structural reinforcement layer 105. The space between the semiconductor chips and the structural reinforcement layer 105 is filled with a sealing body 107, or in this case, a second portion 107B of the sealing body. In some embodiments, the second portion 107B of the sealing body further surrounds the structural reinforcement layer 105. In some embodiments, the structural reinforcement layer 105 occupies a continuous area around each of the semiconductor chips so as to provide sufficient mechanical reinforcement to the semiconductor package structure. However, other arrangements of the structural reinforcement layer are also applicable, as long as the hardness of the semiconductor package can be enhanced to a desired degree.

[0047] refer to Figure 3 , Figure 3 3 is a cross-sectional view of a semiconductor package structure 30 according to some embodiments of the present invention. The semiconductor package structure 30 includes a semiconductor chip 303A and a semiconductor chip 303B placed on a conductive trace layer 301. The semiconductor chips 303A and 303B are surrounded by a structural reinforcement layer 305 from the sidewalls of the semiconductor chips 303A and 303B. It should be noted that the thickness of the semiconductor chips 303A and 303B is substantially the same, and the corresponding structural reinforcement layer 305 surrounding the semiconductor chips 303A and 303B can have a uniform thickness. The space between the structural reinforcement layer 305 and the sidewalls of the semiconductor chips 303A and 303B is filled with a sealing compound 307, as previously described. Figure 1 As discussed in .

[0048] The encapsulant 307 covers the semiconductor chips 303A and 303B, the structural reinforcement layer 305, and the conductive trace layer 301. In some embodiments, the conductive trace layer 301 may be a redistribution layer (RDL) having one side connected to the conductive terminals 306, e.g., solder bumps, and an opposite side electrically coupled to the semiconductor chips 303A and 303B.

[0049] In some embodiments, semiconductor chip 303A and semiconductor chip 303B are connected to the top surface of conductive trace layer 301 through one or more conductive bumps 302. Underfill material 304 surrounds conductive bumps 302 of semiconductor chip 303A and is placed between the bottom of semiconductor chip 303A and the top of conductive trace layer 301.

[0050] In some embodiments, the structural reinforcement layer 305 is substantially the same as the structural reinforcement layer 105 described herein and can be referenced thereto. In some embodiments, the encapsulant 307 (including the first encapsulant portion 307A and the second encapsulant portion 307B) is substantially the same as the encapsulant 107 of the semiconductor package structure 10. The top surfaces 303t and top surfaces 303t' of the semiconductor chips 303A and 303B, respectively, are exposed from the top surface 307t of the encapsulant 307.

[0051] In some embodiments, the semiconductor package structure 30 has a geometric center plane, which is a plane parallel to the top surfaces 303t and 303t' of the semiconductor chips 303A and 303B, as viewed in a cross-sectional view, and located at the geometric center of the package structure. The semiconductor package structure 30 has a mass center plane, which is also a plane parallel to the top surfaces 303t and 303t' of the semiconductor chips 303A and 303B, as viewed in a cross-sectional view, and located at the mass center of the package structure. In some embodiments, the geometric center plane of the semiconductor package structure 30 coincides with the mass center plane, thereby effectively enhancing the mechanical strength of the semiconductor package and alleviating the bowing problem described above.

[0052] refer to Figure 4A and Figure 4B , Figure 4A and Figure 4B According to some embodiments of the present invention Figure 3 An enlarged view of a portion of the semiconductor package structure 30 in FIG. Figure 4A In FIG. 4 , a portion of the structural reinforcement layer 305 is placed between the semiconductor chip 303A and the semiconductor chip 303B. The space between the structural reinforcement layer 305 and the two semiconductor chips is filled with the second portion 307B of the encapsulant to form a filling gap 401. The first portion 307A of the encapsulant has a continuous horizontal surface 307t′ that supports the structural reinforcement layer 305. Figure 4B Further zoomed in, conductive filler 403A for heat conduction is illustrated in first portion 307A of the encapsulant. Because no planarization operation was applied to first portion 307A of the encapsulant, conductive filler 403A (particularly those near continuous horizontal surface 307t') all retain their original shapes, e.g., spherical, elliptical, or needle-shaped. In contrast, conductive filler 403B in second portion 307B of the encapsulant (particularly those near top surface 307t) exhibits cutoff characteristics, e.g., hemispherical or segmented elliptical shapes, due to the planarization operation applied thereto.

[0053] Figures 5A to 5Jis a cross-sectional view of a semiconductor package structure 30 during various intermediate manufacturing operations according to some embodiments of the present invention. Like reference numerals refer to substantially the same components or their equivalents and are not repeated here for the sake of brevity. A carrier 500 (e.g., a temporary substrate) is provided on Figure 5A The conductive trace layer 301 is then formed on the receiving surface of the carrier 500, as shown in FIG. Figure 5B As shown in . Figure 5C , semiconductor chips 303A and 303B are then flip-chip bonded to conductive trace layer 301 via conductive bumps 302 on the active surfaces of semiconductor chips 303A and 303B. Underfill 304 is applied around conductive bumps 302 under semiconductor chip 303A, as in Figure 5D In Figure 5E and Figure 5F In the embodiment, the first portion 307A of the encapsulant is formed on the conductive trace layer 301 and surrounds the conductive bump 302 and a portion of the sidewalls of the semiconductor chips 303A and 303B. The top surface 307t′ of the first portion 307A of the encapsulant is controlled by the manufacturing operation based on the calculation of the position of the structural reinforcement layer 305 in the semiconductor package structure 30. Alternatively stated, because the structural reinforcement layer 305 is directly placed on the top surface 307t′ of the first portion 307A of the encapsulant, as shown in FIG. Figure 5F As shown in FIG, the position of the structural reinforcement layer 305 in the semiconductor package structure 30 is determined before the first portion 307A of the encapsulant is formed. The encapsulant may be composed of a molding compound filled with a first type of conductive filler.

[0054] exist Figure 5G In the embodiment, the second portion 307B of the encapsulant is formed on the structural reinforcement layer 305 to the extent of filling the gap 401 between the semiconductor chips 303A and 303B and covering the top surfaces 303t and 303t' of the semiconductor chips 303A and 303B, respectively. Figure 5H As shown in , an optional grinding operation is performed to expose the top surfaces 303t and 303t' of the semiconductor chips 303A and 303B from the second portion 307B of the encapsulation body. Figure 5I and Figure 5J In the embodiment, the carrier 500 is released and the conductive terminals 306 are mounted to the conductive trace layer 306. The semiconductor package structure 30 is then formed after the chip saw operation. Figures 5A to 5J In , the conductive trace layer is formed before chip bonding and is referred to herein as the chip last operation.

[0055] refer to Figure 6 , Figure 63 is a cross-sectional view of a semiconductor package structure 60 according to some embodiments of the present invention. The semiconductor package structure 60 includes a semiconductor chip 303A and a semiconductor chip 303B placed on a conductive trace layer 301. The semiconductor chips 303A and 303B are surrounded by a structural reinforcement layer 305 from the sidewalls of the semiconductor chips 303A and 303B. It should be noted that the thickness of the semiconductor chips 303A and 303B is substantially the same, and the corresponding structural reinforcement layer 305 surrounding the semiconductor chips 303A and 303B can have a uniform thickness. The space between the structural reinforcement layer 305 and the sidewalls of the semiconductor chips 303A and 303B is filled with a sealing compound 307, as previously described. Figure 1 As discussed in .

[0056] The encapsulant 307 covers the semiconductor chips 303A and 303B, the structural reinforcement layer 305, and the conductive trace layer 301. In some embodiments, the conductive trace layer 301 may be a redistribution layer (RDL) having one side connected to the conductive terminals 306, e.g., solder bumps, and an opposite side electrically coupled to the semiconductor chips 303A and 303B.

[0057] In some embodiments, semiconductor chip 303A and semiconductor chip 303B are connected to the top surface of conductive trace layer 301 through one or more conductive bumps 302. Underfill material 304 surrounds conductive bumps 302 of semiconductor chip 303A and is placed between the bottom of semiconductor chip 303A and the top of conductive trace layer 301.

[0058] In some embodiments, the structural reinforcement layer 305 surrounds the sidewalls 303s of the semiconductor chips 303A and 303B and on the top surface 307t' of the first part 307A of the encapsulation body. It should be noted that the structural reinforcement layer 305 of the semiconductor package structure 60 includes a seed layer 305A and a metal layer 305B on the seed layer 305A. Each of the seed layer 305A and the metal layer 305B forms a continuous layer. The seed layer 305A is thinner than the metal layer 305B, and the metal layer is, for example, electroplated to a predetermined thickness. Due to the transfer from the seed layer deposition operation to the metal layer electroplating operation, a boundary can be observed between the seed layer 305A and the metal layer 305B. In some embodiments, the structural reinforcement layer 305 shows a "U" shape that conforms to the entire sidewalls 303s of the semiconductor chips 303A and 303B and the top surface 307t' of the first part 307A of the encapsulation body.

[0059] In some embodiments, the encapsulant 307 is substantially the same as the encapsulant 107 of the semiconductor package structure 10. The top surfaces 303t and 303t' of the semiconductor chips 303A and 303B are exposed from the top surface 307t of the encapsulant 307. The second portion 307B of the encapsulant does not contact the first portion 307A of the encapsulant and is separated therefrom by the structural reinforcement layer 305 in the semiconductor package structure 60.

[0060] In some embodiments, the semiconductor package structure 60 has a geometric center plane, which is a plane parallel to the top surfaces 303t and 303t' of the semiconductor chips 303A and 303B, as viewed in a cross-sectional view, and located at the geometric center of the package structure. The semiconductor package structure 60 has a mass center plane, which is also a plane parallel to the top surfaces 303t and 303t' of the semiconductor chips 303A and 303B, as viewed in a cross-sectional view, and located at the mass center of the package structure. In some embodiments, the geometric center plane of the semiconductor package structure 60 coincides with the mass center plane, thereby effectively enhancing the mechanical strength of the semiconductor package and alleviating the bending problem described above.

[0061] refer to Figure 7A and Figure 7B , Figure 7A and Figure 7B According to some embodiments of the present invention Figure 6 An enlarged view of a portion of the semiconductor package structure 60 in FIG. Figure 7A In FIG. 3 , a portion of the structural reinforcement layer 305 is placed between the semiconductor chip 303A and the semiconductor chip 303B. The first portion 307A of the encapsulation body has a continuous horizontal surface 307t′ supporting the structural reinforcement layer 305. Figure 7B Further zoomed in, conductive filler 403A for heat conduction is illustrated in first portion 307A of the encapsulant. Because no planarization operation was applied to first portion 307A of the encapsulant, conductive filler 403A (particularly those near continuous horizontal surface 307t') all retain their original shapes, e.g., spherical, elliptical, or needle-shaped. In contrast, conductive filler 403B in second portion 307B of the encapsulant (particularly those near top surface 307t) exhibits cutoff characteristics, e.g., hemispherical or segmented elliptical shapes, due to the planarization operation applied thereto.

[0062] Figures 8A to 8K is a cross-sectional view of a semiconductor package structure 60 during various intermediate manufacturing operations according to some embodiments of the present invention. Like numerical designations refer to substantially like components or their equivalents and are not repeated here for the sake of brevity. Figures 8A to 8E The description can be found in Figures 5A to 5E Reference is made to the description of and is not repeated here for the sake of brevity. Figure 8F In the embodiment, a seed layer deposition operation is performed, for example, by sputtering. The seed layer 305A is conformally formed on the top surface and sidewalls of the semiconductor chips 303A, 303B and the top surface 307t' of the first portion 307A of the encapsulation body. Figure 8G In the embodiment, an electroplating operation is performed to form a conformal metal layer 305B to a predetermined thickness, and the predetermined thickness is generally greater than the thickness of the seed layer 305A. Figure 8H As shown in FIG, the second portion 307B of the encapsulant is formed on the structural reinforcement layer 305 by covering the top surface and the space between the semiconductor chips 303A and 303B.

[0063] Similar to Figures 5H to 5J , Figure 8I An optional grinding operation is shown as being performed to expose the top surfaces 303t and 303t' of the semiconductor chips 303A and 303B from the second portion 307B of the encapsulation body. Figure 8J and Figure 8K In the embodiment, the carrier 500 is released and the conductive ends 306 are mounted to the conductive trace layer 301. The semiconductor package structure 60 is then formed after the chip saw operation. Figures 8A to 8K In , the conductive trace layer is formed before chip bonding and is referred to herein as the chip last operation.

[0064] refer to Figure 9 , Figure 9 is a cross-sectional view of a semiconductor package structure 90 according to some embodiments of the present invention. Like reference numerals refer to substantially the same components or their equivalents and are not repeated here for the sake of brevity. The semiconductor package structure 90 is similar to Figure 3 The semiconductor package structure 30 is different in that the semiconductor package structure 90 is manufactured by a chip first operation, as will be Figures 11A to 11K The top surfaces 303t and 303t′ of the semiconductor chips 303A and 303B are covered by the second portion 307B of the encapsulant. The top surface 307t of the encapsulant is higher than the top surface 305t of the structural reinforcement layer 305.

[0065] refer to Figure 10A and Figure 10B , Figure 10A and Figure 10B According to some embodiments of the present invention Figure 9 An enlarged view of a portion of the semiconductor package structure 90 in FIG. Figure 10A, a portion of the structural reinforcement layer 305 is placed between the semiconductor chip 303A and the semiconductor chip 303B. The space between the structural reinforcement layer 305 and the two semiconductor chips is filled with the second portion 307B of the encapsulation body to form a filling gap 1001. The first portion 307A of the encapsulation body has a continuous horizontal surface 307t' that supports the structural reinforcement layer 305. Conductive fillers 1003A and 1003B for heat conduction are illustrated in the first portion 307A and the second portion 307B of the encapsulation body, respectively. Because no planarization operation is applied to the first portion 307A and the second portion 307B of the encapsulation body, the conductive fillers 1003A and 1003B (especially those close to the continuous horizontal surface 307t' and the top surface 307t) all retain their original shape, for example, a spherical, elliptical or needle shape. In Figure 10B In the embodiment, since the conductive trace layer 301 is formed after the encapsulation body 307 is formed, the surface roughness of the first portion 307A of the encapsulation body can be observed at the bottom surface 307b' of the encapsulation body by filling the conductive trace layer 301 material into the recess at the bottom surface 307b' of the encapsulation body.

[0066] Figures 11A to 11K is a cross-sectional view of a semiconductor package structure 90 during various intermediate manufacturing operations according to some embodiments of the present invention. Like reference numerals refer to substantially the same components or their equivalents and are not repeated here for the sake of brevity. A carrier 500 (e.g., a temporary substrate) is provided on Figure 11A In. Figure 11B A middle adhesive layer 501 is provided on the receiving surface of the carrier 500. Figure 11C In the embodiment, semiconductor chips 303A and 303B are then placed on the adhesive layer 501 with the active surfaces facing the adhesive layer 501. Figure 11D In FIG, the first portion 307A of the encapsulant is formed on the adhesive layer 501 and surrounds a portion of the sidewalls of the semiconductor chips 303A and 303B. Figure 11E In the embodiment, the structural reinforcement layer 305 is laminated on the first portion 307A of the encapsulant. The top surface 307t′ of the first portion 307A of the encapsulant is controlled by the manufacturing operation based on the calculation of the position of the structural reinforcement layer 305 in the semiconductor package structure 90. Alternatively stated, because the structural reinforcement layer 305 is directly placed on the top surface 307t′ of the first portion 307A of the encapsulant, as shown in FIG. Figure 11E As shown in FIG, the position of the structural reinforcement layer 305 in the semiconductor package structure 90 is determined before the first portion 307A of the encapsulant is formed. The encapsulant may be composed of a molding compound filled with a first type of conductive filler.

[0067] exist Figure 11FIn the embodiment, the second portion 307B of the encapsulant is formed on the structural reinforcement layer 305 to the extent of filling the gap 1001 between the semiconductor chips 303A and 303B and covering the top surfaces 303t and 303t' of the semiconductor chips 303A and 303B, respectively. Figure 11G In the embodiment, the carrier 500 and the adhesive layer 501 are detached, exposing the conductive pads at the active surfaces of the semiconductor chips 303A, 303B. Figure 11H In the embodiment, the second carrier 503 is bonded to the top surface 307t of the second portion 307B of the encapsulant. The intermediate semiconductor package structure is then flipped upside down to build the conductive trace layer 301 above the active surfaces of the semiconductor chips 303A, 303B, and then the second carrier 503 is released, as shown in FIG. Figure 11I and Figure 11J As shown in . Figure 11K In the embodiment, the semiconductor package structure 90 is then formed after the chip saw operation. Figures 11A to 11K In , the conductive trace layer is formed after molding of the semiconductor chip and is referred to herein as a chip first operation.

[0068] Figure 12 is a cross-sectional view of a semiconductor package structure 1200 according to some embodiments of the present invention. Like reference numerals refer to substantially the same components or their equivalents and are not repeated here for the sake of brevity. The semiconductor package structure 1200 is similar to Figure 6 The semiconductor package structure 60 is different in that the semiconductor package structure 1200 is manufactured by a chip first operation, as will be Figures 14A to 14L The top surfaces 303t and 303t′ of the semiconductor chips 303A and 303B are covered by the second portion 307B of the encapsulant. The top surface 307t of the encapsulant is higher than the top surface 305t of the structural reinforcement layer 305.

[0069] Figure 13A 、 Figure 13B and Figure 13C According to some embodiments of the present invention Figure 12 An enlarged view of a portion of the semiconductor package structure 1200 in FIG. Figure 13A In the embodiment, a portion of the structural reinforcement layer 305 is placed between the semiconductor chip 303A and the semiconductor chip 303B. The first portion 307A of the encapsulant has a continuous horizontal surface 307t' supporting the structural reinforcement layer 305. Figure 13B, conductive fillers 1303A and 1303B for heat conduction are illustrated in the first and second portions 307A and 307B of the encapsulation, respectively. Because no planarization operation is applied to the first and second portions 307A and 307B of the encapsulation, the conductive fillers 1303A and 1303B (especially those near the continuous horizontal surface 307t' and the top surface 307t) all retain their original shapes, for example, spherical, elliptical, or needle-shaped. Figure 13C In the embodiment, since the conductive trace layer 301 is formed after the encapsulation body 307 is formed, the surface roughness of the first portion 307A of the encapsulation body can be observed at the bottom surface 307b' of the encapsulation body by filling the conductive trace layer 301 material into the recess at the bottom surface 307b' of the encapsulation body.

[0070] Figures 14A to 14L 1 is a cross-sectional view of a semiconductor package structure 1200 during various intermediate manufacturing operations according to some embodiments of the present invention. Like reference numerals refer to substantially the same components or their equivalents and are not repeated here for the sake of brevity. A carrier 500 (e.g., a temporary substrate) is provided on Figure 14A In. Figure 14B A middle adhesive layer 501 is provided on the receiving surface of the carrier 500. Figure 14C In the embodiment, semiconductor chips 303A and 303B are then placed on the adhesive layer 501 with the active surfaces facing the adhesive layer 501. Figure 14D In FIG, the first portion 307A of the encapsulant is formed on the adhesive layer 501 and surrounds a portion of the sidewalls of the semiconductor chips 303A and 303B. Figure 14E In the embodiment, a seed layer deposition operation is performed, for example, by sputtering. The seed layer 305A is conformally formed on the top surface and sidewalls of the semiconductor chips 303A, 303B and the top surface 307t' of the first portion 307A of the encapsulation body. Figure 14F In the embodiment, an electroplating operation is performed to form a conformal metal layer 305B to a predetermined thickness, and the predetermined thickness is generally greater than the thickness of the seed layer 305A. Figure 14G As shown in FIG, the second portion 307B of the encapsulant is formed on the structural reinforcement layer 305 by covering a portion of the top surface and sidewalls of the semiconductor chips 303A, 303B. The encapsulant may be composed of a molding compound filled with a first type of conductive filler.

[0071] exist Figure 14H In , the carrier 500 and the adhesive layer 501 are detached, thereby exposing the conductive pads at the active surfaces of the semiconductor chips 303A, 303B. Figure 14IIn the embodiment, the second carrier 503 is bonded to the top surface 307t of the second portion 307B of the encapsulant. The intermediate semiconductor package structure is then flipped upside down to build the conductive trace layer 301 above the active surfaces of the semiconductor chips 303A, 303B, and then the second carrier 503 is released, as shown in FIG. Figure 14J and Figure 14K As shown in . Figure 14L In the embodiment, the semiconductor package structure 1200 is then formed after the chip saw operation. Figures 14A to 14L In , the conductive trace layer is formed after molding of the semiconductor chip and is referred to herein as a chip first operation.

[0072] Figure 15 FIG1 is a cross-sectional view of a semiconductor package structure 1500 according to some embodiments of the present invention. Semiconductor package structure 1500 includes a semiconductor chip 1503A and a semiconductor chip 1503B placed on a conductive trace layer 1501. Semiconductor chip 1503A is surrounded by a first structural reinforcement layer 1505A from the sidewalls of semiconductor chip 1503A. Semiconductor chip 1503B is surrounded by a second structural reinforcement layer 1505B from the sidewalls of semiconductor chip 1503B.

[0073] When semiconductor chips 1503A and 1503B are composed of substantially the same material and structural reinforcement layer 1505A and structural reinforcement layer 1505B are composed of substantially the same material, thicker semiconductor chips require thinner structural reinforcement layers to obtain the desired package stiffness with respect to the previously discussed bending issues. Figure 15 , the thickness T1 of semiconductor chip 1503A and the thickness T2 of semiconductor chip 1503B are different, for example, thickness T2 is greater than thickness T1. The structural reinforcement layer 1505A surrounding semiconductor chip 1503A has a thickness T1' greater than thickness T2' of the structural reinforcement layer 1505B surrounding semiconductor chip 1503B.

[0074] The encapsulant 1507 covers the semiconductor chips 1503A and 1503B, the structural reinforcement layers 1505A and 1505B, and the conductive trace layer 1501. In some embodiments, the conductive trace layer 1501 may be a redistribution layer (RDL) having one side connected to the conductive terminals 1506, e.g., solder bumps, and an opposite side electrically coupled to the semiconductor chips 1503A and 1503B.

[0075] In some embodiments, semiconductor chip 1503A and semiconductor chip 1503B are connected to the top surface of conductive trace layer 1501 through one or more conductive bumps 1502. An underfill material 1504 surrounds the conductive bumps 1502 of semiconductor chip 1503A and is placed between the bottom of semiconductor chip 1503A and the top of conductive trace layer 1501.

[0076] In some embodiments, the structural reinforcement layers 1505A and 1505B are substantially the same as the structural reinforcement layer 105 described herein and can be referred to as such. In some embodiments, the encapsulant 1507 (including the first encapsulant portion 1507A and the second encapsulant portion 1507B) is substantially the same as the encapsulant 107 of the semiconductor package structure 10. The top surface 1503t′ of the semiconductor chip 1503B having a larger thickness T2 is exposed from the top surface 1507t of the encapsulant 1507.

[0077] In some embodiments, the semiconductor package structure 1500 has a geometric center plane, which is a plane parallel to the top surfaces 1503t and 1503t' of the semiconductor chips 1503A and 1503B, respectively, and located at the geometric center of the package structure, as viewed from a cross-sectional view. The semiconductor package structure 1500 has a mass center plane, which is also a plane parallel to the top surfaces 1503t and 1503t' of the semiconductor chips 1503A and 1503B, respectively, and located at the mass center of the package structure, as viewed from a cross-sectional view. In some embodiments, the geometric center plane of the semiconductor package structure 1500 coincides with the mass center plane, thereby effectively enhancing the mechanical strength of the semiconductor package and alleviating the previously described warping problem.

[0078] refer to Figure 16A and Figure 16B , Figure 16A and Figure 16B According to some embodiments of the present invention Figure 15 An enlarged view of a portion of the semiconductor package structure 1500 in FIG. Figure 16A In FIG, a portion of the structural reinforcement layers 1505A and 1505B is placed between the semiconductor chips 1503A and 1503B. The space between the structural reinforcement layers 1505A and 1505B and the two semiconductor chips is filled with the second portion 1507B of the encapsulant, forming a filling gap 1601. The first portion 1507A of the encapsulant has a continuous horizontal surface 1507t' that supports the structural reinforcement layers 1505A and 1505B. Figure 16B Further zoomed in on FIG, conductive filler 1603A for heat conduction is illustrated in first portion 1507A of the encapsulant. Because no planarization operation was applied to first portion 1507A of the encapsulant, conductive filler 1603A (particularly those near continuous horizontal surface 1507t') all retain their original shapes, e.g., spherical, elliptical, or needle-shaped. In contrast, conductive filler 1603B in second portion 1507B of the encapsulant (particularly those near top surface 1507t) exhibits cutoff characteristics, e.g., hemispherical or segmented elliptical shapes, due to the planarization operation applied thereto.

[0079] Figures 17A to 17J is a cross-sectional view of a semiconductor package structure 1500 during various intermediate manufacturing operations according to some embodiments of the present invention. Like reference numerals refer to substantially the same components or their equivalents and are not repeated here for the sake of brevity. Figures 17A to 17E For a description, please refer to Figures 5A to 5E The description of the semiconductor chip 1503A is not repeated here for the sake of brevity. It should be noted that the thickness T1 of the semiconductor chip 1503A is thinner than the thickness T2 of the semiconductor chip 1503B. Figure 17F In the embodiment, a structural reinforcement layer 1505A having a thickness T1' is laminated on the top surface 1507t' of the first portion 1507A of the encapsulant. Another structural reinforcement layer 1505B having a thickness T2' that is thinner than the thickness T1' is laminated on the top surface 1507t' of the first portion 1507A of the encapsulant. In some embodiments, the respective bottom surfaces of the structural reinforcement layers 1505A and 1505B are coplanar and placed on the top surface 1507t' of the first portion 1507A of the encapsulant. Figure 17G As shown in FIG, a second portion 1507B of the encapsulant is formed on the structural reinforcement layers 1505A and 1505B by covering the top surface and the space between the semiconductor chips 1503A and 1503B.

[0080] Similar to Figures 5H to 5J , Figure 17H An optional grinding operation is shown as being performed to expose the top surface 1503t' of the thicker semiconductor chip 1503B from the second portion 1507B of the encapsulant. Figure 17I and Figure 17J In the embodiment, the carrier 500 is detached and the conductive ends 1506 are mounted to the conductive trace layer 1501. The semiconductor package structure 1500 is then formed after the chip saw operation. Figures 17A to 17J In , the conductive trace layer is formed before chip bonding and is referred to herein as the chip last operation.

[0081] refer to Figure 18 , Figure 18is a cross-sectional view of a semiconductor package structure 1800 according to some embodiments of the present invention. The semiconductor package structure 1800 includes a semiconductor chip 1503A and a semiconductor chip 1503B placed on a conductive trace layer 1501. The semiconductor chip 1503A is surrounded by a first structural reinforcement layer 1505A, and the semiconductor chip 1503B is surrounded by a second structural reinforcement layer 1505B. It should be noted that the thickness T1 of the semiconductor chip 1503A is thinner than the thickness T2 of the semiconductor chip 1503B, and the first structural reinforcement layer 1505A surrounding the semiconductor chip 1503A has a thickness T1' that is thicker than the thickness T2' of the second structural reinforcement layer 1505B. The space reserved between the structural reinforcement layers 1505A, 1505B and the sidewalls of the semiconductor chips 1503A and 1503B is filled with a sealing compound 1507, as previously described. Figure 1 As discussed in .

[0082] The encapsulant 1507 covers the semiconductor chips 1503A and 1503B, the structural reinforcement layers 1505A and 1505B, and the conductive trace layer 1501. In some embodiments, the conductive trace layer 1501 may be a redistribution layer (RDL) having one side connected to the conductive terminals 1506, e.g., solder bumps, and an opposite side electrically coupled to the semiconductor chips 1503A and 1503B.

[0083] In some embodiments, semiconductor chip 1503A and semiconductor chip 1503B are connected to the top surface of conductive trace layer 1501 through one or more conductive bumps 1502. An underfill material 1504 surrounds the conductive bumps 1502 of semiconductor chip 1503A and is placed between the bottom of semiconductor chip 1503A and the top of conductive trace layer 1501.

[0084] In some embodiments, a first structural reinforcement layer 1505A surrounds the sidewalls 1503s of the semiconductor chip 1503A and is located above a portion of the top surface 1507t' of the first portion 1507A of the encapsulant. The first structural reinforcement layer 1505A is placed in the first chip region 1503A' of the semiconductor package structure 1800. It should be noted that the first structural reinforcement layer 1505A of the semiconductor package structure 1800 includes a seed layer 1505A' and a metal layer 1505B' above the seed layer 1505A'. Each of the seed layer 1505A' and the metal layer 1505B' forms a continuous layer. The seed layer 1505A' is thinner than the metal layer 1505B', which is, for example, electroplated to a predetermined thickness. Due to the transition from the seed layer deposition operation to the metal layer electroplating operation, a boundary can be observed between the seed layer 1505A' and the metal layer 1505B'.

[0085] In some embodiments, a second structural reinforcement layer 1505B surrounds the sidewalls 1503s of the semiconductor chip 1503B and extends over a portion of the top surface 1507t' of the first portion 1507A of the encapsulant. The second structural reinforcement layer 1505B is positioned within the second chip region 1503B' of the semiconductor package structure 1800. Unlike the first structural reinforcement layer 1505A within the first chip region 1503A', the second structural reinforcement layer 1505B comprises only a seed layer 1505A'. Therefore, the thickness T2' of the second structural reinforcement layer 1505B is thinner than the thickness T1' of the first structural reinforcement layer 1505A.

[0086] In some embodiments, the encapsulant 1507 is substantially the same as the encapsulant 107 of the semiconductor package structure 10. The top surface 1503t′ of the semiconductor chip 1503B is exposed from the top surface 1507t of the encapsulant 1507. The second portion 1507B of the encapsulant does not contact the first portion 1507A of the encapsulant and is separated from each other by the structural reinforcement layers 1505A and 1505B in the semiconductor package structure 1800.

[0087] In some embodiments, semiconductor package structure 1800 has a geometric center plane, which is a plane parallel to top surfaces 1503t and 1503t' of semiconductor chips 1503A and 1503B, respectively, and located at the geometric center of the package structure, as viewed from a cross-sectional view. Semiconductor package structure 1800 also has a mass center plane, which is also a plane parallel to top surfaces 1503t and 1503t' of semiconductor chips 1503A and 1503B, respectively, and located at the mass center of the package structure, as viewed from a cross-sectional view. In some embodiments, the geometric center plane of semiconductor package structure 1800 coincides with the mass center plane, thereby effectively enhancing the mechanical strength of the semiconductor package and alleviating the previously described warping issue.

[0088] refer to Figure 19A and Figure 19B , Figure 19A and Figure 19B According to some embodiments of the present invention Figure 18 An enlarged view of a portion of the semiconductor package structure 1800 is shown in FIG. Figure 19A In FIG. 1 , a portion of the structural reinforcement layers 1505A and 1505B is placed between the semiconductor chip 1503A and the semiconductor chip 1503B. The first portion 1507A of the encapsulant has a continuous horizontal surface 1507t′ supporting the structural reinforcement layers 1505A and 1505B. Figure 19BFurther zoomed in on FIG, conductive filler 1603A for heat conduction is illustrated in first portion 1507A of the encapsulant. Because no planarization operation was applied to first portion 1507A of the encapsulant, conductive filler 1603A (particularly those near continuous horizontal surface 1507t') all retain their original shapes, e.g., spherical, elliptical, or needle-shaped. In contrast, conductive filler 1603B in second portion 1507B of the encapsulant (particularly those near top surface 1507t) exhibits cutoff characteristics, e.g., hemispherical or segmented elliptical shapes, due to the planarization operation applied thereto.

[0089] like Figure 19B As shown in FIG, metal layer 1505B′ and seed layer 1505A′ conform to sidewalls 1505s and a portion of top surface 1507t′ of semiconductor chip 1505A. Only seed layer 1505A′ conforms to sidewalls 1505s of semiconductor chip 1505B. By filling the recess at top surface 1507t′ of first portion 1507A with seed layer 1505A′ material, the surface roughness of first portion 1507A of the encapsulant can be observed at top surface 1507t′.

[0090] FIG. 20A to FIG. 20L 1 is a cross-sectional view of a semiconductor package structure 1800 during various intermediate manufacturing operations according to some embodiments of the present invention. Like reference numerals refer to substantially the same components or their equivalents and are not repeated here for the sake of brevity. Figures 20A to 20G For a description, please refer to Figures 8A to 8G The description of and is not repeated here for the sake of brevity. Figure 20H In, a photolithography operation is performed to remove the metal layer 1505B' above the second chip region 1503B'. For example, a photomask layer (not shown) may be patterned to cover the semiconductor chip 1503A and the associated first chip region 1503A', and to expose the second semiconductor chip 1503B and the associated second chip region 1503B'. An etching operation may then be performed to remove the metal layer 1505B' in the second chip region 1503B', thereby exposing the seed layer 1505A' in the second chip region 1503B'. After the photolithography operation, the second structural reinforcement layer 1505B above the second chip region 1503B' is thinner than the first structural reinforcement layer 1505A above the first chip region 1503A'. In Figure 20I In the embodiment, the second portion 1507B' of the encapsulant is formed on the first chip region 1503A' and the second chip region 1503B', covering the semiconductor chips 1503A, 1503B, and the corresponding first and second structural reinforcement layers 1505A and 1505B.

[0091] Similar to Figures 8I to 8K , Figure 20J An optional grinding operation is shown as being performed to expose the top surface 1503t' of the semiconductor chip 1503B from the second portion 1507B of the encapsulant. Figure 20K and Figure 20L In the embodiment, the carrier 500 is detached and the conductive ends 1506 are mounted to the conductive trace layer 1501. The semiconductor package structure 1800 is then formed after the chip saw operation. FIG. 20A to FIG. 20L In , the conductive trace layer is formed before chip bonding and is referred to herein as the chip last operation.

[0092] Figure 21 is a flow chart of a method for manufacturing a semiconductor package structure according to some embodiments of the present invention. The method includes operation 211, identifying a geometric center plane of the semiconductor package structure. Figure 23 As shown in , in some comparative embodiments of the present invention, the figure is a cross-sectional view of a semiconductor package structure, and a geometric center plane G can be determined to be at a half height H / 2 of the semiconductor package structure.

[0093] The method further includes operation 213 of calculating a center plane of mass of the semiconductor package structure having the structural reinforcement layer in the semiconductor package structure. Figure 22 , the figure shows sub-operations for operation 213, and Figure 24A In some comparative embodiments of the present invention, the diagram is a cross-sectional view of a semiconductor package structure, and the mass center plane M is calculated based on the volume and density of each main component of the semiconductor package structure. For example, the main components include a semiconductor chip 2403, a structural reinforcement layer 2405A, a sealing body 2407, a conductive bump 2402, an underfill 2404, a conductive trace layer 2401, and a conductive terminal 2406. Figure 24A Comparative examples and Figure 22 In operation 2131, the structural reinforcement layer 2405A is placed in the first position, or close to the top surface of the semiconductor chip 2403, and therefore, after calculation, the mass center plane M is at a level higher than the level of the geometric center plane G. Because according to operation 2132 and operation 2132A Figure 24A The center of mass plane M does not match the geometric center plane G, so the structural reinforcement layer 2405A is not determined to be placed at the first position previously used to calculate the center of mass plane M. Instead, a second position different from the first position is used to calculate the center of mass plane M at the location where the structural reinforcement layer is placed.

[0094] The method further includes an operation 215 of determining the position of the structural reinforcement layer by matching the mass center plane with the geometric center plane. Figure 24BIn some embodiments of the present invention, the figure is a cross-sectional view of a semiconductor package structure, and the structural reinforcement layer 2405B is placed in the second position, or a position close to the bottom surface of the semiconductor chip 2403. Therefore, after calculation, the mass center plane M is at a level that matches the level of the geometric center plane G. Because according to operation 2132 and operation 2132B, Figure 24B The mass center plane M matches the geometric center plane G, so the structural reinforcement layer 2405A is determined to be placed at the second position previously used to calculate the mass center plane M. Figure 24B The embodiments described in Figure 24A The bending problem can be better reduced than the comparative embodiment illustrated in FIG, as previously described herein.

[0095] Figure 25 Also shown is a semiconductor package structure having its geometric center plane G matching its mass center plane M. A structural reinforcement layer 2505 is placed at the corresponding mass center plane M. The bottom surface of the structural reinforcement layer 2505 contacts the conductive trace layer 2501 , and the top surface of the structural reinforcement layer 2505 contacts the encapsulant 2507 .

[0096] As used herein and not otherwise defined, the terms "substantially," "essentially," "approximately," and "about" are used to describe and take into account minor variations. When used in conjunction with an event or circumstance, the terms may encompass situations where the event or circumstance definitely occurs as well as situations where the event or circumstance is very approximately likely to occur. For example, when used in conjunction with a numerical value, the terms may encompass a range of variation of less than or equal to ±10% of the numerical value, e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces that are positioned along the same plane within a few microns, e.g., within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm positioned along the same plane.

[0097] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass both the case where the former component is directly on (e.g., physically in contact with) the latter component and the case where one or more intermediate components are located between the former and the latter component.

[0098] Although the present invention has been described and illustrated with reference to specific embodiments of the present invention, these descriptions and illustrations are not restrictive. Those skilled in the art will understand that various changes may be made and equivalents substituted without departing from the true spirit and scope of the present invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction of the present invention and the actual device. There may be other embodiments of the present invention that are not specifically described. This specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of operations are not restrictive.

Claims

1. A semiconductor package structure, comprising: a conductive trace layer; a semiconductor chip overlying the conductive trace layer; a structural reinforcement layer surrounding the semiconductor chip; a sealing body covering the semiconductor chip and the structural reinforcement layer, The structural reinforcement layer coincides with a mass center plane of the semiconductor package structure, the mass center plane is parallel to the top surface of the semiconductor chip, and the mass center plane of the semiconductor package structure coincides with a geometric center plane of the semiconductor package structure. 2 . The semiconductor package structure according to claim 1 , wherein the geometric center plane is parallel to the top surface of the semiconductor chip. 3 . The semiconductor package structure according to claim 1 , wherein a hardness of the structural reinforcement layer is greater than a hardness of the conductive trace layer. 4 . The semiconductor package structure according to claim 1 , further comprising a first encapsulant under the structural reinforcement layer and a second encapsulant above the structural reinforcement layer. The semiconductor package structure according to claim 1 , wherein the conductive trace layer is a redistribution layer. The semiconductor package structure according to claim 1 , wherein a top surface of the structural reinforcement layer is lower than the top surface of the semiconductor chip. 7 . The semiconductor package structure according to claim 1 , wherein a sidewall of the semiconductor chip and a sidewall of the structural reinforcement layer are separated by the encapsulant.

8. A semiconductor package structure, comprising: a conductive trace layer; a first semiconductor chip electrically coupled to the conductive trace layer; a first structural reinforcement layer surrounding a sidewall of the first semiconductor chip; as well as a sealing compound covering the first semiconductor chip and the first structural reinforcement layer; The top surface of the first semiconductor chip is exposed from the encapsulation body, wherein the first structural reinforcement layer in the first semiconductor chip region coincides with a first mass center plane of the semiconductor package structure, the first mass center plane is parallel to the top surface of the first semiconductor chip, and wherein the first mass center plane of the semiconductor package structure coincides with a geometric center plane of the semiconductor package structure.

9. The semiconductor package structure according to claim 8, further comprising: a second semiconductor chip electrically coupled to the conductive trace layer; a second structural reinforcement layer surrounding the second semiconductor chip; as well as The encapsulant covers the second semiconductor chip and the second structural reinforcement layer. 10 . The semiconductor package structure according to claim 9 , wherein the second structural reinforcement layer coincides with a second mass center plane of the semiconductor package structure in a second semiconductor chip region, the second mass center plane being parallel to the top surface of the second semiconductor chip. 11 . The semiconductor package structure according to claim 9 , wherein a thickness of the first semiconductor chip is greater than a thickness of the second semiconductor chip. 12 . The semiconductor package structure according to claim 11 , wherein a thickness of the first structural reinforcement layer is thinner than a thickness of the second structural reinforcement layer.

13. The semiconductor package structure according to claim 9, further comprising: a first sealing compound, which is below the first structural reinforcement layer and the second structural reinforcement layer; as well as A second encapsulant is located on the first structural reinforcement layer and the second structural reinforcement layer. 14 . The semiconductor package structure according to claim 9 , wherein the first structural reinforcement layer comprises a seed layer and a plated metal layer at the sidewalls and top surface of the first semiconductor chip. 15 . The semiconductor package structure according to claim 14 , wherein the second structural reinforcement layer comprises a seed layer at the sidewall of the second semiconductor chip.

16. A method for manufacturing a semiconductor package structure, comprising: providing a conductive trace layer; placing a semiconductor chip on the conductive trace layer; as well as A structural reinforcement layer is placed at a mass center plane of the semiconductor package structure and surrounds the semiconductor chip, wherein the mass center plane of the semiconductor package structure coincides with a geometric center plane of the semiconductor package structure.

17. The method of claim 16, wherein the structural reinforcement layer is positioned at the center-of-mass plane by a lamination operation.

18. The method of claim 16, wherein positioning the structural reinforcement layer at the center-of-mass plane comprises: depositing a seed layer in contact with the sidewalls and top surface of the semiconductor chip; as well as A metal layer is plated on top of the seed layer.

19. The method of claim 16, further comprising: disposing a first semiconductor chip and a second semiconductor chip over the conductive trace layer, the first semiconductor chip being thicker than the second semiconductor chip; as well as A first structural reinforcement layer is placed around the first semiconductor chip and a second structural reinforcement layer is placed around the second semiconductor chip, the first structural reinforcement layer being thinner than the second structural reinforcement layer.

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