Bias circuit, bias current adjustment method and input receiver

Abstract

The present invention provides a bias circuit, a bias current adjustment method and an input receiver. The bias circuit includes a first transistor, a second transistor, a first fixed resistor and an amplifier. The first transistor is respectively connected to a power supply voltage and a gate of the first transistor, and the gate of the first transistor is connected to a bias voltage; the second transistor is connected to the first transistor; one end of the first fixed resistor is connected to the second transistor, and the other end of the first fixed resistor is grounded; the amplifier is respectively connected to a common-mode reference voltage, the first fixed resistor and the gate of the second transistor; the input end of the amplifier is connected to the common-mode reference voltage and one end of the first fixed resistor, and the output end of the amplifier is connected to the gate of the second transistor; the sum of the common-mode reference voltage and the reference voltage is a set value. In the present invention, when the input frequency is high, the reference voltage is reduced, the common-mode reference voltage is increased, and the bias current is increased, thereby improving the response speed of the input receiving circuit.

Description

Technical Field

[0001] The invention relates to a semiconductor memory, and in particular to a bias circuit, a bias current adjustment method and an input receiver. Background Art

[0002] In the application field of LPDDR4 (Low Power Double Data Rate SDRAM 4), LVSTL (Low Voltage Swing Terminated Logic) is adopted as the high-speed interface standard.

[0003] According to the LVSTL standard, there is only one on-chip termination resistor (ODT On DieTerminator) to ground (VSSQ), so during data transmission, the swing of the input waveform is between ground and the output resistor and the ODT voltage divider value. Figure 1 As shown in the figure, when the conversion rate (slew rate) is only within a certain range, the swing (swing) of the low-frequency signal at the input end will become larger, and the swing (swing) center point will also become higher, and the swing (swing) of the high-frequency signal at the input end will become smaller, and the swing (swing) center point will also become lower, so the reference voltage (vref) of the input receiver (input buffer) must also be changed accordingly to obtain the best signal reception effect. Since the memory controller can set different output drive capabilities and output high levels, the input signal swing received by LPDDR4 is very small, but the common-mode bias voltage of the input signal will vary greatly. Therefore, when the input receiving circuit works in a wide common-mode input range, the accuracy and sensitivity will be affected, and the power consumption requirement will increase with the different input common-mode bias voltages. Summary of the invention

[0004] The present invention provides a bias circuit, a bias current adjustment method and an input receiver to solve one or more technical problems in the above prior art.

[0005] To achieve the above object, the present invention provides a bias circuit in a first aspect, comprising:

[0006] a first transistor, wherein one end of the first transistor is connected to a power supply voltage, a gate of the first transistor is connected to a bias voltage (VBIAS), the other end of the first transistor is connected to the gate of the first transistor, the first transistor is used to output a bias current to an input receiving circuit, and an operating frequency of an input signal in the input receiving circuit is negatively correlated with a reference voltage (VREF);

[0007] a second transistor, one end of the second transistor being connected to the other end of the first transistor;

[0008] a first fixed value resistor, one end of the first fixed value resistor is connected to the other end of the second transistor, and the other end of the first fixed value resistor is grounded;

[0009] an amplifier, wherein a first input terminal of the amplifier is connected to a common mode reference voltage (VCOM), a second input terminal of the amplifier is connected to one end of the first fixed value resistor, an output terminal of the amplifier is connected to a gate of the second transistor, and the amplifier is used to amplify the common mode reference voltage so that the bias circuit generates the bias current;

[0010] The sum of the common-mode reference voltage in the bias circuit and the reference voltage in the input receiving circuit is a set value.

[0011] In one embodiment, the bias circuit further includes:

[0012] A third transistor, one end of the third transistor is connected to the other end of the first transistor, the other end of the third transistor is connected to the other end of the second transistor, and a gate of the third transistor is connected to the common mode reference voltage.

[0013] In one embodiment, the bias circuit further includes:

[0014] A fourth transistor, wherein the fourth transistor is arranged on a line connecting the other end of the first transistor and the gate of the first transistor, one end of the fourth transistor is connected to the other end of the first transistor, the gate of the fourth transistor is connected to the reference voltage, the other end of the fourth transistor is respectively connected to the gate of the first transistor, one end of the second transistor and one end of the third transistor, and the fourth transistor and the transistor in the input receiving circuit for accessing the reference voltage are transistors of the same type and size.

[0015] In one implementation, the bias circuit further includes a voltage regulator, the voltage regulator is used to adjust the voltage values ​​of the common-mode reference voltage and the reference voltage, and the voltage regulator includes:

[0016] A selection module, the selection module includes a plurality of selection units, the selection units include a first NOR gate, a second NOR gate, a NAND gate and a NOT gate, the first NOR gate and the second NOR gate each have at least three input terminals, the output terminals of the first NOR gate and the second NOR gate are both connected to the input terminals of the NAND gate, and the output terminal of the NAND gate is connected to the input terminal of the NOT gate;

[0017] A voltage divider module, the voltage divider module includes a plurality of second fixed value resistors connected in series, a first multiplexer and a second multiplexer; one end of the first second fixed value resistor is connected to a reference voltage (VDD2), and one end of the last second fixed value resistor is grounded; an input end of the first multiplexer is connected between each adjacent two second fixed value resistors, the first multiplexer is connected to the selection unit, and the first multiplexer is used to obtain the reference voltage (VREF) of the first value according to the selection unit; an input end of the second multiplexer is connected between each adjacent two second fixed value resistors, the second multiplexer is connected to the selection unit, and the second multiplexer is used to obtain the common mode reference voltage (VCOM) of the second value according to the selection unit.

[0018] In one implementation, the set value is 50% of the reference voltage, the first value includes 10% to 42% of the reference voltage, the second value includes 8% to 40% of the reference voltage, and the sum of the first value and the second value is 50% of the reference voltage.

[0019] In one embodiment, the first transistor is a PMOS transistor; the source of the first transistor is connected to a power supply voltage;

[0020] The second transistor is an NMOS transistor, and the drain of the second transistor is connected to the drain of the first transistor;

[0021] The third transistor is a PMOS transistor, the source of the third transistor is connected to the drain of the first transistor, and the drain of the third transistor is connected to the source of the second transistor;

[0022] The fourth transistor is a PMOS transistor, the source of the fourth transistor is connected to the drain of the first transistor, and the drain of the fourth transistor is respectively connected to the gate of the first transistor, the drain of the second transistor and the source of the third transistor.

[0023] In one embodiment, the bias circuit further includes:

[0024] A fifth transistor, one end of the fifth transistor is connected to the power supply voltage, the gate of the fifth transistor is connected to the common mode reference voltage (VCOM), the other end of the fifth transistor is connected to one end of the first fixed resistor, and the fifth transistor is used to provide additional bias current to compensate for process deviations.

[0025] In one implementation, the fifth transistor is a PMOS transistor; the source of the fifth transistor is connected to the power supply voltage, and the drain of the fifth transistor is connected to one end of the first fixed resistor.

[0026] To achieve the above object, the second aspect of the present invention provides a bias current adjustment method, comprising:

[0027] adjusting a voltage value of a reference voltage (VREF) according to a frequency of an input signal input to a receiving circuit;

[0028] According to the voltage value adjusted by the reference voltage, the voltage value of the common mode reference voltage (VCOM) in the bias circuit is adjusted; wherein the sum of the reference voltage (VREF) and the common mode reference voltage (VCOM) is the set value;

[0029] A bias current is generated according to a voltage value of the common mode reference voltage (VCOM), and the bias current is input to the input receiving circuit.

[0030] In one implementation, the specific step of adjusting the voltage value of the common-mode reference voltage in the bias circuit according to the voltage value adjusted by the reference voltage includes:

[0031] Inputting the decoded signal of the input signal into each group of selection units to obtain a plurality of selection signals;

[0032] A selection signal is received to determine that the reference voltage is adjusted to a first value, and a second value of the common mode reference voltage is selected; wherein the sum of the first value and the second value is a 50% reference voltage.

[0033] To achieve the above objective, a third aspect of the present invention provides an input receiver, comprising the bias circuit as described in the above embodiment.

[0034] The present invention adopts the above technical solution and has the following advantages: when the input frequency is high, the reference voltage of the input receiving circuit is reduced, the common-mode reference voltage is increased, and the bias current passing through the same first fixed resistor in the bias circuit is increased through the amplifier, thereby improving the response speed of the input receiving circuit.

[0035] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present invention will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present invention and should not be regarded as limiting the scope of the present invention.

[0037] Figure 1is the swing curve of the frequency signal at the input end in the background technology;

[0038] Figure 2 is a schematic diagram of a bias circuit in an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the connection between the bias circuit and the input receiving circuit in an embodiment of the present invention;

[0040] Figure 4 is a schematic diagram of another bias circuit connected to an input receiving circuit in an embodiment of the present invention;

[0041] Figure 5 is a schematic diagram of a power node adjustment module in an embodiment of the present invention;

[0042] Figure 6 is a circuit diagram of a selection module in an embodiment of the present invention;

[0043] Figure 7 is a circuit diagram of a voltage divider module in an embodiment of the present invention;

[0044] Figure 8 is a flow chart of a bias current adjustment method in an embodiment of the present invention;

[0045] Fig. 9 4 is another flow chart of the bias current adjustment method in the embodiment of the present invention.

[0046] Reference numerals:

[0047] 110 first transistor;

[0048] 120 second transistor;

[0049] 130 third transistor;

[0050] 140 first fixed value resistor;

[0051] 150 amps;

[0052] 160 fourth transistor;

[0053] 170 Voltage regulator;

[0054] 171 Select Module;

[0055] 171a Select Unit;

[0056] 171b First NOR gate;

[0057] 171c Second NOR gate;

[0058] 171d NAND gate;

[0059] 171e NOT gate;

[0060] 172 voltage divider module;

[0061] 172a a second fixed value resistor;

[0062] 172b first multiplexer;

[0063] 172c second multiplexer;

[0064] 180 Fifth Transistor;

[0065] 200 input receiving circuit;

[0066] 210 first PMOS tube;

[0067] 220 second PMOS tube;

[0068] 230 the third PMOS tube;

[0069] 240 first NMOS tube;

[0070] 250 second NMOS tube;

[0071] 260 data input terminal;

[0072] 270 Data output terminal. DETAILED DESCRIPTION

[0073] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0074] A first aspect of this embodiment provides a bias circuit.

[0075] See also Figure 2 As shown, the bias circuit includes a first transistor 110 , a second transistor 120 , a first fixed resistor 140 and an amplifier 150 .

[0076] One end of the first transistor 110 is connected to the power supply voltage, the gate of the first transistor 110 is connected to the bias voltage, the other end of the first transistor 110 is connected to the gate of the first transistor 110, and the first transistor 110 is used to output a bias current to the input receiving circuit 200. The operating frequency of the input signal in the input receiving circuit 200 is negatively correlated with the reference voltage.

[0077] One end of the second transistor 120 is connected to the other end of the first transistor 110 .

[0078] One end of the first fixed resistor 140 is connected to the other end of the second transistor 120 , and the other end of the first fixed resistor 140 is grounded.

[0079] A first input terminal of the amplifier 150 is connected to a common mode reference voltage (VCOM), a second input terminal of the amplifier 150 is connected to one end of the first fixed resistor 140 , and an output terminal of the amplifier 150 is connected to the gate of the second transistor 120 .

[0080] The sum of the common mode reference voltage and the reference voltage of the input receiving circuit 200 is the set value. Further, the first transistor 110 is a PMOS transistor; the source of the first transistor 110 is connected to the power supply voltage.

[0081] The second transistor 120 is an NMOS transistor, and a drain of the second transistor 120 is connected to a drain of the first transistor 110 .

[0082] In one embodiment, see Figure 3 As shown, one structure of the input receiving circuit 200 includes a first PMOS transistor 210 , a second PMOS transistor 220 , a third PMOS transistor 230 , a first NMOS transistor 240 and a second NMOS transistor 250 .

[0083] The source of the first PMOS transistor 210 is connected to the power supply voltage, and the gate of the first PMOS transistor 210 is connected to the gate of the first transistor 110 and is connected to the bias voltage. The source of the second PMOS tube 220 is connected to the drain of the first PMOS tube 210, the source of the third PMOS tube 230 is connected to the drain of the first PMOS tube 210, the gate of the second PMOS tube 220 is used as the data input terminal 260 to input the signal, the gate of the third PMOS tube 230 is connected to the reference voltage, the drain of the first NMOS tube 240 is connected to the drain of the second PMOS tube 220, the gate of the first NMOS tube 240 is connected to the drain of the first NMOS tube 240, the source of the first NMOS tube 240 is grounded, the drain of the second NMOS tube 250 is connected to the drain of the third PMOS tube 230, the gate of the second NMOS tube 250 is connected to the gate of the first NMOS tube 240, the source of the second NMOS tube 250 is grounded, and a point of the connection line between the drain of the second NMOS tube 250 and the drain of the third PMOS tube 230 is selected as the data output terminal 270 to output the signal. The circuit structure of the input receiver 200 is not unique, and the above is only a preferred embodiment.

[0084] According to the LVSTL standard, the swing of a high-frequency input signal becomes smaller, while the swing of a low-frequency input signal increases, so the input receiver needs to reduce the reference voltage when receiving a high-frequency signal.

[0085] It can be seen that the relationship between the reference voltage and the operating frequency defined by the internal register of LPDDR4 satisfies:

[0086] The lower the reference voltage, the higher the operating frequency.

[0087] In this embodiment, when the input frequency is high, the reference voltage of the input receiving circuit is reduced, and the common-mode reference voltage is increased, and the bias current passing through the first constant resistor 140 in the bias circuit is increased through the amplifier 150, thereby improving the response speed of the input receiving circuit.

[0088] In one embodiment, see Figure 4 As shown, the bias circuit further includes a third transistor 130 .

[0089] The third transistor 130 is a PMOS transistor. The source of the third transistor 130 is connected to the drain of the first transistor 110 , and the drain of the third transistor 130 is connected to the source of the second transistor 120 .

[0090] In one embodiment, see Figure 4 As shown, the bias circuit further includes a fourth transistor 160 .

[0091] The fourth transistor 160 is arranged on a line connecting the other end of the first transistor 110 and the gate of the first transistor 110, one end of the fourth transistor 160 is connected to the other end of the first transistor 110, the gate of the fourth transistor 160 is connected to the reference voltage VREF, the other end of the fourth transistor 160 is respectively connected to the gate of the first transistor 110, one end of the second transistor 120 and one end of the third transistor 130, and the fourth transistor 160 and the transistor used to access the reference voltage in the input receiving circuit 200 are transistors of the same type and size.

[0092] Furthermore, the fourth transistor 160 is a PMOS transistor, the source of the fourth transistor 160 is connected to the drain of the first transistor 110 , and the drain of the fourth transistor 160 is respectively connected to the gate of the first transistor 110 , the drain of the second transistor 120 , and the source of the third transistor 130 .

[0093] In this embodiment, the fourth transistor 160 and the transistor connected to the reference voltage in the input receiving circuit 200 are MOS tubes of the same type and size, and the same size, so that when both are in the same working state, the input receiving circuit is in the best working state.

[0094] In one embodiment, the bias circuit further includes a voltage regulator 170 .

[0095] The voltage regulator 170 is used to adjust the voltage values ​​of the common mode reference voltage and the reference voltage. Figure 5As shown, the voltage regulator 170 includes a selection module 171 and a voltage division module 172 .

[0096] See also Figure 6 As shown, the selection module 171 includes multiple selection units 171a, and the selection unit 171a includes a first NOR gate 171b, a second NOR gate 171c, a NAND gate 171d and a NOT gate 171e. The first NOR gate 171b and the second NOR gate 171c each have at least three input terminals, and the output terminals of the first NOR gate 171b and the second NOR gate 171c are both connected to the input terminal of the NAND gate 171d, and the output terminal of the NAND gate 171d is connected to the input terminal of the NOT gate 171e. The output terminals of the NOT gates 171e of the multiple selection units 171a are connected to a node as the output terminal of the selection module 171.

[0097] See also Figure 7 As shown, the voltage divider module 172 includes a plurality of second fixed-value resistors 172a connected in series, a first multiplexer 172b and a second multiplexer 172c; one end of the first second fixed-value resistor 172a is connected to the reference voltage, and one end of the last second fixed-value resistor 172a is grounded; the input end of the first multiplexer 172b is connected between the lines between each adjacent two second fixed-value resistors 172a, the first multiplexer 172b is connected to the selection unit 171a, and the first multiplexer 172b is used to obtain a reference voltage of a first value according to the selection unit 171a, the input end of the second multiplexer 172c is connected between the lines between each adjacent two second fixed-value resistors 172a, the second multiplexer 172c is connected to the selection unit 171a, and the second multiplexer 172c is used to obtain a common-mode reference voltage of a second value according to the selection unit 171a.

[0098] Further, the set value is 50% of the reference voltage, the first value includes 10% to 42% of the reference voltage, the second value includes 8% to 40% of the reference voltage, and the sum of the first value and the second value is 50% of the reference voltage.

[0099] In this embodiment, the voltage regulator 170 is used to keep the sum of the reference voltage and the common-mode reference voltage constant, so that when the reference voltage changes according to the input signal frequency, the common-mode reference voltage is inversely proportional to it, so that the bias circuit provides an optimal bias current, thereby improving the response performance of the input receiving circuit 200.

[0100] In one embodiment, see Figure 4 As shown, the bias circuit further includes a fifth transistor 180 .

[0101] One end of the fifth transistor 180 is connected to the power supply voltage, the gate of the fifth transistor 180 is connected to the common mode reference voltage, the other end of the fifth transistor 180 is connected to one end of the first fixed resistor 140, and the fifth transistor 180 is used to provide additional bias current to compensate for process deviation.

[0102] Furthermore, the fifth transistor 180 is a PMOS transistor; the source of the fifth transistor 180 is connected to the power supply voltage, and the drain of the fifth transistor 180 is connected to one end of the first fixed resistor 140 .

[0103] The fifth transistor 180 provided in this embodiment is used for providing an additional bias current to compensate for the process deviation when the process tends to be slow and the bias current is smaller than the calculated value in a typical case.

[0104] A second aspect of the embodiment provides a bias current adjustment method.

[0105] See also Figure 8 As shown, the adjustment methods include:

[0106] Step S110: adjusting the voltage value of the reference voltage according to the frequency of the input signal input to the receiving circuit.

[0107] Step S120: adjusting the voltage value of the common-mode reference voltage (VCOM) in the bias circuit according to the voltage value adjusted by the reference voltage, wherein the sum of the reference voltage and the common-mode reference voltage is the set value.

[0108] Step S130: Generate a bias current according to the voltage value of the common-mode reference voltage, and input the bias current to the input receiving circuit. In this embodiment, when the input frequency is high, the reference voltage of the input receiving circuit becomes lower, thereby increasing the common-mode reference voltage, increasing the bias current passing through the same resistor in the bias circuit, and thus improving the response speed of the input receiving circuit.

[0109] In one embodiment, see Fig. 9 As shown, the specific steps of step 120 for adjusting the voltage value of the common-mode reference voltage in the bias circuit according to the voltage value adjusted by the reference voltage include:

[0110] Step S121: inputting the decoded signal of the input signal into each group of selection units to obtain a plurality of selection signals;

[0111] Step S122: receiving a selection signal to determine that the reference voltage is adjusted to a first value, and selecting a common-mode reference voltage of a second value; wherein the sum of the first value and the second value is a 50% reference voltage.

[0112] A third aspect of the embodiment provides an input receiver, wherein the input receiver comprises the bias circuit in the above embodiment.

[0113] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of various changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0114] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0115] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0116] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0117] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0118] The disclosure above provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described above. Of course, they are merely examples, and the purpose is not to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art may appreciate the application of other processes and / or the use of other materials.

Claims

1. A bias circuit, characterized in that: include: a first transistor, one end of the first transistor is connected to a power supply voltage, a gate of the first transistor is connected to a bias voltage, the other end of the first transistor is connected to the gate of the first transistor, the first transistor is used to output a bias current to an input receiving circuit, and an operating frequency of an input signal in the input receiving circuit is negatively correlated with a reference voltage; a second transistor, one end of the second transistor being connected to the other end of the first transistor; a first fixed value resistor, one end of the first fixed value resistor is connected to the other end of the second transistor, and the other end of the first fixed value resistor is grounded; an amplifier, wherein a first input terminal of the amplifier is connected to a common-mode reference voltage, a second input terminal of the amplifier is connected to one end of the first fixed resistor, an output terminal of the amplifier is connected to a gate of the second transistor, and the amplifier is used to amplify the common-mode reference voltage so that the bias circuit generates the bias current; The sum of the common-mode reference voltage in the bias circuit and the reference voltage in the input receiving circuit is a set value.

2. The bias circuit according to claim 1, wherein: The bias circuit further comprises: A third transistor, one end of the third transistor is connected to the other end of the first transistor, the other end of the third transistor is connected to the other end of the second transistor, and a gate of the third transistor is connected to the common mode reference voltage.

3. The bias circuit according to claim 2, wherein: The bias circuit further comprises: A fourth transistor, wherein the fourth transistor is arranged on a line connecting the other end of the first transistor and the gate of the first transistor, one end of the fourth transistor is connected to the other end of the first transistor, the gate of the fourth transistor is connected to the reference voltage, the other end of the fourth transistor is respectively connected to the gate of the first transistor, one end of the second transistor and one end of the third transistor, and the fourth transistor and the transistor in the input receiving circuit for accessing the reference voltage are transistors of the same type and size.

4. The bias circuit according to claim 3, wherein: The bias circuit further includes a voltage regulator, which is used to adjust the voltage values ​​of the common-mode reference voltage and the reference voltage, and the voltage regulator includes: A selection module, the selection module includes a plurality of selection units, the selection units include a first NOR gate, a second NOR gate, a NAND gate and a NOT gate, the first NOR gate and the second NOR gate each have at least three input terminals, the output terminals of the first NOR gate and the second NOR gate are both connected to the input terminals of the NAND gate, and the output terminal of the NAND gate is connected to the input terminal of the NOT gate; A voltage divider module, the voltage divider module includes a plurality of second fixed value resistors connected in series, a first multiplexer and a second multiplexer; one end of the first second fixed value resistor is connected to a reference voltage, and one end of the last second fixed value resistor is grounded; the input end of the first multiplexer is connected between each adjacent two second fixed value resistors, the first multiplexer is connected to the selection unit, the first multiplexer is used to obtain the reference voltage of the first value according to the selection unit, the input end of the second multiplexer is connected between each adjacent two second fixed value resistors, the second multiplexer is connected to the selection unit, and the second multiplexer is used to obtain the common-mode reference voltage of the second value according to the selection unit.

5. The bias circuit according to claim 4, wherein: The set value is 50% of the reference voltage, the first value includes 10% to 42% of the reference voltage, the second value includes 8% to 40% of the reference voltage, and the sum of the first value and the second value is 50% of the reference voltage.

6. The bias circuit according to claim 5, wherein: The first transistor is a PMOS transistor; the source of the first transistor is connected to a power supply voltage; The second transistor is an NMOS transistor, and the drain of the second transistor is connected to the drain of the first transistor; The third transistor is a PMOS transistor, the source of the third transistor is connected to the drain of the first transistor, and the drain of the third transistor is connected to the source of the second transistor; The fourth transistor is a PMOS transistor, the source of the fourth transistor is connected to the drain of the first transistor, and the drain of the fourth transistor is respectively connected to the gate of the first transistor, the drain of the second transistor and the source of the third transistor.

7. The bias circuit according to claim 5, wherein: The bias circuit further comprises: A fifth transistor, one end of the fifth transistor is connected to the power supply voltage, the gate of the fifth transistor is connected to the common-mode reference voltage, the other end of the fifth transistor is connected to one end of the first fixed resistor, and the fifth transistor is used to provide additional bias current to compensate for process deviations.

8. The bias circuit according to claim 7, wherein: The fifth transistor is a PMOS transistor; the source of the fifth transistor is connected to the power supply voltage, and the drain of the fifth transistor is connected to one end of the first fixed resistor.

9. A bias current adjustment method, characterized in that: include: adjusting a voltage value of a reference voltage according to a frequency of an input signal input to a receiving circuit; According to the voltage value adjusted by the reference voltage, the voltage value of the common-mode reference voltage in the bias circuit is adjusted; wherein the sum of the reference voltage and the common-mode reference voltage is the set value; A bias current is generated according to a voltage value of the common mode reference voltage, and the bias current is input to the input receiving circuit.

10. The adjustment method according to claim 9, characterized in that: The specific steps of adjusting the voltage value of the common-mode reference voltage in the bias circuit according to the voltage value adjusted by the reference voltage include: Inputting the decoded signal of the input signal into each group of selection units to obtain a plurality of selection signals; A selection signal is received to determine that the reference voltage is adjusted to a first value, and a second value of the common mode reference voltage is selected; wherein the sum of the first value and the second value is a 50% reference voltage.

11. An input receiver, characterized in that Comprising a bias circuit as described in any one of claims 1-8.

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