Methods and apparatuses for encoding and decoding data in a memory system

Abstract

A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a syndrome stage for generating a syndrome based on a BCH coded word, a Berlekamp-Massey stage for performing a Berlekamp-Massey (BM) algorithm on the syndrome to generate error location polynomial (ELP) coefficients, a Chien stage for performing a Chien search on the ELP coefficients using a fast Fourier transform (FFT) to generate error bits and iterative information, and a framer stage configured to reorder the error bits into an ordered frame based on the iterative information. The BCH decoder decodes the BCH coded word using the reordered error bits.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept relate to methods and apparatuses for encoding and decoding data in a memory system. Background Art

[0002] NAND flash memory is an example of Electrically Erasable And Programmable Read Only Memory (EEPROM). By using a group of NAND cell units in which multiple memory cells are connected in series with each other, NAND flash memory can store a large amount of information in a small chip area.

[0003] When storing data at a memory device and reading the stored data from the memory device, errors may occur. Various error correction codes can be used to detect and correct such errors. Error correction codes may include Reed-Solomon (RS) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, Low Density Parity Check (LDPC) codes, and the like. Summary of the Invention

[0004] According to an exemplary embodiment of the inventive concept, a decoding circuit including a Bose-Chaudhuri-Hocquenghem (BCH) decoder is provided. The BCH decoder includes a syndrome stage for generating a syndrome based on a BCH codeword, a Berlekamp-Massey stage for performing a Berlekamp-Massey (BM) algorithm on the syndrome to generate Error Location Polynomial (ELP) coefficients, a Chien stage for performing a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iterative information, and a frame restorer stage configured to reorder the error bits into an ordered sequence based on the iterative information. The BCH decoder decodes the BCH codeword using the reordered error bits.

[0005] According to an exemplary embodiment of the inventive concept, a method for decoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword is provided. The method includes: generating a syndrome based on the BCH codeword; performing a Berlekamp-Massey algorithm on the syndrome to generate error location polynomial (ELP) coefficients; performing a Chien search on the ELP coefficients using a fast Fourier transform (FFT) to generate error bits and iteration information; reordering the error bits into an ordered sequence based on the iteration information; and decoding the BCH codeword using the reordered error bits.

[0006] According to an exemplary embodiment of the inventive concept, a decoding circuit including a Bose-Chaudhuri-Hocquenghem (BCH) decoder is provided. The BCH decoder includes: a syndrome stage configured to generate a syndrome based on the BCH codeword; a Berlekamp-Massey stage that performs a Berlekamp-Massey algorithm on the syndrome to generate error location polynomial (ELP) coefficients; a first fast Fourier transform (FFT) stage that iteratively performs a first FFT operation on the ELP coefficients to generate a first result; a second FFT stage that iteratively performs a second FFT operation on the first result to generate a second result; and a logic circuit configured to generate error bits from the second result. The BCH decoder decodes the BCH codeword using the error bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0008] Figure 1 A diagram showing a memory system according to an exemplary embodiment of the inventive concept is shown;

[0009] Figure 2A A high-level block diagram of an SBCH encoder according to an exemplary embodiment of the inventive concept is shown;

[0010] Figure 2B Coded data that can be output by the SBCH encoder is shown;

[0011] Figure 3 A high-level block diagram of an SBCH decoder according to an exemplary embodiment of the inventive concept is shown;

[0012] Figure 4 An output buffer according to an exemplary embodiment of the inventive concept that can be used in the SBCH decoder is shown;

[0013] Figure 5Shows an output buffer according to an exemplary embodiment of the inventive concept that can be used in an SBCH decoder;

[0014] Figure 6 Shows a BCH decoder of an SBCH encoder according to an exemplary embodiment of the inventive concept;

[0015] Figure 7 Shows the BM stage of a BCH decoder according to an exemplary embodiment of the inventive concept;

[0016] Figure 8 Shows the BM stage of a BCH decoder according to an exemplary embodiment of the inventive concept;

[0017] Figure 9 Shows a part of the BM stage according to an exemplary embodiment of the inventive concept; and

[0018] Figure 10 Shows the CS stage of a BCH decoder according to an exemplary embodiment of the inventive concept. Detailed Description

[0019] Example embodiments will now be described more fully with reference to the accompanying drawings. Many alternative forms can be embodied, and the example embodiments should not be construed as limited to the example embodiments set forth herein. In the drawings, like reference numerals refer to like elements.

[0020] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0021] As used herein, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0022] Unless otherwise specifically stated, or obvious from the discussion, terms such as "processing" or "operation" or "computing" or "determining" or "displaying" etc. refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical, electronic quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers of the computer system or other such information storage, transmission, or display devices.

[0023] In the following description, illustrative embodiments will be described with reference to the actions and symbolic representations of operations (e.g., in the form of flowcharts, process diagrams, data flow diagrams, structural diagrams, block diagrams, etc.), where the operations can be implemented as program modules or functional processes including routines, programs, objects, components, data structures, etc., which perform specific tasks or implement specific abstract data types, and can be implemented using existing hardware in existing electronic systems (e.g., non-volatile memory universal flash memory, universal flash memory controller, non-volatile memory and memory controller, digital autofocus camera, personal digital assistant (PDA), smartphone, tablet personal computer (PC), laptop computer, etc.). Such existing hardware can include one or more central processing units (CPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computers, etc.

[0024] Although a flowchart may describe operations as a sequential process, many operations can be performed in parallel, concurrently, or simultaneously. In addition, the order of operations can be rearranged. A process can be terminated when its operations are completed, but it can also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0025] As disclosed herein, the terms “storage medium,” “computer-readable storage medium,” or “non-transitory computer-readable storage medium” can represent one or more devices for storing data, including read-only memory (ROM), random access memory (RAM), magnetic RAM, core memory, disk storage media, optical storage media, flash memory devices, and / or other tangible machine-readable media for storing information. The term “computer-readable medium” can include, but is not limited to, portable or fixed storage devices, optical storage devices, and various other media capable of storing, containing, or carrying instructions and / or data.

[0026] In addition, the example embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments for performing the necessary tasks may be stored in a machine or computer-readable medium, such as a computer-readable storage medium. When implemented in software, one or more processors may be programmed to perform the necessary tasks, thereby being transformed into (a) dedicated processor(s) or (a) computer(s).

[0027] Figure 1 is a block diagram of a memory system to which a memory according to some embodiments of the inventive concept is applied. Referring to Figure 1 , the memory system 900 includes a memory controller 1000 and a non-volatile memory device 2000.

[0028] The non-volatile memory device 2000 may be, but is not limited to, a flash memory device, a NAND flash memory device, a phase change RAM (PRAM), a ferroelectric RAM (FRAM), a magnetic RAM (MRAM), etc. According to at least one example embodiment of the inventive concept, the non-volatile memory device 2000 may include a plurality of NAND flash memory devices. The non-volatile memory device 2000 may have a planar structure or a three-dimensional (3D) memory cell structure in which memory cells are stacked.

[0029] The non-volatile memory device 2000 may include a memory cell array 2100, an X decoder 121, a voltage generator 125, an I / O buffer 124, a page buffer 123, and a control logic 126, each of which may be implemented as one or more circuits. The memory device may also include input / output (I / O) pins (pad) 127.

[0030] The memory cell array 2100 includes a plurality of word lines W / L and a plurality of bit lines B / L. Each memory cell of the memory cell array 2100 may be implemented as a non-volatile memory cell. For example, each memory cell of the memory cell array 2100 may have, for example, a floating gate or a charge storage layer (such as a charge trapping layer).

[0031] The memory cell array 2100 may include a plurality of blocks and a plurality of pages. One block includes a plurality of pages. A page may be a unit of programming and reading operations, and a block may be a unit of erasing operations. For example, the memory cell array 2100 includes a first block 2120 and a second block 2130. As Figure 1 shown, the first block 2120 includes pages 1 - page N, and the second block 2130 includes pages 1 - page N, where N is a positive integer greater than 1.

[0032] The control logic 126 controls the overall operation of the non-volatile memory device 2000. When a command CMD is received from the memory controller 1000, the control logic 126 interprets the command CMD and controls the non-volatile memory device 2000 to perform an operation (e.g., a programming operation, a read operation, a read retry operation, or an erase operation) according to the interpreted command CMD.

[0033] The X decoder 121 is controlled by the control logic 126 and drives at least one of the word lines W / L in the memory cell array 2100 according to a row address.

[0034] The voltage generator 125 is controlled by the control logic 126 to generate one or more voltages required for a programming operation, a read operation, or an erase operation and supplies the generated voltages to one or more rows selected by the X decoder 121.

[0035] The register 128 is a space in which information input from the memory controller 1000 is stored and may include a plurality of latches. For example, the register 128 may group the read voltage information and store the information in a table form.

[0036] The page buffer 123 is controlled by the control logic 126 and operates as a sense amplifier or a write driver according to an operation mode (e.g., a read operation or a programming operation).

[0037] The I / O pins 127 and the I / O buffer 124 may be used as an I / O path for data exchanged between an external device (e.g., the memory controller 1000 or a host) and the non-volatile memory device 2000.

[0038] The memory controller 1000 may include a microprocessor 111, a read-only memory (ROM) 113, a random access memory (RAM) 112, an encoder 1100, a decoder 1200, a memory interface 116, and a bus 118. The elements 111 to 116 of the memory controller 1000 may be electrically connected to each other through the bus 118.

[0039] The microprocessor 111 controls the overall operation of the memory system 900 including the memory controller 1000. The microprocessor 111 is a circuit that controls other components by generating control signals. When power is supplied to the memory system 900, the microprocessor 111 drives firmware (e.g., stored in the ROM 113) for operating the memory system 900 on the RAM 112, thereby controlling the overall operation of the memory system 900. According to at least one exemplary embodiment of the inventive concept, the microprocessor 111 may also issue instructions for controlling the operation of other components of the memory controller 1000, where the other components include some or all of, for example, the ROM 113, the RAM 112, the encoder 1100, the decoder 1200, the memory interface 116, and the bus 118. According to at least one exemplary embodiment of the inventive concept, any operation described herein as being performed by the memory controller 1000 may be performed by the microprocessor 111 or under the control of the microprocessor 111. According to at least one exemplary embodiment of the inventive concept, any operation described herein as being performed by the memory controller 1000 may be performed by the microprocessor 111 or under the control of the microprocessor 111, where the microprocessor 111 executes instructions corresponding to the operation and included in program code (e.g., stored in the ROM 113).

[0040] Although the drive firmware code of the memory system 900 is stored in the ROM 113, one or more exemplary embodiments of the inventive concept are not limited thereto. The firmware code may also be stored in a part of the non-volatile memory device 2000 other than the ROM 113. Accordingly, the control or intervention of the microprocessor 111 may include not only the direct control of the microprocessor 111 but also the intervention of the firmware driven by the microprocessor 111 software.

[0041] The RAM 112, which serves as a buffer memory, may store initial commands, data, and various variables input from a host or the microprocessor 111, or data output from the non-volatile memory device 2000. The RAM 112 may store data input to and output from the non-volatile memory device 2000, as well as various parameters and variables.

[0042] The memory interface 116 may serve as an interface between the memory controller 1000 and the non-volatile memory device 2000. The memory interface 116 is connected to the I / O pins 127 of the non-volatile memory device 2000 and may exchange data with the I / O pins 127. In addition, the memory interface 116 may create commands suitable for the non-volatile memory device 2000 and provide the created commands to the I / O pins 127 of the non-volatile memory device 2000. The memory interface 116 provides a command to be executed by the non-volatile memory device 2000 and an address ADD of the non-volatile memory device 2000.

[0043] According to at least one exemplary embodiment of the inventive concept, the decoder 1200 may be an Error Correcting Code (ECC) decoder, and the encoder 1100 may be an ECC encoder. According to at least one exemplary embodiment of the inventive concept, the decoder 1200 and the encoder 1100 perform error bit correction. The encoder 1100 may generate data added with one or more parity bits and / or redundant bits by performing error correction encoding on the data before the data is provided to the non-volatile memory device 2000. One or more parity bits and / or redundant bits may be stored in the non-volatile memory device 2000.

[0044] The decoder 1200 may perform error correction decoding on the output data, determine whether the error correction decoding is successful based on the result of the error correction decoding, and output an instruction signal based on the determination result. The read data may be sent to the decoder 1200, and the decoder 1200 may use one or more parity bits and / or redundant bits to correct the error bits of the data. When the number of error bits exceeds the limit of the error bits that can be corrected, the decoder 1200 cannot correct the error bits, resulting in error correction failure. In an exemplary embodiment, the encoder 1100 and the decoder 1200 perform error correction using Super Bose-Chaudhuri-Hocquenghem (SBCH).

[0045] SBCH is a multilevel algebraic code composed of several short binary Bose-Chaudhuri-Hocquenghem (BCH) codes and non-binary Reed-Solomon (RS) codes. Contrary to the message passing decoding algorithm of low-density parity-check (LDPC) codes that requires iteratively exchanging a large amount of soft information between variable and check nodes, the decoding algorithm of SBCH codes is completely algebraic, using standard algebraic decoding modes for short component BCH codes and RS codes. For this reason, the power consumption of the SBCH decoder is much smaller than that of the corresponding LDPC decoder.

[0046] Figure 2A shows a high - level block diagram of the SBCH encoder of an encoder 1100 that can be used to implement Figure 1 .

[0047] The SBCH encoder includes an input control block 200 (e.g., an input control circuit) configured to receive a certain amount of data bits for encoding. For example, Figure 2A the input control block shown in i is configured to periodically receive 32 - bit input data from an input data bus. The input control block 200 applies the input data as an information part in

[0048] to a BCH encoder 201 (e.g., a systematic BCH encoder) and a multiplexer 203. i-1 in i in i+1 etc.). The BCH encoder 201 performs BCH encoding on each input information part (e.g., in BCH,i-1 P BCH,i P BCH,i+1 etc.). The BCH encoder 201 can support multiple BCH code rates with a fixed code length n and different numbers of parity bits. The BCH encoding results in the generation of BCH parity parts (e.g., P

[0049] The SBCH encoder also includes an adder (e.g., an adder circuit) 202 that generates SBCH parity (e.g., P BCH,i ) by adding the BCH parity part (e.g., P DSCi ) to the Delta - syndrome coset parity P SBCH,i-1 P SBCH,i P SBCH,i+1 etc.) output by the Delta - syndrome coset encoder 206 of the SBCH encoder. The Delta - syndrome coset encoder 206 generates the Delta - syndrome coset parity (e.g., P DSCi ) by performing an encoding operation on the Delta - syndrome coset DSi, where the Delta - syndrome coset DSi is generated from the previous Delta - syndrome value ds i-1 generated from the previous input information part in i-1,r .

[0050] The multiplexer 203 combines the current information part (e.g., in i ) with the SBCH parity (e.g., P SBCH,i ) to generate the current frame x i (e.g., a BCH codeword), where the current frame x i is output at a certain rate (e.g., 32 bits per cycle).

[0051] for a previous input information part in i-1 and the previous SBCH parity P SBCH,i-1 The Delta syndrome calculator 204 of the SBCH encoder is operated to generate a previous Delta syndrome value ds i-1,r which can be generated in a manner similar to the current Delta syndrome ds i,r according to Equation 1 below.

[0052]

[0053] The RS encoder 205 of the SBCH encoder calculates RS parity symbols according to the previous Delta syndrome value ds i defining the Delta syndrome coset DS i-1,r

[0054] The SBCH encoder continues frame by frame until all information parts have been processed. For example, if the information part is 4 KB in total, the SBCH encoder adds 472 bytes of additional parity data to create a result including multiple BCH codes.

[0055] Figure 2B shows an example of data encoded by the Figure 2A SBCH encoder. Figure 2B Each line in the data shown in is a frame.

[0056] Figure 3 shows a high-level block diagram of the SBCH decoder of the decoder 1200 that can be used to implement Figure 1

[0057] The input to the decoder can be an SBCH-encoded word read from a memory (e.g., NAND such as memory device 2000). The bits of the SBCH-encoded word can be referred to as hard decision bits. The input to the decoder can also include soft information from the memory (e.g., soft decision bits), where the soft information includes information about the reliability of each bit. When the SBCH decoder fails, the soft decision bits can be read.

[0058] The input control block (e.g., input control circuit) 300 of the decoder applies the hard decision bits to the hard decision buffer 301 of the decoder. If soft decision bits are available, the input control block 300 applies them to the soft decision buffer 302 of the decoder. The BCH decoder 304 (e.g., multi-rate BCH decoder) of the decoder reads data from the hard decision buffer 301 at a certain rate (e.g., 40 bits per cycle) and decodes the frame with a certain correction capability. As part of the BCH decoding, the BCH decoder 304 also reads the delta syndrome ds from the delta syndrome memory 305 of the decoder i,p ​​(p = 0…r). The result of BCH decoding by the BCH decoder 304 is written into the output buffer 308 at a certain rate (e.g., 40 bits per cycle).

[0059] The frames successfully decoded by the BCH decoder 304 are applied to the delta - syndrome calculator 306 of the decoder, which calculates all the delta syndromes ds i,r , and writes them into the delta - syndrome memory 305.

[0060] Once the BCH decoder stage is terminated, according to the decoding process, the required delta syndromes are read from the delta - syndrome memory 305 and applied to the RS decoder 307 of the decoder. In an embodiment, the RS decoder 307 processes (e.g., corrects) 2 delta - syndromes per cycle and writes the corrected delta - syndrome results back to the delta - syndrome memory 305.

[0061] Once the decoding is terminated, the corrected codeword (including parity bits) appears in the output buffer 308. The output control block 309 (e.g., output control circuit) can read from the output buffer 308 and output the original data (e.g., 4K information) at a certain rate.

[0062] When soft - decision bits are read from the memory, they are stored in the soft - decision buffer 302. The SBCH decoder 304 reads the soft - decision bits from the soft - decision buffer 302, and for bits with low reliability, it flips (from the hard - decision buffer 301) the word bits with a certain probability controlled by the pseudo - random (or random) number generator 303.

[0063] Figure 4 Shows the output buffer 308 of the Figure 3 SBCH decoder according to an exemplary embodiment of the inventive concept.

[0064] Figure 4The output buffer includes an even memory 401, an odd memory 402, a first multiplexer 403 (e.g., a 2-to-1 multiplexer), a first First-In-First-Out (FIFO) buffer 404, a plurality of second multiplexers 406 (e.g., 60-to-1 multiplexers), a buffer 409, a third multiplexer 410 (e.g., a 2-to-1 multiplexer), and a second FIFO 411. The BCH decoder 304 outputs a first quantity of data (e.g., 40 bits) to the output buffer. Each row of the even memory 401 and each row of the odd memory 402 stores three times the first quantity (e.g., 120 bits). The even memory 401 and the odd memory 402 each include multiple rows. For ease of discussion, it is assumed that the first quantity is 40 bits, but the inventive concept is not limited thereto.

[0065] Accordingly, the BCH decoder 304 can output a 40-bit block three times to the even memory 401 to fill one row in the rows of the even memory 401, and continue this process until the even memory 401 is full. Then, after filling the even memory 401, the BCH decoder 304 holds the output of the 40-bit block until the odd memory 402 is full. Accordingly, the BCH decoder 304 can then switch back and forth between outputting data to the even memory 401 and the odd memory 402.

[0066] The first multiplexer 403 is configured to output 120 bits (i.e., three times the first quantity of data output by the BCH decoder) from one of the even memory 401 and the odd memory 402 to the first FIFO 404. For example, the first multiplexer 403 can alternate between outputting data from the even memory 401 and the odd memory 402. For example, there can be 120 2-to-1 first multiplexers 403, where each of the first multiplexers 403 receives one bit of the even memory 401 and one bit of the odd memory 402.

[0067] The output buffer can include circuitry for determining when the first FIFO 404 is full or almost full (e.g., the number of empty cells is less than a threshold). The output buffer can include a read control circuit 405 that receives a control signal indicating whether the first FIFO 404 is full or almost full. For example, the read control circuit 405 can transmit a signal to the BCH decoder 304 notifying the BCH decoder 304 to stop transmitting new data when the first FIFO 404 is full.

[0068] The second multiplexer 406 includes a plurality (e.g., 256) of multiplexers, where each multiplexer receives a different half (e.g., 60 bits) of the available bits (e.g., 120 bits) output by the first FIFO 404 and outputs only one of the received bits. For example, when each cell of the first FIFO 404 is 120 bits, the second multiplexer 406 is a 60-to-1 multiplexer. The second multiplexer 406 can be controlled by a wired register 408, where the wired register 408 can be controlled by a configuration register 407.

[0069] The buffer 409 receives the data output by the second multiplexer 406. The width of the buffer 409 corresponds to the number of bits output by the second multiplexer 406. For example, when there are 256 second multiplexers 406, the width of the buffer 409 is 256 bits. The wired register 408 can control the second multiplexer 406 to output the first half (e.g., 128 bits) of its output data to the first half (first part) of the buffer 409 and output the second half of its output data to the second half (second part) of the buffer 409.

[0070] Each of the third multiplexers 410 receives two different bits of the output buffer 409 and outputs only one of the received bits to the second FIFO 411, where the second FIFO 411 finally outputs the received data to the output control block 309. For example, the first data received from the third multiplexer 410 is moved to the first cell of the second FIFO 411, the first data is moved to the second cell of the second FIFO 411, and the second data received from the third multiplexer 410 is moved to the first cell, and so on. When the second FIFO 411 is full, when the next data is received from the third multiplexer 410, the data in the last cell of the second FIFO 411 can be output to the output control block 309.

[0071] Figure 5 An output buffer 308 of an SBCH decoder according to an exemplary embodiment of the inventive concept is shown. Figure 3 of the

[0072] Figure 5 The output buffer of Figure 4 has some of the same elements as the

[0073] The multiplexer 500 includes one more multiplexer than the bit width of the first FIFO 404, the multiplexer 501 includes three more multiplexers than the bit width of the first FIFO 404, the multiplexer 502 includes seven more multiplexers than the bit width of the first FIFO 404, and the multiplexer 503 includes 174 more multiplexers than the bit width of the first FIFO 404. For example, when the bit width is 120 bits, there are 121 multiplexers 500, 123 multiplexers 501, 127 multiplexers 502, and 374 multiplexers 503.

[0074] Each of the multiplexers 500 receives different 2 bits output by the first FIFO 404 and outputs only 1 bit of the received bits to output a 121-bit output. Each of the multiplexers 501 receives different 2 bits output by the multiplexer 500 and outputs only 1 bit of the received bits to output a 123-bit output. Each of the multiplexers 502 receives different 2 bits output by the multiplexer 501 and outputs only 1 bit of the received bits to output a 127-bit output. Each of the multiplexers 503 receives different 2 bits output by the multiplexer 502 and outputs only 1 bit of the received bits to output 374 bits to the buffer 504.

[0075] The buffer 504 includes a first part (e.g., 128 bits), a second part (e.g., 128 bits), and a third part (e.g., 118 bits). Each of the 2-to-1 multiplexers 505 receives one bit of the first part and one bit of the third part and outputs only 1 bit of the received bits to output 118 bits to the first part of the buffer 506. The remaining bits (e.g., 10 bits) of the first part are copied to the end of the first part of the buffer 506. The second part of the buffer 504 is copied to the second part of the buffer 506. Each of the 2-to-1 multiplexers 507 receives two bits of the buffer 506 and outputs only one bit of the received bits to output 128 bits to the second FIFO 411.

[0076] Figure 6 A BCH decoder 604 according to an exemplary embodiment of the inventive concept is shown, which may be used to implement Figure 3 the BCH decoder 304. Refer to Figure 6, the BCH decoder 604 includes a syndrome stage 605, a Berlekamp-Massey (BM) stage 606, a Chien Search (CS) stage 607, and a frame corrector stage 608. The syndrome stage 605 generates "t" syndromes from encoded data such as a BCH codeword, where "t" is the number of errors that can be corrected. The BM stage 606 performs the Berlekamp-Massey algorithm on the output (syndromes) of the syndrome stage 605. The BM stage 606 iteratively builds two polynomials, an error location polynomial (ELP) and an auxiliary polynomial (AP). The CS stage 607 performs a Chien search on the ELP coefficients output by the BM stage 606, modified to use a fast Fourier transform (FFT). The CS stage 607 outputs error bit data and iteration ID data or iteration information. For example, if the decoded data has 40 bits, the error bit data will indicate whether each bit of the decoded data has an error. For example, if the first bit of the decoded data has an error and the second bit of the decoded data has no error, the first bit of the error bit data will be 1, and the second bit of the error bit data will be 0. The error bit data output by a conventional CS stage is sorted sequentially. However, the error bit data output by the CS stage 607 is not sorted sequentially. The frame corrector stage 608 is configured to reorder the error bits so that they sequentially use the iteration ID data.

[0077] Figure 7 illustrates a BM stage according to an exemplary embodiment of the inventive concept, which can be used to implement Figure 6 the BM stage 606. Figure 7 The BM stage includes a pair of multipliers 701 and 702, four multipliers 721, 722, 723, and 724, a first adder 710, and a second adder 730. The multiplier 701 receives inputs D and delta, and inputs the ELP (e.g., error location polynomial) and AP (e.g., auxiliary polynomial). D is the difference calculated by the BM stage 606, and delta is the previous value of D. The multiplexer 702 receives inputs D and delta, and inputs the ELP and AP. The first adder 710 sums the outputs of the multipliers 701 and 702 and provides the sum as an input to the multipliers 723 and 724. The multipliers 701 and 702 are Galois field multipliers. The multiplier 721 receives input delta and Si, multiplies the received inputs, and provides the result to the multiplier 723. The multiplier 722 receives input D and Si, multiplies the received inputs, and provides the result to the multiplier 724. The multiplier 723 multiplies the ELP by the output of the multiplier 721. The multiplier 724 multiplies the AP by the output of the multiplier 722.

[0078] The second adder 730 sums the outputs of the multipliers 723 and 724 to generate a difference for output to the CS stage 607.

[0079] Figure 8 Shows the BM stage according to an exemplary embodiment of the inventive concept, which can be used to implement Figure 6 the BM stage 606. Figure 8 The BM stage of includes some components identical to those of the Figure 7 BM stage, such as the first multiplier 701, the second multiplier 702, and the first adder 710. Figure 8 The BM stage of includes a multiplier 821 that receives the Si input (i.e., the i-th syndrome) and one of the ELP and AP inputs from the first adder 710. The multiplier 821 multiplies Si by ELP and / or multiplies Si by AP to generate a difference for output to the CS stage.

[0080] Figure 7 and Figure 8 provides a non-inverse version of the BM stage 606. The non-inverse version requires two multipliers: one for multiplying ELP by D (e.g., 701), and one for multiplying AP by delta (e.g., 702). In the non-inverse version of the BM stage 606, only one such multiplier for multiplying a scalar by a polynomial is required, and a scalar-by-scalar multiplier that requires less power is added.

[0081] In an embodiment, in the non-inverse version, the first coefficient of ELP is always 1, which is beneficial for power savings and improved Chien search. The non-non-inverse implementation consumes less power than the non-inverse, but requires more area due to the inversion.

[0082] Figure 9 Shows a part of the non-non-inverse version of the BM stage 606 according to an exemplary embodiment of the inventive concept. For example, Figure 8 the components to the left of the dashed line in are replaced by Figure 9 Reference Figure 9 shows that this part includes an inverter 901, a multiplier 903, Figure 8 the multiplier 702 of, multiplexers 904, 905, 906, 908, 909, and 910, and D-type flip-flops 902, 907, and 911. The multiplexer 904 receives the syndromes K and k-1.

[0083] Figure 10 Shows the CS stage according to an exemplary embodiment of the inventive concept, which can be used to implement Figure 6CS level 607. The CS level receives the ELP coefficients as input from the BM level 606. The CS level includes a first FFT stage 1001 that performs a first iterative FFT operation on the output of the multiplexer 1000. Each iteration of the first iterative FFT operation generates a result that is provided as feedback. The multiplexer 1000 selects between the next one in the output ELP coefficients and the feedback based on the start count indication. Each time an iteration of the first FFT stage is performed, the iteration counter 1003 is incremented.

[0084] The BM level 606 can provide the start count indication. The result of the first iterative FFT operation is provided to a first sampling device 1002 that samples the result, and the sampled result is provided to a second FFT stage 1004. The second FFT stage 1004 performs a second iterative FFT operation on the sampled result output by the sampling device 1002. The result of the second iterative FFT operation is provided to a second sampling device 1005. Logic 1006 operates on the sampled result output by the second sampling device 1005 to calculate an error bit.

[0085] Although the inventive concept has been described in connection with exemplary embodiments of the inventive concept, those skilled in the art will understand that various modifications can be made to these embodiments without substantially departing from the principles of the inventive concept.

Claims

1. A decoding circuit for performing error correction in a memory system, the decoding circuit comprising: A Bose-Chaudhuri-Hocquenghem (BCH) decoder, comprising: A syndrome stage for generating a syndrome based on a BCH codeword stored in the memory system; A Berlekamp-Massey (BM) stage that performs the Berlekamp-Massey algorithm on the syndrome to generate error location polynomial (ELP) coefficients; A Chien stage that performs a Chien search on the ELP coefficients using a fast Fourier transform (FFT) circuit to generate error bits and iteration information, wherein the Chien stage includes a first FFT stage for operating on the ELP coefficients and a counter; and A frame restorer stage configured to reorder the error bits into sequential order based on the iteration information output from the counter incremented for each iteration of the first FFT stage, wherein the BCH decoder uses the reordered error bits to perform error correction on the data of the BCH codeword.

2. The decoding circuit according to claim 1, wherein The Chien stage includes: A second FFT stage that iteratively performs FFT operations on the output of the first FFT stage; and A logic circuit configured to generate the error bits from the output of the second FFT stage.

3. The decoding circuit according to claim 1, further comprising: A hard decision buffer; A soft decision buffer; And An input control circuit configured to store the BCH codeword as hard decision bits in the hard decision buffer for output to the BCH decoder, and to store soft decision bits in the soft decision buffer to indicate the reliability of the bits of the BCH codeword.

4. The decoding circuit according to claim 3, wherein, The decoding circuit additionally uses the soft decision bits to perform error correction on the BCH codeword.

5. The decoding circuit according to claim 3, further comprising a delta syndrome memory for storing a delta syndrome, and the BCH decoder additionally uses the stored delta syndrome to perform error correction on the data of the BCH codeword.

6. The decoding circuit according to claim 5, further comprising a delta syndrome calculator, wherein a result of successful decoding of the BCH codeword by the BCH decoder is output to the delta syndrome calculator for calculating the delta syndrome.

7. The decoding circuit according to claim 5, further comprising a Reed-Solomon decoder for correcting at least one of the delta syndromes stored in the delta syndrome memory.

8. The decoding circuit according to claim 3, wherein, The BCH decoder reads the soft decision bits from the soft decision buffer, and the BCH decoder flips one or more of the hard decision bits corresponding to the bits with low reliability in the soft decision bits based on a certain probability.

9. The decoding circuit according to claim 8, further comprising a pseudo-random number generator for generating a pseudo-random number, and the certain probability is generated from the pseudo-random number.

10. The decoding circuit according to claim 1 further includes an output buffer configured to store a certain amount of data output by the BCH decoder at a predetermined rate.

11. The decoding circuit according to claim 10, wherein, The output buffer includes: an even memory including a plurality of first rows each configured to store three times the certain amount of data output; and an odd memory including a plurality of second rows each configured to store three times the certain amount of data output, wherein the BCH decoder continues to output additional first data to the even memory until the even memory is full, and then starts to output additional second data to the odd memory.

12. The decoding circuit according to claim 11, wherein, The output buffer further includes: a plurality of 2-to-1 first multiplexers, each of which receives one bit from the even memory and one bit from the odd memory to output three times the certain amount of data output; and a FIFO configured to receive the output of the plurality of 2-to-1 first multiplexers.

13. The decoding circuit according to claim 12, wherein the output buffer further includes: a plurality of 60-to-1 multiplexers receiving output from the FIFO; a buffer including a first portion storing the first half of the data output by the 60-to-1 multiplexer and a second portion storing the second half of the data output by the 60-to-1 multiplexer; and a plurality of 2-to-1 second multiplexers, each of which receives one bit from the first portion and one bit from the second portion.

14. A method for performing error correction in a memory system, the method comprising: generating a syndrome based on a Bose-Chaudhuri-Hocquenghem (BCH) codeword stored in the memory system; performing the Berlekamp-Massey algorithm on the syndrome to generate error location polynomial (ELP) coefficients; performing a Chien search on the ELP coefficients using a fast Fourier transform (FFT) circuit to generate error bits and iteration information; reordering the error bits into sequential order based on the iteration information; and performing error correction on the data of the BCH codeword using the reordered error bits, wherein the FFT circuit includes a first FFT stage that iteratively operates on the ELP coefficients, and the iteration information is generated from the output of a counter that increments for each iteration of the first FFT stage.

15. The method according to claim 14, wherein, Performing the Chien search includes: using a second FFT stage of the FFT circuit to iteratively operate on the output of the first FFT stage; and generating the error bits from the output of the second FFT stage.

16. A decoding circuit for performing error correction in a memory system, the decoding circuit comprising: a Bose-Chaudhuri-Hocquenghem (BCH) decoder including: a syndrome stage for generating a syndrome based on a BCH codeword stored in the memory system; A Berlekamp-Massey (BM) stage that performs the Berlekamp-Massey algorithm on the syndrome to generate error location polynomial (ELP) coefficients; A first fast Fourier transform (FFT) stage that iteratively performs a first FFT operation on the ELP coefficients to generate a first result; A second FFT stage that iteratively performs a second FFT operation on the first result to generate a second result; and Logic circuitry configured to generate error bits from the second result, generate iteration information from the output of a counter that increments for each iteration of the first FFT stage, and reorder the error bits based on the iteration information, wherein the BCH decoder performs error correction on the data of the BCH-encoded word using the reordered error bits.

17. The decoding circuit according to claim 16, further comprising: A hard decision buffer; A soft decision buffer; and An input control circuit configured to store the BCH-encoded word as hard decision bits in the hard decision buffer for output to the BCH decoder and store soft decision bits in the soft decision buffer to indicate the reliability of the bits of the BCH-encoded word.

18. The decoding circuit according to claim 17, wherein, The BCH decoder reads the soft decision bits from the soft decision buffer, and the BCH decoder flips one or more of the hard decision bits corresponding to the bits with low reliability in the soft decision bits based on a certain probability.

Images