Low resistivity interconnect for integrated circuits and method of forming the same

Abstract

The present disclosure proposes an interconnect for an integrated circuit and a method for forming the same. The method for forming an interconnect for an integrated circuit comprises: identifying an interconnect barrier material; identifying a plurality of potential doping elements; forming a collection of potential barrier structures comprising the interconnect barrier material, the interconnect barrier material being doped at a plurality of doping positions and with a plurality of doping amounts of each of the plurality of potential doping elements; calculating the density of states of each of the barrier structures of the collection; selecting the doping element and the doping amount based on the density of states; and depositing a barrier layer comprising an alloy comprising the interconnect barrier material and the selected doping element at the selected doping amount. The interconnect of the present disclosure can reduce the resistivity of the conductive metal / barrier interface and the vertical resistivity of the conductive metal / barrier stack.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 62 / 793,766, filed on January 17, 2019, entitled “LOW RESISTIVITY INTERCONNECT BARRIER FORMED BY ALLOYING TO INCREASE DENSITY OF STATES,” and U.S. Non-Provisional Application No. 16 / 410,787, filed on May 13, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to interconnects and methods of forming the same. Background Art

[0004] Back-end-of-line (BEOL) interconnects are used in integrated circuits to interconnect individual devices (eg, transistors) of the circuit together and to form chip-to-package connections.

[0005] BEOL interconnects include wires (or wires) and vias (i.e., plugs that connect a network of wires vertically to each other). Wires connect devices of a circuit horizontally, and vias form vertical connections. The resistance of a BEOL interconnect includes the resistance of the wires and the resistance of the vias. For ultra-scaled line widths such as interconnects with critical dimensions of 10 to 20 nanometers, the resistance of the vias can become a significant source of resistance in the interconnect, especially at high via densities at or below the 5 nanometer node.

[0006] There is still a need to reduce the resistance of the vias.

[0007] The above information in the Background section is only for enhancement of understanding of the background of the technology, and therefore the information should not be construed as an admission of the existence or relevance of prior art. Summary of the invention

[0008] According to an embodiment of the present disclosure, an interconnect for an integrated circuit includes an interlayer dielectric (ILD) layer having a trench, a barrier layer on the ILD layer and covering the wall of the trench, and a conductive metal layer on the barrier layer and inside the trench. The barrier layer includes an alloy, the alloy including an interconnect barrier material and a doping element. The state density of the alloy may be at least 50% greater than the state density of the interconnect barrier material.

[0009] In the alloy, the doping element may be interstitially and / or substitutionally doped in the interconnect barrier material.

[0010] In one embodiment, the interconnect barrier material may include a two-dimensional (2D) conductor selected from the group consisting of graphene, transition metal di-chalcogenides, black phosphorus, and nitrides.

[0011] In one embodiment, the conductive metal may include Cu, and the interconnect barrier material may include Ta. x N y and Ti x N y At least one of .

[0012] In one embodiment, the conductive metal may include Ru and the interconnect barrier material may include Ti x Hf y N z and Ti x Zr y N z At least one of .

[0013] In one embodiment, the conductive metal may include Co and the interconnect barrier material may include Ta x N y 、Ti x N y 、Ti x Hf y N z and Ti x Zr y N z At least one of .

[0014] In one embodiment, the total conductivity of the barrier layer may be greater than the total conductivity of the interconnect barrier material.

[0015] In one embodiment, the interconnect barrier material may be TiN, and the doping elements may be selected from dysprosium (Dy), molybdenum (Mo), platinum (Pt), palladium (Pd), erbium (Er), silicon (Si), boron (B), niobium (Nb), tungsten (W), tantalum (Ta), aluminum (Al), zirconium (Zr), and hafnium (Hf).

[0016] In one embodiment, the density of states of the alloy may be 1 to 10 times greater than the density of states of the interconnect barrier material, and the vertical conductivity of the alloy may be greater than the vertical conductivity of the interconnect barrier material.

[0017] In one embodiment, the doping element may be distributed in the interconnect barrier material uniformly or non-uniformly throughout the thickness of the barrier layer.

[0018] In one embodiment, the doping element may be more concentrated on the surface of the interconnect barrier material.

[0019] According to an embodiment of the present disclosure, a method for forming an interconnect for an integrated circuit includes: forming a collection of potential barrier structures, each of the potential barrier structures including an interconnect barrier material doped at multiple doping positions and at multiple doping amounts of one of multiple potential doping elements; calculating the state density near the Fermi Level of each of the barrier structures of the collection; selecting the doping element and the doping amount based on the state density; and depositing a barrier layer including an alloy including the interconnect barrier material and the selected doping element at the selected doping amount. The state density of the alloy may be at least 50% greater than the state density of the interconnect barrier material.

[0020] In one embodiment, calculating the density of states may include detailed physics-based simulations or machine learning-based predictions about the corresponding barrier structures. For example, calculating the density of states may be performed using at least one simulation program selected from: first-principles based density functional theory atomistic simulations; a combination of first-principles based density functional theory simulations and predictive modeling using a machine learning model trained from data generated by simulations of interconnect barrier materials doped with dopants; a combination of first-principles based density functional theory simulations and experimental information about the conductivity of interconnect barrier materials in the presence of dopants; and a combination of material simulations and experimental data available in public and proprietary repositories.

[0021] In one embodiment, depositing the barrier layer may include depositing an interconnect barrier material on the interlayer dielectric layer and doping the interconnect barrier material with a selected dopant at a selected doping level.

[0022] In one embodiment, depositing the interconnect barrier material may include utilizing one or more selected from the group consisting of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma enhanced ALD.

[0023] In one embodiment, doping the interconnect barrier material with the selected doping element at the selected doping amount may include one or more selected from ion implantation and diffusion.

[0024] In one embodiment, depositing the barrier layer may include co-depositing the interconnect barrier material with the selected doping element using ALD, PVD, CVD, or PE-ALD.

[0025] In one embodiment, the interconnect barrier material may include a first atomic element, and depositing the barrier layer may include co-depositing the interconnect barrier material with a compound including a doping element and the first atomic element.

[0026] In one embodiment, the interconnect barrier material may include Ti x N y , and the compound may include Ta x N y .

[0027] In one embodiment, the amount of the compound can be selected to achieve a selected doping level.

[0028] In one embodiment, the method may further include depositing an interlayer dielectric layer. Depositing the barrier layer may include: depositing a monolayer of a doping element on a surface of the interlayer dielectric layer, depositing an interconnect barrier material on the monolayer of the doping element, and diffusing the doping element into the interconnect barrier material to form an alloy. Depositing the monolayer of the doping element includes a vapor-based or liquid-based deposition method. In one embodiment, depositing the monolayer of the doping element includes plating the monolayer of the doping element using a plating solution containing the doping element.

[0029] In one embodiment, doping the interconnect barrier material with a selected doping element at a selected doping amount may include exposing a surface of the interconnect barrier material to a gas including the doping element, and reacting the surface of the interconnect barrier material with the doping element to form an alloy on the surface.

[0030] In one embodiment, depositing a barrier layer may include: depositing a first interconnect barrier material layer including an interconnect barrier material and a selected doping element on an interlayer dielectric layer, depositing a second interconnect barrier material layer on the first interconnect barrier material layer, and reacting the first interconnect barrier material layer with the second interconnect barrier material layer to form an alloy of the interconnect barrier material and the doping element.

[0031] In one embodiment, depositing the barrier layer may include a dual-damascene flow in which the interconnect barrier material may be co-deposited for the via trench and the interconnect line in the same back-end processing step.

[0032] In one embodiment, depositing the barrier layer may include a single damascene flow where the interconnect barrier material may be deposited in the via trench and the interconnect line in separate steps.

[0033] In one embodiment, the method further includes depositing an interlayer dielectric layer, wherein depositing the barrier layer includes depositing an interconnect barrier material on the interlayer dielectric layer, plating a dopant element layer on the interconnect barrier material, and diffusing the dopant element into the interconnect barrier material to form an alloy.

[0034] According to embodiments of the present disclosure, the increase in the density of states leads to a reduction in the mismatch between the mode densities of the conductive metal and the barrier material, thereby reducing the resistivity of the conductive metal / barrier interface and the vertical resistivity of the conductive metal / barrier stack.

[0035] This Summary is provided to introduce a selection of features and concepts of embodiments of the present disclosure, which are further described in the Detailed Description below. This Summary is neither intended to identify key or essential features of the claimed subject matter nor to be used to limit the scope of the claimed subject matter. One or more of the described features may be combined with one or more other described features to provide a workable device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] These and other features and advantages of the embodiments of the present disclosure will become apparent by reference to the following detailed description when considered in conjunction with the following figures. In the drawings, like reference numerals are used throughout the various figures to refer to like features and components. The various figures are not necessarily drawn to scale.

[0037] Figure 1 is a cross-sectional view of an interconnect according to an embodiment of the present disclosure.

[0038] Figure 2 is a flow chart illustrating a process for fabricating an interconnect for an integrated circuit.

[0039] Figure 3 Graphs show the percentage increase in the density of states of TiN when doped with various doping elements.

[0040] Figure 4 is a schematic illustration of an example process for depositing a barrier layer comprising a low resistance alloy.

[0041] Figure 5 is a schematic illustration of vertical conduction through an interconnect via.

[0042] Figure 6 is a schematic representation of the increase in mode-space coverage due to the increase in density of states. DETAILED DESCRIPTION

[0043] The present disclosure relates to various embodiments of interconnects for integrated circuits and methods of manufacturing the same. The interconnects of the present disclosure include an interconnect barrier layer formed of an alloy of an interconnect barrier material and a doping element, the interconnect barrier layer having improved electrical conductivity compared to related art interconnects without the alloy.

[0044] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which similar reference numerals refer to similar elements throughout the text. However, the present invention can be implemented in various different forms, and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects and features of the present invention to those skilled in the art. Accordingly, processes, elements and technologies that are not necessary for making those of ordinary skill in the art fully understand the various aspects and features of the present invention may not be described. Unless otherwise noted, similar reference numerals represent similar elements throughout the drawings and written descriptions, and therefore their descriptions may not be repeated.

[0045] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated and / or simplified for clarity. For ease of explanation, spatially relative terms such as "below ... ", "below ... ", "lower part", "under ... ", "above ... ", "upper part" may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It should be understood that, in addition to the orientation depicted in the figure, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, the element described as "below" or "below" or "below" other elements or features will be oriented as "above" other elements or features. Therefore, the example terms "below ... " and "under ... " may cover orientations above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0046] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, first component, first region, first layer or first part described below may be referred to as the second element, second component, second region, second layer or second part without departing from the spirit and scope of the present invention.

[0047] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it should be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0048] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular form "a / an" is also intended to include plural forms. It should be further understood that when used in this specification, the terms "comprises / comprising", "includes / including" specify the existence of stated features, integers, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As the expression of "at least one of ... " modifies the entire list of elements before the list of elements and does not modify the individual elements in the list.

[0049] As used herein, the terms "substantially," "about," and the like are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent deviations of measurements or calculations that would be recognized by one of ordinary skill in the art. In addition, the use of "may" when describing embodiments of the present invention refers to "one or more embodiments of the present invention." As used herein, the terms "use / using / used" may be considered synonymous with the terms "utilize / utilizing / utilized," respectively. In addition, the term "exemplary" is intended to refer to an example or illustration.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense unless so explicitly defined in this article.

[0051] The electronic device or electrical device according to the embodiment of the present invention described herein and / or any other related device or component can be implemented using any suitable hardware, firmware (such as an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on an independent IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB) or formed on a substrate. In addition, the various components of these devices can be processes or threads running on one or more processors, in one or more computing devices, executing computer program instructions, and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that can be implemented in a computing device using a standard memory device such as a random access memory (RAM). Computer program instructions can also be stored in other non-temporary computer-readable media such as CD-ROMs, flash drives, or the like. In addition, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or that the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the present invention.

[0052] According to an embodiment of the present disclosure, an interconnect for an integrated circuit includes an interlayer dielectric (ILD) layer having a groove, a barrier layer on the ILD layer and covering the wall of the groove, and a conductive metal layer on the barrier layer and inside the groove. The barrier layer includes an alloy, and the alloy includes an interconnect barrier material alloyed with a doping element. The doping element includes an atomic substance. The state density of the alloy is greater than the state density of the interconnect barrier material. In addition, when used to form the barrier layer respectively, the conductivity (e.g., vertical conductivity) of the alloy is greater than the conductivity (e.g., vertical conductivity) of the interconnect barrier material. In one embodiment, a liner layer may be included between the barrier layer and the conductive metal layer.

[0053] As used herein, the term "density of states" or "DOS" refers to the number of different states at a particular energy level that an electron is allowed to occupy, i.e., the number of electronic states per unit volume at a given energy. The density of states can be derived from basic quantum mechanics, as known to those skilled in the relevant art. A high density of states at a particular energy level means that there are many states available for occupation.

[0054] Figure 1 is a cross-sectional view of an interconnect according to an embodiment of the present disclosure.

[0055] refer to Figure 1 , an interconnect 100 for an integrated circuit includes an interlayer dielectric (ILD) layer 110 having a trench 120, a barrier layer 130 on the ILD layer 110 and covering a wall of the trench 120, a liner layer 140 on the barrier layer 130, and a conductive metal layer 150 on the liner layer 140 and inside the trench 120.

[0056] The barrier layer 130 comprises an alloy, which is an alloy of an interconnect barrier material and a doping element. The doping element comprises an atomic species, which is selected so that the density of states of the alloy near the Fermi level is greater than the density of states of the interconnect barrier material alone. In one embodiment, the density of states within + / - kT (e.g., 1 kT) of the Fermi level is used to account for the thermal distribution of electrons. For example, the density of states of the alloy may be 50%, 75%, 100%, or 200% greater than the density of states of the interconnect barrier material alone.

[0057] Throughout this disclosure, the term "alloy" refers to a material in which a doping element is interstitially or substitutionally doped in the lattice structure of the interconnect barrier material. A stack of only a doping element layer and an interconnect barrier material layer or a mixture of only a doping element and an interconnect barrier material without interstitial doping or substitutional doping is not considered an alloy.

[0058] In one embodiment, the alloy may have a density of states 1 to 10 times greater than that of the interconnect barrier material, and the alloy may have a vertical conductivity greater than (e.g., 10%, 20%, 50%, or 100%) that of the interconnect barrier material.

[0059] In one embodiment, in the alloy, the doping element may be intermittently and / or substitutionally doped in the interconnect barrier material. The doping element may be uniformly distributed throughout the barrier layer 130. However, the embodiments of the present disclosure are not limited thereto. In one embodiment, the doping element may be unevenly distributed or alloyed with the interconnect barrier material throughout the entire thickness of the barrier layer. In one embodiment, the doping element may be more concentrated on the surface of the interconnect barrier material. That is, the concentration of the doping element in the surface region of the barrier layer may be higher than the concentration in the base (or middle) region of the barrier layer.

[0060] The interconnect barrier material may comprise any suitable material. In one embodiment, the interconnect barrier material may comprise a 2D conductor selected from the group consisting of graphene, transition metal dichalcogenides (such as but not limited to MoS 2 , WS 2 、MoSe 2 ,WSe 2 、MoTe 2 etc.), black phosphorus and nitrides (such as Ta x N y 、Ti x N y 、Ti x Hf y N z and Ti x Zr y N z ). In one embodiment, the interconnect barrier material may be amorphous.

[0061] The conductive metal layer 150 may be formed of copper (Cu), cobalt (Co), ruthenium (Ru), aluminum (Al), tin (Sn), nickel (Ni), gold (Au), silver (Ag), and / or any other suitable conductive material. In one embodiment, the conductive metal layer 150 may include Cu, Co, or Ru. The vertical resistivity of Cu may increase with scaling due to a variety of reasons, such as grain boundary scattering, liner layer interface scattering, and / or interface roughness scattering. Co and Ru have shown promising vertical resistivity scaling and may be used as a substitute for Cu at least in lower levels of interconnect metallization where the scaling effect is most effective.

[0062] The interconnect barrier material may be selected based on the conductive metal used to form the conductive metal layer. In one embodiment, the conductive metal may include Cu, and the interconnect barrier material may include Ta. x N y and Ti x N y In another embodiment, the conductive metal may include Ru, and the interconnect barrier material may include Ti x Hfy N z and Ti x Zr y N z In another embodiment, the conductive metal may include Co, and the interconnect barrier material may include Ta. x N y 、Ti x N y 、Ti x Hf y N z and Ti x Zr y N z Here, the values ​​of x, y, and z can be appropriately selected.

[0063] The doping element may be selected based on the interconnect barrier material to increase the density of states of the interconnect barrier material. In one embodiment, the interconnect barrier material may be Ti x N y , and the doping element may be selected from dysprosium (Dy), molybdenum (Mo), platinum (Pt), palladium (Pd), erbium (Er), silicon (Si), boron (B), niobium (Nb), tungsten (W), tantalum (Ta), aluminum (Al), zirconium (Zr) and hafnium (Hf). The doping element may be different from the element included in the interconnect barrier material. For example, the doping element may be a metal element different from the metal element included in the interconnect barrier material.

[0064] The barrier layer 130 is a required element of BEOL interconnect technology. The barrier layer 130 blocks the diffusion of the conductive metal in the conductive metal layer 150 into the underlying ILD layer 110 (also referred to as the low-k dielectric matrix) and blocks oxygen diffusion into the conductive metal layer 150. Here, the barrier layer 130 serves the dual purpose of helping to maintain the integrity of the conductor (i.e., the conductive metal in the conductive metal layer) and the integrity of the dielectric (i.e., the dielectric material in the ILD layer). In the Damascene process BEOL approach, the liner layer 140 enables the conductive metal layer 150 to adhere to the barrier layer 130 and the trench 120. Although Figure 1 An interconnection including a liner layer 140 is shown, but the embodiments of the present disclosure are not limited thereto, and the interconnection may not include a liner layer. In one embodiment, the conductive metal layer 150 is formed directly on the barrier layer 130 without the liner layer 140 therebetween.

[0065] Figure 5 is a schematic illustration of electrical conduction in an interconnect. Figure 5, the total BEOL resistance can be roughly divided into vertical (via) and horizontal (line) contributions. As scaling continues to increase and the density of vias continues to increase, the via resistance contributes an increasingly larger proportion of the total BEOL resistance. At critical dimensions of 10 nm to 20 nm (expected in ≤4 nm technology nodes), a reasonable via density of 4 vias per cell already contributes a resistance greater than the line component. Therefore, reducing via resistance plays an increasingly important role in scaling technology nodes. Here, the barrier resistance is the largest component of the via resistance, and reducing the barrier resistance by, for example, an order of magnitude will result in a larger reduction in the total BEOL resistance. According to an embodiment of the present disclosure, the barrier resistance reduction is achieved by forming an alloyed barrier that increases the density of states of the barrier material and reduces the vertical resistivity. As used herein, the terms "vertical resistivity" and "vertical conductivity" refer to the direction in which electrons are transported through the barrier layer in the interconnect (i.e., as Figure 5 In addition, the terms "filler" and "conductive metal" are used interchangeably in the present disclosure.

[0066] In the related art, the vertical resistivity of the liner layer plus the barrier layer stack tends to be extremely high due to the high vertical resistivity of the material suitable for use as a barrier layer. In the semiconductor industry, nitrides such as TaN and TiN have conventionally been used as diffusion barriers. The vertical resistivity of these materials is typically two or more orders of magnitude greater than that of conductive metals (such as Cu, Co, or Ru). This results in an increase in the resistance of the interconnect (or interconnect metal stack). The problem is more severe for vertical conduction through metal vias than for horizontal conduction along the length of the interconnect. For vertical conduction (such as in a via), the barrier resistance is in series with the conductive metal layer resistance and the liner layer resistance, such as Figure 5 As shown in . Due to the difference of two or more orders of magnitude between the resistance of the conductive metal layer and the barrier material, the barrier resistance can dominate the vertical conduction.

[0067] According to an embodiment of the present disclosure, the barrier layer 130 comprises an alloy of an interconnect barrier material and a doping element, wherein the alloy comprises atomic substances. The doping element is selected so that the state density of the alloy is greater than the state density of the interconnect barrier material alone. In this way, the conductivity of the barrier layer is greater than the conductivity of the interconnect barrier material alone, and thus the total resistance of vertical conduction is reduced.

[0068] According to an embodiment of the present disclosure, a method for forming an interconnect for an integrated circuit includes: forming a collection of potential barrier structures, each of the potential barrier structures including an interconnect barrier material doped at multiple doping positions and with multiple doping amounts of one of multiple potential doping elements; calculating the density of states close to the Fermi level of each of the barrier structures of the collection; selecting the doping element and the doping amount based on the density of states; and depositing a barrier layer comprising an alloy, the alloy comprising the interconnect barrier material and the selected doping element at the selected doping amount.

[0069] Figure 2 is a flow chart illustrating a process for fabricating an interconnect for an integrated circuit.

[0070] refer to Figure 2 , a process for manufacturing an interconnect for an integrated circuit includes action 210, identifying an interconnect barrier material; action 220, identifying multiple potential doping elements; action 230, forming a collection of potential barrier structures including the interconnect barrier material, wherein the interconnect barrier material is doped at multiple doping locations and with multiple doping amounts of each of the multiple potential doping elements; and action 240, calculating the state density of each of the barrier structures of the collection.

[0071] The interconnect barrier material may comprise any suitable material. In one embodiment, the interconnect barrier material may be selected from a 2D conductor selected from graphene, transition metal dichalcogenides, black phosphorus, and nitrides. In one embodiment, the interconnect barrier material may be amorphous. The interconnect barrier material may be selected based on the conductive metal used to form the conductive metal layer. In one embodiment, the conductive metal may comprise Cu, and the interconnect barrier material may comprise Ta. x N y and Ti x N y In one embodiment, the conductive metal may include Ru, and the interconnect barrier material may include Ti x Hf y N z and Ti x Zr y N z In one embodiment, the conductive metal may include Co, and the interconnect barrier material may include Ta. x N y 、Ti x N y 、Ti x Hf y N z and Ti x Zr y N z At least one of .

[0072] In action 220, a plurality of potential doping elements may be identified or selected. There is no particular limitation on the selection of potential doping elements, as long as the potential doping elements do not have undesirable effects on the barrier layer, the ILD layer, the liner layer, and the conductive metal layer. In other words, after identifying the interconnect barrier material, any element that does not have undesirable effects on the periodic table may be identified as a potential doping element.

[0073] In action 230, a collection of potential barrier structures is formed. The collection of potential barrier structures includes an interconnect barrier material doped at a plurality of doping locations and with a plurality of doping amounts of each of a plurality of potential doping elements. The plurality of doping locations may include any suitable location in a lattice structure of the interconnect barrier material that may include a doping element. Furthermore, the plurality of doping amounts may include any suitable amount, such as from 0.1% to 100% (fully saturated amount). In each of the potential barrier structures, the selected potential doping element is doped at a selected location of the interconnect barrier material in a selected amount.

[0074] For example, TiN may be selected as the interconnect barrier material, and Mo may be selected as one of the potential doping elements. One of the potential barrier structures may be a substitution of one Ti atom or one N atom by one Mo atom from 10 TiN molecules. Another potential barrier structure may be a substitution of two Ti atoms or two N atoms by two Mo atoms from 10 TiN molecules. A collection of potential barrier structures for TiN may include any element from the periodic table and may be formed and stored in a computing device.

[0075] In action 240, the calculation of the density of states of each of the barrier structures of the collection can be performed using a computer program. For example, the calculation can use at least one simulation program selected from the following: a density functional theory atomistic simulation based on first principles; a combination of density functional theory simulation based on first principles and predictive modeling using a machine learning model, the machine learning model is trained based on data generated by simulation of interconnect barrier materials doped with dopants; a combination of density functional theory simulation based on first principles and experimental information about the conductivity of interconnect barrier materials in the presence of dopants; and a combination of material simulation and experimental data available in public and proprietary repositories. For example, the public and proprietary repositories can include any suitable repository, such as Materials Project, Inorganic Crystal Structure Database (ICSD), AFlowLib, NOMAD, Citrine, and Materials Platform for Data Science (MPDS), etc.

[0076] The calculations may be performed on a computer suitable for fast calculations.

[0077] The process further includes an act 250 of selecting a doping element and a doping amount based on an increase in conductivity due to an increase in density of states. Here, the doping element and the doping amount may be selected to have a greater conductivity due to an increased density of states of the barrier structure compared to the presence of only the interconnect barrier material. Among the doping elements that provide the barrier structure with increased conductivity and density of states, the selection may also take into account the availability of the doping element and the processability of the doping element.

[0078] Figure 3 FIG. 1 is a graph showing the percentage increase in the density of states of TiN when doped with various doping elements, calculated using the first principle of density of states. Based on 100 mol % of Ti, the dopant is included at 8.3 mol %. Figure 3 As shown in , doping TiN with Dy results in an increase of more than 200% in the state density, and doping TiN with Mo results in an increase of more than 100% in the state density. In addition, doping with Al, Ta, W, Nb, and B all result in a significant increase in the state density. Thus, doping elements such as Er, Pt, Pd, Mo, or Dy can be selected. Although Figure 3 Specific elements are shown in FIG. 1 , but the embodiments of the present disclosure are not limited thereto, and various additional elements may be used to dope TiN as long as the elements increase the density of states and improve the vertical conductivity.

[0079] Figure 6is a schematic representation of the increase in mode spacing coverage due to an increase in state density according to an embodiment of the present disclosure. Figure 6 As shown in , when the state density is low, less mode spacing coverage is allowed, which results in less vertical transmission through the barrier layer. Therefore, the barrier layer has a higher vertical resistivity and a lower vertical conductivity. However, when the state density is increased to a larger value by alloying, more mode spacing coverage and more vertical transmission through the barrier layer are allowed. Therefore, the barrier layer has a lower vertical resistivity and a higher vertical conductivity. Here, alloying elements are selected to increase the barrier conductivity by increasing the state density of the barrier material, which results in increased mode spacing coverage in the barrier layer. In addition, the improvement in conductivity according to embodiments of the present disclosure is not limited by the specific conductive metal used to form the interconnect. In this way, the method according to embodiments of the present disclosure can be used to form a low vertical resistivity barrier material from an existing barrier material of any given (e.g., arbitrary) conductive metal material.

[0080] The process further includes act 260 of depositing a barrier layer comprising an alloy comprising the interconnect barrier material and a selected doping element at a selected doping level.

[0081] The deposition of the barrier layer may include depositing an interconnect barrier material on a dielectric substrate (e.g., an interlayer dielectric layer) and doping the interconnect barrier material with a selected dopant at a selected doping amount. The interconnect barrier material may be deposited using one or more techniques selected from the following: atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma-enhanced ALD (PE-ALD).

[0082] Figure 4 is a schematic illustration of an example process for depositing a barrier layer comprising an alloy.

[0083] refer to Figure 4 , the process of depositing a barrier layer comprising an alloy includes: depositing an interlayer dielectric (ILD) layer 410 in action (a), etching the ILD layer 410 to form a trench 420 in action (b), depositing an interconnect barrier material 430 on the ILD layer 410 and inside the trench 420 in action (c), depositing a doping element 440 in action (d), and reacting the interconnect barrier material 430 with the doping element 440 to form a barrier layer 450 comprising an alloy of the interconnect barrier material and the doping element.

[0084] Although Figure 4, the interconnect barrier material and the doping element are separately deposited, but the embodiments of the present disclosure are not limited thereto, and any suitable method may be used to form the barrier layer. In one embodiment, the alloy may be formed by doping the interconnect barrier material with the selected doping element using ion implantation and / or diffusion.

[0085] In one embodiment, depositing the barrier layer may include co-depositing the interconnect barrier material with the selected doping element using ALD, PVD, CVD, or PE-ALD.

[0086] In one embodiment, the interconnect barrier material may include a first atomic element, and depositing the barrier layer may include co-depositing the interconnect barrier material with a compound including both the doping element and the first atomic element. For example, the interconnect barrier material may include Ti x N y , and the compound may include Ta x N y , to provide a barrier layer comprising an alloy of TiN and Ta. Ta can be appropriately adjusted x N y to provide the desired doping level.

[0087] In one embodiment, depositing the barrier layer may include depositing an interlayer dielectric layer, depositing a monolayer of a doping element on a surface of the interlayer dielectric, and then depositing an interconnect barrier material on the monolayer of the doping element, and then diffusing the doping element into the interconnect barrier material to form an alloy. Diffusion of the doping element into the interconnect barrier material to form an alloy may be performed under suitable conditions, such as by thermal treatment. Depositing the monolayer of the doping element may include vapor-based and / or liquid-based deposition methods. In one embodiment, depositing the monolayer of the doping element includes electroplating the monolayer of the doping element using a plating solution containing the doping element.

[0088] In one embodiment, the interlayer dielectric layer can be deposited and patterned using standard photolithography and etching techniques to form vias (single damascene process) or vias and trenches (dual damascene process). Subsequently, the interconnect barrier material can be deposited on the interlayer dielectric layer using a suitable deposition technique. Subsequently, a plating process can be used to add doping elements and allow the doping elements to alloy with the underlying interconnect barrier material. A seed layer of a conductive metal layer can be deposited on the barrier layer using, for example, physical vapor deposition (PVD) or electroplating, and the conductive metal layer can be deposited on the seed layer. In one embodiment, the doping element is deposited simultaneously with the seed layer by an electroplating process. In another embodiment, the doping element is deposited using an electroplating process before the seed layer is deposited.

[0089] In one embodiment, depositing the barrier layer may include: after depositing the interconnect barrier material, exposing a surface (e.g., a top surface) of the interconnect barrier material to a gas containing a doping element, and reacting the surface of the interconnect barrier material with the doping element to form an alloy on the surface.

[0090] In one embodiment, depositing the barrier layer may include: depositing a first interconnect barrier material layer including an interconnect barrier material and a selected doping element on a dielectric substrate (e.g., an interlayer dielectric layer), depositing a second interconnect barrier material layer on the first interconnect barrier material layer, and reacting the first interconnect barrier material layer with the second interconnect barrier material layer to form an alloy of the interconnect barrier material and the doping element. Reacting the first interconnect barrier material layer with the second interconnect barrier material layer to form an alloy of the interconnect barrier material and the doping element may be performed under suitable conditions, such as by heating.

[0091] In one embodiment, depositing the barrier layer may include a dual damascene process flow where the interconnect barrier material may be co-deposited for the via trench and the interconnect line in the same back-end processing step.

[0092] In one embodiment, the deposition of the barrier layer may include a single damascene process flow where the interconnect barrier material may be deposited in the via trench and the interconnect line in separate steps.

[0093] In one embodiment, depositing the interconnect barrier material may include depositing a crystalline interconnect barrier material, and rapidly melting and quenching or laser annealing the crystalline interconnect barrier material to form an amorphous interconnect barrier material.

[0094] In the embodiments of the present disclosure, the increase in state density leads to a reduction in the mismatch between the mode densities in the conductive metal layer and the barrier layer, thereby reducing the vertical resistivity of the conductive metal layer / barrier layer interface and the vertical resistivity of the conductive metal layer / barrier layer stack.

[0095] Although the present invention has been described in detail with particular reference to exemplary embodiments of the present invention, the exemplary embodiments described herein are not intended to be exhaustive or to limit the scope of the present invention to the precise forms disclosed. Those skilled in the art and technology to which the present invention belongs should understand that modifications and changes of the described structures and methods of assembly and operation may be practiced without materially departing from the principles, spirit and scope of the present invention as set forth in the following claims.

Claims

1. An interconnect for an integrated circuit, comprising: an interlayer dielectric layer having a trench; a barrier layer on the interlayer dielectric layer and covering the wall of the trench; as well as a conductive metal layer on the barrier layer and inside the trench, wherein the barrier layer comprises an alloy comprising an interconnect barrier material and a doping element, and wherein the density of states of the alloy is at least 50% greater than the density of states of the interconnect barrier material, The density of states of the alloy is 1 to 10 times greater than the density of states of the interconnect barrier material, and the vertical conductivity of the interconnect is greater than the vertical conductivity of the same interconnect except that only the barrier material is included in the barrier layer. 2 . The interconnect for an integrated circuit according to claim 1 , wherein in the alloy, the doping element is interstitially and / or substitutionally doped in the interconnect barrier material.

3. The interconnect for an integrated circuit of claim 1, wherein the interconnect barrier material comprises a two-dimensional conductor selected from the group consisting of graphene, transition metal dichalcogenides, black phosphorus, and nitrides. 4 . The interconnect for an integrated circuit of claim 1 , wherein a total conductivity of the barrier layer is greater than a total conductivity of the interconnect barrier material.

5. The interconnect for an integrated circuit of claim 1, wherein the interconnect barrier material comprises TiN, and the doping element comprises at least one selected from the group consisting of dysprosium, molybdenum, platinum, palladium, erbium, silicon, boron, niobium, tungsten, tantalum, aluminum, zirconium, and hafnium. 6 . The interconnect for an integrated circuit according to claim 1 , wherein the doping element is uniformly or non-uniformly distributed in the interconnect barrier material throughout the entire thickness of the barrier layer. 7 . The interconnect for an integrated circuit according to claim 6 , wherein the doping element is more concentrated on a surface of the interconnect barrier material.

8. A method of forming an interconnect for an integrated circuit, the method comprising: forming a collection of potential barrier structures, each of the potential barrier structures comprising an interconnect barrier material doped at a plurality of doping locations and at a plurality of doping amounts of one of a plurality of potential doping elements; calculating the density of states of each of the barrier structures of the assembly; selecting a doping element and a doping amount based on the state density; as well as depositing a barrier layer comprising an alloy comprising the interconnect barrier material and a selected doping element at a selected doping level, Wherein the density of states of the alloy is at least 50% greater than the density of states of the interconnect barrier material.

9. A method for forming an interconnect for an integrated circuit according to claim 8, wherein calculating the density of states includes utilizing at least one simulation program selected from the following: first principles based density functional theory atomic simulation; a combination of first principles based density functional theory simulation and predictive modeling utilizing a machine learning model, wherein the machine learning model is trained from data generated by simulations of the interconnect barrier material doped with a dopant; a combination of first principles based density functional theory simulation and experimental information about the conductivity of the interconnect barrier material in the presence of the dopant; and a combination of material simulation and experimental data available in public and proprietary repositories.

10. The method of forming an interconnect for an integrated circuit according to claim 8, wherein the deposition of the barrier layer comprises co-depositing the interconnect barrier material with a selected doping element using atomic layer deposition, physical vapor deposition, or chemical vapor deposition.

11. The method of forming an interconnect for an integrated circuit according to claim 8, wherein The interconnect barrier material includes a first atomic element, and The depositing of the barrier layer includes co-depositing the interconnect barrier material with a compound including the doping element and the first atomic element.

12. The method of forming an interconnect for an integrated circuit according to claim 11, wherein the interconnect barrier material comprises Ti x N y , and the compound includes Ta x N y .

13. The method of forming an interconnect for an integrated circuit according to claim 8, further comprising: Deposition of interlayer dielectric layers, The deposition of the barrier layer comprises: depositing a monolayer of the doping element on a surface of the interlayer dielectric layer; depositing the interconnect barrier material over the monolayer of the doping element; and The doping element is diffused into the interconnect barrier material to form the alloy.

14. The method of forming an interconnect for an integrated circuit according to claim 8, wherein the deposition of the barrier layer comprises: depositing a first interconnect barrier material layer including the interconnect barrier material and a selected doping element on the interlayer dielectric layer; depositing a second interconnect barrier material layer on the first interconnect barrier material layer; as well as The first interconnect barrier material layer and the second interconnect barrier material layer are reacted to form the alloy of the interconnect barrier material and the doping element.

15. The method of forming an interconnect for an integrated circuit according to claim 8, wherein the density of states of the alloy is 1 to 10 times greater than the density of states of the interconnect barrier material, and the vertical conductivity of the alloy is greater than the vertical conductivity of the interconnect barrier material.

16. The method of forming an interconnect for an integrated circuit as recited in claim 8, wherein the doping element is non-uniformly distributed in the interconnect barrier material throughout the entire thickness of the barrier layer.

17. The method of forming an interconnect for an integrated circuit according to claim 8, wherein the deposition of the barrier layer comprises: depositing the interconnect barrier material on an interlayer dielectric layer; as well as The interconnect barrier material is doped with a selected doping element at a selected doping amount.

18. The method of forming an interconnect for an integrated circuit of claim 17, wherein doping the interconnect barrier material with a selected doping element at a selected doping amount comprises: exposing a surface of the interconnect barrier material to a gas including the dopant element; as well as The interconnect barrier material is reacted with the doping element to form an alloy on the surface.

19. The method of forming an interconnect for an integrated circuit according to claim 8, further comprising: Deposition of interlayer dielectric layers, The deposition of the barrier layer comprises: depositing the interconnect barrier material on the interlayer dielectric layer; plating a layer of the doping element on the interconnect barrier material; and The doping element is diffused into the interconnect barrier material to form the alloy.

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