Thyristor-type electrostatic discharge device and integrated circuit

Abstract

A thyristor-type electrostatic discharge device and an integrated circuit are disclosed. The thyristor-type electrostatic discharge device is based on a conventional LDMOS-SCR device. The N-well region at the drain end is split into a first N-well region and a second N-well region that match the second P-doped region and the second N-doped region in the N-well region, improving the parasitic resistance of the N-well region, making the voltage drop under the ESD discharge current increase faster, making the turn-on speed of the parasitic PNP transistor faster, improving the turn-on speed of the thyristor-type electrostatic discharge device, and improving the electrostatic discharge protection level. The integrated circuit includes the thyristor-type electrostatic discharge device. The structural improvement of the thyristor-type electrostatic discharge device of the present invention is simple, and the turn-on speed of the thyristor-type electrostatic discharge device is increased without increasing the process cost, and the electrostatic discharge protection level is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electrostatic discharge protection of integrated circuits, and in particular to a thyristor type electrostatic discharge device and an integrated circuit. Background Art

[0002] Electrostatic discharge (ESD) is a common phenomenon in daily life. Although it is not easily perceived by the human body, it can pose a serious threat to integrated circuit products.

[0003] The modes of electrostatic discharge phenomena are usually divided into several types: human body discharge mode (HBM), machine discharge mode (MM), and component charge and discharge mode (CDM). Compared with HBM and MM discharge, CDM is an ESD mode in which a pin of a chip with its own static charge contacts the ground, causing the static charge inside the chip to be transferred to the ground. Since the charge is stored in the relatively small parasitic capacitance of the chip and the total resistance of the discharge loop in the CDM mode is very small, the rising speed of the waveform is very fast, about 0.2 to 0.4ns, the pulse duration is about 5ns, and the peak current can reach 15 to 20 times the peak value of HBM discharge under the same ESD stress. This requires that the ESD protection device be turned on quickly enough and have the characteristics of high robustness.

[0004] According to statistics from National Semiconductor, 38% of all integrated circuits fail due to ESD / EOS (Electrical-Over-Stress). High-voltage CMOS (Complementary Metal Oxide Semiconductor) or high-voltage BCD (bipolar-CMOS-DMOS, a monolithic integration process) processes are widely used in the manufacture of integrated circuit products in the fields of power management, high-voltage drive, and automotive electronics. However, such integrated circuit products often work in high-current, high-voltage, and strong electromagnetic interference environments. ESD protection devices will have problems such as low robustness and false triggering, and require highly reliable and robust ESD device solutions.

[0005] For high-voltage power integrated circuits, lateral double diffusion metal-oxide-semiconductor (LDMOS) transistors are widely used as protection devices for high-voltage input / output pins because they can withstand higher breakdown voltages. LDMOS devices are a type of ESD protection device. Figure 1The schematic diagram of the structure of a conventional LDMOS device according to the prior art is shown. The existing LDMOS device 100 includes a P-type substrate 110, a P-well region 120 and an N-drift region 130 formed on the P-type substrate 110 and having no overlap with each other. A P-doped region 121 and an N-doped region 122 are arranged in the P-well region 120, and an isolation layer 123 separates the P-doped region 121 and the N-doped region 122; an N-well region 131 and a gate oxide layer 140 are arranged in the N-drift region 130, and an N-doped region 132 is arranged in the N-well region 131; two ends of the gate oxide layer 140 are respectively connected to the N-doped region 122 and the N-doped region 132, and a gate 150 is arranged on a part of the gate oxide layer 140. A drain electrode is arranged on the N-doped region 132 as an anode, and source electrodes are arranged on the P-doped region, the N-doped region and the gate to be interconnected as a cathode, wherein the electrode layer is not drawn, and the anode is an electrostatic input terminal.

[0006] like Figure 1 The working principle of the conventional LDMOS device shown in the figure when an ESD shock occurs at the anode of the electrostatic input end is as follows: when the electric field strength of the pn junction in the drain region of the LDMOS transistor is greater than its critical electric field for avalanche breakdown, the carriers in the drain region obtain enough energy under the acceleration of the electric field and an avalanche multiplication effect occurs, generating a large number of electron-hole pairs, causing the drain current to increase sharply. At the same time, the parasitic bipolar transistor inside the LDMOS transistor is turned on, generating a collector-to-emitter current, and reducing the voltage that maintains avalanche breakdown, forming a negative resistance hysteresis effect of voltage reduction and current increase, until the device reaches thermal breakdown and burns. The trigger voltage of the LDMOS transistor not only depends on the critical electric field of the avalanche breakdown of the pn junction in the drain region, but also the lateral withstand voltage of the drift region of the LDMOS transistor plays a great role, effectively improving the trigger voltage of the LDMOS ESD device, and the trigger voltage of the LDMOS ESD device can be adjusted by changing the length of the drift region. However, the parasitic bipolar transistor inside the LDMOS transistor is affected by the base widening effect, and a large hysteresis will occur after avalanche breakdown occurs, and the current rises rapidly. When it reaches the hysteresis point, the LDMOS transistor quickly enters a thermal breakdown state and cannot continue to discharge electrostatics. Therefore, the electrostatic discharge current per unit area of ​​the existing traditional LDMOS ESD device is small, and it is difficult to obtain a high ESD protection level.

[0007] Figure 2The schematic diagram of the structure of a conventional LDMOS-SCR device according to the prior art is shown. The existing LDMOS-SCR device 200 is formed with a P-well region 220 and an N-drift region 230 that do not overlap each other on a P-type substrate 210. A P-doped region 221 and an N-doped region 222 are arranged in the P-well region 220, and an isolation layer 223 separates the P-doped region 221 from the N-doped region 222; an N-well region 231 and a gate oxide layer 240 are arranged in the N-drift region 230, an N-doped region 232 and a P-doped region 233 are arranged in the N-well region 231, and an isolation layer 234 isolates the N-doped region 232 from the P-doped region 233; two ends of the gate oxide layer 240 are connected to the N-doped region 222 and the P-doped region 233, respectively, and a gate 250 is arranged on a partial area of ​​the gate oxide layer 240. Drain electrodes are provided on the N-doped region 232 and the P-doped region 233 and are interconnected as an anode. Source electrodes are provided on the P-doped region, the N-doped region and the gate and are interconnected as a cathode. The electrode layer is not drawn and the anode is an electrostatic input terminal.

[0008] like Figure 2 The equivalent circuit diagram of the LDMOS-SCR device is shown in Figure 3 As shown, it is mainly composed of two parasitic bipolar transistors, including PNP tube T1 and NPN tube T2, R1 is the equivalent parasitic resistance of the N well region, and R2 is the equivalent parasitic resistance of the P well region. When a forward ESD pulse comes, the positive voltage causes the PN junction formed by the N drift region and the P well region in the SCR to be reverse biased. As the ESD voltage gradually increases, the PN junction gradually enters avalanche breakdown. The holes generated by the PN junction avalanche flow from the N well region to the P well region, and are finally collected by the P doped region in the P well region to generate current; similarly, the generated electrons flow from the P well region to the N well region and are finally collected by the N doped region in the N well region to generate current. Since both the N well region and the P well region have parasitic resistances R1 and R2, a voltage drop will be formed on the N well region and the P well region. When the voltage drop on the N well region or the P well region reaches 0.7V, one of the parasitic transistors NPN or PNP will be turned on. When one transistor is turned on, the voltage drop caused by the current generated on its collector will immediately turn on the other parasitic transistor. Eventually, the two transistors form an open-circuit positive feedback mechanism, and the SCR is fully turned on, forming a low-resistance path. When the parasitic resistances R1 and R2 of the N-well and P-well regions are small, a larger ESD current is required to trigger the SCR path to turn on, causing the SCR to turn on slowly, resulting in delayed electrostatic discharge and damage to the system. Summary of the invention

[0009] In view of the above problems, an object of the present invention is to provide a thyristor-type electrostatic discharge device and an integrated circuit, so as to improve the response speed of electrostatic discharge protection.

[0010] According to one aspect of the present invention, there is provided a thyristor type electrostatic discharge device, characterized in that it comprises:

[0011] substrate;

[0012] A P-well region, located in the substrate;

[0013] A drift region, located in the substrate and not overlapping with the P-well region;

[0014] A first P-doped region and a first N-doped region are located in the P-well region, and the first P-doped region is farther away from the drift region than the first N-doped region;

[0015] A first N-well region and a second N-well region are located in the drift region and have a distance greater than zero between them;

[0016] A second P-doped region and a second N-doped region are respectively located in the first N-well region and the second N-well region, and the second P-doped region is closer to the P-well region than the second N-doped region;

[0017] a gate oxide layer, disposed between the P-well region and the N-well region, with one end in contact with the first N-doped region and the other end in contact with the second P-doped region;

[0018] The polysilicon layer is disposed on the gate oxide layer.

[0019] Optionally, a distance between the first N-well region and the second N-well region is adjustable.

[0020] Optionally, the first P-doped region, the first N-doped region and the gate layer are all electrically connected to the cathode of the thyristor-type electrostatic discharge device, and the second P-doped region and the second N-doped region are all electrically connected to the anode of the thyristor-type electrostatic discharge device.

[0021] Optionally, the gate oxide layer includes a continuous first segment and a second segment, the thickness of the first segment is smaller than the thickness of the second segment, the first segment extends to the first N-doped region, the second segment extends to the second P-doped region, and the second segment is located in the drift region.

[0022] Optionally, the polysilicon layer is a stepped structure matching the gate oxide layer, and completely covers the first segment and partially covers the second segment.

[0023] Optionally, a distance between the P-well region and the drift region is greater than zero.

[0024] According to another aspect of the present invention, there is provided an integrated circuit, characterized in that it comprises:

[0025] According to one aspect of the present invention, a thyristor electrostatic discharge device is provided.

[0026] The thyristor-type electrostatic discharge device provided by the present invention is based on a traditional LDMOS-SCR device, and splits the N-well region at the drain end into a first N-well region and a second N-well region that match the second P-doped region and the second N-doped region in the N-well region, thereby increasing the parasitic resistance of the N-well region, so that the voltage drop under the ESD discharge current is increased faster, the turn-on speed of the parasitic PNP tube is increased faster, the turn-on speed of the thyristor-type electrostatic discharge device is increased, and the electrostatic discharge protection level is improved.

[0027] The change in the number of N-well regions in the lateral structure does not require additional use of graphic masks in the manufacturing process, will not increase the process cost, and is highly feasible.

[0028] The magnitude of the parasitic resistance of the N-well region is affected by the distance between the first N-well region and the second N-well region. By adjusting the distance, the trigger voltage can be adjusted.

[0029] The thickness of the second section of the gate oxide layer located in the drift region is thick, which can improve the current driving capability, improve the device turn-on current increase speed, and improve the device electrostatic protection turn-on speed.

[0030] The integrated circuit of the present invention comprises the thyristor-type electrostatic discharge device provided by the present invention, and has fast response speed of electrostatic discharge protection and high reliability of electrostatic discharge protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0032] Figure 1 A schematic diagram of the structure of a conventional LDMOS device according to the prior art is shown;

[0033] Figure 2 A schematic diagram of the structure of a conventional LDMOS-SCR device according to the prior art is shown;

[0034] Figure 3 An equivalent circuit diagram of a conventional LDMOS-SCR device according to the prior art is shown;

[0035] Figure 4 A schematic structural diagram of a thyristor-type electrostatic discharge device according to the present invention is shown;

[0036] Figure 5 A performance comparison diagram of the thyristor-type electrostatic discharge device according to the present invention and the LDMOS-SCR device of the prior art is shown. DETAILED DESCRIPTION

[0037] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0038] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0039] Figure 4 The schematic diagram of the structure of the thyristor type electrostatic discharge device according to the present invention is shown. As shown in the figure, the thyristor type electrostatic discharge device 300 of the present invention includes a P well region 320 and an N drift region 330 that do not overlap each other on a P substrate 310. The depth of the drift region 330 is greater than the depth of the P well region 320.

[0040] The distance between the N drift region 330 and the P well region 320 is greater than zero, which can suppress the extraction of holes from the drift region by the P well region, thereby facilitating the increase of hole concentration and the reduction of conduction voltage drop.

[0041] A P-doped region 321 , an N-doped region 322 and an isolation layer 323 are provided in the P-well region 320 . The isolation layer 323 separates the P-doped region 321 from the N-doped region 322 .

[0042] The N drift region 330 is provided with a separated N well region 331 and an N well region 332, the N well region 331 is provided with a P doping region 333, the N well region 332 is provided with an N doping region 334, and the isolation layer 335 separates the P doping region 333 and the N doping region 334, wherein the P doping region 333 and the N doping region 334 constitute a drain terminal.

[0043] The gate oxide layer 340 is arranged between the P-doped region 333 and the N-doped region 322. The polysilicon layer 350 is arranged on a partial area of ​​the gate oxide layer 340. In this embodiment, the gate oxide layer 340 includes a first section and a second section with different thicknesses, wherein the thickness of the first section is less than that of the second section, the second section is located in the N drift region 330, one end is connected to the first section, and the other end extends to the edge area of ​​the P-doped region 333; the first section extends to the edge area of ​​the N-doped region 322. The polysilicon layer 350 is designed to be a stepped structure to match the gate oxide layer 240, and completely covers the first section of the gate oxide layer 340 and covers a partial area of ​​the second section. The high-thickness gate oxide layer can also improve the large current load capacity of the device, improve the voltage resistance, and improve the robustness of the device. The polysilicon layer 350 is designed to match the gate oxide layer 340, which can optimize the corresponding electrical characteristics and improve the reliability. The gate oxide layer can also be used as a mask for forming a doped region.

[0044] An undrawn electrode layer is also provided on the P-doped region 321, the N-doped region 322, the P-doped region 333, the N-doped region 334 and the polysilicon layer 350, wherein the electrode layers of the P-doped region 321, the N-doped region 322P and the polysilicon layer 350 are interconnected to form a cathode, and the electrode layers of the P-doped region 333 and the N-doped region 334 are interconnected to form an anode, which is an electrostatic voltage input terminal, and the cathode can be grounded.

[0045] The thyristor type electrostatic discharge device 300 of the embodiment of the present invention is Figure 2 The equivalent circuit diagram of the conventional LDMOS-SCR device 200 shown is the same, and the main difference is that the N-well region corresponding to the P-doped region 333 and the N-doped region 334 at the drain end of the thyristor-type electrostatic discharge device 300 of the present invention is divided into an N-well region 331 and an N-well region 332 to increase the parasitic resistance R1, accelerate the voltage drop of the parasitic resistance R1 as the electrostatic discharge current increases, and accelerate the turn-on speed of the parasitic transistor (the voltage drop of the parasitic resistance R1 reaches 0.7V faster to quickly turn on the parasitic PNP transistor T1, thereby turning on the entire SCR path), thereby reducing the trigger current required to turn on the SCR path and improving the turn-on speed of the SCR.

[0046] The distance between the N-well region 332 and the N-well region 331 can be adjusted according to the requirements, and the actual parameters are not uniquely fixed. The larger the distance, the larger the parasitic resistance of the N-well region, and the faster the turn-on speed.

[0047] Moreover, the improvement of the structure lies in the increase of the number of well regions in the lateral structure, without the increase of the longitudinal layer structure, that is, in the manufacturing process of the device, there is no need to increase the number of layers of the patterned mask, and the thyristor-type electrostatic discharge device with a fast opening speed of the present invention can be obtained without increasing the process cost. Moreover, the process applicability of the thyristor-type electrostatic discharge device of the present invention is high, and the isolation layer can be manufactured by using the high-voltage silicon local oxidation isolation (Local Oxidation of Silicon) technology, or other high-voltage processes are also applicable.

[0048] Figure 5 The performance comparison diagram of the thyristor type electrostatic discharge device according to the present invention and the LDMOS-SCR device of the prior art is shown. As shown in the figure, the thyristor type electrostatic discharge device (also called SCR device) of the present invention and the traditional SCR device ( Figure 2The TLP (Transmission Line Pulse) curve of the LDMOS-SCR device shown in the figure is generally the same in appearance, that is, it has basic electrostatic discharge protection function and has high robustness. Furthermore, the SCR device of the present invention has a low trigger voltage and a small trigger current, and can be triggered under a smaller ESD current, thereby releasing the ESD current by hysteresis, and its turn-on time is greatly shortened. The trigger voltage is low, and the protection reliability of the protected device is high. The secondary breakdown current is higher than the secondary breakdown current of the traditional SCR device, has stronger robustness, and has a higher ESD protection level.

[0049] The thyristor type electrostatic discharge device of the present invention is based on the traditional LDMOS-SCR device, and the N well area of ​​the drain area is divided into two N well areas that match the P doping area and the N doping area of ​​the N well area of ​​the drain area, so as to increase the parasitic well area resistance of the parasitic PNP transistor, reduce the opening current of the thyristor electrostatic discharge path of the thyristor type electrostatic discharge device, so that the SCR path can be triggered under a smaller ESD current, shorten the device opening time, so that it can be quickly opened in the CDM mode, and effectively protect the integrated circuit using the thyristor type electrostatic discharge device. The overall structure of the device is simple and effective, and is simply improved on the basis of the traditional device, and has excellent practicality.

[0050] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A thyristor-type electrostatic discharge device, characterized in that, it comprises: a substrate; a P-well region located in the substrate; a drift region located in the substrate and having no overlap with the P-well region; a first P-doped region and a first N-doped region located in the P-well region, the first P-doped region being farther from the drift region than the first N-doped region, and the first P-doped region and the first N-doped region being separated by a first isolation layer; a first N-well region and a second N-well region located in the drift region and having a spacing greater than zero between them; a second P-doped region and a second N-doped region respectively located in the first N-well region and the second N-well region, the second P-doped region being closer to the P-well region than the second N-doped region, and the second P-doped region and the second N-doped region being separated by a second isolation layer; a gate oxide layer disposed between the P-well region and the first N-well region, one end in contact with the first N-doped region and the other end in contact with the second P-doped region; a polysilicon layer disposed on the gate oxide layer.

2. The thyristor-type electrostatic discharge device according to claim 1, characterized in that, the spacing between the first N-well region and the second N-well region is adjustable.

3. The thyristor-type electrostatic discharge device according to claim 1, characterized in that, the first P-doped region, the first N-doped region and the polysilicon layer are all electrically connected to the cathode of the thyristor-type electrostatic discharge device, and the second P-doped region and the second N-doped region are all electrically connected to the anode of the thyristor-type electrostatic discharge device.

4. The thyristor-type electrostatic discharge device according to claim 1, characterized in that, the gate oxide layer comprises a continuous first section and a second section, the thickness of the first section is less than the thickness of the second section, the first section extends to the first N-doped region, the second section extends to the second P-doped region, and the second section is located in the drift region.

5. The thyristor-type electrostatic discharge device according to claim 4, characterized in that, the polysilicon layer is a stepped structure matching the gate oxide layer and completely covers the first section and partially covers the second section.

6. The thyristor-type electrostatic discharge device according to claim 1, characterized in that, the spacing between the P-well region and the drift region is greater than zero.

7. An integrated circuit, characterized in that, it comprises: the thyristor-type electrostatic discharge device according to any one of claims 1 to 6.

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