Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to a semiconductor device and a manufacturing method thereof. A semiconductor chip is mounted to a chip mounting portion of a lead frame, one or more leads in the lead frame are arranged to face the chip mounting portion. The leads are located in a first plane and the chip mounting portion is located in a second plane, the first plane and the second plane being offset from each other with a gap therebetween. An electronic component, such as a capacitor, is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.

Description

[0001] CLAIM

[0002] This application claims priority to Italian Patent Application No. 102019000000929 filed on January 22, 2019, the contents of which are incorporated herein in its entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] The present description relates to semiconductor devices.

[0004] For example, one or more embodiments can be applied to integrated circuits (ICs). BACKGROUND

[0005] Currently, printed circuit boards (PCBs) for integrated circuits (ICs) are “filled” with (many) components, such as integrated circuit (IC) devices (which can be arranged in plastic / ceramic packages), passive components, connectors, etc.

[0006] There is a growing trend to integrate components (passive components, such as capacitors, inductors) into IC device packages, thereby removing them from the PCB surface.

[0007] With this approach, generally referred to as “system-in-package” or SiP, it can be advantageous in terms of PCB space saving and can facilitate PCB miniaturization.

[0008] It can be considered to apply this approach to arrangements employing SMD (surface mount device) technology, where SMDs are electrically connected via conductive structures, such as wire bonds and / or leads from a lead frame (LF).

[0009] Despite the extensive activity in this field, there is still a desire for further improved solutions. For example, there is a desire for improvements in terms of impedance behavior exhibited by components integrated in a package.

[0010] Therefore, there is a need in the art for improved solutions.

[0011] To address problems related to the integration of electronic components in semiconductor product packages, various solutions have been proposed.

[0012] Documents such as U.S. Patent No. 6,611,434 and 7,960,816 B2 or U.S. Patent Application Publication No. 2002 / 195693 are examples of such solutions (these documents are incorporated herein by reference).

[0013] These solutions can suffer from various drawbacks related to poor electrical performance associated with the long connection structures provided for coupling (e.g., passive) electronic components to integrated circuits (e.g., application specific integrated circuits or ASICs) with intermediate elements or possibly intervening substrate portions. SUMMARY

[0014] According to one or more embodiments, a semiconductor device and a respective method of manufacturing a semiconductor device are provided.

[0015] One or more embodiments can include components integrated in a package (e.g., SMD) that is mounted “vertically” on a die pad that abuts and is coupled to a dedicated lead of a leadframe.

[0016] One or more embodiments are found to provide an impedance reduction of up to 40% in capacitive components above 30 MHz.

[0017] One or more embodiments can provide a leadframe package that includes a two-terminal SMD mounted / coupled vertically on a die pad, and whose other terminal is electrically coupled, e.g., through a lead or wire. BRIEF DESCRIPTION OF DRAWINGS

[0018] One or more embodiments are now described, by way of example only, with reference to the accompanying drawings, in which:

[0019] FIG. 1 is a diagram of a portion of a semiconductor device according to embodiments of the present specification,

[0020] FIG. 2 is a side view representation of a portion of a semiconductor device according to embodiments of the present specification,

[0021] FIGS. 3A-3E is an example of possible steps to produce an arrangement as FIG. 2 illustrated,

[0022] FIG. 4 , FIG. 5 and FIGS. 6A-6D are examples of possible further steps to produce according to embodiments of the present specification,

[0023] FIG. 7 and FIG. 8 are side view representations of a portion of a semiconductor device according to embodiments of the present specification, and

[0024] FIG. 9 is an example graph of possible impedance versus frequency behavior in embodiments of the present specification. DETAILED DESCRIPTION

[0025] In the following description, one or more specific details are described to provide an example embodiment of the disclosure. Other embodiments can be utilized, and not all specific details are required to practice the embodiments. In other instances, well-known structures, materials, or operations are not described in detail in order to avoid obscuring the specific aspects of the embodiments.

[0026] Within the framework of this specification, a reference to "an embodiment" or "one embodiment" is intended to indicate that a particular configuration, structure, or characteristic described in relation to this embodiment is included in at least one embodiment. Thus, appearances of the phrase "in one embodiment" or "in an embodiment" in one or more places in the specification are not necessarily all referring to the same embodiment. Furthermore, a particular configuration, structure, or characteristic can be combined in any suitable way in one or more embodiments.

[0027] The references used herein are provided merely for convenience and thus do not limit the scope of the protection or the embodiments.

[0028] FIG. 1 is an example of a part of a semiconductor product package, which includes one or more leads 10 in a leadframe (not visible as a whole), inner ends of the leads facing and at least partially overlapping a part 12 (so-called die pad or slug) of the package, intended for mounting one or more semiconductor chips or dies 14 (in a manner known to the skilled person) on the part 12.

[0029] In the remainder of this specification, for simplicity, only one such semiconductor chip or die 14 will be considered.

[0030] Reference numeral 16 denotes an electronic component (e.g. a passive component, such as a decoupling capacitor) arranged in a bridge-like fashion between one (conductive) lead 10 and (conductive) pad or slug 12, to provide an electrical coupling therebetween.

[0031] In as FIG. 2 (As well as in FIG. 7 and FIG. 8 ) one or more embodiments exemplified, the leads 10 and the pad or slug 12 can be considered to extend in respective - at least approximately parallel - (e.g. median) planes X10 and X12, which are mutually offset from the component 16 extending between these two planes.

[0032] In one or more embodiments, as discussed below, such electrical coupling can be provided via conductive masses 18 and 20.

[0033] SMD capacitors such as EIA SIZE 0201 (0.6 mm x 0.3 mm in length x width) capacitors or EIA SIZE 0402 (1.0 mm x 0.5 mm in length x width) capacitors can be an example of components such as component 16.

[0034] As exemplified herein, component 16 can be in an elongated form or shape, i.e. a form that is longer with respect to its width, for example in the case of the EIA SIZE 0201 or EIA SIZE 402 capacitors mentioned by way of example above, the length is twice the width.

[0035] In one or more embodiments, component 16 can thus be mounted in a bridge-like manner between lead 10 and pad or die 12, with longitudinal axis X16 (i.e. the axis along the longer or longest extension of component 16) arranged transversely to pad or die 12 (e.g. perpendicular to and extending between planes X10 and X12).

[0036] For example, component 16 can be mounted with longitudinal axis X16 orthogonal to the extension plane X12 of pad or die 12. For example, by assuming that pad or die 12 can be considered to lie in a horizontal plane X12, elongated component 16 can be arranged with its axis X16 arranged perpendicularly.

[0037] In FIGS. 3A-3E an exemplary sequence of steps, FIG. 3A it is shown that the leadframe (in a manner known to the person skilled in the art) is provided with one or more leads 10, the (inner) end of which faces a respective (e.g. peripheral) portion of pad or die 12 and has a separation gap 22 therebetween.

[0038] As FIG. 3A exemplified, the inner end of lead 10 can overlap (i.e. protrude above) the portion of pad or die 12. It will otherwise be understood (e.g. see FIG. 7 and FIG. 8 discussed below) that such an overlap is not a mandatory feature.

[0039] In FIG. 3A , semiconductor chip or die 14 is shown as having been attached (in any manner known to the person skilled in the art) on pad or die 12.

[0040] FIG. 3B is an example of an act of providing (first) conductive masses on die pad or die 12, which are aligned (vertically) with the end portions of lead 10 protruding above pad or die 12.

[0041] In one or more embodiments, block 18 may include pre-formulated or solder material applied to the pad or strip 12 after dispensing a reagent (or flux) to promote a strong bond between block 18 and pad or strip 12.

[0042] FIG. 3C This is an example of placing component 16 on block 18, as discussed earlier. This involves placing the elongated component 16 "vertically," meaning that its main dimension X16 extends laterally to the pad or insert 12.

[0043] FIG. 3D This is an example of a (second) block of conductive material 20 disposed between the (upper) terminal of component 16 and the inner tip of lead 10.

[0044] In one or more embodiments, block 20 may include prefabricated or solder material. In one or more embodiments, FIG. 3D The actions illustrated may also include solder reflow and reagent (or flux) cleaning.

[0045] FIG. 3E This is an example of a possible setup that provides electrical coupling of lead 10 to a corresponding die pad (see reference numeral 24a) located on the front or upper surface of a semiconductor chip or die 14 with (other conventional) wire or strip junction 24.

[0046] Although it benefits all aspects, FIGS. 3A-3E The illustrated sequence of actions is not mandatory. For example, mentioning only one possible alternative, the semiconductor die or chip 14 may be attached to the pad or strip 12 after the component 16 is arranged in a bridge-like manner across the gap 22 between the lead 10 and the pad or strip 12.

[0047] FIG. 1 and FIG. 2 (as well as FIGS. 3C-3E This is an example of the possibility that component 16 extends in a bridge-like manner between the chip mounting portion 12 and the side of the lead 10, with component 16 adjacent to the side, thereby extending the lead 10 laterally, rather than being sandwiched between the lead 10 and the pad or insert 12.

[0048] like FIG. 1 and FIG. 2 (as well as FIGS. 3C-3E As shown, lead 10 may present a side surface (such as a "vertical" end face transverse to planes X10 and / or X12) such that component 16 may face lead 10 at its end (here, the upper end) against the side surface of lead 10.

[0049] like FIG. 1 and FIG. 2 (as well as FIGS. 3C-3E) as illustrated, this can also facilitate the placement from the top of the leadframe and / or the use of components 16 having a length greater than the distance between the leads 10 and the pads or lands 12 measured transversely (orthogonally) to the planes X10 and X12.

[0050] One or more embodiments can take into account the fact that, in particular embodiments, the leads 10 can be power leads. Since the leads are clamped at the wire joints (as FIG. 4 illustrated at the clamping area A), the rigid joints to the pads or lands 12 created via the electronic components 16 can thus be exposed to the risk of breaking.

[0051] In one or more embodiments, this problem can be solved by providing a physical connection (e.g., a bridge contact as illustrated in 100) between the (power) lead 10 coupled with the component 16 and at least one adjacent lead 10 having such a rigid joint to the pads or lands 12. FIG. 5

[0052] One or more embodiments can take into account the modification of the clamping foot design intended to act at the clamping area A by providing a gap therein (as FIG. 5 illustrated at 102).

[0053] Thus, by avoiding the application of the clamping force thereto, a local release can be provided at the lead 10 coupled with the component 16, while as FIG. 5 illustrated, the power lead 10 can be provided with a (power) line coupling to the die of the die 12, wherein the component 16 is coupled with the power lead 10 via an adjacent lead 10 (e.g., via a bridge contact 100) physically connected thereto. FIG. 5

[0054] FIGS. 6A-6D The sequence of 1000 is an example of a stamping process applied to the original substrate (e.g., a roll of copper) of the leadframe. FIG. 5 The sequence of 1000 is an example of a stamping process applied to the original substrate (e.g., a roll of copper) of the leadframe.

[0055] In particular, FIG. 6A and FIG. 6B The sequence of 1000 is an example of a stamping process applied to the original substrate (e.g., a roll of copper) of the leadframe.

[0056] In this process, the flexibility of the stamping tool can facilitate (possibly during the manufacturing of the leadframe by the supplier) the addition / removal of punches and their change of position in order to provide pin-pin (lead-lead) electrical connections (e.g., 100) where needed.

[0057] For example, FIG. 6B is an example of a stamping process via a stamping tool ST as FIG. 6C ​​As shown, the stamping process results in the plurality of leads 10 being physically (and electrically) coupled to each other via the bridges 100.

[0058] The stamping process exemplified herein can include stamping out (e.g. FIG. 6D Further actions (exemplified in the middle at P) to the pin-pin connection that can not be required for a particular application.

[0059] The possibility of using the same leads 10 as power leads for a plurality of semiconductor products (e.g. ICs) can facilitate the adoption of a standardized location of the physical connection, thereby facilitating the standardization of the leadframe design.

[0060] FIG. 7 And FIG. 8 One or more embodiments are exemplified that apply to an arrangement comprising leads 10 facing pads or lands 12 and defining a gap 22 therebetween without protruding over the pads or lands 12, e.g. a QFP package - QFP is an acronym for Quad Flat Package.

[0061] Here again, the leads 10 and the pads or lands 12 can be seen as extending in respective (at least approximately parallel) planes X10 and X12 (e.g. mid-value planes of the leads 10 and the pads or lands 12, respectively), which are mutually offset from the component 16 extending between these two planes.

[0062] In FIG. 7 And FIG. 8 In one or more embodiments exemplified above, the conductive bumps 20 discussed above can be replaced by wire (or possibly ribbon) bonds 200, which are electrically coupled to the leads 10 at the terminal ends of the component 16 opposite the pads or lands 12.

[0063] Such wire or ribbon bonding of the component 16 to the leads 10 can be:

[0064] - direct, as exemplified in FIG. 7 This can involve electrode finishing compatible with wire bonding technology, as exemplified in

[0065] - indirect, as exemplified in FIG. 8 i.e. via the die-pad 24a provided for the lead-die bonding 24, which can facilitate and optimize wire length.

[0066] As exemplified in FIG. 7 And FIG. 8 One or more embodiments exemplified can retain the advantage of arranging the elongated component 16 (such as an EIA SIZE 0201 or EIA SIZE 0402 capacitor) transversely (e.g. perpendicularly) to the pads or lands 12, thereby reducing the footprint of the component 16 on the pads or lands 12.

[0067] FIG. 7 and FIG. 8 One or more embodiments illustrated in Fig. 6 again illustrate the possibility of having a length of the component 16 that is longer than the distance between the lead 10 and the pad or tab 12 measured transversely (orthogonally) to the planes X10 and X12 due to the lateral extension of the lead 10.

[0068] FIG. 9 The graph of Fig. 5 is an example of impedance (Ohms) measured for a 0201 SMD capacitor with a nominal capacitance value of 10 nF in a frequency range between 0.001 GHz and 1.000 GHz.

[0069] The impedance behavior of a capacitor assembly according to an embodiment of the present specification (as shown by the chain line in Fig. 6) shows an improvement of more than 40% over the entire frequency range above the frequency at which the lowest impedance is measured compared to the impedance behavior of a conventional capacitor assembly (as shown by the continuous line). FIG. 9

[0070] Hence, one or more embodiments can provide for an optimized electronic connection from the ground electrode (provided by the pad or tab 12) to the backside of the die 14 by the tab and not by the lead, while also showing a shorter lead connection from the lead 10 (e.g. power supply lead) to the die 14.

[0071] One or more embodiments can facilitate a reduction (theoretically halving) of the number of dedicated power supply pins in a semiconductor device (such as an integrated circuit) compared to a conventional planar SMD assembly, while also facilitating a standardization of the lead frame design as discussed earlier.

[0072] A device as illustrated herein can comprise:

[0073] - at least one semiconductor chip (e.g. 14),

[0074] - a lead frame (e.g. 10, 12) comprising a chip mounting portion (e.g. 12) with the at least one semiconductor chip on it and at least one lead (e.g. 10) arranged to face the chip mounting portion, the at least one lead being located in a first plane (e.g. X10) and the chip mounting portion being located in a second plane (e.g. X12), the first plane and the second plane being mutually offset with a gap (e.g. 22) therebetween, and

[0075] - an electronic component (e.g. 16) arranged on the chip mounting portion and extending between the first plane and the second plane.

[0076] ​The devices exemplified herein can comprise an elongated electronic component extending along a longitudinal axis (e.g., X16), the electronic component being arranged on a chip mounting portion, wherein the longitudinal axis is transverse (e.g., orthogonal) to the second plane.

[0077] The devices exemplified herein can comprise:

[0078] - a first electrically conductive structure (e.g., 18) electrically coupling the chip mounting portion and the electronic component arranged on the chip mounting portion, and

[0079] - at least one second electrically conductive structure (e.g., 20; 200; 200, 24) electrically coupling the electronic component to at least one lead arranged facing the chip mounting portion.

[0080] In the devices exemplified herein, the first electrically conductive structure can comprise an electrically and mechanically conductive material electrically and mechanically coupling the electronic component and the chip mounting portion.

[0081] In the devices exemplified herein, the at least one lead can be arranged facing the chip mounting portion and at least partially overlapping the chip mounting portion (e.g., see FIG. 2 ), the electronic component extending in a bridge-like manner between the chip mounting portion and the at least one lead arranged facing the chip mounting portion.

[0082] In the devices exemplified herein, the second electrically conductive structure can comprise an electrically and mechanically conductive material electrically and mechanically coupling the electronic component to the at least one lead arranged facing the chip mounting portion and at least partially overlapping the chip mounting portion (e.g., see FIG. 2 ).

[0083] In the devices exemplified herein, the at least one second electrically conductive structure can comprise a wire-like (wire or ribbon) material (e.g., 200 or 200, 24) directly electrically coupling the electronic component to the at least one lead arranged facing the chip mounting portion (e.g., see FIG. 7 200) or electrically coupling the electronic component to the at least one lead arranged facing the chip mounting portion via at least one semiconductor chip on the chip mounting portion (e.g., see FIG. 8 200, 24).

[0084] In the devices exemplified herein (e.g., see FIG. 1 and FIG. 2 as well as FIGS. 3C-3E ), the electronic component (e.g., 16) can laterally extend between the chip mounting portion and a side of the at least one lead, the electronic component being contiguous to the side.

[0085] In the devices exemplified herein (e.g., seeFIG. 1 and FIG. 2 and FIGS. 3C-3E plus FIG. 7 and FIG. 8 ) the length of the electronic component can be greater than the distance between the chip mounting portion and the at least one lead wire transverse (e.g., orthogonal) to the first plane and the second plane.

[0086] The device as exemplified herein can comprise:

[0087] - at least one second lead wire (e.g., see the third lead wire 10 from the left in FIG. 5 ) arranged laterally with respect to the at least one lead wire arranged facing the chip mounting portion, the at least one second lead wire being mechanically and electrically coupled (100) to the at least one lead wire arranged facing the chip mounting portion in the lead frame, and

[0088] - a linear (e.g., wire or ribbon) bond (see FIG. 5 ) between the at least one semiconductor chip on the chip mounting portion and the at least one second lead wire in the lead frame, wherein the electronic component is electrically coupled to the at least one semiconductor chip on the chip mounting portion via the linear bond between the at least one semiconductor chip on the chip mounting portion and the at least one second lead wire in the lead frame.

[0089] The method of manufacturing a device as exemplified herein can comprise:

[0090] - arranging at least one semiconductor chip on a chip mounting portion of a lead frame, the lead frame having the at least one lead wire arranged facing the chip mounting portion, the at least one lead wire being located in a first plane, and the chip mounting portion being located in a second plane, the first plane and the second plane being offset from each other with a gap therebetween,

[0091] - arranging an electronic component on the chip mounting portion, the electronic component extending between the first plane and the second plane.

[0092] The method as exemplified herein can comprise providing a linear material (e.g., FIG. 4 and FIG. 5 ) to electrically couple the lead frame to the at least one semiconductor chip on the chip mounting portion, wherein providing the linear material can comprise applying a clamp (e.g., at A) to the lead frame, wherein the method can comprise avoiding (e.g., FIG. 5 ) applying a clamp to the at least one lead wire arranged facing the chip mounting portion in the lead frame at 102.

[0093] Details and embodiments can vary without affecting the essence of the principles described by way of example only, even significantly, without departing from the scope of protection. The scope of protection is defined by the claims that follow.

[0094] The claims are an integral part of the technical teaching provided herein for the embodiments.

Claims

1. A device comprising: a semiconductor chip, a leadframe comprising a chip mounting portion, wherein the semiconductor chip is mounted to the chip mounting portion and at least one lead is arranged facing the chip mounting portion, the at least one lead lying in a first plane and the chip mounting portion lying in a second plane, the first plane and the second plane being mutually offset with a gap therebetween; and an electronic component arranged on the chip mounting portion and extending between the first plane and the second plane; wherein: the at least one lead is arranged facing the chip mounting portion and at least partially overlapping the chip mounting portion, the electronic component extending in a bridge-like manner between the chip mounting portion and the at least one lead arranged facing the chip mounting portion; and the electronic component extends along a lateral direction of the at least one lead between the chip mounting portion and a side face of the at least one lead, the electronic component abutting the side face, wherein a first electrically conductive structure electrically couples the electronic component to the chip mounting portion and a second electrically conductive structure electrically couples the electronic component to the side face of the at least one lead in the leadframe.

2. The device of claim 1, wherein the electronic component comprises an elongate electronic component extending along a longitudinal axis, the electronic component being arranged on the chip mounting portion, wherein the longitudinal axis is transverse to the second plane.

3. The device of claim 1, wherein the first electrically conductive structure comprises an electrically conductive material electronically and mechanically coupling the electronic component and the chip mounting portion.

4. The device of claim 3, wherein the second electrically conductive structure comprises an electrically conductive material electronically and mechanically coupling the electronic component to the at least one lead arranged facing the chip mounting portion and at least partially overlapping the chip mounting portion.

5. The device of claim 1, wherein the at least one second electrically conductive structure comprises a wire-like material electrically coupling the electronic component to the at least one lead arranged facing the chip mounting portion directly or via the at least one semiconductor chip on the chip mounting portion.

6. The device of claim 1, wherein a length of the electronic component is greater than a distance between the chip mounting portion and the at least one lead transverse to the first plane and the second plane.

7. The device of claim 1, comprising: at least one second lead in the leadframe, the at least one second lead being arranged parallel and adjacent to the at least one lead arranged facing the chip mounting portion, the at least one second lead being mechanically and electrically coupled to the at least one lead arranged facing the chip mounting portion, and ​ a linear junction between the at least one semiconductor chip on the chip mounting portion and the at least one second lead of the lead frame, wherein the electronic component is electrically coupled to the at least one semiconductor chip on the chip mounting portion via the linear junction between the at least one semiconductor chip on the chip mounting portion and the at least one second lead of the lead frame.

8. A method of manufacturing, comprising: arranging a semiconductor chip on a chip mounting portion of a lead frame, wherein the lead frame has at least one lead arranged facing the chip mounting portion, the at least one lead being located in a first plane and the chip mounting portion being located in a second plane, the first plane and the second plane being mutually offset with a gap therebetween; arranging an electronic component on the chip mounting portion, the electronic component extending between the first plane and the second plane; and arranging the at least one lead facing the chip mounting portion and at least partially overlapping the chip mounting portion, the electronic component extending in a bridge-like manner between the chip mounting portion and the at least one lead arranged facing the chip mounting portion wherein the electronic component extends along a lateral direction of the at least one lead between the chip mounting portion and a side of the at least one lead, the electronic component being contiguous with the side, wherein a first electrically conductive structure electrically couples the electronic component to the chip mounting portion and a second electrically conductive structure electrically couples the electronic component to the side of the at least one lead of the lead frame.

9. The method of claim 8, comprising: providing a linear material electrically coupling the lead frame to the semiconductor chip on the chip mounting portion, wherein providing the linear material comprises applying a clamp to the lead frame, wherein the clamp does not apply a clamp to the at least one lead of the lead frame arranged facing the chip mounting portion.

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