Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed adjacent to the semiconductor die. The metal layer is disposed on and electrically connected to the second conductive element. The first RDL is disposed on and electrically connected to the metal layer.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device package, and more specifically to a semiconductor device package including a metal layer and a method of manufacturing the same. Background Technology

[0002] When manufacturing semiconductor device packages, carriers are typically used to support the semiconductor structure during operations such as die attachment or molding. A carrier removal operation is usually required to remove the carrier before the manufacturing process is complete. However, adhesive materials such as tape or film used when placing the carrier may remain on the semiconductor structure, leading to subsequent problems, such as reliability concerns due to contamination from the remaining material. Furthermore, bending of the semiconductor structure may occur after carrier removal. Summary of the Invention

[0003] In one aspect, according to some embodiments, a semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed adjacent to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.

[0004] In another embodiment, according to some embodiments, a semiconductor device package includes a semiconductor die, an encapsulation body, and a metal layer. The semiconductor die includes a back surface and an active surface. The encapsulation body surrounds the semiconductor die. The encapsulation body includes a first surface coplanar with the back surface of the semiconductor die and a second surface opposite to the first surface of the encapsulation body. The metal layer is disposed on the back surface of the semiconductor die and the first surface of the encapsulation body.

[0005] In another aspect, according to some embodiments, a method of manufacturing a semiconductor device package includes: (a) providing a carrier; (b) providing a metal layer on the carrier, the metal layer including a first layer and a second layer on the first layer; (c) placing a semiconductor die on the second layer of the metal layer; (d) forming an encapsulation covering the semiconductor die and the second layer of the metal layer; and (e) removing the carrier and the first layer of the metal layer. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale, and the dimensions of features depicted in the drawings may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0008] Figure 1B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0009] Figure 1C An enlarged view illustrating a portion of a semiconductor device package according to some embodiments of the present disclosure.

[0010] Figure 2 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0011] Figure 3 A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K ,

[0013] Figure 4L and Figure 4M This is a cross-sectional view of a semiconductor device package manufactured at various stages according to some embodiments of the present disclosure.

[0014] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K , Figure 5L , Figure 5M , Figure 5N and Figure 5O This is a cross-sectional view of a semiconductor device package manufactured at various stages according to some embodiments of the present disclosure.

[0015] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0016] According to some embodiments of this disclosure, a metal layer comprising two metal foils contained between a carrier and a semiconductor structure is used instead of conventional adhesive materials, such as tape or film. Removing one of the metal foils during a carrier removal operation eliminates the problem of residual adhesive material, and the remaining metal foil (or metal layer) can reduce the bending of the semiconductor structure and act as a seed layer for subsequent operations.

[0017] Figure 1A A cross-sectional view of a semiconductor device package 1a according to some embodiments of the present disclosure is shown.

[0018] The semiconductor device package 1a includes a semiconductor die 10, conductive elements 20 and 30, a metal layer 40, redistribution layers 50 and 60, an encapsulation 70, insulating layers 80 and 85, and a connecting element 90.

[0019] Semiconductor die 10 includes a surface 101 and a surface 102 opposite to said surface 101. In some embodiments, surface 101 may be referred to as a back surface, and surface 102 may be referred to as an active surface. Surface 102 may have circuitry disposed thereon. Semiconductor die 10 may be a chip or die in which a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures are included. The integrated circuit devices may include active devices such as transistors, and / or passive devices such as resistors, capacitors, inductors, or combinations thereof.

[0020] A conductive element 20 is disposed on the surface 102 of the semiconductor die 10. The conductive element 20 may be electrically connected to the semiconductor die 10. The conductive element 20 may be a conductive pillar. The conductive element 20 has a surface 202 exposed from the encapsulation 70 or from the surface 702 of the encapsulation 70. The conductive element 20 may have a height between 20 μm and 30 μm. The conductive element 20 may comprise a conductive material, such as aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), stainless steel, or a mixture, alloy, or other combination of conductive materials.

[0021] The conductive element 30 is disposed adjacent to the semiconductor die 10. The conductive element 30 is spaced apart from the semiconductor die 10. The conductive element 30 may be a conductive pillar. The conductive element 30 has a surface 302 exposed from the encapsulation 70 or from the surface 702 of the encapsulation 70. The surface 302 of the conductive element 30 may be substantially coplanar with the surface 202 of the conductive element 20. In some embodiments, the surface 301 of the conductive element 30 is coplanar with the surface 101 of the semiconductor die 10. The height H3 of the conductive element 30 may be the sum of the height H2 of the conductive element 20 and the thickness H1 of the semiconductor die 10. The conductive element 30 may comprise a conductive material, such as Al, Cu, Cr, Sn, Au, Ag, Ni, stainless steel, or a mixture, alloy, or other combination of conductive materials. Depending on different design requirements, the material of the conductive element 30 may be the same as or different from the material of the conductive element 20.

[0022] Encapsulation 70 includes a surface 701 and a surface 702 opposite to surface 701. Encapsulation 70 encapsulates or surrounds the semiconductor die 10, conductive element 20, and conductive element 30. Surface 701 of encapsulation 70 is coplanar with surface 101 of the semiconductor die 10. Figure 1A In the embodiment shown, the encapsulation 70 exposes surface 202 of conductive element 20, surfaces 301 and 302 of conductive element 30, and surface 101 of semiconductor die 10. The encapsulation 70 may comprise an epoxy resin with filler, a molding compound (e.g., epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material in which polysiloxane is dispersed, or a combination thereof.

[0023] A metal layer 40 is disposed on and electrically connected to the conductive element 30. For example, the metal layer 40 contacts a surface 301 of the conductive element 30, which is exposed from the encapsulation 70. The metal layer 40 is disposed on the surface 701 of the encapsulation 70. In some embodiments, the thickness T of the metal layer 40 is equal to or greater than 1 μm. For example, the thickness T of the metal layer 40 may be in the range of 3 μm to 5 μm. The metal layer 40 may be a seed layer of RDL 50. The metal layer 40 may comprise a metallic material, such as Al, Cu, Cr, Sn, Au, Ag, Ni, stainless steel, or a mixture, alloy, or other combination of metallic materials. The metal layer 40 may be or comprise copper foil.

[0024] RDL 50 is disposed on and electrically connected to metal layer 40. RDL 50 includes an under bump metallurgy (UBM) 55 exposed from insulating layer 80. RDL 60 is disposed on or above surface 702 of encapsulation 70. RDL 60 includes a UBM 65 exposed from insulating layer 85. RDL 60 may be electrically connected to conductive element 20 and / or conductive element 30. RDL 50 and RDL 60 may be electrically connected via conductive element 30.

[0025] An insulating layer 80 is disposed on surface 701 of the encapsulation 70 and surface 101 of the semiconductor die 10. The insulating layer 80 surrounds or covers metal layer 40 and RDL 50, and exposes UBM 55 of RDL 50. A portion of the insulating layer 80 lies between UBM 55 of RDL 50 and a portion of RDL 50 on metal layer 40. An insulating layer 85 is disposed on surface 702 of encapsulation 70, surface 202 of conductive element 20, and surface 302 of conductive element 30. The insulating layer 85 surrounds or covers RDL 60, and exposes UBM 65 of RDL 60. Insulating layers 80 and 85 may comprise a dielectric or polyimide (PI) material.

[0026] Connector 90 is mounted on UBM 55 of RDL 50 and UBM 65 of RDL 60. Connector 90 may contain solder balls.

[0027] Figure 1B This illustration shows a cross-sectional view of a semiconductor device package 1b according to some embodiments of the present disclosure. The semiconductor device package 1b is similar to... Figure 1A The semiconductor device package 1a in the present invention has some differences as described below.

[0028] A metal layer 40 is disposed on or covers the surfaces 701 of the encapsulation 70, the conductive element 30, and the semiconductor die 10. In some embodiments, the metal layer 40 may completely cover the surfaces 701 of the encapsulation 70, the conductive element 30, and / or the semiconductor die 10. The configuration of the metal layer 40 may enhance the mechanical or structural strength of the semiconductor device package 1b, and the maximum bending value of the semiconductor device package 1b may be equal to or less than 10 mm.

[0029] Figure 1C An enlarged view illustrating a portion of a semiconductor device package according to some embodiments of the present disclosure. (See attached image.) Figure 1CAs shown, notch 50r is defined or formed on the side surface of RDL 50, and notch 40r is defined or formed on the side surface of metal layer 40. The side surfaces of RDL 50 and metal layer 40 may be coplanar. In some embodiments, notches 40r and 50r may be created due to etching / patterning / photolithography operations during semiconductor device packaging fabrication.

[0030] Figure 2 This illustration shows a cross-sectional view of a semiconductor device package 2a according to some embodiments of the present disclosure. The semiconductor device package 2a is similar to... Figure 1A The semiconductor device package 1a in the present invention has some differences as described below.

[0031] Omit Figure 1A The semiconductor device package 1a contains conductive elements 20, RDL 60, and connection elements 90. Metal layer 40 is not completely covered by RDL 50. For example, surface 401 of metal layer 40 is exposed from RDL 50. Figure 2 As shown, a gap G1 is defined between the metal layer 40 and the RDL 50, and the gap is filled by the insulating layer 80.

[0032] Figure 3 This illustration shows a cross-sectional view of a semiconductor device package 3a according to some embodiments of the present disclosure. The semiconductor device package 3a includes a semiconductor device package 3a1 and a semiconductor device package 3a2. Semiconductor device packages 3a1 and / or 3a2 are similar to... Figure 1A Semiconductor device package 1a. For example... Figure 3 As shown, the surface 701 of the encapsulation 70 of semiconductor device package 3a1 faces the surface 701 of the encapsulation 70 of semiconductor device package 3a2. Semiconductor device package 3a1 and semiconductor device package 3a2 are electrically connected via a connecting element 90, which is connected to the RDL 60 of semiconductor device package 3a1 and the RDL 60 of semiconductor device package 3a2.

[0033] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L and Figure 4M A cross-sectional view of a semiconductor device package 4m manufactured at various stages according to some embodiments of the present disclosure.

[0034] refer to Figure 4AA carrier CR is provided. The carrier CR may comprise glass or other materials. A metal layer ML is disposed on the carrier CR. The metal layer ML includes a metal layer 45 disposed on and in contact with the carrier CR, and a metal layer 40 disposed on the metal layer 45. The metal layer 40 and / or the metal layer 45 may have a... Figure 1A The semiconductor device package 1a exhibits similar characteristics to metal layer 40. The thickness of metal layer 40 may be equal to or greater than 1 μm. For example, the thickness of metal layer 40 may be in the range of 3 μm to 5 μm. The thickness of metal layer 45 may be equal to or greater than 15 μm. For example, the thickness of metal layer 45 may be 18 μm. The thickness configuration of metal layers 40 and 45 may contribute to... Figure 4D The separation operation of metal layer 40 and metal layer 45 is described in the document.

[0035] refer to Figure 4B Semiconductor die 10 is disposed on layer M2 of metal layer ML. Semiconductor die 10 may be disposed by die bonding operation or flip-chip bonding operation (which may include a curing operation). Conductive element 20 is disposed on semiconductor die 10 and may be electrically connected to circuitry of semiconductor die 10, wherein the circuitry may be on an active surface of semiconductor die 10. Conductive element 30 is disposed on metal layer 40 and may be connected to metal layer 40 by metal bonding force, wherein a curing operation may be performed.

[0036] refer to Figure 4C Encapsulation 70 is formed on metal layer 40 and semiconductor die 10. Encapsulation 70 encapsulates or covers conductive element 20, conductive element 30, semiconductor die 10 and metal layer ML of metal layer 40. Encapsulation 70 may be formed by molding operation.

[0037] refer to Figure 4D Remove the carrier CR and the metal layer ML of metal layer 45. The removal operation may include a sawing operation, such as a wire sawing operation, in which a wire cuts between metal layer 40 and metal layer 45, and separates metal layer 40 and metal layer 45.

[0038] refer to Figure 4E A grinding operation is performed to remove a portion of the encapsulation 70 and expose conductive elements 20 and 30. In some embodiments, a portion of conductive element 20 and / or a portion of conductive element 30 may also be removed by the grinding operation.

[0039] refer to Figure 4FRDL 60 is formed on encapsulation 70. An insulating layer 85 is formed on encapsulation 70 to surround RDL 60. RDL 60 may be electrically connected to conductive element 20 or conductive element 30. RDL 60 includes UBM 65 exposed from insulating layer 85. RDL 60 may be formed by photolithography or electroplating. Insulating layer 85 may be formed by stacking or screening.

[0040] refer to Figure 4G Connector 90 is mounted on UBM 65 of RDL 60. Connector 90 can be mounted via a ball mount operation that may include a reflow soldering operation. (See reference) Figure 4H A photoresist pattern P1 is applied to the metal layer 40. The photoresist pattern P1 may be applied by a coating operation. The photoresist pattern P1 may subsequently be exposed and developed. An adhesive tape T1 is applied to the insulating layer 85, surrounding the connecting element 90, where a lamination operation can be performed. The adhesive tape T1 may protect the connecting element 90 in subsequent processes.

[0041] refer to Figure 4I The photoresist pattern P1 and a portion of the metal layer 40 are removed, allowing for etching operations. An RDL 50 is formed on the metal layer 40, which may act as a seed layer for the RDL 50. (Reference) Figure 4J An insulating layer 80 is formed on the encapsulation 70 and the semiconductor die 10 to surround or cover the RDL 50. The insulating layer 80 may be formed by a stacking operation or a screening operation. An opening O1 is formed within the insulating layer 80 to expose the RDL 50.

[0042] refer to Figure 4K UBM 55 is formed on the exposed portions of RDL 50 and insulating layer 80, where electroplating operations can be performed. (Reference) Figure 4L Connector 90 is mounted on the UBM 55. Connector 90 can be mounted via a ball mount operation that may include a reflow soldering process. (See reference) Figure 4M Remove tape T1 and form a 4m semiconductor device package. The 4m semiconductor device package may be related to... Figure 1A The semiconductor device package 1a is similar to or the same.

[0043] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K , Figure 5L , Figure 5M , Figure 5Nand Figure 5O A cross-sectional view of a semiconductor device package 5p manufactured at various stages according to some embodiments of the present disclosure.

[0044] refer to Figure 5A A carrier CR is provided. The carrier CR may comprise glass or other materials. A metal layer ML is disposed on the carrier CR. The metal layer ML includes a metal layer 45 disposed on and in contact with the carrier CR, and a metal layer 40 disposed on the metal layer 45. The metal layer 40 and / or the metal layer 45 may have a... Figure 1A The semiconductor device package 1a exhibits similar characteristics to metal layer 40. The thickness of metal layer 40 may be equal to or greater than 1 μm. For example, the thickness of metal layer 40 may be in the range of 3 μm to 5 μm. The thickness of metal layer 45 may be equal to or greater than 15 μm. For example, the thickness of metal layer 45 may be 18 μm. The thickness configuration of metal layers 40 and 45 may contribute to... Figure 5D The separation operation of metal layer 40 and metal layer 45 is described in the document.

[0045] refer to Figure 5B Semiconductor die 10 is disposed on layer M2 of metal layer ML. Semiconductor die 10 may be disposed by die bonding operation or flip-chip bonding operation (which may include a curing operation). Conductive element 20 is disposed on semiconductor die 10 and may be electrically connected to circuitry of semiconductor die 10, wherein the circuitry may be on an active surface of semiconductor die 10. Conductive element 30 is disposed on metal layer 40 and may be connected to metal layer 40 by metal bonding force, wherein a curing operation may be performed.

[0046] refer to Figure 5C Encapsulation 70 is formed on metal layer 40 and semiconductor die 10. Encapsulation 70 encapsulates or covers conductive element 20, conductive element 30, semiconductor die 10 and metal layer ML of metal layer 40. Encapsulation 70 may be formed by molding operation.

[0047] refer to Figure 5D Remove the carrier CR and the metal layer ML of metal layer 45. The removal operation may include a sawing operation, such as a wire sawing operation, in which a wire cuts between metal layer 40 and metal layer 45, and separates metal layer 40 and metal layer 45.

[0048] refer to Figure 5E A grinding operation is performed to remove a portion of the encapsulation 70 and expose conductive elements 20 and 30. In some embodiments, a portion of conductive element 20 and / or a portion of conductive element 30 may also be removed by the grinding operation.

[0049] refer to Figure 5FRDL 60 is formed on encapsulation 70. An insulating layer 85 is formed on encapsulation 70 to surround RDL 60. RDL 60 may be electrically connected to conductive element 20 or conductive element 30. RDL 60 includes UBM 65 exposed from insulating layer 85. RDL 60 may be formed by photolithography or electroplating. Insulating layer 85 may be formed by stacking or screening.

[0050] refer to Figure 5G Connector 90 is mounted on UBM 65 of RDL 60. Connector 90 can be mounted via a ball mount operation that may include a reflow soldering operation. (See reference) Figure 5H A photoresist pattern P2 is applied to the metal layer 40. The photoresist pattern P2 may be applied by a coating operation. The photoresist pattern P2 may subsequently be exposed and developed. An adhesive tape T1 is applied to the insulating layer 85, surrounding the connecting element 90, where a lamination operation can be performed. The adhesive tape T1 may protect the connecting element 90 in subsequent processes.

[0051] refer to Figure 5I A portion of metal layer 40 is removed, where an etching operation can be performed. (See reference) Figure 5J The photoresist pattern P2 is removed to expose the metal layer 40, where etching operations can be performed. (Reference) Figure 5K An insulating layer 80 is formed on the encapsulation 70 and the semiconductor die 10 to surround or cover the metal layer 40. The insulating layer 80 may be formed by a stacking operation or a screening operation. An opening O1 is formed within the insulating layer 80 to expose the metal layer 40.

[0052] refer to Figure 5L RDL or UBM 55 is formed on the exposed portions of the metal layer 40 and the insulating layer 80, where electroplating operations can be performed. (Reference) Figure 5M Connector 90 is mounted on the UBM 55. Connector 90 can be mounted via a ball mount operation that may include a reflow soldering process. (See reference) Figure 5N Tape T1 is removed, and a semiconductor device package 5p1 is formed to expose the connecting element 90. (Reference) Figure 5O A semiconductor device package 5p2, similar to semiconductor device package 5p1, is provided. Semiconductor device packages 5p1 and 5p2 are joined and electrically connected by connecting element 90 to form semiconductor device package 5p, in which reflow operations can be performed. Semiconductor device package 5p can be used with... Figure 3 The semiconductor device package 3a is similar to or the same.

[0053] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred exactly or very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" or "approximately" the same. For example, "substantially" parallel can refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “generally” vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0054] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the difference between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered planar or substantially planar.

[0055] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0056] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes may be made and equivalent components may be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to variations in manufacturing processes, etc. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt specific circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: a semiconductor die comprising a top surface and a bottom surface; a first conductive element disposed on the bottom surface of the semiconductor die and comprising a top surface and a bottom surface; a second conductive element disposed adjacent to the semiconductor die and comprising a top surface and a bottom surface; an encapsulation body encapsulating the semiconductor die, the first conductive element, and the second conductive element, the encapsulation body comprising a top surface and a bottom surface, wherein the top surface of the encapsulation body is coplanar with the top surface of the semiconductor die, wherein the bottom surface of the encapsulation body is coplanar with the bottom surface of the first conductive element and the bottom surface of the second conductive element; a metal layer disposed on the second conductive element, wherein the metal layer directly contacts the top surface of the encapsulation body, the top surface of the semiconductor die, and the top surface of the second conductive element; and a first redistribution layer disposed on and electrically connected to the metal layer, wherein the metal layer directly contacts the first redistribution layer, and the metal layer is a seed layer for the first redistribution layer.

2. The semiconductor device package of claim 1, further comprising an insulating layer formed on the encapsulation body, wherein sidewalls of the metal layer are coplanar with sidewalls of the encapsulation body, wherein the sidewalls of the metal layer are coplanar with sidewalls of the insulating layer.

3. The semiconductor device package of claim 2, wherein the metal layer covers a first portion of the top surface of the semiconductor die and covers all of the top surface of the second conductive element, wherein a second portion of the top surface of the semiconductor die is covered by the insulating layer.

4. The semiconductor device package of claim 1, wherein the encapsulation body directly contacts the semiconductor die, the first conductive element, and the second conductive element.

5. The semiconductor device package of claim 2, wherein a gap is defined between the metal layer and the first redistribution layer, wherein the gap is filled by the insulating layer.

6. The semiconductor device package of claim 5, wherein the first redistribution layer directly contacts a first portion of a top surface of the metal layer, and a second portion of the top surface of the metal layer is exposed from the first redistribution layer.

7. The semiconductor device package of claim 1, further comprising a second redistribution layer disposed under the encapsulation body, wherein the semiconductor die directly contacts the top surface of the first conductive element, wherein the bottom surface of the first conductive element directly contacts second redistribution layer, and a portion of the bottom surface of the first conductive element is exposed from the second redistribution layer.

8. The semiconductor device package of claim 1, wherein a thickness of the metal layer is in a range of 3 pm to 5 pm, wherein a bottom surface of the metal layer is coplanar with the top surface of the encapsulation body and the top surface of the semiconductor die.

9. The semiconductor device package of claim 2, wherein the first redistribution layer includes an under bump metal layer exposed from the insulating layer, wherein the semiconductor device package further includes a connection element disposed on the under bump metal layer, wherein sidewalls of the under bump metal layer are exposed to air.

10. The semiconductor device package of claim 1, wherein a configuration of the metal layer enhances a mechanical or structural strength of the semiconductor device package, and a maximum bend value of the semiconductor device package is equal to or less than 10 millimeters (mm).

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