Fabry-Perot resonant cavity for testing Josephson junction and manufacturing method

Abstract

The invention discloses a Fabry-Perot resonant cavity for testing a Josephson junction and a manufacturing method, and relates to the technical field of Josephson junction testing devices. Comprising a reflecting spherical surface and a reflecting plane, and the reflecting plane is formed by the surface of one side of the metal reflecting substrate; a patterned dielectric layer is locally arranged on the surface of the metal reflection substrate; a metal redistribution layer is arranged on the patterned dielectric layer, and the metal redistribution layer forms an electrical path connected with a Josephson junction chip; wherein the patterned dielectric layer is only located right below the area covered by the metal redistribution layer. According to the invention, reliable electrical connection of Josephson junctions can be realized on the premise of not sacrificing the high Q value characteristic of the resonant cavity.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Josephson junction testing devices, and particularly to a Fabry-Perot resonant cavity for testing Josephson junctions and a manufacturing method thereof. BACKGROUND

[0002] As a high-quality factor (high Q value) microwave resonant structure, the hemispherical Fabry-Perot resonant cavity is mainly composed of a reflective spherical surface and a reflective plane, and can establish and maintain a highly stable microwave standing wave field in a small mode volume. In the resonant cavity, when the Josephson junction is precisely placed in the strong field region near the reflective plane, it can effectively couple with the microwave field in the cavity, and then generate a Shapiro step for precise measurement under appropriate microwave driving. To excite this coupling state, the microwave signal usually needs to be fed into the cavity through a waveguide, and its frequency needs to be precisely matched with a certain resonant mode of the cavity, so as to obtain a high enough equivalent field strength at the Josephson junction position with a lower input power.

[0003] In the actual test of the hemispherical Fabry-Perot resonant cavity, a printed circuit board (PCB) is generally used to fix the chip and lead out the signal line, such as a Josephson junction array microwave coupling cavity in patent CN202510989383.8. However, this PCB introduction scheme will cause multiple damages to the high Q value performance. First, the high dielectric loss of the PCB substrate and the conductor loss of its metal traces, combined with the significant scattering of the precise electromagnetic field mode in the cavity, will irreversibly destroy the stable standing wave field, resulting in a sharp decrease in the quality factor of the resonant cavity. Second, the introduction of the PCB will change the intrinsic field distribution in the cavity, which will destroy the optimal coupling condition between the Josephson junction and the microwave field, thereby significantly reducing the coupling efficiency. In addition, the PCB will also introduce multiple additional noises in the low-temperature environment: the heat converted by the dielectric loss will exacerbate the thermal noise, and the impurities and defects in the material will form a large number of two-energy-level systems, which will become significant 1 / f noise sources. The superposition of these noises seriously deteriorates the signal-to-noise ratio of the system, resulting in a decrease in the measurement resolution of the Shapiro step.

[0004] The above physical limitations introduced by the substantially independent circuit structure such as the PCB highlight a fundamental contradiction faced by the current technology: it is difficult to achieve both the introduction of necessary test functions in the cavity and the maintenance of extremely high intrinsic Q value of the cavity. This also confirms a common and deeply rooted technical understanding in this field: in the high Q value Fabry-Perot resonant cavity, any additional, non-intrinsic dielectric and conductor structures should be avoided as much as possible, otherwise the excellent resonant performance will inevitably be severely damaged. Therefore, there is an urgent need for a new resonant cavity structure and manufacturing method that can realize reliable electrical connection and testing of the Josephson junction without sacrificing the high Q value characteristics of the resonant cavity. SUMMARY

[0005] In view of the deficiencies of the prior art, the present application provides a Fabry-Perot resonant cavity for testing a Josephson junction and a manufacturing method, which integrates a Josephson junction performance test circuit structure and a reflection plane on the premise of not sacrificing the high Q value characteristic of the resonant cavity, and directly constructs the core structure of the test circuit on the reflection plane.

[0006] The specific technical solutions are as follows: In a first aspect, the present application discloses a Fabry-Perot resonant cavity for testing a Josephson junction, comprising a reflection sphere and a reflection plane, wherein the reflection plane is formed by one side surface of a metal reflection substrate; A patterned dielectric layer is locally arranged on the surface of the metal reflection substrate; A metal redistribution layer is arranged on the patterned dielectric layer, and the metal redistribution layer constitutes an electrical path for connecting a Josephson junction chip; The patterned dielectric layer is located directly below the area covered by the metal redistribution layer.

[0007] Preferably, the material of the patterned dielectric layer is silicon dioxide or silicon nitride.

[0008] Preferably, the thickness of the patterned dielectric layer is 100 nanometers to 2 micrometers.

[0009] Preferably, the material of the metal reflection substrate is high-purity copper or oxygen-free copper.

[0010] Preferably, the surface roughness Ra of the exposed reflection surface of the metal reflection substrate is not more than 1.6 micrometers.

[0011] Preferably, the metal redistribution layer forms metal traces and electrical pads by a sputtering seed layer process and an electroplating process, thereby constituting the electrical path.

[0012] Preferably, the electrical pads are located at the edge of the reflection plane, and the Josephson junction chip is attached to the exposed area of the reflection plane and electrically connected to the electrical pads by wire bonding.

[0013] Preferably, the coverage area of the patterned dielectric layer on the reflection plane accounts for not more than 10%.

[0014] Preferably, the patterned dielectric layer is in a strip shape, a T shape or a microcolumn array structure.

[0015] In a second aspect, the present application discloses a manufacturing method of a Fabry-Perot resonant cavity for testing a Josephson junction, comprising: Polishing the reflection surface of the metal reflection substrate constituting the reflection plane; A dielectric thin film is deposited globally on the reflective surface of the metal reflective substrate; The dielectric thin film is patterned using photolithography and etching processes to form a patterned dielectric layer; wherein the patterned dielectric layer is located only directly below the area covered by the metal redistribution layer; A metal redistribution layer is prepared on the patterned dielectric layer by sputtering a seed layer and electroplating to form an electrical path connecting the Josephson junction chip. The Josephson junction chip is mounted on the exposed area of ​​the reflective surface of the metal reflective substrate and electrically connected to the electrical pads of the metal redistribution layer by wire bonding.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention achieves integrated testing circuitry and a reflective plane by constructing a locally patterned dielectric layer and a metal redistribution layer on the surface of a metal reflective substrate, replacing the traditional external PCB board electrical lead-out method. This structure places an extremely thin dielectric layer only below the necessary circuit paths while keeping the main reflective surface area exposed, effectively avoiding the high dielectric loss, microwave absorption, and scattering problems introduced by the PCB board. This ensures a high-quality factor environment for the Fabry-Perot resonator and improves the coupling efficiency between the Josephson junction and the microwave field.

[0017] This invention further reduces microwave energy loss and thermal noise generation by strictly controlling the coverage area of ​​the patterned dielectric layer to no more than 10% of the reflective surface, selecting low-loss dielectric materials such as silicon dioxide and silicon nitride, and optimizing its thickness to between 500 nanometers and 2 micrometers. The metal redistribution layer is formed using sputtering and electroplating processes to create a low-impedance, highly uniform conductive path, effectively suppressing 1 / f noise caused by impurities and defects, thereby significantly improving the signal-to-noise ratio and testing accuracy of Shapiro step measurements.

[0018] This invention integrates the test circuitry onto the reflective plane, avoiding external connection structures and complex assembly processes, and reducing performance degradation caused by interface contact and material thermal mismatch. The integrated design enhances the system's mechanical and thermal stability at low temperatures, reducing maintenance and debugging costs and providing a cleaner, more controllable electromagnetic environment for Josephson junction performance testing, thus contributing to the development of quantum metrology and related device technologies. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the hemispherical Fabry-Perot resonator structure in the invention.

[0020] Figure 2 This is a schematic diagram of the reflective plane of the hemispherical Fabry-Perot resonator in the invention.

[0021] Figure 3 A schematic diagram of the process for fabricating a reflective planar patterned circuit.

[0022] In the attached diagram, 1-rectangular waveguide, 2-reflective sphere, 3-chip, 4-dielectric layer, 5-reflective plane, 6-circuit layer. Detailed Implementation

[0023] The embodiments of the invention will be described in further detail below with reference to the accompanying drawings, so that the objectives, technical solutions and technical effects of the invention will be more clearly presented.

[0024] The Fabry-Perot resonant cavity for testing Josephson junctions provided by this invention significantly reduces dielectric loss and noise interference while maintaining the high quality factor of the resonant cavity by directly integrating the test circuit structure onto the reflecting plane, replacing the traditional external PCB interconnection method. Detailed embodiments will be described around the technical features of the claims, ensuring that each feature is fully disclosed and described in detail.

[0025] like Figures 1-2 As shown, in a typical embodiment of the present invention, the Fabry-Perot resonant cavity for testing a Josephson junction includes a reflective sphere and a reflective plane, wherein the reflective plane is formed by one side surface of a metal reflective substrate. Figure 1 As shown, the overall structure of the resonant cavity includes a rectangular waveguide 1, a reflective sphere 2, a chip 3, a dielectric layer 4, a reflective plane 5, and a circuit layer 6. The rectangular waveguide 1 is used to input microwave signals into the cavity. The reflective sphere 2 and the reflective plane 5 together constitute the resonant cavity. The chip 3 is mounted on the reflective plane 5 and includes a Josephson junction array. The dielectric layer 4 is partially disposed on the surface of the reflective plane 5, and the circuit layer 6 is formed on the dielectric layer 4, forming an electrical path. The key improvement lies in the structural design of the reflective plane 5, namely, a patterned dielectric layer 4 is locally disposed on the surface of the metal reflective substrate, and a metal redistribution layer is disposed on the patterned dielectric layer 4 as the circuit layer 6, wherein the patterned dielectric layer 4 is only located directly below the area covered by the metal redistribution layer. This design ensures that most of the area of ​​the reflective plane 5 remains metal-exposed, thereby minimizing disturbance to the microwave field.

[0026] In the specific implementation, the metal reflective substrate serves as the carrier of the reflective plane 5. Its material is preferably high-purity copper or oxygen-free copper to ensure high conductivity and low microwave loss. High-purity copper has excellent electromagnetic reflection characteristics, while oxygen-free copper exhibits better stability at low temperatures, making it suitable for Josephson junction testing scenarios. The exposed reflective surface of the metal reflective substrate requires ultra-precision polishing to ensure its surface roughness Ra does not exceed 1.6 micrometers. This parameter is confirmed by measurement using a contact profilometer or atomic force microscope. Lower surface roughness helps reduce microwave scattering loss and improve the Q value of the resonant cavity. The polishing process can employ mechanical polishing or chemical mechanical polishing. In practice, coarse sandpaper is used for initial sanding, followed by fine sandpaper and polishing fluid for final polishing to achieve the target roughness.

[0027] The patterned dielectric layer is made of either silicon dioxide or silicon nitride, both of which offer low dielectric loss and good insulation properties, making them suitable for microwave frequencies. Silicon dioxide can be formed via chemical vapor deposition or atomic layer deposition, while silicon nitride is commonly prepared using plasma-enhanced chemical vapor deposition. The thickness of the dielectric layer is controlled within the range of 500 nanometers to 2 micrometers, preferably 700 nanometers to 1 micrometer, to provide sufficient electrical isolation while avoiding excessive thickness that introduces additional losses. The thickness selection is based on microwave penetration depth and insulation requirements, and is calibrated using an ellipsometry or scanning electron microscope. The coverage area of ​​the patterned dielectric layer on the reflective plane does not exceed 10%, a limitation achieved through photolithographic mask design to ensure that most of the reflective surface remains exposed. The patterned shape can be a strip, a T-shape, or a micropillar array structure, determined based on circuit layout requirements. For example, strip structures are suitable for long-distance traces, T-shaped structures facilitate pad connections, and micropillar arrays are used for high-density interconnects.

[0028] The metal redistribution layer forms metal traces and electrical pads through sputtering seed layer technology and electroplating, thus constituting an electrical pathway. Specific steps include: first, sputtering an adhesion layer, such as titanium or chromium, approximately 10-50 nanometers thick, onto a patterned dielectric layer to enhance adhesion; then, sputtering a copper seed layer, approximately 100-200 nanometers thick, onto the adhesion layer; next, defining the electroplating area using photolithography, and electroplating copper to a target thickness of 1-5 micrometers; finally, removing the photoresist and etching the seed layer to isolate the metal traces. The electrical pads are located at the edge of the reflective plane for easy connection to external test lines. The Josephson junction chip is mounted on the exposed area of ​​the reflective plane and electrically connected to the electrical pads via wire bonding. Gold or aluminum wires are used for wire bonding, and bonding parameters such as temperature, pressure, and ultrasonic energy need to be optimized to ensure reliability.

[0029] In this invention, patterning the dielectric layer and the metal redistribution layer is key to achieving high-performance integration of the test circuit and the reflective plane. This patterning design has a clear and synergistic dual effect: First, the patterning of the dielectric layer serves to achieve localized and selective electrical insulation. By forming a patterned dielectric layer of a specific shape, such as a strip or T-shape, on the surface of the metal reflective substrate only below the specific paths where subsequent metal traces will be laid, this dielectric layer provides a necessary localized insulating platform for the metal redistribution layer above. This design ensures the normal operation of the electrical path while strictly limiting the coverage area of ​​the high-loss dielectric material to a very small area of ​​the reflective surface, thereby minimizing the absorption and scattering of microwave energy within the cavity by the dielectric material and avoiding the degradation of the resonant cavity quality factor caused by the presence of a large area of ​​continuous dielectric.

[0030] Secondly, the patterning of the metal redistribution layer and the dielectric layer are mutually corresponding and synergistically designed. The patterning range of the dielectric layer precisely defines the area where the upper metal circuitry can be laid out. This synergy allows the physical structure of the entire electrical test circuitry to be highly integrated and constrained within a local area of ​​the reflecting plane. The effect is to minimize the disturbance of the test circuitry to the microwave electromagnetic field modes within the Fabry-Perot resonator. The microwave field can propagate freely in the exposed metal area largely uncovered by the reflecting plane and form a stable standing wave, thereby effectively maintaining the uniformity and stability of the electromagnetic field within the cavity. This not only protects the high quality factor environment of the resonator but also ensures efficient coupling between the Josephson junction and the microwave field.

[0031] Therefore, the patterned design of the present invention is a systematic solution that simultaneously solves the electrical isolation problem and the problem of minimizing electromagnetic disturbance required for integrated test circuits by achieving a minimized layout of functional areas on the reflective plane.

[0032] like Figure 3 As shown, the present invention also provides a method for fabricating the Fabry-Perot resonant cavity, comprising the following steps: First, the reflective surface of the metal reflective substrate constituting the reflective plane is polished to ensure that its surface roughness Ra does not exceed 1.6 micrometers. After polishing, the substrate is cleaned to remove contaminants.

[0033] Then, a dielectric thin film, such as silicon dioxide or silicon nitride, with a thickness of 100 nanometers to 2 micrometers, is globally deposited on the reflective surface of the metal reflective substrate. After deposition, the dielectric thin film is patterned using photolithography and etching processes to form a patterned dielectric layer.

[0034] The photolithography process includes coating photoresist, pre-baking, UV exposure, development, and etching. Dry etching methods such as reactive ion etching are used to maintain precision. The photoresist is removed after patterning.

[0035] Next, a metal redistribution layer is prepared on the patterned dielectric layer by sputtering a seed layer and electroplating to form an electrical path connecting the Josephson junction chip.

[0036] Finally, the Josephson junction chip is mounted on the exposed area of ​​the reflective surface of the metal reflective substrate and electrically connected to the electrical pads of the metal redistribution layer via wire bonding. Throughout the process, the patterned dielectric layer is located only directly below the area covered by the metal redistribution layer, thereby maximizing the preservation of the integrity of the reflective surface.

[0037] The above embodiments offer significant technical advantages: the locally integrated interconnect structure avoids the dielectric loss and noise problems introduced by traditional PCB boards. The limited coverage of the patterned dielectric layer reduces microwave absorption and scattering, helping to maintain a high Q-value environment in the resonant cavity. The low impedance design of the metal redistribution layer improves signal transmission efficiency. Simultaneously, this structure reduces thermal noise and 1 / f noise, thereby improving the signal-to-noise ratio of the Josephson junction Shapiro step measurement. Those skilled in the art can implement this invention based on the above description and the accompanying drawings without excessive experimentation.

[0038] It should be noted that the above-mentioned implementation improvements stem from a profound understanding of the inherent technical contradictions in the specific application scenario of Fabry-Perot resonators, as illustrated in previous work 202510989383.8, a Josephson junction array microwave coupling cavity. When it is necessary to introduce electrical test circuitry into the Josephson junction within the cavity, the conventional and direct technical approach in this field is to use a separate connection carrier, such as a printed circuit board or flexible circuit, encapsulate the required circuitry on this carrier, and then mechanically fix it and electrically connect it to the cavity. However, in the pursuit and maintenance of extremely high quality factors, i.e., high Q values, within Fabry-Perot resonators, such separate carriers and their associated leads, solder joints, and substrate materials will irreversibly degrade the Q value of the resonator due to their inherent conductor losses, dielectric losses, and significant scattering of the cavity's precise electromagnetic field modes. This physical limitation leads to a widespread technical understanding: introducing any substantial, independent circuit structure inside the cavity will severely impair its high-frequency resonant performance.

[0039] To address the aforementioned technical problems, this invention departs from the conventional design approach of introducing an independent packaging carrier. Instead, it proposes an in-situ integration scheme that is highly integrated with the resonant cavity's reflective plane. This scheme is not a simple application or modification of existing packaging technologies, but rather addresses the technical requirement of introducing necessary electrical functions while maintaining the original electromagnetic environment with near-zero disturbance.

[0040] Specifically, this invention utilizes micro-nano fabrication processes to directly functionalize localized regions on the metal reflective plane constituting the core of the Fabry-Perot resonant cavity. First, an extremely thin patterned dielectric layer is formed in a selected micro-region of the reflective plane, rather than the entire surface. The material selection, thickness control, and coverage area of ​​this dielectric layer are designed to achieve necessary electrical isolation while minimizing its impact on microwave dielectric loss and the overall reflective characteristics of the reflective surface. Subsequently, a metal redistribution layer is fabricated on top of this patterned dielectric layer. Its pattern is designed to form only the minimum conductive paths necessary to connect the Josephson junction to the external test port, thereby minimizing the disturbance of the intracavity electromagnetic field by the additional metal.

[0041] Through the above method, the necessary electrical testing pathway is established, but this pathway exists in a highly localized form, integrated with the reflecting plane. This allows it to achieve electrical connection functions while minimizing its impact on the intrinsic electromagnetic field distribution of the resonant cavity, thus ensuring that the high Q-value characteristics required for the Fabry-Perot resonant cavity can still be effectively maintained after the introduction of testing functions.

[0042] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the patent application of the present invention. All equivalent changes, substitutions or modifications made within the technical spirit and principles indicated by the present invention should be included within the scope of patent protection covered by the present invention.

Claims

1. A Fabry-Perot resonator for testing Josephson junctions, comprising a reflective sphere and a reflective plane formed by one side surface of a metal reflective substrate; characterized in that: a patterned dielectric layer is locally provided on the surface of the metal reflective substrate; a metal redistribution layer is provided on the patterned dielectric layer, the metal redistribution layer constituting an electrical path for connecting a Josephson junction chip; wherein the patterned dielectric layer is located directly below the area covered by the metal redistribution layer only. The material of the patterned dielectric layer is silicon dioxide or silicon nitride. The thickness of the patterned dielectric layer is 500 nm to 2 microns. The material of the metal reflective substrate is 99.999% high-purity copper or oxygen-free copper.

2. The Fabry-Perot resonator for testing a Josephson junction according to claim 1, characterized in that: The surface roughness Ra of the exposed reflective surface of the metal reflective substrate is not more than 1.6 microns.

3. The Fabry-Perot resonator for testing a Josephson junction according to claim 1 or 2, characterized in that: The metal redistribution layer forms metal tracks and electrical pads by sputtering seed layer process and electroplating process, thereby constituting an electrical path.

4. The Fabry-Perot resonator for testing a Josephson junction of claim 1, wherein: The electrical pads are located at the edge of the reflective plane; the Josephson junction chip is mounted on the exposed area of the reflective plane and is electrically connected to the electrical pads by wire bonding.

5. The Fabry-Perot resonator for testing a Josephson junction of claim 3, wherein: The coverage area of the patterned dielectric layer on the reflective plane is not more than 10%.

6. The Fabry-Perot resonator for testing a Josephson junction of claim 1, wherein: The patterned dielectric layer is in the form of a strip, a T-shape or a micro-column array structure.

7. The Fabry-Perot resonator for testing a Josephson junction according to claim 6, characterized in that: Comprising:

8. The Fabry-Perot resonator for testing a Josephson junction of claim 1, wherein: polishing the reflective surface of the metal reflective substrate constituting the reflective plane; 9. The Fabry-Perot resonator for testing a Josephson junction of claim 1, wherein: globally depositing a dielectric film on the reflective surface of the metal reflective substrate; 10. A method of fabrication of a Fabry-Perot resonator for testing a Josephson junction as claimed in any one of claims 1 to 9, characterized in that, patterning the dielectric film by photolithography and etching process to form a patterned dielectric layer; wherein the patterned dielectric layer is located directly below the area covered by the metal redistribution layer only; preparing a metal redistribution layer on the patterned dielectric layer by sputtering seed layer process and electroplating process to constitute an electrical path for connecting a Josephson junction chip; mounting a Josephson junction chip on the exposed area of the reflective surface of the metal reflective substrate and electrically connecting the metal redistribution layer through wire bonding. ​ ​ ​

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