Negative impedance circuit and corresponding device

Abstract

Embodiments of the present disclosure relate to a negative impedance circuit and corresponding devices. The negative impedance circuit includes: a differential circuit stage; a positive feedback path from an output of the differential circuit stage to a first input of the differential circuit stage; a negative feedback path from the output of the differential circuit stage to a second input of the differential circuit stage. The negative feedback path includes a first transistor and a unity gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unity gain path being coupled to ground via a reference impedance. The positive feedback path includes a second transistor. The first transistor and the second transistor are coupled in a current mirror arrangement and have respective control electrodes configured to be driven by the output of the differential circuit stage, wherein the negative impedance circuit induces a negative impedance at the first input of the differential circuit stage.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Italian Patent Application No. 102019000000883, filed on January 21, 2019, which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to an electronic system and method, and in particular embodiments, to a negative impedance circuit and corresponding apparatus. Background Art

[0004] Various types of analog circuits benefit from the possible use of negative impedance circuits.

[0005] In addition, various types of devices are known, and various types of devices are employed to provide negative impedance circuits.

[0006] Circuits that employ both positive and negative feedback are examples of such devices: for example, the so-called negative capacitance converters are known, in which high negative capacitance can be achieved in a process involving low density capacitors.

[0007] These known devices may exhibit limitations related to an undesirably high ratio of, for example, the resistance included in the negative feedback path, which may translate into limitations on the input signal dynamics. Summary of the Invention

[0008] This description relates to a negative impedance circuit.

[0009] Some embodiments provide improvements to negative impedance circuits.

[0010] One or more embodiments can be applied to various types of devices, such as, for example, read interfaces for ultrasonic probes and the like.

[0011] A read interface for a piezoelectric micromachined ultrasonic transducer (PMUT) is an example of a possible application area for embodiments.

[0012] One or more embodiments can relate to a corresponding apparatus.

[0013] A PMUT read interface can be an example of such an apparatus. Brief Description of the Drawings

[0014] One or more embodiments will now be described by way of example only with reference to the drawings, in which:

[0015] Figure 1 is an example diagram of the possible use of a negative impedance circuit;

[0016] Figure 2 andFigure 3 is an example circuit diagram of a negative impedance circuit;

[0017] Figure 4 and Figure 5 is an example circuit diagram of the negative impedance circuit of an embodiment of the present description;

[0018] Figure 6 and Figure 7 is an example circuit diagram of a possible transistor-level implementation of an embodiment of the present description; and

[0019] Figure 8 is an example block diagram that may be used in an exemplary embodiment shown herein. Detailed Description

[0020] In the following description, one or more specific details are shown, aiming to provide an in-depth understanding of examples of embodiments of the present description. Embodiments may be obtained without one or more specific details, or in other cases, with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail, so certain aspects of the embodiments will not be obscured.

[0021] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that the specific configurations, structures, or characteristics described relative to the embodiment are included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to the same embodiment. Moreover, in one or more embodiments, specific configurations, structures, or characteristics may be combined in any appropriate manner.

[0022] The references used herein are provided only for convenience and thus do not define the scope of protection or the scope of the embodiments.

[0023] Furthermore, throughout the specification, for simplicity and ease of explanation, certain circuit nodes and the signals at these nodes will be represented using the same reference numerals (V x 、V OUT ).

[0024] Figure 1 The schematic diagram of IN is an example of certain electronic devices, where the circuit AC may exhibit a low input impedance Z

[0025] Known methods for solving such problems involve applying a "negative" impedance Z NEG (-Z NEGCoupled to (low) impedance Z IN such that the input impedance V’ X / I’ X seen towards the circuit AC can be expressed as

[0026] Z IN,EQ = V’ X / ’I X = Z NEG Z IN / (Z NEG – Z IN )

[0027] Thus, the unwanted low impedance Z IN is converted to a higher impedance value as a result of being multiplied by the ratio Z NEG / (Z NEG - Z IN ) where (Z NEG - Z IN ) provides a small value for the denominator of the ratio Z NEG / (Z NEG - Z IN ).

[0028] Figure 2 And Figure 3 are examples of possible ways to obtain the negative impedance Z NEG = V X / I X by relying on the differential stage 10 (an operational amplifier or op-amp can be an example of such a differential stage) using the combined use of positive feedback (loop A – shown by the solid line) and negative feedback (loop B – shown by the dashed line).

[0029] For example, in the device shown in Figure 2 the output terminal of the differential stage 10 is coupled via a feedback impedance Z PFB to the non-inverting input of the differential stage 10 (regarded as the input node of the circuit) (where there is an input voltage V x and current I x ), thus providing a positive feedback path A.

[0030] The output of stage 10 is also coupled to the inverting input of the differential stage 10 via a voltage divider.

[0031] Such a voltage divider can be provided by a first resistor R1 (the lower branch of the voltage divider, between the inverting input of stage 10 and ground GND) and a second resistor R2 (the upper branch of the voltage divider, between the output of the differential stage 10 and the inverting input).

[0032] In Figure 2In the exemplary device, the output voltage VOUT from the differential stage 10 can be expressed as

[0033] V OUT =(1 + R2 / R1)V X

[0034] Therefore, the negative impedance ZNEG = VX / IX can be expressed as:

[0035] Z NEG = V X / I X = -Z PFB (R1 / R2)

[0036] Figure 3 is an example of the possibility of implementing the device as FB shown by using the capacitor C PFB as the feedback impedance Z Figure 2 shown.

[0037] In Figure 3 the device shown, the following relationship will apply:

[0038] Z NEG = V X / I X = -(1 / sC FB )(R1 / R2)

[0039] where s = jω (ω = angular frequency), thus providing a negative input capacitance C IN , which can be expressed as

[0040] C IN = -C FB (R2 / R1)

[0041] To provide a high negative capacitance in a process with low-density capacitors, implementing the arrangement as Figure 3 shown involves a high value of the ratio R2 / R1.

[0042] In the case of V OUT =(1 + R2 / R1)V X selecting a higher value for R2 / R1 results in a dynamic of the signal V OUT that is (significantly) higher than the dynamic of the input signal V x . This in turn leads to an undesirable limitation of the input dynamics based on the relationship

[0043] V X,MAX = V OUT,MAX / (1 + R2 / R1)

[0044] In Figure 4In the embodiments illustrated, components or elements such as those already discussed in connection with the previous figures are denoted by the same reference numerals, and thus a detailed description thereof will not be repeated for the sake of brevity.

[0045] In Figure 4 one or more embodiments generally illustrated in, a negative feedback path B from the output terminal of differential stage 10 to the non-inverting input of differential stage 10 is achieved without voltage amplification, i.e., where the output makes the voltage of differential stage 10 (i.e., V OUT ) substantially equal to the input voltage V X to the circuit, where a reference impedance Z REF is provided between the inverting input of differential stage 10 and ground GND.

[0046] For purposes of completeness and ease of understanding, in Figure 4 (which also applies to Figure 5 ), a current generator I OUT is also shown to illustrate that in the embodiments illustrated herein, two or more operational amplifiers or OpAmps may be used, where the triangle labeled 10 can be regarded as an example of a first (differential) amplifier stage, and the transistor M1 and the corresponding current generator represent the output stage.

[0047] In Figure 4 the embodiment shown

[0048] the (negative) feedback path B coupling the output terminal from differential stage 10 to the non-inverting input of differential stage 10 includes a first transistor M1, and

[0049] the (positive) feedback path A coupling the output terminal from differential stage 10 to the inverting input of differential stage 10 includes a second transistor M2,

[0050] the control electrodes of transistors M1 and M2 (the gates in the case of field effect transistors such as MOSFETs illustrated herein) are included in a 1:M current mirror such that current I REF flows through M1 and Z REF , while current MI x corresponding to -I REF flows through M2.

[0051] In Figure 4 the device shown (which also applies to the devices shown in the following figures), a positive feedback path A can be provided that couples the output terminal from differential stage 10 to the reverse input of differential stage 10, while a negative feedback path B can be provided that couples the output terminal of differential stage 10 to the non-inverting input of differential stage 10. Such a device takes into account the fact that in the devices exemplary herein, such as Figure 4 and5 M1 in (current I OUT ) or Figure 6 an output stage such as 10A - 10B in is an inverting stage.

[0052] That is, to provide positive feedback, Figure 4 and Figure 5 and Figure 6 the differential stage 10 in (described below) is shown as having a "reversed" input.

[0053] Those skilled in the art will understand that, as exemplified herein, the coupling options for the inverting / non - inverting inputs to the differential stage 10 are related to the inverting behavior of the associated output stage. Thus, the coupling options exemplified herein are not themselves mandatory. Accordingly, one or more embodiments may employ different coupling options, such as complementary coupling options (inverting to non - inverting, inverting to non - inverting), to provide positive and negative feedback paths as needed.

[0054] In Figure 4 the device exemplified in, the transistors M1, M2 of the current mirror are exemplified in the form of MOSFETs having control terminals (gates) that are coupled to each other and that are commonly coupled to the output terminal of the differential stage 10.

[0055] As previously described, in Figure 4 the device shown, the current paths of transistors M1 and M2 (source / drain in the case of field - effect transistors such as MOSFETs) extend between the power supply terminals V DD and the non - inverting and inverting inputs such that current I REF flows through M1 and Z REF , while the current MI x corresponding to - I REF flows through M2.

[0056] In Figure 4 the device shown, the following relationships may be applied:

[0057] I REF = V X / Z REF

[0058] Z NEG = V X / I X = - Z REF / M

[0059] Again, no input - output voltage amplification is provided such that V X,MAX = V OUT,MAX .

[0060] In Figure 5In this case, components or elements that have been discussed in connection with the previous figures, for example, are again denoted by the same reference signs, and accordingly, the corresponding descriptions will not be repeated for the sake of brevity.

[0061] Figure 5 is an example of a device in which, by using a reference capacitor C REF as a reference impedance Z coupled between the non-inverting input of the differential stage 10 and ground GND REF is implemented Figure 4 the general circuit of the example in

[0062] In Figure 5 the device shown, the following relationships can be applied:

[0063] Z NEG = V X / I X = -1 / sC REF M

[0064] C IN = -C REF M

[0065] where again, s = jω (ω = angular frequency) and there is no voltage amplification, so

[0066] V X,MAX = V OUT,MAX ..

[0067] As previously discussed, Figure 4 and Figure 5 are examples of embodiments employing an operational amplifier including two (or more) stages, where the triangle labeled 10 can be regarded as an example of the first (differential) amplifier stage, and the transistor M1 and the corresponding current generator represent the corresponding output stage.

[0068] In Figure 6 and Figure 7 components or elements that have been discussed in connection with the previous figures, for example, are again denoted by the same reference signs, and accordingly, the corresponding descriptions will not be repeated for the sake of brevity.

[0069] Figure 6 and Figure 7 are examples of possible implementations, where the reference impedance Z REF (which may include the reference capacitor C REF : Figure 6 and Figure 7 show the general impedance Z REFTo provide a more comprehensive representation) is coupled to the output node O of the differential stage 10 at the negative feedback path B. The output node O is arranged between two output transistors 10A, 10B (MOSFETs are mentioned as an example again). The output transistors 10A, 10B have a current path (source / drain in the case of a field effect transistor such as a MOSFET) cascaded between the power node, again designated as VDD, and ground GND.

[0070] As Figure 6 and FIG Figure 7 shown, the control terminals (gates in the case of field effect transistors such as MOSFETs exemplified here) of transistors 10A and 10B are coupled to the respective outputs of the input stage 100 in current. A mirror stage operational transconductance amplifier or OTA provides the differential core of stage 10. The dual outputs of the differential input stage 100 are in-phase (the same in terms of the AC component), and at the same time also provide the correct DC bias for transistors 10A and 10B (MOSFETs).

[0071] For the sake of completeness, it can be noted that Figure 6 the implementation of includes a current mirror OTA, where transistors 10A and 10B (MOSFETs) represent the output transistors, and triangle 100 represents the differential input stage. Using such an amplifier to provide negative impedance is a concern in some embodiments.

[0072] In Figure 6 and Figure 7 the embodiment shown, the positive feedback path is divided into two branches, namely:

[0073] The first branch A1, from one of the output nodes of the differential input stage 100 to the control electrode of transistor 10A, and via the first transistor 10C all the way to the non-inverting input (V x , I x )(i.e., to the inverting input of the differential input stage 100), and

[0074] The second branch A2 from the other output node of the differential input stage 100 to the control electrode of transistor 10B, and via the second transistor 10D all the way to the non-inverting input (V x , I x )(i.e., to the inverting input of the differential input stage 100).

[0075] Dividing the positive feedback path A into two branches A1, A2 involves the use of a current mirror OTA as exemplified herein. In some embodiments, compared with the implementation using, for example, a standard two-stage OpAmp, the device advantageously provides a significant improvement in terms of frequency response.

[0076] In some embodiments, alternative methods for providing satisfactory bandwidth performance may involve using a two-stage OpAmp as shown in Figure 4 and Figure 5 , where circuit 10 and (e.g., MOSFET) transistor M1 plus generator I OUT serve as the input stage and output stage, respectively.

[0077] As shown in Figure 6 and Figure 7 , transistors 10C, 10D (again mentioned by way of example as MOSFETs) are arranged respectively between their current paths (source / drain in the case of a field effect transistor such as a MOSFET):

[0078] Power supply terminal V DD and the non-inverting input of differential stage 10 (the inverting input of differential input stage 100), i.e., the input node to which V X is applied, and

[0079] the input node to which V X is applied, i.e., the non-inverting input of differential stage 10 (the inverting input of differential input stage 100) and ground GND.

[0080] In the device shown in Figure 6 , transistors 10A and 10C (on the one hand) and transistors 10B and 10D (on the other hand) provide respective current mirror devices 10A, 10C and 10B, 10D, just as in the more general representation in Figure 4 and Figure 5 , the 1:M current mirror device illustrated by transistors M1 and M2.

[0081] Figure 7 's transistor-level circuit representation further details a possible implementation of differential input stage 100 (including four transistors 100A, 100B, 100C, 100D) and tail current generator 2I B , where two current paths are respectively between power supply terminal V DD and ground terminal GND via the current paths through transistors 100A, 100B and transistors 100C, 100D.

[0082] In Figure 7 , two other transistors 10E, 10F (again mentioned as MOSFETs for simplicity) are shown, the latter being in diode configuration, so - in the current mirror amplifier considered here - transistors 100C, 10E and 10F mirror the current of input transistor 100D to output transistor 10D, and transistor 100A mirrors the current through input transistor 100B to output transistor 10C.

[0083] InFigure 7 Also shown are currents I flowing from transistor 10A to node O and from node O to transistor 10B, respectively. B +I L / 2 and I B –I L / 2.

[0084] These currents are reflected as currents M(I X +I B +I L / 2) and M(I B –I L / 2) flowing from transistor 10C to the input node to which voltage V is applied and from that node to transistor 10D, resulting in current MI REF flowing at input terminal V X .

[0085] It should be understood that in Figure 7 , current MI REF is represented by an arrow pointing outside node V X (on the right side of the figure), i.e., as a current flowing out of the circuit in node VX. The presence of the assumed positive voltage V X illustrates the negative impedance behavior of the example circuit (i.e., the negative impedance "visible" at that node).

[0086] Those skilled in the art will again recognize that, as exemplified herein, the coupling options to the inverting / non-inverting inputs of the differential input stage 100 are related to the inverting behavior of the associated output stage. Thus, the coupling options illustrated herein are not themselves mandatory. Accordingly, one or more embodiments may employ different coupling options, such as complementary coupling options (inverting to non-inverting, non-inverting to inverting), to provide positive and negative feedback paths as needed.

[0087] Figure 8 is an example of a plurality (in fact, any number) of circuits that may be used within the framework of the PMUT read interface 200 to provide a negative impedance ZNEG as shown in Figures 4 to 7 .

[0088] In Figure 8 , reference numeral 202 generally denotes a PMUT array, where the PMUTs in the array are coupled to corresponding amplifiers 204 (e.g., low-noise amplifiers or LNAs), the outputs of which are applied to corresponding analog delay circuits, collectively referred to as 206 to perform beamforming operations, and the outputs of which are provided to an adder 208 to provide the desired output signal.

[0089] Figure 8The general architecture of the interface 200 therein is known to those skilled in the art, making it unnecessary to provide a more detailed description here.

[0090] In such an interface architecture, each delay block in the set 206 can be regarded as a capacitive load for the associated LNA 204, and such a capacitive load may reduce the bandwidth of the LNA. The coupling between each LNA 204 and the associated delay module 206 has a negative impedance Z NEG , the negative impedance Z NEG includes a negative capacitance parallel to the input capacitance of the delay module (for example, see Figure 1 ), which will cause the negative capacitance to subtract from the input capacitance of the delay block, and the resulting smaller capacitance will be converted into an increased LNA bandwidth.

[0091] Since voltage amplification is omitted (i.e., as exemplified herein V X,MAX = V OUT,MAX ), the dynamics of the output signal will not be restricted as may occur in the case of conventional solutions.

[0092] In some embodiments, the circuit may include:

[0093] A differential circuit stage (for example, see 10, which may include a differential input stage 100) The input stage 100) has a first input (for example, the non-inverting input of stage 10 that may be provided by the inverting input node of the differential), a second input (for example, the inverting input of stage 10 that may be provided by the non-inverting input node of the differential input stage 100), and an output (for example, the output from input 10, which may be provided as a dual output including the first output and the second output nodes of the differential input stage 100),

[0094] At least one positive feedback path from the output of the differential circuit stage to the first input (for example, Figure 4 and Figure 5 the A in or Figure 6 and Figure 7 the A1, A2 in),

[0095] A negative feedback path from the output of the differential circuit stage to the second input (for example, B),

[0096] wherein:

[0097] The negative feedback path includes a unity-gain path from the output of the differential circuit stage to the second input,

[0098] The unity-gain path is coupled to ground (for example, GND) via a reference impedance (for example, Z REF or C REF ),

[0099] The negative feedback path and at least one positive feedback path each include a first transistor (e.g., Figure 4 and 5 M1 in Figure 6 and 7 or 10A, 10B in Figure 4 and 5 ), and a second transistor (e.g., Figure 6 and Figure 7 M2 in NEG or C IN or 10C, 10D as shown in

[0100] The first and second transistors have respective control electrodes (e.g., gates, for field effect transistors such as MOSFETs), are driven by the output of a differential circuit stage, and the first and second transistors are coupled in a current mirror arrangement, where a negative impedance (e.g., Z REF ) is available at a first input (e.g., Vx) of the differential circuit stage.

[0101] In some embodiments, the reference impedance may include a capacitive impedance (e.g., C Figure 4 and Figure 5 M1 in Figure 6 and Figure 7 or 10A, 10B in Figure 4 and Figure 5 ), and a second transistor (e.g., Figure 6 and Figure 7 M2 in

[0102] In some embodiments:

[0103] The differential circuit stage may include a differential input stage (e.g., 100) having a first input node, a second input node, and a dual output including a first output node and a second output node,

[0104] A first positive feedback path (e.g., A1) may be provided from the first output node of the differential input stage to the first input node,

[0105] A second positive feedback path (e.g., A2) may be provided from the second output node of the differential input stage to the first input node,

[0106] A negative feedback path can be provided from a feedback node (e.g., O) to a second input node of a differential input stage, and the feedback node (e.g., O) is coupled to a first output node and a second output node of a differential output of the differential input stage via a respective first transistor of a pair of first transistors (e.g., 10A, 10B in Figure 6 and Figure 7 ). Figure 6 and Figure 7 in 10A, 10B),

[0107] The first positive feedback path and the second positive feedback path can include a respective second transistor of a pair of second transistors (e.g., 10C, 10D in Figure 6 and Figure 7 ). Figure 6 and Figure 7 in 10C, 10D),

[0108] Each first transistor of the pair of first transistors can be coupled to a respective second transistor of the pair of second transistors (e.g., 10C to 10A and 10D to 10B) in a current mirror arrangement, where a negative impedance is available at a first input node (e.g., Vx) of the differential circuit stage.

[0109] In some embodiments, the transistors (e.g., M1, M2 or 10A, 10B, 10C, 10D) can include MOSFETs.

[0110] In some embodiments, an electronic device (e.g., 200) can include:

[0111] at least one circuit block (e.g., 206) having an input impedance,

[0112] at least one circuit as illustrated herein is arranged with a first input (e.g., V x ) of a differential circuit stage, which is coupled to the at least one circuit block, wherein the input impedance is modified according to the negative impedance available at the first input of the differential circuit stage. x )

[0113] In some embodiments, the input impedance of the at least one circuit block and the negative impedance available at the first input of the differential circuit stage can include capacitive impedance.

[0114] In some embodiments, the electronic device as illustrated herein can include an ultrasonic transducer reading interface, which includes at least one (e.g., beamforming) circuit module (e.g., 206) having an input node configured to receive an ultrasonic transducer signal from an ultrasonic transducer (e.g., 202), wherein at least one circuit is arranged with a first input of a differential circuit stage coupled to the input node of the at least one circuit module.

[0115] Without prejudice to the basic principles, details and embodiments can vary even significantly with respect to what is described herein only by way of example, without departing from the scope of protection.

[0116] Although the present invention has been described with reference to illustrative embodiments, such description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to the specification. Accordingly, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A negative impedance circuit, comprising: a differential circuit stage having a first input, a second input, and an output; a positive feedback path from the output of the differential circuit stage to the first input of the differential circuit stage; and a negative feedback path from the output of the differential circuit stage to the second input of the differential circuit stage, wherein: the negative feedback path includes a first transistor and a unity gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unity gain path being coupled to ground via a reference impedance, the positive feedback path includes a second transistor, the first transistor and the second transistor have respective control electrodes configured to be driven by the output of the differential circuit stage, the first transistor and the second transistor are coupled in a current mirror arrangement, and the negative impedance circuit is configured to cause a negative impedance at the first input of the differential circuit stage.

2. The negative impedance circuit according to claim 1, further comprising a second positive feedback path from the output of the differential circuit stage to the first input of the differential circuit stage.

3. The negative impedance circuit according to claim 2, wherein the differential circuit stage includes a differential input stage having a first output coupled to the control terminal of the first transistor and a second output coupled to the control terminal of a third transistor, the third transistor having a current path coupled between the current path of the first transistor and ground.

4. The negative impedance circuit according to claim 3, further comprising a fourth transistor having a control terminal coupled to the control terminal of the third transistor and having a current path coupled between the current path of the second transistor and ground.

5. The negative impedance circuit according to claim 4, wherein the differential input stage comprises: a fifth transistor having a control terminal coupled to a first intermediate node, the first intermediate node being coupled between the current paths of the second transistor and the fourth transistor; a sixth transistor having a control terminal coupled to a second intermediate node, the second intermediate node being coupled between the current paths of the first transistor and the third transistor; and a first current source coupled between the fifth transistor and the sixth transistor and ground.

6. The negative impedance circuit according to claim 5, wherein the differential circuit stage further comprises: a seventh transistor having a control terminal coupled to the control terminal of the sixth transistor; and an eighth transistor having a current path coupled between the current path of the seventh transistor and ground and having a control terminal coupled to the control terminal of the third transistor.

7. The negative impedance circuit according to claim 1, wherein the reference impedance includes a capacitive impedance and wherein the negative impedance includes a negative capacitive impedance.

8. The negative impedance circuit according to claim 1, wherein the first transistor and the second transistor are coupled in a current mirror arrangement having a current gain M from the first transistor to the second transistor, where M is greater than 1.

9. The negative impedance circuit according to claim 1, wherein: the differential circuit stage includes a differential input stage having a first input node, a second input node, a first output node, and a second output node; the positive feedback path is provided from the first output node of the differential input stage to the first input node; a second positive feedback path is provided from the second output node of the differential input stage to the first input node; the negative feedback path is provided from a feedback node coupled to the first output node and the second output node of the differential input stage to the second input node of the differential input stage via a respective first transistor of a pair of first transistors; the positive feedback path and the second positive feedback path include respective second transistors of a pair of second transistors; each first transistor of the first transistors of the pair of first transistors is coupled in a current mirror arrangement to a respective second transistor of the second transistors of the pair of second transistors; and the negative impedance is available at the first input node of the differential circuit stage.

10. The negative impedance circuit according to claim 1, wherein the first transistor and the second transistor comprise metal-oxide-semiconductor field effect transistors MOSFETs.

11. An electronic device, comprising: a circuit block having an input impedance; and a negative impedance circuit comprising: a differential circuit stage having a first input, a second input, and an output, the first input being coupled to the circuit block, a positive feedback path from the output of the differential circuit stage to the first input of the differential circuit stage, and a negative feedback path from the output of the differential circuit stage to the second input of the differential circuit stage, wherein: the negative feedback path includes a first transistor and a unity gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unity gain path being coupled to ground via a reference impedance, the positive feedback path includes a second transistor, the first transistor and the second transistor have respective control electrodes configured to be driven by the output of the differential circuit stage, the first transistor and the second transistor are coupled in a current mirror arrangement, and the negative impedance circuit is configured to cause a negative impedance at the first input of the differential circuit stage, the negative impedance being configured to modify the input impedance of the circuit block.

12. The electronic device according to claim 11, wherein the input impedance of the circuit block and the negative impedance at the first input of the differential circuit stage include capacitive impedance.

13. The electronic device according to claim 11, further comprising: an ultrasonic transducer reading interface including the circuit block, wherein the circuit block has an input configured to receive an ultrasonic transducer signal from an ultrasonic transducer, and wherein the first input of the differential circuit stage is coupled to the input of the circuit block.

14. The electronic device according to claim 13, wherein the ultrasonic transducer includes a piezoelectric micromachined ultrasonic transducer PMUT.

15. The electronic device according to claim 11 further includes a second circuit block and a second negative impedance circuit, wherein the circuit block has an input coupled to the first input of the differential circuit stage and an output coupled to the output of the adder, and wherein the second circuit block has an input coupled to the second negative impedance circuit and an output coupled to the output of the adder.

16. A method for operating a negative impedance circuit, comprising: driving a control node of a first transistor of a negative feedback path with an output of a differential circuit stage, wherein the negative feedback path is coupled from the output of the differential circuit stage to a second input of the differential circuit stage, and wherein the negative feedback path includes a unity gain path from the output of the differential circuit stage to the second input of the differential circuit stage, the unity gain path being coupled to ground via a reference impedance; driving a control node of a second transistor of a positive feedback path with the output of the differential circuit stage, wherein the positive feedback path is coupled from the output of the differential circuit stage to a first input of the differential circuit stage, and wherein the first transistor and the second transistor are coupled in a current mirror arrangement; and generating a negative impedance at the first input of the differential circuit stage based on driving the control nodes of the first transistor and the second transistor to modify an input impedance at an input of a circuit block, wherein the first input of the differential circuit stage is coupled to the input of the circuit block.

17. The method according to claim 16, further comprising: driving a control node of a third transistor of a second positive feedback path with the differential circuit stage, wherein the second positive feedback path is coupled to the first input of the differential circuit stage.

18. The method according to claim 16, wherein the reference impedance includes a capacitive impedance and wherein the negative impedance includes a negative capacitive impedance.

19. The method according to claim 16, further comprising receiving an ultrasonic transducer signal from an ultrasonic transducer using the input of the circuit block.

20. The method according to claim 19, wherein the ultrasonic transducer includes a piezoelectric micromachined ultrasonic transducer (PMUT).

Images