Memory system including multiple controllers

Abstract

A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a nonvolatile memory configured to store data. The second controller is configured to receive the control signal and the data from the first controller and control the memory device based on the control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0009242 filed on January 24, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory system, and more particularly, to a memory system including a plurality of controllers. Background Art

[0004] An information communication device generally includes a processor and a memory device. However, the capacity of the memory device may need to be large, and the memory device may need to be highly integrated so that the information communication device supports multiple functions. As the size of the memory unit of the memory device decreases in order to increase the integration of the memory device, the operating circuits and / or wiring included in the memory device for the operation and electrical connection of the memory device become more complex. Summary of the invention

[0005] At least one embodiment of the inventive concept provides a memory controller and a memory system, and more particularly, provides a memory system including a plurality of memory controllers and memory devices.

[0006] According to an exemplary embodiment of the present invention, a memory system is provided, including a memory device, a first controller and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store data. The second controller is configured to receive a control signal and data from the first controller, and control the memory device based on the control signal.

[0007] According to an exemplary embodiment of the present invention, a memory system is provided, including a memory device, a first controller, a second controller and a non-volatile memory. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a first memory interface configured to receive data from the first controller; and a second memory interface configured to output data to the memory device. The non-volatile memory is configured to receive data from the second controller and store the data.

[0008] According to an exemplary embodiment of the present invention, a memory controller is provided, including a first memory interface, a second memory interface, a non-volatile memory and a scheduler. The first memory interface is configured to receive a plurality of commands for a memory device and data to be stored in the memory device from a first controller. The second memory interface is electrically connected to the memory device. The non-volatile memory is configured to cache data. The scheduler is configured to output the plurality of commands and the data stored in the non-volatile memory to the memory device through the second memory interface based on a set schedule. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments of the present inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept;

[0011] Figure 2 It shows Figure 1 A circuit diagram of an example of an equivalent circuit of a memory block included in a memory cell array of FIG. 1 ;

[0012] Figure 3 is a block diagram illustrating a detailed configuration of a second controller according to an exemplary embodiment of the present inventive concept;

[0013] Figure 4 is a view illustrating data movement according to an exemplary embodiment of the inventive concept;

[0014] Figure 5A is a block diagram of a nonvolatile memory according to an exemplary embodiment of the inventive concept;

[0015] Figure 5B yes Figure 5A A circuit diagram of a memory cell array;

[0016] Figure 5C and Figure 5D It shows that Figure 5B Conceptual diagram of data stored along the magnetization direction in a magnetic tunnel junction (MTJ) structure;

[0017] Figure 6 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept;

[0018] Figure 7 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept;

[0019] Fig. 8A is a view illustrating an error correction code (ECC) encoding process according to an exemplary embodiment of the inventive concept;

[0020] Figure 8B is a view illustrating an ECC decoding process according to an exemplary embodiment of the inventive concept;

[0021] Fig.9A is a view illustrating an ECC encoding process according to an exemplary embodiment of the inventive concept;

[0022] Fig. 9B is a view illustrating an ECC decoding process according to an exemplary embodiment of the inventive concept;

[0023] Fig. 10A is a block diagram illustrating a detailed configuration of a second controller according to an exemplary embodiment of the present inventive concept;

[0024] Fig. 10B is a flow chart illustrating the operation of the second controller;

[0025] Fig.11A is a block diagram illustrating a detailed configuration of a memory system according to an exemplary embodiment of the inventive concept;

[0026] Fig. 11B is a flow chart illustrating the operation of the memory system; and

[0027] Fig.12 is a block diagram illustrating an example in which each memory system according to an exemplary embodiment of the inventive concept is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating a memory system 1 according to an exemplary embodiment of the inventive concept.

[0030] refer to Figure 1 , the memory system 1 includes a first controller 10 (e.g., a control circuit), a second controller 100 (e.g., a control circuit), and a memory device 200. The memory device 200 includes a memory cell array 210 and may also include a circuit for performing a write operation and a read operation on the memory cell array 210 according to the control of the first controller 10. For example, when the memory cell array 210 includes flash memory cells, as an example, the memory device 200 may be referred to as a flash memory device, and the memory system 1 may be referred to as a flash memory system. However, the inventive concept is not limited to a flash memory device.

[0031] According to an exemplary embodiment, the memory cell array 210 includes a two-dimensional (2D) memory cell array implemented by a NAND flash memory having a 2D horizontal structure. According to another exemplary embodiment, the memory cell array 210 includes a three-dimensional (3D) memory cell array implemented by a NAND flash memory having a 3D vertical structure. The 3D memory cell array is monolithically formed in an active region arranged on a silicon substrate, and is formed with at least one physical level of memory cell array, which at least one physical level of memory cell array is formed with a circuit on or in the silicon substrate as a circuit related to the operation of the memory cell. The term "monolithic" means that each level of the layer configuring the 3D memory cell array is stacked on each lower level of the layer in the memory cell array.

[0032] In an embodiment according to the present invention, a 3D memory cell array has a vertical direction characteristic and may include a vertical NAND string, wherein at least one memory cell is located on another memory cell. At least one memory cell may include a charge trap layer. Each vertical NAND string may include at least one selection transistor located above the memory cell. The at least one selection transistor has the same structure as the memory cell and is formed monolithically with the memory cell.

[0033] The following patent documents (incorporated herein by reference) describe configurations suitable for three-dimensional memory arrays, where the three-dimensional memory array can be configured into multiple levels with word lines and / or bit lines shared between the levels: U.S. Patents Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0034] The first controller 10 outputs various signals for controlling the memory device 200 in response to a write / read request from a host HOST (e.g., a host device) to write data in the memory device 200 or read data stored in the memory device 200. In an exemplary embodiment, the first controller 10 provides an address ADDR, a command CMD, and a control signal CTRL to the second controller 100 in order to control a program (or write) operation, a read operation, and an erase operation for the memory device 200. For example, when the memory cells are arranged in rows and columns in the memory cell array 210, the address ADDR may include a row address and a column address.

[0035] In an exemplary embodiment, the first controller 10 provides the data DT to be written to the memory device 200 to the second controller 100. For example, the data DT to be written to the memory device 200 may be received from the host HOST or may be generated by the first controller 10. In addition, the first controller 10 may receive the data DT read by the memory device 200 through the second controller 100.

[0036] In an exemplary embodiment, the first controller 10 provides data DT obtained by performing error correction code (ECC) encoding on data received from the host HOST or data generated by the first controller 10 to the memory device 200 through the second controller 100. In addition, the first controller 10 may perform ECC decoding on the data DT transmitted through the second controller 100. For example, the first controller 10 may perform an ECC encoding operation on unencoded data received from the host HOST to generate encoded data for storage in the memory device 200. For example, the first controller 10 may receive first unencoded data from the host HOST, perform an operation on the first unencoded data to generate second unencoded data, and perform an ECC encoding operation on the second unencoded data to generate encoded data for storage in the memory device 200. For example, the second controller 100 may retrieve the encoded data from the memory device 200, output the encoded data to the first controller 100, and the first controller 100 may perform an ECC decoding operation on the encoded data.

[0037] although Figure 1 Although not shown in the figure, the first controller 10 may also include a random access memory (RAM), a processor, a host interface (e.g., a host interface circuit), and a memory interface (e.g., a memory interface circuit). The RAM may be used as an operating memory of the processor, and the processor may control the operation of the first controller 10. The host interface may include a protocol for exchanging data between the host HOST and the first controller 10. In addition, the memory interface may include a protocol for exchanging data between the first controller 10 and the second controller 100.

[0038] In addition, although not shown, the first controller 10 may further include a flash translation layer (FTL). In an exemplary embodiment, the first controller 10 converts a logical address received from the host HOST into a physical address through the FTL. Therefore, the first controller 10 provides the physical address to the second controller 100, and the second controller 100 accesses the memory device 200 based on the physical address.

[0039] The second controller 100 may control the memory device 200 based on various signals received from the first controller 10. In an exemplary embodiment, the second controller 100 outputs an address ADDR′, a command CMD′, and a control signal CTRL′ to the memory device 200 based on the signals received from the first controller 10. For example, the address ADDR′, the command CMD′, and the control signal CTRL′ output from the second controller 100 to the memory device 200 may be respectively the same as the address ADDR, the command CMD, and the control signal CTRL output from the first controller 10 to the second controller 100. That is, the second controller 100 may transmit various signals received from the first controller 10 to the memory device 200.

[0040] The second controller 100 includes a nonvolatile memory 140. The nonvolatile memory 140 may include a plurality of memory cells, each of which has a state corresponding to stored data. The nonvolatile memory 140 includes a nonvolatile memory cell that maintains stored data even when power supply is blocked. For example, the nonvolatile memory 140 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive RAM (RRAM), a nano floating gate memory (NFGM), a polymer RAM (PoRAM), a magnetic RAM (MRAM), or a ferroelectric RAM (FRAM).

[0041] In an exemplary embodiment, the second controller 100 stores the data DT received from the first controller 10 in the nonvolatile memory 140. The data DT may be stored in the memory device 200. That is, the nonvolatile memory 140 may be used as a buffer for data to be stored in the memory device 200. For example, the data DT may be stored in the nonvolatile memory 140 during a first time period and then moved from the nonvolatile memory 140 to the memory device 200 during a second time period after the first time period. For example, if power is cut off after writing the data DT to the nonvolatile memory 140, the data may be moved from the nonvolatile memory 140 to the memory device 200 after power is restored. For example, the first controller 10 outputs a command CMD for instructing to store the data DT in the nonvolatile memory 140, and the second controller 100 stores the data DT in the nonvolatile memory 140 in response to the command CMD. Therefore, the first controller 10 may directly access the nonvolatile memory 140.

[0042] In another example, the first controller 10 outputs a command CMD for instructing to store the data DT in the memory device 200, and the second controller 100 stores the data DT in the nonvolatile memory 140 in response to the command CMD. Therefore, the first controller 10 may access the nonvolatile memory 140 through the second controller 100, rather than directly accessing the nonvolatile memory 140. For example, even if the host has requested to store the data DT in the memory device 200, the second controller 100 may ignore the request and store the data in the nonvolatile memory 140.

[0043] In an exemplary embodiment, the second controller 100 outputs data DT′ to the memory device 200 based on the data DT stored in the nonvolatile memory 140. For example, the data DT output from the first controller 10 and stored in the nonvolatile memory 140 may be the same as the data DT′ output from the second controller 100. For example, the second controller 100 may directly transmit the data DT received from the first controller 10 to the memory device 200. In another example, the second controller 100 performs ECC encoding for the nonvolatile memory 140 on the data DT received from the first controller 10, stores the data DT in the nonvolatile memory 140, and outputs the data DT′ obtained by performing ECC decoding on the data DT stored in the nonvolatile memory 140 to the memory device 200 according to a previously set schedule. For example, the second controller 100 may receive unencoded data from the first controller 10, perform an ECC encoding operation on the received unencoded data to generate encoded data, temporarily store the encoded data in the non-volatile memory 140, then retrieve the encoded data from the non-volatile memory 140, and store the retrieved encoded data in the memory device 200.

[0044] In an exemplary embodiment, the first controller 10, the second controller 100 and the memory device 200 are implemented by separate semiconductor devices. Alternatively, the first controller 10, the second controller 100 and the memory device 200 can be integrated into one semiconductor device. For example, the first controller 10, the second controller 100 and the memory device 200 can be integrated into one semiconductor device to implement a memory card. For example, the first controller 10, the second controller 100 and the memory device 200 can be integrated into one semiconductor device to implement a PC card, such as a (Personal Computer Memory Card International Association) PCMCIA card, a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Reduced Size Multimedia Card (RS-MMC) or an MMC micro card, a Secure Digital (SD) card, a Mini SD card, a Micro SD card or a Universal Flash (UFS) card. In another example, the first controller 10, the second controller 100 and the memory device 200 are integrated into one semiconductor device to implement a solid state disk / drive (SSD).

[0045] In an alternative embodiment, the first controller 10 and the second controller 100 are integrated into one semiconductor device, and the memory device 200 is implemented by an additional semiconductor device. The first controller 10 and the second controller 100 may be connected to each other by, for example, an interconnector or an interposer, and may be implemented as a semiconductor module.

[0046] Figure 2 It shows that the Figure 1 2 is a circuit diagram of an example of an equivalent circuit of a memory block in the memory cell array 210.

[0047] refer to Figure 2 , the memory block BLK1 may be a NAND flash memory having a vertical structure, and Figure 1 The memory cell array 210 may include a plurality of memory blocks having the same shape as the memory block BLK1. The memory block BLK1 may include a plurality of NAND cell strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may vary according to the embodiment.

[0048] NAND cell strings NS11, NS21, and NS31 are disposed between a first bit line BL1 and a common source line CSL. NAND cell strings NS12, NS22, and NS32 are disposed between a second bit line BL2 and a common source line CSL. NAND cell strings NS13, NS23, and NS33 are disposed between a third bit line BL3 and a common source line CSL. Each NAND cell string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST connected in series.

[0049] NAND cell strings commonly connected to one bit line may configure one column. For example, NAND cell strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 may correspond to the first column, NAND cell strings NS12, NS22, and NS32 commonly connected to the second bit line BL2 may correspond to the second column, and NAND cell strings NS13, NS23, and NS33 commonly connected to the third bit line BL3 may correspond to the third column.

[0050] The NAND cell strings connected to one string selection line may configure a row. For example, the NAND cell strings NS11, NS12, and NS13 connected to the first string selection line SSL1 may correspond to the first row, the NAND cell strings NS21, NS22, and NS23 connected to the second string selection line SSL2 may correspond to the second row, and the NAND cell strings NS31, NS32, and NS33 connected to the third string selection line SSL3 may correspond to the third row.

[0051] The string selection transistor SST may be connected to the corresponding string selection lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be connected to the corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1 to BL3. The ground selection transistor GST may be connected to the common source line CSL.

[0052] In the current embodiment, each word line (e.g., WL1) having the same height is connected in common, the string selection lines SSL1 to SSL3 are separated from each other, and the ground selection lines GSL1 to GSL3 are separated from each other. For example, when programming the memory cells included in the NAND cell strings NS11, NS12, and NS13 connected to the first word line WL1 and corresponding to the first column, the first word line WL1 and the first string selection line SSL1 are selected. However, the inventive concept is not limited thereto. In another embodiment, the ground selection lines GSL1 to GSL3 may be connected in common.

[0053] In one embodiment, each memory cell included in the memory block BLK1 is a single-level cell (SLC) for storing 1-bit data. In another embodiment, each memory cell included in the memory block BLK1 may be a multi-level cell (MLC) for storing not less than 2 bits of data. For example, each memory cell included in the memory block BLK1 may be a triple-level cell (TLC) for storing 3-bit data or a quad-level cell (QLC) for storing 4-bit data.

[0054] Figure 3 is a block diagram showing a detailed configuration of the second controller 100 according to an exemplary embodiment of the inventive concept. For example, Figure 3 Can be Figure 1 1 is a block diagram of a second controller 100.

[0055] refer to Figure 3 , the second controller 100 includes a first memory interface 110 (e.g., an interface circuit), a second memory interface 120 (e.g., an interface circuit), a volatile memory 130, a nonvolatile memory 140, and a scheduler 150. Although not shown, the second controller 100 may further include a processor for controlling operations of the second controller 100 and a random access memory (RAM) used as an operation memory of the processor.

[0056] The first memory interface 110 may include a protocol for exchanging various signals and data between the first controller 10 and the second controller 100. The second memory interface 120 may include a protocol for exchanging various signals and data between the second controller 100 and the memory device 200. For example, each of the first memory interface 110 and the second memory interface 120 may communicate with the first controller 10 and the memory device 200 through at least one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small drive interface (ESDI), and an integrated drive electronics (IDE).

[0057] The nonvolatile memory 140 may store data DT received from the first controller 10 through the first memory interface 110. That is, the nonvolatile memory 140 may cache data DT to be stored in the memory device 200. The data DT may be host data HD received from the host or data generated by the first controller 10. For example, the data DT may be obtained by the first controller 10 performing ECC encoding on the host data HD.

[0058] In an exemplary embodiment, metadata MD for managing data DT may be generated while the nonvolatile memory 140 stores data DT. The nonvolatile memory 140 or a processor (not shown) of the second controller 100 may generate metadata MD. In addition, the volatile memory 130 may store metadata MD. For example, metadata MD as management information may include information related to a physical address, information related to pass / failure of data programming, information related to the temperature of the nonvolatile memory 140, and information related to the time elapsed after writing the data. For example, metadata MD may include a mapping table that maps a logical address of a host associated with data DT to a physical address within the nonvolatile memory 140 and / or a physical address within the memory device 200. For example, if the controller 100 attempts to write data DT from the nonvolatile memory 140 to the memory device 200, and the write fails, metadata MD may indicate a programming failure of data DT. For example, if the controller 100 completes writing data DT from the nonvolatile memory 140 to the memory device 200 within a certain amount of time, metadata MD associated with data DT may include the certain amount.

[0059] The volatile memory 130 may include a plurality of memory cells, each memory cell having a state corresponding to stored data. The volatile memory 130 may include a volatile memory cell that loses stored data when power supply is blocked. For example, the volatile memory 130 may include a dynamic RAM (DRAM), a static RAM (SRAM), a mobile DRAM, a double data rate synchronous DRAM (DDR SDRAM), a low power DDR (LPDDR) SDRAM, a graphic DDR (GDDR) SDRAM, or a Rambus DRAM (RDRAM).

[0060] The scheduler 150 may output data DT′ and various signals to the memory device 200 through the second memory interface 120 based on a previously set schedule (or a previously set programming technique). For example, the scheduler 150 may output commands such as read, write, erase, stop erase, and stop write received from the first controller 10 to the memory device 200 in a previously defined order. In addition, the scheduler 150 may output data DT′ received from the memory device 200 to the first controller 10 through the first memory interface 110 based on a previously set schedule. For example, the scheduler 150 may be implemented by at least one of hardware, software, and firmware.

[0061] Figure 4 is a view illustrating data movement according to an exemplary embodiment of the inventive concept.

[0062] refer to Figure 4 , the first controller 10 receives host data HD (①) from the host HOST. Figure 4 In FIG. 1 , as an example, the movement of data is described based on the host data HD. The same inventive concept can be applied to data generated by the first controller 10 .

[0063] The second controller 100 receives the host data HD from the first controller 10, and stores the host data HD in the nonvolatile memory 140 (②). For example, the first controller 10 outputs a command for instructing to store the host data HD in the nonvolatile memory 140, and the second controller 100 stores the host data HD in the nonvolatile memory 140 in response to the command. In another example, the first controller 10 outputs a command for instructing to store the host data HD in the memory device 200, and the second controller 100 stores the host data HD in the nonvolatile memory 140 in response to the command.

[0064] The non-volatile memory 140 generates metadata MD for managing the host data HD while storing the host data HD, and provides the metadata MD to the volatile memory 130 (③). The volatile memory 130 stores the received metadata MD, and can, for example, transmit the metadata MD to the volatile memory 130 through the second memory interface 120 ( Figure 3 ) outputs metadata MD to the memory device 200 (④-1). In addition, the nonvolatile memory 140 may output stored host data HD to the memory device 200 through the second memory interface 120, for example, according to the scheduling of the scheduler 150 (④-2).

[0065] The memory system 1 according to the inventive concept includes the second controller 100 located between the first controller 10 and the memory device 200, so the first controller 10 can reduce the burden of complex management and operation processing requests of the memory device 200. In addition, the second controller 100 includes a non-volatile memory 140 that operates as a buffer of the memory device 200, and the non-volatile memory 140 can store a large amount of data and retain the stored data even if a sudden power failure occurs. Since data loss is prevented when a sudden power failure occurs, the memory system 1 does not need to include a large-capacity capacitor to provide auxiliary power when a sudden power failure occurs.

[0066] Figure 5A is a block diagram of a nonvolatile memory 140 according to an exemplary embodiment of the inventive concept. Figure 5B yes Figure 5A A circuit diagram of a memory cell array 141. Figure 5C and Figure 5D It shows that Figure 5BA conceptual diagram of data stored along the magnetization direction in a magnetic tunnel junction (MTJ) structure 40. For example, Figure 5A and Figure 5B It can be shown Figure 1 The non-volatile memory 140 is provided.

[0067] refer to Figure 5A The nonvolatile memory 140 includes a memory cell array 141, a write / read circuit 142, a control logic device 143 (e.g., a logic circuit), a row decoder 144 (e.g., a decoding circuit), a voltage generator 145, and a column decoder 146 (e.g., a decoding circuit). The write / read circuit 142 may include a sense amplifier SA and a write driver WD (e.g., a drive circuit).

[0068] The memory cells included in the memory cell array 141 may be connected to a plurality of first signal lines and a plurality of second signal lines. The plurality of first signal lines may be bit lines BL, and the plurality of second signal lines may be word lines WL. When various voltage signals or current signals are provided through the plurality of bit lines BL and word lines WL, data is written to or read from the selected memory cells, and data may be prevented from being written to or read from the remaining unselected memory cells.

[0069] An address ADDR for indicating a memory cell to be accessed may be received together with the command CMD, and the address ADDR may include a row address X-ADDR for selecting a word line WL of the memory cell array 141 and a column address Y-ADDR for selecting a bit line BL of the memory cell array 141. The row decoder 144 performs a word line selection operation in response to the row address X-ADDR, and the column decoder 146 may perform a bit line selection operation in response to the column address Y-ADDR.

[0070] The write / read circuit 142 is connected to the bit line BL and can write data to the memory cell or read data from the memory cell. For example, at least a portion of a voltage signal or a current signal can be provided to the memory cell array 141 through the write / read circuit 142. In the current embodiment, the write / read circuit 142 is shown as being connected to the bit line BL. However, in another embodiment, the write / read circuit 142 can be connected to the word line WL.

[0071] In an exemplary embodiment, the control logic device 143 outputs a control signal CTRL_RW for writing data in the memory cell array 141 or reading data from the memory cell array 141, and a control signal CTRL_vol for generating various voltages based on the command CMD, the address ADDR, and the control signal CTRL received from the first controller 10. In one embodiment, the voltage generator 145 generates a word line voltage V_WL based on the control signal CTRL_vol. For example, the voltage generator 145 can generate different voltages for output based on the state of the control signal CTRL_vol. Therefore, the control logic device 143 can control various operations in the non-volatile memory 140.

[0072] refer to Figure 5B The memory cell array 141 may include a plurality of word lines WL, a plurality of bit lines BL, a plurality of source lines SL, and a plurality of memory cells U arranged in regions where the word lines WL and the bit lines BL cross each other. The memory cell array 141 may include, for example, an MRAM cell array.

[0073] One unit memory cell U includes the MTJ structure 40 and the cell transistor CT, and may be selected by selecting one bit line BL and one source line SL. For example, the memory cell array 141 may have a 1MTJ-1TR structure.

[0074] In an exemplary embodiment, the MTJ structure 40 includes a free layer 41, a barrier layer 42, and a pinned layer 43. The free layer 41 is connected to the bit line BL, and the pinned layer 43 is connected to the drain of the cell transistor CT. In addition, the source of the cell transistor CT is connected to the source line SL, and the gate of the cell transistor CT is connected to the word line WL.

[0075] On the other hand, the MTJ structure 40 may be replaced by a resistance element such as a PRAM using a phase change material or a PRAM using a variable resistance material such as a composite metal oxide. In addition, the MTJ structure 40 may be replaced by a resistance element such as an MRAM using a ferroelectric material. The material comprising the resistance element has a resistance value that changes according to the magnitude and / or direction of a current or voltage, and may have a non-volatile characteristic of maintaining a resistance value even if the current or voltage is blocked.

[0076] refer to Figure 5C and Figure 5D, the resistance value of the MTJ structure 40 may be changed according to the magnetization direction of the free layer 41. When the memory cell read signal MC_S is applied to the MTJ structure 40, a data voltage according to the resistance value of the MTJ structure 40 may be output. On the other hand, since the strength of the memory cell read signal MC_S is much smaller than the strength of the programming signal, the magnetization direction of the free layer 41 is not changed by the memory cell read signal MC_S.

[0077] like Figure 5C As shown, in the MTJ structure 40, the magnetization direction of the free layer 41 and the magnetization direction of the pinned layer 43 are arranged in parallel. The MTJ structure in this state can have a smaller resistance value. For example, data "0" can be output through a read operation.

[0078] like Figure 5D As shown, in the MTJ structure 40, the magnetization direction of the free layer 41 is antiparallel to the magnetization direction of the pinned layer 43. The MTJ structure 40 in this state may have a large resistance value. For example, data "1" may be output through a read operation.

[0079] Figure 6 is a block diagram showing a memory system 1b according to an exemplary embodiment of the inventive concept. Figure 6 The components of Figure 3 The description of the element is the same as the element.

[0080] refer to Figure 6 , the nonvolatile memory 140b is located outside the second controller 100b, and the second controller 100b also includes a third memory interface 160b (eg, an interface circuit). The third memory interface 160b may include a protocol for exchanging various signals and data items between the second controller 100b and the nonvolatile memory 140b.

[0081] In an exemplary embodiment, the second controller 100b transmits data received from the first controller 10b to the nonvolatile memory 140b. In an exemplary embodiment, the second controller 100b receives data from the first controller 10b through the first memory interface 110b and transmits the received data to the nonvolatile memory 140b through the third memory interface 160b. The nonvolatile memory 140b may be similar to Figure 1 , Figure 3 , Figure 4 or Figure 5A The non-volatile memory 140 shown in .

[0082] The nonvolatile memory 140b stores the received data and may send metadata MD for managing the data to the second controller 100b. The second controller 100b may receive the metadata MD from the nonvolatile memory 140b through the third memory interface 160b, or generate the metadata MD. In an exemplary embodiment, the volatile memory 130b stores the metadata MD and may send the stored metadata MD to the memory device 200b according to the schedule of the scheduler 150b. In an exemplary embodiment, the nonvolatile memory 140b sends the stored data to the memory device 200b through the third memory interface 160b, the scheduler 150b, and the second memory interface 120b. The memory device 200b may be similar to Figure 1 or Figure 4 The memory device 200 shown in FIG.

[0083] Figure 7 is a block diagram showing a memory system 1c according to an exemplary embodiment of the inventive concept. Figure 7 The components of Figure 6 The description of the element is the same as the element.

[0084] refer to Figure 7 , the non-volatile memory 140c is located outside the second controller 100c, and the second controller 100c also includes a third memory interface 160c. The non-volatile memory 140c may be similar to the non-volatile memory 140b or the non-volatile memory 140. In one embodiment, the first controller 10c also includes a memory interface 12c, which is used to send various signals to the non-volatile memory 140c and receive various signals from the non-volatile memory 140c. The memory interface 12c may include a protocol for exchanging various signals and data items between the first controller 10c and the non-volatile memory 140c.

[0085] In an exemplary embodiment, the first controller 10c directly sends data to the nonvolatile memory 140c through the memory interface 12c. For example, the first controller 10c can provide the host data HD received from the host HOST or the data generated by the first controller 10c to the nonvolatile memory 140c by directly accessing the nonvolatile memory 140c. In addition, the first controller 10c can receive data read from the nonvolatile memory 140c through the memory interface 12c. Therefore, the first controller 10c can directly access the nonvolatile memory 140c or can indirectly access the nonvolatile memory 140c through the second controller 100c.

[0086] Fig. 8Ais a view illustrating an error correction code (ECC) encoding process according to an exemplary embodiment of the inventive concept performed in a memory system 1 d . Figure 8B is a view illustrating an ECC decoding process according to an exemplary embodiment of the inventive concept performed in a memory system 1 d .

[0087] refer to Fig. 8A , the first controller 10d receives the host data HD (①) from the host HOST. Fig. 8A In FIG. 1 , as an example, the movement of data is described based on the host data HD. The same inventive concept can be applied to data generated by the first controller 10 d.

[0088] The first controller 10d includes an ECC encoder 14d (e.g., an encoder circuit) and an ECC decoder 16d (e.g., a decoder circuit). The ECC encoder 14d can perform ECC encoding on the received host data HD. The first controller 10d outputs host data HD′ obtained by performing ECC encoding on the host data HD to the second controller 100d (②).

[0089] The second controller 100d receives the host data HD′ obtained by performing ECC encoding on the host data HD through the first memory interface 110d, and transmits the host data HD′ to the second memory interface 120d (③). The second controller 100d transmits the host data HD′ obtained by performing ECC encoding on the host data HD to the memory device 200d through the second memory interface 120d (④). That is, the second controller 100d can transmit the host data HD′ obtained by performing ECC encoding on the host data HD from the first controller 10d to the memory device 200d. The memory device 200d can store the received host data HD′.

[0090] refer to Figure 8B , when reading the host data HD′ stored in the memory device 200d, the second controller 100d receives the host data HD′ through the second memory interface 120d (①). The second controller 100d sends the host data HD′ received through the second memory interface 120d to the first memory interface 110d (②), and outputs the host data HD′ to the first controller 10d through the first memory interface 110d (③). That is, the second controller 100d can send the host data HD′ read from the memory device 200d to the first controller 10d.

[0091] The ECC decoder 16d provided in the first controller 10d may perform ECC decoding on the host data HD' received from the second controller 100d. The first controller 10d may output the host data HD on which the ECC decoding is performed to, for example, the host HOST (④).

[0092] Fig.9A is a view illustrating an ECC encoding process of a memory system 1e according to an exemplary embodiment of the inventive concept. Fig. 9B is a diagram showing an ECC decoding process of a memory system 1e according to an exemplary embodiment of the inventive concept. Fig.9A and Fig. 9B The components of Fig. 8A and Figure 8B The description of the element is the same as the element in the.

[0093] refer to Fig.9A , the first controller 10e receives host data HD from the host HOST (①), and the ECC encoder 14e performs ECC encoding on the received host data HD. The first controller 10e outputs host data HD′ obtained by performing ECC encoding on the host data HD to the second controller 100e (②).

[0094] In an exemplary embodiment, the second controller 100e further includes an ECC encoder 142e for nonvolatile memory and an ECC decoder 144e for nonvolatile memory. The ECC encoder 142e for nonvolatile memory performs ECC encoding on data to be stored in the nonvolatile memory 140e, and the ECC decoder 144e for nonvolatile memory performs ECC decoding on data read from the nonvolatile memory 140e.

[0095] The second controller 100e receives host data HD′ obtained by performing ECC encoding on the host data HD through the first memory interface 110e, and sends the host data HD′ to the ECC encoder 142e for the nonvolatile memory (③). The ECC encoder 142e for the nonvolatile memory performs ECC encoding for the nonvolatile memory on the host data HD′, and sends the host data HD″ obtained by performing ECC encoding for the nonvolatile memory on the host data HD′ to the nonvolatile memory 140e (④). The nonvolatile memory 140e stores the host data HD″.

[0096] For example, based on the scheduler 150 ( Figure 2) scheduling, the host data HD″ stored in the non-volatile memory 140e can be sent to the memory device 200e. To this end, the host data HD″ read from the non-volatile memory 140e is sent to the ECC decoder 144e for the non-volatile memory (⑤). The ECC decoder 144e for the non-volatile memory performs ECC decoding for the non-volatile memory on the host data HD″ to generate host data HD′ output by the ECC encoder 14e, and sends the host data HD′ to the second memory interface 120e (⑥). The second controller 100e sends the host data HD′ to the memory device 200e through the second memory interface 120e (⑦). The memory device 200e stores the received host data HD′.

[0097] refer to Fig. 9B , when reading the host data HD′ stored in the memory device 200e, the second controller 100e receives the host data HD′ through the second memory interface 120e (①), and sends the host data HD′ to the first memory interface 110e (②). The second controller 100e outputs the host data HD′ to the first controller 10e through the first memory interface 110e (③), and the ECC decoder 16e provided in the first controller 10e performs ECC decoding on the host data HD′ to generate the host data HD. The first controller 10e outputs the host data HD to, for example, the host HOST (④).

[0098] Fig. 10A is a block diagram illustrating a detailed configuration of a second controller 100f according to an exemplary embodiment of the inventive concept. Fig. 10B is a flowchart showing the operation of the second controller 100f. Fig. 10A The components of Figure 3 The second controller 100f may be used to replace any previously described second controller (eg, 100, 100a, 100b, 100c, 100d, or 100e).

[0099] refer to Fig. 10A The second controller 100f further includes a timer 170f (e.g., a timer circuit) and a temperature sensor 172f. For example, the temperature sensor 172f may include a negative temperature coefficient thermistor, a resistance temperature detector, a thermocouple, or a semiconductor-based temperature sensor. The timer 170f may measure the time at which the memory device (e.g., Figure 1 In addition, the temperature sensor 172f can measure the time after which the data in the memory device (e.g., Figure 1200 in FIG. 200). However, the inventive concept is not limited thereto. The temperature sensor 172f may measure the temperature of the second controller 100f or the temperature of the first controller (eg, Figure 1 10) in the temperature.

[0100] The second controller 100f may control output of signals and data to a memory device (eg, Figure 1 200). For example, when the time measured by the timer 170f after programming the prescribed data is greater than or equal to a previously set threshold, the scheduler 150f can rearrange the distribution of the memory cells storing the corresponding data. For example, if the second controller 100f writes the prescribed data to the first group of memory cells and it takes longer than a certain amount of time to complete, the second controller 100f can instruct to move the prescribed data from the first group of memory cells to other second group of memory cells. In addition, for example, when the temperature measured by the temperature sensor 172f is greater than or equal to a previously set threshold, the scheduler 150f can stop outputting signals and data to the memory device (e.g., Figure 1 For example, if the second controller 100f is to write data to a memory cell of a memory device (e.g., 200, 200b, 200c, etc.) on behalf of the first memory controller (e.g., 10, 10b, 10c, etc.), and the second controller 100f determines that the temperature is too high, the second controller 100f may postpone performing the write for a period of time.

[0101] Reference Fig. 10B The operation of the second controller 100f is described in detail. In operation S110, the second controller 100f measures the time of accessing the memory device (eg, Figure 1 The time after which the specified data in 200) is programmed, and the memory device (e.g., Figure 1 200 in). For example, the timer 170f and the temperature sensor 172f can respectively measure the elapsed time and the temperature after performing programming in a prescribed period to generate measurement information, and provide the measurement information to the scheduler 150f. In another example, when the elapsed time and the temperature respectively measured after performing programming are greater than or equal to a previously set threshold value, the timer 170f and the temperature sensor 172f can provide the measured information to the scheduler 150f according to the occurrence of the event.

[0102] In an exemplary embodiment, in operation S120, the second controller 100f determines whether to stop the memory device (eg, Figure 1For example, when the temperature measured by the temperature sensor 172f is greater than or equal to a previously set threshold, the scheduler 150f stops a memory operation such as data programming during a prescribed time in operation S130.

[0103] When the temperature measured by the temperature sensor 172f is lower than the previously set threshold value, the second controller 100f determines whether to rearrange the distribution of the memory cells based on the information measured by the timer 170f in operation S140. For example, when the time elapsed after the programming is performed measured by the timer 170f is greater than or equal to the previously set threshold value, the second controller 100f controls the rearrangement of the distribution of the memory cells storing the corresponding data in operation S150.

[0104] Fig.11A is a block diagram illustrating a detailed configuration of a memory system 1g according to an exemplary embodiment of the inventive concept. Fig. 11B is a flowchart showing the operation of the memory system 1g.

[0105] refer to Fig.11A The first controller 100g includes a manager circuit 18g. In addition, the second controller 100g includes a first memory interface 110g, a second memory interface 120g, and a monitor circuit 180g.

[0106] In an exemplary embodiment, the second controller 100g obtains information M_INF related to the memory device 200g from the memory device 200g through the second memory interface 120g. For example, the information M_INF may include at least one of data read result information and information related to the distribution of memory cells storing data. The second controller 100g may monitor the state of the memory device 200g by sending the information M_INF to the monitor circuit 180g.

[0107] In an exemplary embodiment, the monitor circuit 180g transmits the state information M_STT of the memory device 200g to the first controller 10g through the first memory interface 110g. The manager circuit 18g provided in the first controller 10g receives the state information M_STT, so the first controller 10g can check the state of the memory device 200g. The manager circuit 18g can change the policy of the memory device 200g, or can execute a defense code on the memory device 200g based on the received state information M_STT. In an exemplary embodiment, the defense code is used to determine an optimal or desired level of a read voltage according to a change in the threshold voltage distribution of a non-volatile memory cell during a read operation of the non-volatile memory. For example, the manager circuit 18g can select one of a plurality of available defense codes using the received state information M_STT, determine the level of a read voltage used to perform a read operation based on the selected defense code, and perform a read operation by using the read voltage having the determined level. For example, when the manager circuit 18g determines a change in the policy (e.g., write / erase policy) of the memory device 200g based on the state information M_STT, the manager circuit 18g outputs a changed policy-related signal M_Pol to the second controller 100g. The second controller 100g may transmit the changed policy-related signal M_Pol received through the first memory interface 110g to the memory device 200g through the second memory interface 120g.

[0108] Reference Fig. 11B The operation of the memory system 1g is described in detail. In operation S210, the second controller 100g obtains information M_INF related to the memory device 200g from the memory device 200g. In operation S220, the second controller 100g may obtain the state of the memory device 200g based on the information M_INF received from the memory device 200g. For example, the monitor circuit 180g provided in the second controller 100g may determine the state of the memory device 200g based on the information M_INF including information related to the distribution of the memory cells.

[0109] The status information M_STT of the memory device 200g is provided to the first controller 10g through the monitor circuit 180g, and the first controller 10g can obtain the status of the memory device 200g. For example, the first controller 10g requests the status information M_STT from the second controller 100g, and the second controller 100g provides the status information M_STT to the first controller 10g in response to the request. In another example, when the obtained status information M_STT corresponds to a previously set condition, the second controller 100g provides the status information M_STT to the first controller 10g without the request of the first controller 10g. Alternatively, without the request of the first controller 10g, the second controller 100g provides the obtained status information M_STT to the first controller 10g at each prescribed time period. For example, the second controller 100g can periodically provide the status information M_STT to the first controller 10g.

[0110] In operation S230, the first controller 10g determines whether it is necessary to change the policy of the memory device 200g based on the received status information M_STT. Whether it is necessary to change the policy of the memory device 200g may be determined by the manager circuit 18g. For example, when it is determined by the manager circuit 18g to change the policy for the memory device 200g based on the status information M_STT, the first controller 10g may change various policies for controlling the memory device 200g in operation S240. Specifically, the manager circuit 18g outputs the changed policy-related signal M_Pol, and the changed policy-related signal M_Pol may be provided to the memory device 200g through the second controller 100g.

[0111] Fig.12 1 is a block diagram illustrating an example in which a memory system according to an exemplary embodiment of the inventive concept is applied to a solid state drive (SSD) system 1000 .

[0112] refer to Fig.12 , the SSD system 1000 includes a host 1100 (e.g., a host device) and an SSD 1200. The SSD 1200 sends signals to and receives signals from the host 1100 through a signal connector, and may receive power through a power connector. The SSD 1200 includes an SSD controller 1210 and a plurality of memory devices 1230, 1240, and 1250. The SSD controller 1210 includes a first controller 1211 and a second controller 1212. The second controller 1212 includes a non-volatile memory NVM. For example, Figure 3 The second controller 100 may be used to implement the second controller 1212 .

[0113] The memory system according to the exemplary embodiment of the inventive concept may be installed in or applied to a memory card system, a computing system, or a UFS and SSD system 1000. In addition, the memory system according to the exemplary embodiment of the inventive concept may be applied to various electronic systems in each of which a nonvolatile memory is installed.

[0114] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A memory system, comprising: Memory devices; a first controller configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host; as well as The second controller includes a nonvolatile memory configured to store the data, the second controller being configured to receive the control signal and the data from the first controller and control the memory device based on the control signal.

2. The memory system according to claim 1, wherein the second controller comprises: a first memory interface electrically connected to the first controller; as well as A second memory interface is electrically connected to the memory device. 3 . The memory system of claim 2 , wherein the second controller receives the data through the first memory interface and outputs the data to the memory device through the second memory interface.

4. The memory system according to claim 1, wherein the first controller outputs a command for instructing to store the data in the non-volatile memory, and The second controller stores the data in the non-volatile memory in response to the command.

5. The memory system according to claim 1, wherein the first controller outputs a command for instructing to store the data in the memory device, and The second controller stores the data in the non-volatile memory in response to the command.

6. The memory system according to claim 1, The second controller further includes a volatile memory, wherein the non-volatile memory generates metadata for managing the data when storing the data, and The volatile memory stores the metadata. 7 . The memory system of claim 6 , wherein the second controller outputs the data stored in the nonvolatile memory and the metadata stored in the volatile memory to the memory device. 8 . The memory system according to claim 1 , wherein the second controller further comprises a scheduler for controlling output of the control signal and the data to the memory device based on a previously set programming technique.

9. The memory system according to claim 1, wherein the first controller further comprises: An error correction code (ECC) encoder, used for performing ECC encoding on the data; as well as an ECC decoder for performing ECC decoding on data read from the memory device, and The second controller receives data encoded by the ECC encoder and sends the encoded data to the memory device.

10. The memory system according to claim 1, wherein the second controller further comprises: An error correction code (ECC) encoder, configured to perform ECC encoding on the data for the non-volatile memory; as well as The ECC decoder is used to perform ECC decoding on the data read from the non-volatile memory.

11. The memory system according to claim 1, wherein the second controller further comprises: a temperature sensor for measuring the temperature of the memory device; as well as A timer is used to measure the time that has passed after programming the data in the memory device. 12 . The memory system according to claim 11 , wherein the second controller controls output of a signal and data to the memory device based on items of information measured by the temperature sensor and the timer, respectively.

13. The memory system according to claim 1, The second controller further includes a monitor circuit, the monitor circuit being configured to receive information related to the memory device from the memory device and generate status information of the memory device based on the information, The first controller further includes a manager circuit configured to determine a policy change of the memory device based on the status information.

14. The memory system of claim 1, wherein the non-volatile memory comprises a magnetic random access memory (MRAM).

15. The memory system according to claim 1, The first controller further includes a flash translation layer FTL, wherein the FTL is used to convert a logical address received from a host into a physical address of the memory device, wherein the first controller outputs the physical address to the second controller, and The second controller controls the memory device based on the physical address.

16. A memory system comprising: Memory devices; a first controller configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host; a second controller including a first memory interface configured to receive the data from the first controller; and a second memory interface configured to output the data to the memory device; as well as The nonvolatile memory is configured to receive the data from the second controller and store the data.

17. The memory system of claim 16, wherein the second controller further comprises a third memory interface electrically connected to the non-volatile memory. 18 . The memory system of claim 16 , wherein the second controller further comprises a volatile memory for storing metadata for managing data stored in the nonvolatile memory.

19. The memory system of claim 16, wherein the first controller further comprises a memory interface electrically connected to the non-volatile memory.

20. The memory system of claim 16, wherein the second controller further comprises a scheduler configured to receive a plurality of commands for the memory device from the first controller and output the commands to the memory device in a previously defined order.

21. A memory controller comprising: a first memory interface configured to receive, from a first controller, a plurality of commands for a memory device and data to be stored in the memory device; a second memory interface electrically connected to the memory device; A non-volatile memory, used for caching the data; as well as A scheduler is configured to output the plurality of commands and the data stored in the non-volatile memory to the memory device through the second memory interface based on a set schedule, wherein the scheduler outputs metadata for managing the data and the data to the memory device through the second memory interface based on a previously set schedule.

22. The memory controller of claim 21 further comprising a volatile memory, in, The non-volatile memory generates the metadata during the caching, and The volatile memory stores the metadata.

23. The memory controller according to claim 21, in, Data read from the memory device is received via the second memory interface, and The read data is output to the first controller through the first memory interface.

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