Semiconductor die, method for manufacturing the same, and package for accommodating the die

Abstract

This document describes a semiconductor die, a method for manufacturing the same, and a package housing the die. A semiconductor die includes a structure having a power region and a peripheral region surrounding the power region. At least one power device is located in the power region. A trench insulating device extends in the structure from a front side toward a rear side along a first direction. The trench insulating device is adapted to prevent heat from being conducted from the power region toward the peripheral region along a second direction orthogonal to the first direction. The trench insulating device extends in the second direction greater than the thickness of the structure along the first direction.

Description

Technical Field

[0001] The present disclosure relates to semiconductor dies, methods of manufacturing semiconductor dies, and packages housing semiconductor dies. Background Art

[0002] Gallium nitride (GaN)-based semiconductor devices have attracted considerable attention in the field of power electronics applications due to their properties, such as high breakdown electric field, high carrier density, high electron mobility, and high saturation rate. On the other hand, there are known technologies for implementing intelligent power integrated circuits (Intelligent Power ICs) based on a GaN-on-silicon (GaN-on-Si) platform with large size, low cost, and high scalability.

[0003] Currently, high-voltage power components (e.g., power transistors, GaN-based HEMT (High Electron Mobility Transistor) devices, etc.) are manufactured on or bonded to chips that house low-voltage peripheral devices and form mixed digital / analog circuits. In particular, analog functional blocks such as reference voltage generators, voltage comparators, and voltage converters are achieved using GaN-based technology in conjunction with peripheral circuits achieved using CMOS silicon technology.

[0004] In the above technical solution, the peripheral circuit has functions such as protecting and / or controlling the power components against harmful operating conditions (e.g., overcurrent and overvoltage situations), and is necessary to ensure robust control, greater functionality and higher reliability of the high-voltage power components.

[0005] It is highly desirable to integrate power devices into the same chip that houses peripheral functional blocks, thereby maximizing integration density.

[0006] However, the performance of peripheral circuits (eg, power devices) depends on temperature. Excessive temperatures generated by power devices can cause peripheral circuit failures or, in extreme cases, burn out the chip or parts thereof.

[0007] Solutions for managing temperature at the circuit level have been proposed (eg, over-temperature protection circuits). Likewise, cooling solutions using heat sinks at the package level are known.

[0008] However, as the integration density increases and the distance between electronic power devices and peripheral circuits becomes smaller, the above solutions are not satisfactory. Summary of the Invention

[0009] The present disclosure provides a semiconductor die, a method of manufacturing a semiconductor die, and a package housing a semiconductor die that overcomes limitations of the prior art.

[0010] According to the present disclosure, there are provided a semiconductor die, a method of manufacturing a semiconductor die, and a package housing a semiconductor die as defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a better understanding of the present disclosure, some embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0012] Figure 1 According to some embodiments of the present invention Figure 2 A cross-sectional view of a portion of a die having an electrically insulating region disposed between a power region and a peripheral region, taken along section line II of FIG.

[0013] Figure 2 yes Figure 1 A top view of the die;

[0014] Figure 3 is a cross-sectional view of a portion of a die having an electrically insulating region disposed between a power region and a peripheral region according to some embodiments of the present disclosure;

[0015] Figure 4 Illustration of the accommodation Figure 1 or Figure 3 a portion of a package of a die; and

[0016] Figures 5 to 7 The diagram illustrates a method according to some embodiments Figure 1 or Figure 3 Variations in the manufacturing of the power areas of the die. DETAILED DESCRIPTION

[0017] Figure 1 A portion of a die 1 according to one aspect of the present disclosure is illustrated in a side cross-sectional view of a three-axis Cartesian reference system X, Y, Z. Figure 1 The elements illustrated in the drawings are not represented to the same scale but are represented schematically and by way of example to facilitate understanding of the present disclosure.

[0018] The tube core 1 includes: a substrate 2, which is made of a semiconductor material such as silicon and, for example, is made of silicon with P-type doping, and has a front side 2a and a back side 2b opposite to each other along the Z-axis direction; an epitaxial layer 4, which is made of epitaxially grown silicon (for example, with N-type doping) and extends over the front side 2a of the substrate 2; and a dielectric layer 6, which is made of, for example, silicon oxide (SiO2) and extends over the top surface 4a of the epitaxial layer 4.

[0019] It will be understood that between the substrate 2 and the epitaxial layer 4, there may be a further epitaxial layer or some other type of layer (not shown). Hereinafter, the assembly of the substrate 2 and the epitaxial layer 4 (including the possible further layers, if present) will be referred to as "structure 3", with a thickness, considered along the axis X, between the top face 4a of the epitaxial layer 4 and the back side 2b of the substrate 2, denoted by h. As will be better understood in the following description, the possible further layers present are thermally conductive materials having a thermal conductivity comparable to or higher than that of the material of the substrate 2 and / or the epitaxial layer 4.

[0020] According to one aspect of the present disclosure, in order to achieve high integration density, a planar process is used to manufacture a high voltage power device 10 and a low voltage peripheral device 8 , eg obtained using CMOS technology, which implements functional blocks adapted to control / support the operation of the power device.

[0021] The layout of the die 1 can be organized so as to group the high-voltage power devices 10 together in the same area of ​​the die 1, and to group the low-voltage peripheral devices 8 together in the same corresponding area of ​​the die 1. In particular, the low-voltage peripheral devices 8 are formed in an area that surrounds the area accommodating the high-voltage power devices 10 in a top view (in the plane XY).

[0022] For this purpose, refer to Figure 1 and Figure 2 The die 1 (or more specifically, the structure 3) includes a first region 1a that houses low-voltage peripheral components 8. In some embodiments, the low-voltage peripheral components 8 are integrated into the structure 3 and at least partially into the epitaxial layer 4. Hereinafter, the first region 1a will also be referred to as the "peripheral region 1a," and the components housed therein will also be referred to as the "peripheral components 8." Extending over the dielectric layer 6 are one or more electrical contact pads 7, which are electrically coupled to the peripheral components 8 via conductive vias and a metal layer (generally indicated by reference numeral 9).

[0023] The die 1 (or more specifically, the structure 3) further includes a second region 1b that houses one or more high-voltage power devices 10, such as one or more GaN-based HEMTs. Typically, the high-voltage power devices 10 dissipate hundreds of microjoules of thermal energy during device operation. Hereinafter, this second region 1b will also be referred to as the "power region 1b," and the high-voltage power devices 10 will also be referred to as the "power devices 10."

[0024] For example, the components / circuits of the peripheral area 1a and the power area 1b together form a DC / DC converter, wherein the components / circuits of the peripheral area 1a form a control part, such as a pre-amplification circuit, a drive circuit for biasing one or more gate terminals of the DC / DC converter, etc., while the power devices accommodated in the power area 1b form the switching elements of the DC / DC converter.

[0025] The die 1 (or more specifically, the structure 3) further includes a third region 1c, which extends between the first region 1a and the second region 1b in a top view (e.g., in plane XY) and houses one or more trenches 12. The trenches 12 are adapted to form obstacles to the lateral heat propagation of heat generated by the power devices 10 in the power region 1b during device operation. As shown, arrow T2 indicating heat propagation in direction X is intercepted and obstructed by the trenches 12. Hereinafter, the third region 1c will also be referred to as the "thermal insulation region 1c."

[0026] Figure 2 The diagram is shown in a top view in plane XY. Figure 1 In some embodiments, Figure 1 The cross-sectional view is specifically along Figure 2 Take the section line II of Figure 2 It can be noted that the thermal insulation region 1 c extends so as to completely surround the power region 1 b. Furthermore, the peripheral region 1 a extends so that it completely surrounds the thermal insulation region 1 c.

[0027] As already described, the function of thermal insulation region 1c is to provide a barrier to the propagation or transfer of heat generated in power region 1b toward peripheral region 1a during device operation. It should be understood that, in the case where peripheral region 1a extends toward or adjacent to a portion of power region 1b, for example, peripheral region 1a does not completely surround power region 1b, thermal insulation region 1c may extend between peripheral region 1a and power region 1b without completely surrounding power region 1b.

[0028] In any heat propagation direction considered (ie, along X, along Y, or a direction having components along both X and Y), the heat generated at the power region 1 b is intercepted by the trenches 12 of the thermal insulation region 1 c.

[0029] return Figure 1One or more trenches 12 (a plurality of trenches 12 are shown here by way of example) include a first filler layer 12a of a dielectric material (e.g., SiO2) and a second filler layer 12b completely contained within the first filler layer 12a. In some embodiments, the second filler layer 12b is made of a material adapted to compensate for thermal stresses generated in the trenches 12 during device operation. The applicant has observed that the filler layer 12a can suffer physical damage due to the different thermal expansion of the silicon oxide of the filler layer 12a relative to the silicon of the structure 3. The use of the second filler layer 12b (here, for example, polysilicon) can overcome this undesirable phenomenon.

[0030] However, it should be understood that if the structure 3 and the first filling layer 12a are made of materials such that the above-mentioned undesirable phenomenon does not occur, the second filling layer 12b can be omitted. In addition, if the specific operating application of the tube core 1 is such that thermal stress that causes damage to the trench 12 is not generated, the second filling layer 12b can also be omitted regardless of the material used.

[0031] Typically, the first filling layer 12a is made of a thermally insulating material, ie a material having a thermal conductivity approximately equal to 1 W / mK.

[0032] The trench 12 extends in depth in the structure 3, starting from the top surface 4a of the epitaxial layer 4, completely passing through the epitaxial layer 4 and through a portion of the substrate 2, and terminating in the substrate 2. These embodiments present the following advantage: the trench 12 is formed simultaneously with the trench area for electrical insulation between the devices / components in the peripheral area 1a. In fact, it is known to electrically insulate electronic components (for example, transistors) from each other by trenches filled with dielectric material. During the processing of the tube core 1, the step of forming such an electrically insulating trench further includes the step of simultaneously forming the thermally insulating trench 12. Therefore, the manufacturing costs are reduced and the production process is accelerated.

[0033] Alternatively or additionally, however, the trenches 12 may be formed in a separate step. In this case, the depth of the trenches 12 is not limited to the depth of the trenches present in the peripheral region 1 a. In particular, the trenches 12 may extend only through the thickness of the epitaxial layer 4 or may terminate generally at the front side 2 a of the substrate 2.

[0034] according to Figure 3 In some further embodiments shown, one or more grooves 12 (in Figure 3 In the embodiment, all trenches 12) may extend through the entire thickness of the structure 3, ie completely through the epitaxial layer 4 and through the substrate 2 until reaching the back side 2b of the substrate 2.

[0035] In use, the heat generated in the power region 1b is dissipated through the structure 3. Among the various possible directions of dissipation, Figure 1 The arrow T1 in FIG. 1 identifies the vertical propagation direction along the Z-axis toward the back side 2b of the substrate 2. Figure 1 1 , a first lateral propagation direction along the axis X, indicated by arrow T2, is identified. This heat propagation in direction T2 is hindered by the presence of the trenches 12. Furthermore, a second lateral propagation direction along the axis X is indicated by arrow T3, which passes through the substrate 2 in regions of the substrate 2 that do not have trenches 12.

[0036] The thermally insulating region 1 c has a transverse extension d in the direction of the axis X, so that the thermal path T3 will have a greater distance than the thermal path T1. To meet this requirement, during the design phase, a value of d is conservatively chosen that is greater than the value of h, where h is the thickness of the structure 3 as described. In particular, the transverse extension d is given by the sum of the extension of each trench 12 along X plus the extension of the portion of the structure 3 between one trench 12 and the adjacent trench 12, again along X.

[0037] The number, material and lateral extension of the grooves 12 are also chosen so that the grooves 12 will provide sufficient thermal insulation with respect to the heat wave T2, for example so that the heat propagating through the grooves 12 to the peripheral area 1a in the direction of the axis X (arrow T2') will be below a threshold value preset in the design step.

[0038] The design of the trenches 12 (eg, in terms of the number of trenches, the material and thickness of the filling layer, the lateral extension of the trenches, etc.) can be performed by a simulation program, which is understandable to those skilled in the art.

[0039] Obviously, the description above with specific reference to the heat propagation direction along X (in particular with reference to the lateral extension d of the thermal insulation area 1c) applies to any heat propagation direction considered, i.e. along X, along Y, and a direction having components in both the X and Y directions.

[0040] The trenches 12 therefore define preferential propagation paths or channels for the heat generated in the power region 1 b , and this heat is therefore preferentially propagated towards the back side 2 b of the substrate 2 .

[0041] like Figure 4 As schematically illustrated in FIG. 1 , during packaging, the die 1 is coupled to a base plate 20 (in FIG. 1 ) of a package 25 made of a thermally conductive material, in particular a metal material such as copper. Figure 4 Only a portion of the package 25 is shown. The base plate 20 of the package 25 is adapted to support the die 1 and is made of a thermally conductive material to facilitate dissipation of heat generated by the power device 10 during use. Typically, the base plate 20 is thermally coupled to a heat sink 22.

[0042] Thus, in use, heat that propagates along T1 or generally reaches the back side of the substrate 2 is transferred to the base plate 20 of the package 25 and then dissipated by the heat sink 22 .

[0043] Figure 5 The diagram shows an enlarged detail of the power region 1b of the die 1. In some embodiments, power devices (specifically, only a GaN-based HEMT device 10 is shown here) are formed on the structure 3 in a manufacturing step simultaneously with or subsequent to the manufacturing step of the peripheral components 8. The manufacture of GaN-based HEMT devices is known per se and is not described herein, as long as it does not constitute the subject matter of the present disclosure. The device 10 includes a heterostructure 10a formed by a channel layer 10b, on which extends a barrier layer 10c made of aluminum gallium nitride (AlGaN). An insulating layer 10d made of a dielectric material extends over the barrier layer 10c. A gate terminal 10e extends over the barrier layer 10c between a source terminal 10f and a drain terminal 10g.

[0044] To facilitate adhesion of channel layer 10 b of device 10 to structural body 3 of die 1, an interface layer 26 made of aluminum nitride is present. Interface layer 26 functions to form a lattice-matched interface between the crystal lattice of epitaxial layer 4 (here, made of silicon) and the crystal lattice of channel layer 10 b (here, made of GaN), and also facilitates thermal coupling between HEMT device 10 and underlying structural body 3.

[0045] The HEMT device 10 is of the lateral conduction type and has a source terminal 10 f , a drain terminal 10 g , and a gate terminal 10 e on its top side to facilitate their electrical contact (eg, via wire bonds) for device biasing.

[0046] In some different embodiments, Figure 6 China and Israel Figure 5 The same enlarged view shows that after the peripheral components 8 are manufactured, one or more power devices 10 are coupled to the structural body 3 ( Figure 6 , again only a single GaN-based HEMT device 10 is illustrated).

[0047] In this case, the HEMT device 10 has a substrate 10h, for example, made of Si or SiC, with a heterostructure 10a extending on the substrate 10h. A thermally conductive coupling region 30, for example, made of a thermally conductive adhesive or solder paste, extends between the substrate 10h of the HEMT device 10 and the structure 3, thereby coupling them together.

[0048] According to some further embodiments, Figure 7 As shown, dielectric layer 6 houses a plurality of metal layers 32a-32c, which collectively form a metal stack. Figure 7By way of example, a bottom layer 32c, a top layer 32a, and an intermediate layer 32b disposed between the bottom layer 32c and the top layer 32a are illustrated. The metal layers 32a-32c are coupled together via thermally conductive vias 34. The bottom metal layer 32c is in thermal contact with the structure 3 (possibly via an interface layer), while the top metal layer 32a is in thermal contact with the substrate 10h of the device 10 via a coupling region 30 (here, for example, made of solder paste, such as lead or tin). The metal layers 32a-32c further improve the thermal coupling between the HEMT device 10 and the structure 3. As will be appreciated by those skilled in the art, other coupling or bonding techniques between the HEMT device 10 and the structure 3 may be used.

[0049] By examining the features of the present disclosure provided in accordance with the present disclosure, the advantages it provides can be understood.

[0050] In particular, the present disclosure enables thermal decoupling of low-power (CMOS) circuits from high-power circuits, thereby increasing the integration density of components on a single die without causing failures due to the high heat generated by the power devices during use.

[0051] Finally, it is evident that modifications and variations may be made to the disclosure herein described and illustrated without departing from the scope thereof as defined by the appended claims.

[0052] For example, the power devices accommodated in the power region 1 b include one or more of the following: lateral (LDMOS), BJT, power MOS (eg, based on SiC), IGBT, and the like.

[0053] Furthermore, the components / circuits of the peripheral region 1 a and the power region 1 b may together form an AC / AC cycloconverter, a DC / AC inverter and an AC / DC rectifier.

[0054] The various embodiments described above can be combined to provide further embodiments.

[0055] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to encompass all possible embodiments claimed by such claims, as well as the full scope of equivalents. Therefore, the claims are not limited by the disclosure.

Claims

1. A semiconductor structure comprising: a structure made of a semiconductor material and having a first side and a second side, the first side of the structure including a first region and a second region, the second region at least partially surrounding the first region; at least one low-voltage semiconductor device disposed in the second region; at least one semiconductor power device, arranged in the first region; a thermally conductive coupling interface coupled between the at least one semiconductor power device and the structure; a third region located between the first region and the second region, the third region comprising a trench insulating structure extending in the structural body along a first direction from the first side toward the second side, the trench insulating structure having a size and a material so as to form an obstacle to heat conduction from the first region toward the second region along a second direction substantially orthogonal to the first direction; The trench insulating structure is formed such that its extension along the second direction is greater than a thickness of the structure body measured from the first side to the second side along the first direction. 2 . The semiconductor structure according to claim 1 , wherein an extension of the third region in the second direction is greater than a thickness of the structure measured from the first side to the second side along the first direction.

3. The semiconductor structure according to claim 2, wherein the trench isolation structure comprises: a plurality of grooves, successive to one another in the second direction and spaced apart from one another in the second direction by separation regions, the extension of the third region in the second direction comprising the sum of the extension of the grooves in the second direction and the extension of the separation regions in the second direction; or A single trench, the extension of the third region is an extension of the single trench along the second direction. 4 . The semiconductor structure of claim 3 , wherein each trench of the plurality of trenches or the single trench comprises a thermally insulating material. 5 . The semiconductor structure of claim 3 , wherein each trench of the plurality of trenches or the single trench comprises a dielectric material layer and a polysilicon region, each dielectric material layer completely surrounding the polysilicon region. The semiconductor structure according to claim 1 , wherein the trench isolation structure extends along the first direction through the entire structure body to the second side. 7 . The semiconductor structure according to claim 1 , wherein the trench insulating structure extends along the first direction through a portion of the thickness of the structural body in the first direction and terminates inside the structural body. 8 . The semiconductor structure according to claim 7 , wherein the structure comprises a P-type silicon substrate and an N-type silicon epitaxial layer on the substrate, and the trench insulating structure completely extends through the epitaxial layer and terminates inside the substrate. 9 . The semiconductor structure of claim 1 , wherein the thermally conductive coupling interface comprises one or more of an aluminum nitride layer, a thermally conductive adhesive, a solder paste, or a metal stack. 10 . The semiconductor structure of claim 1 , wherein the at least one low voltage semiconductor device in the second region comprises a plurality of electronic components fabricated using CMOS technology.

11. The semiconductor structure of claim 1, wherein the at least one semiconductor power device is a GaN-based high electron mobility transistor (HEMT) device. 12 . The semiconductor structure according to claim 1 , wherein the trench insulation structure completely surrounds the first region in the second direction and forms a ring-shaped thermal insulation structure.

13. A method of manufacturing a semiconductor structure, comprising: providing a structure of semiconductor material having a first side and a second side, the first side including a first region and a second region at least partially surrounding the first region; coupling the second side of the structure to a bottom plate of a package; coupling at least one semiconductor power device on the first side of the structure in the first region through a thermally conductive coupling interface; In the structure, a trench insulating structure is formed between the first region and the second region, the trench insulating structure extending from the first side toward the second side along a first direction, the trench insulating structure having a size and a material selected so as to form an obstacle to heat conduction from the first region toward the second region along a second direction substantially orthogonal to the first direction, Forming the trench insulation structure includes forming the trench insulation structure such that the trench insulation structure has an extension along the second direction that is greater than a thickness of the structure measured from the first side to the second side along the first direction.

14. The method of claim 13, wherein coupling the at least one semiconductor power device comprises: forming the thermally conductive coupling interface; as well as The semiconductor power device is formed on the thermally conductive coupling interface.

15. The method of claim 13, wherein coupling the at least one semiconductor power device comprises: forming the thermally conductive coupling interface of thermally conductive adhesive or solder paste; as well as The semiconductor power device is mounted on the thermal conductive coupling interface.

16. The method according to claim 13, wherein forming the trench isolation structure comprises: forming a plurality of trenches continuous with each other along the second direction, the trenches being separated from each other by corresponding separation regions, the extension of the trench insulation structure being the sum of extensions of the trenches and the separation regions along the second direction; or A single trench is formed, and the extension of the trench insulation structure is an extension of the single trench along the second direction.

17. The method of claim 16, wherein forming each of the plurality of trenches or forming the single trench comprises: forming recesses by etching selected portions of the structure on the first side; as well as A thermal insulation material is deposited in the groove.

18. A package comprising: a base plate made of a thermally conductive material; as well as A semiconductor die is coupled to the base plate, the semiconductor die comprising: a structure made of a semiconductor material having a first side and a second side, the second side being coupled to the base plate, the structure including a first region and a second region, the second region at least partially surrounding the first region; at least one low-voltage semiconductor device arranged in the second region at the first side of the structural body; at least one semiconductor power device disposed in the first region at the first side of the structure; a thermally conductive coupling interface coupled between the at least one semiconductor device and the structure; a third region located between the first region and the second region, the third region comprising a trench insulating structure extending in the structural body along a first direction from the first side toward the second side, the trench insulating structure having a size and a material so as to form an obstacle to heat conduction from the first region toward the second region along a second direction substantially orthogonal to the first direction; The trench insulating structure is formed such that its extension along the second direction is greater than a thickness of the structure body measured from the first side to the second side along the first direction. 19 . The package of claim 18 , wherein the at least one semiconductor power device is a GaN-based high electron mobility transistor (HEMT) device, and the at least one low voltage semiconductor device is a CMOS device.

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