An automatic equalization circuit for the midpoint voltage of a type I three-level bus in a converter

Abstract

The present invention belongs to the technical field of power electronic converters, and discloses an I-type three-level busbar midpoint voltage automatic equalization circuit in a converter, comprising: an input soft start device, a series branch consisting of a busbar capacitor C1 and a busbar capacitor C2 in series, an automatic equalization circuit, an I-type NPC three-level bridge arm, and an output filter; the automatic equalization circuit comprises a power device IGBT5, a power device IGBT6, a transformer TR1, a capacitor C3, and a capacitor C4. The present invention realizes the ability to automatically and dynamically adjust the busbar capacitor midpoint voltage in real time, so that the DC / AC output positive and negative half-cycle waveforms are more symmetrical.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronic converters, and in particular relates to an I-type three-level bus midpoint voltage automatic balancing circuit in a converter. Background Art

[0002] With the continuous research and breakthroughs of multi-level technology by universities / research institutes / high-tech enterprises in recent years, multi-level circuits are increasingly used in DC / AC products. As a relatively classic and practical multi-level circuit topology, the I-type three-level DC / AC inverter circuit is more common in many AC transmission products, new energy off-grid / grid-connected power generation devices, new energy vehicle electric drive and electronic control products, etc., because of its advantages such as good output waveform sinusoidality, low harmonic content, low voltage stress, and low EMI output. However, in practical applications, when the I-type three-level DC / AC inverter device adopts PWM modulation, the bus capacitor midpoint voltage is unbalanced, resulting in a DC bias in the output AC waveform, causing the output waveform to be asymmetric, seriously affecting the output characteristics of the machine, and causing adverse effects on the load. Therefore, it is very necessary and of great significance to solve the problem of bus midpoint imbalance in the I-type three-level circuit.

[0003] At present, the common technical methods for dealing with the bus midpoint voltage imbalance problem in the diode midpoint clamped I-type three-level inverter circuit are as follows: 1) connecting equalizing resistors in parallel to the upper and lower DC bus capacitor banks; 2) adding an independent DC / DC converter device or functional module; 3) using bus midpoint voltage sampling and online adjustment through optimization software algorithm.

[0004] Although these existing common technologies have achieved certain results in solving the bus midpoint voltage imbalance problem, they all have some shortcomings based on their inherent circuit characteristics and control features.

[0005] 1) Connecting resistors in parallel to the upper and lower DC bus capacitor banks: In a type I three-level inverter circuit, connecting resistors in parallel to the upper and lower DC bus capacitor banks can, to a certain extent, reduce the midpoint voltage offset caused by the discrete parasitic parameters inside the bus capacitors. However, this method cannot achieve dynamic adjustment and is limited by the accuracy of the resistors. Therefore, the effect of solving the bus midpoint voltage imbalance problem is very limited, and there is also a certain amount of resistive energy consumption.

[0006] 2) Adding an independent DC / DC converter device or functional module: Although this method can better solve the problem of unbalanced midpoint voltage of type I three-level bus, it requires more external circuit components and independent power circuit and control circuit, which will result in high machine cost, large size, complex system, and greater power loss.

[0007] With the help of bus midpoint voltage sampling, online adjustment is made through optimizing software algorithms: Although this technical method requires fewer peripheral devices, it has high requirements for the accuracy of bus midpoint voltage sampling and the control loop algorithm is also relatively complex. In addition, when the bus midpoint voltage sampling is disturbed, the machine will work abnormally, which may produce worse results; when the machine is running in certain states such as the power on / off process / load switching process, reliable and effective adjustment cannot be achieved. Summary of the invention

[0008] The purpose of the embodiment of the present invention is to provide a type I three-level bus midpoint voltage automatic balancing circuit in a converter, which can automatically and dynamically balance the bus capacitor midpoint voltage in real time, so that the DC / AC output positive and negative half-cycle waveforms are more symmetrical.

[0009] The embodiment of the present invention is implemented as follows:

[0010] An I-type three-level bus midpoint voltage automatic equalization circuit in a converter comprises: an input soft-start device, a series branch consisting of a bus capacitor C1 and a bus capacitor C2 connected in series, an automatic equalization circuit, an I-type NPC three-level bridge arm and an output filter; a DC input terminal is connected to the input soft-start device, the series branch is connected in parallel between the DC input terminals, the automatic equalization circuit is connected between the DC input terminals and connected to a connection point between the bus capacitor C1 and the bus capacitor C2, the I-type NPC three-level bridge arm is connected between the DC input terminals and connected to the automatic equalization circuit, and the output filter is connected to a voltage output terminal of the I-type NPC three-level bridge arm and to a connection point between the bus capacitor C1 and the bus capacitor C2;

[0011] The automatic balancing circuit includes a power device IGBT5, a power device IGBT6, a transformer TR1, a capacitor C3 and a capacitor C4. The power device IGBT5, the N2 winding of the transformer TR1, the capacitor C3, the capacitor C4, the N3 winding of the transformer TR1 and the power device IGBT6 are sequentially connected in series and connected between the DC input terminals, wherein the power device IGBT5 is connected to the same-name end of the N2 winding of the transformer TR1, the other end of the N2 winding of the transformer TR1 is connected to the capacitor C3, the power device IGBT6 is connected to the same-name end of the N3 winding of the transformer TR1, and the other end of the N3 winding of the transformer TR1 is connected to the capacitor C4; the same-name end of the N1 winding of the transformer TR1 is connected to the connection point of the capacitor C3 and the capacitor C4, the other end of the N1 winding of the transformer TR1 is connected to the I-type NPC three-level bridge arm, and the connection point of the capacitor C3 and the capacitor C4 is connected to the connection point of the bus capacitor C1 and the bus capacitor C2;

[0012] Among them, the power device IGBT5 and the power device IGBT6 are both provided with anti-parallel freewheeling diodes.

[0013] In the I-type three-level bus midpoint voltage automatic balancing circuit in the converter, the bus capacitor C1 and the bus capacitor C2 have the same capacitance value, and the capacitor C3 and the capacitor C4 have the same capacitance value; the capacitance value of the capacitor C3 and the capacitor C4 is greater than or equal to 1 / 10 of the capacitance value of the bus capacitor C1 and the bus capacitor C2 and less than or equal to 1 / 5 of the capacitance value of the bus capacitor C1 and the bus capacitor C2.

[0014] In the I-type three-level busbar midpoint voltage automatic balancing circuit in the converter, the inductance of the N1 winding of the transformer TR1 is less than or equal to 1 / 20 of the inductance of the filter inductor in the output filter.

[0015] Based on the research and application of the I-type three-level circuit topology with the midpoint clamped by the diode, the bus capacitor midpoint potential automatic balancing circuit proposed in the embodiment of the present invention is composed of only five devices, namely, a transformer TR1, two capacitors C1 and C2, and two switch devices Q5 and Q6. A reasonable design is performed without the need for complex peripheral control circuits and control algorithms. In each PWM modulation working cycle of the I-type three-level inverter device, the bus capacitor midpoint potential is automatically adjusted in real time, so that the voltages of the upper and lower bus capacitors connected in series are automatically balanced, ensuring that the output waveform of the I-type three-level inverter is more sinusoidal and symmetrical, the DC component is smaller, and the machine output performance is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a topological diagram of the hardware circuit for automatic equalization of the midpoint voltage of the I-type three-level bus capacitor in the present invention;

[0017] Figure 2 It is a working principle diagram of the second stage of the I-type three-level bus capacitor midpoint voltage automatic balancing hardware circuit topology in the present invention;

[0018] Figure 3 It is a working principle diagram of the third stage of the I-type three-level bus capacitor midpoint voltage automatic balancing hardware circuit topology in the present invention;

[0019] Figure 4 It is a working principle diagram of the fifth stage of the I-type three-level bus capacitor midpoint voltage automatic balancing hardware circuit topology in the present invention;

[0020] Figure 5 It is a working principle diagram of the sixth stage of the I-type three-level bus capacitor midpoint voltage automatic balancing hardware circuit topology in the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0022] The present invention mainly aims at the problem of unbalanced bus capacitor midpoint voltage during operation when the DC / AC inverter device or functional module in the power electronic converter adopts a diode midpoint clamped I-type three-level topology, and the application field mainly involves power electronic converter products in various industries.

[0023] The application method is as follows: based on the I-type three-level circuit topology with diode midpoint clamping, the present invention proposes a reliable and practical automatic balancing circuit for dynamically adjusting the bus capacitor midpoint potential, which can dynamically balance the bus capacitor midpoint voltage in real time during the operation of the I-type three-level inverter or functional module, so as to achieve a more symmetrical DC / AC output positive and negative half-cycle waveform.

[0024] The specific implementation of the present invention is described in detail below in conjunction with specific embodiments:

[0025] An I-type three-level bus midpoint voltage automatic equalization circuit in a converter comprises: an input soft-start device, a series branch consisting of a bus capacitor C1 and a bus capacitor C2 connected in series, an automatic equalization circuit, an I-type NPC three-level bridge arm and an output filter; a DC input terminal is connected to the input soft-start device, the series branch is connected in parallel between the DC input terminals, the automatic equalization circuit is connected between the DC input terminals and connected to a connection point between the bus capacitor C1 and the bus capacitor C2, the I-type NPC three-level bridge arm is connected between the DC input terminals and connected to the automatic equalization circuit, and the output filter is connected to a voltage output terminal of the I-type NPC three-level bridge arm and to a connection point between the bus capacitor C1 and the bus capacitor C2;

[0026] The automatic balancing circuit includes a power device IGBT5, a power device IGBT6, a transformer TR1, a capacitor C3 and a capacitor C4. The power device IGBT5, the N2 winding of the transformer TR1, the capacitor C3, the capacitor C4, the N3 winding of the transformer TR1 and the power device IGBT6 are sequentially connected in series and connected between the DC input terminals, wherein the power device IGBT5 is connected to the same-name end of the N2 winding of the transformer TR1, the other end of the N2 winding of the transformer TR1 is connected to the capacitor C3, the power device IGBT6 is connected to the same-name end of the N3 winding of the transformer TR1, and the other end of the N3 winding of the transformer TR1 is connected to the capacitor C4; the same-name end of the N1 winding of the transformer TR1 is connected to the connection point of the capacitor C3 and the capacitor C4, the other end of the N1 winding of the transformer TR1 is connected to the I-type NPC three-level bridge arm, and the connection point of the capacitor C3 and the capacitor C4 is connected to the connection point of the bus capacitor C1 and the bus capacitor C2;

[0027] Among them, the power device IGBT5 and the power device IGBT6 are both provided with anti-parallel freewheeling diodes.

[0028] When a diode-clamped I-type three-level DC / AC inverter device or functional module is in operation, the unbalanced midpoint voltage of the DC-side bus capacitor causes asymmetry of the upper and lower bus voltages, resulting in inverter output waveform distortion, large DC component and other problems. Based on the diode-clamped I-type three-level circuit topology, the present invention proposes a reliable and practical automatic balancing circuit for dynamically adjusting the midpoint potential of the bus capacitor, so as to achieve more symmetric positive and negative half-cycle waveforms of the I-type three-level inverter output.

[0029] The busbar capacitor midpoint potential automatic balancing circuit topology proposed by the present invention is as follows: Figure 1 The dotted box shows the Figure 1 From the circuit topology, it can be seen that the input soft start device is composed of switches S1, S2 and resistor R1, and the I-type NPC three-level bridge arm is composed of power devices IGBT1, IGBT2, IGBT3, IGBT4 and diodes D1, D2; the output filter is composed of inductor Lo and capacitor Co; bus capacitors C1 and C2 are connected in series and then in parallel at the DC input end, and the connection point of C1 and C2 provides a midpoint voltage DCN, which is connected to one end of the output filter capacitor Co; the bus capacitor midpoint potential automatic equalization circuit is composed of power switch devices IGBT5 and IGBT6, transformer TR1, capacitors C3 and C4, among which power devices IGBT1, IGBT2, IGBT3, IGBT4, IGBT5 and IGBT6 are all equipped with anti-parallel freewheeling diodes. From the perspective of topological structure, the circuit has the advantages of simple topology, convenient implementation, no need for software control, and high working reliability.

[0030] In the present invention, in order to make the bus capacitor midpoint potential automatic equalization circuit not have a greater impact on the original diode midpoint clamped I-type three-level circuit topology during PWM modulation, the inductance of the transformer TR1 N1 winding is less than or equal to 1 / 20 (one twentieth) of the inductance of the filter inductor Lo, the bus capacitor C1 and the bus capacitor C2 have the same capacitance value, and the capacitor C3 and the capacitor C4 have the same capacitance value; the capacitance of the capacitor C3 and the capacitor C4 is greater than or equal to 1 / 10 (one tenth) of the capacitance of the bus capacitor C1 and the bus capacitor C2 and less than or equal to 1 / 5 (one fifth) of the capacitance of the bus capacitor C1 and the bus capacitor C2. The specific design parameters of the transformer TR1 and the capacitor C3 / C4 need to be reasonably designed according to the product rated power / voltage / current.

[0031] The specific working process of the I-type three-level inverter bus capacitor midpoint voltage automatic balancing circuit proposed by the present invention is as follows:

[0032] First, under the premise that the auxiliary control low-voltage electricity works normally, the software of the I-type three-level inverter device or functional module detects that there are no faults in each input signal. After the input high-voltage electricity part completes the soft start, IGBT5 and IGBT6 are closed in sequence to ensure that the voltages VC3 and VC4 on C3 and C4 are fully charged to Vin / 2 respectively, and then IGBT5 and IGBT6 are closed to prepare for the startup of the machine.

[0033] According to the working characteristics of the switch combination of the I-type three-level inverter topology power device, within one working cycle of the DC / AC inverter, the working process of the bus capacitor midpoint voltage automatic balancing circuit proposed in the present invention can be roughly divided into six stages.

[0034] The first stage: IGBT1 and IGBT2 are turned on, and IGBT3 and IGBT4 are turned off. The voltage on the bus capacitor C1 corresponding to the upper half bridge arm passes through the power devices IGBT1 and IGBT2, outputs a positive voltage of Vin / 2, and after passing through the filter inductor Lo and the filter capacitor Co, provides a positive half-cycle output of the Vo sinusoidal voltage. In this stage, the voltage on the bus capacitor C1 will decrease due to the load condition, causing an imbalance in the bus midpoint potential. At this time, since the current changes on each winding of the transformer TR1 are very small, it can be ideally assumed that the bus capacitor midpoint voltage automatic balancing circuit does not participate in the work.

[0035] The second stage: IGBT1 and IGBT4 are turned off, and IGBT2 and IGBT3 are turned on. At this time, the current Io on the filter inductor completes the switch from the first stage loop to the second stage loop, and Io continues to flow, such as Figure 2 shown.

[0036] In loop 1, the current Io on the filter inductor passes through the transformer TR1 N1 winding, the clamping diode D1, the power device IGBT2, its own filter inductor Lo and the filter capacitor Co, and continues to provide a positive half-cycle sinusoidal current for the output power supply Vo.

[0037] In this stage, the current flowing through the N1 winding of transformer TR1 changes greatly, and the voltage generated on the N1 winding is also large. According to the working principle of the same-name ends of multiple windings of the transformer, large voltages are also generated on the N2 and N3 windings.

[0038] In loop 2, a voltage VN2 with positive top and negative bottom is generated on the N2 winding of transformer TR1. After being superimposed on the voltage on VC3, this voltage can charge the bus capacitor C1 through the anti-parallel diode of IGBT5.

[0039] During this stage, since a voltage VN3 with a negative top and a positive bottom is generated on the N3 winding of the transformer TR1, the power device IGBT6 does not participate in the work due to the blocking effect of the anti-parallel diode.

[0040] The third stage: the switching transition process between IGBT2 and IGBT4. In this stage, when the current Io on the filter inductor is zero, it normally enters the fourth stage.

[0041] When the current Io on the filter inductor is not zero, three loops will be generated, such as Figure 3 shown.

[0042] In loop 1, the transformer TR1 N1 winding continues to flow, and the bus capacitor C1 is charged through the clamping diode D1 and the parasitic capacitance of IGBT1.

[0043] In loop 2, a voltage VN3 with positive top and negative bottom is induced on the N3 winding of transformer TR1. After being superimposed on the voltage on VC4, this voltage can charge the bus capacitor C2 through the anti-parallel diode of IGBT6.

[0044] In loop 3, bus capacitor C2, IGBT4, and IGBT3 provide a freewheeling loop to enable the filter inductor current Io to complete zero crossing as quickly as possible. The voltage on the bus capacitor C2 will also slightly decrease due to external output during this stage.

[0045] During this stage, due to the joint action of loop 1, loop 2 and loop 3, the voltages at both ends of VC1 and VC2 are finally restored to Vin / 2, achieving a balance between the midpoint potentials DCN of the upper and lower bus capacitors, preparing for the next stage of inversion to produce a better waveform.

[0046] In this stage, Uo is a negative voltage of -Vin / 2.

[0047] The fourth stage: IGBT1 and IGBT2 are turned off, and IGBT3 and IGBT4 are turned on. The voltage on the bus capacitor C1 corresponding to the upper half bridge arm passes through the power devices IGBT3 and IGBT4, outputs a negative voltage of -Vin / 2, and provides a positive half-cycle output of the Vo sinusoidal voltage after passing through the filter inductor Lo and the filter capacitor Co. In this stage, the voltage on the bus capacitor C2 will decrease due to the load condition, causing an unbalanced potential at the bus midpoint. At this time, since the current changes on each winding of the transformer TR1 are very small, it can also be ideally considered that the bus capacitor midpoint voltage automatic balancing circuit does not participate in the work.

[0048] The fifth stage: IGBT1 and IGBT4 are turned off, and IGBT2 and IGBT3 are turned on. At this time, the current Io on the filter inductor completes the switch from the fourth stage loop to the fifth stage, and the Io loop is freewheeling, such as Figure 4 shown.

[0049] In loop 1, the current Io on the filter inductor passes through IGBT3, clamping diode D1, transformer TR1N1 winding, its own filter inductor Lo and filter capacitor Co, and continues to provide negative half-cycle sinusoidal current for the output Vo.

[0050] In this stage, the current flowing through the N1 winding of transformer TR1 changes greatly, and the voltage generated on the N1 winding is also large. According to the working principle of the same-name ends of multiple windings of the transformer, large voltages are also generated on the N2 and N3 windings.

[0051] In loop 2, a voltage VN3 with a positive top and a negative bottom is generated on the N3 winding of transformer TR1. This voltage is superimposed on the voltage on VC4 to charge the bus capacitor C2.

[0052] During this stage, since a voltage VN2 with a negative top and a positive bottom is generated on the N2 winding of the transformer TR1, the power device IGBT5 does not participate in the work due to the blocking effect of the anti-parallel diode.

[0053] The sixth stage: IGBT1 and IGBT3 switching transition process. In this stage, when the current Io on the filter inductor is zero, it normally enters the next stage.

[0054] When the current Io on the filter inductor is not zero, three loops will be generated, such as Figure 5 shown.

[0055] In loop 1, the transformer TR1 N1 winding continues to flow, and the bus capacitor C2 is charged through the clamping diode D2 and the parasitic capacitance of IGBT4.

[0056] In loop 2, a voltage VN2 with positive top and negative bottom is induced on the N2 winding of transformer TR1. After being superimposed on the voltage on VC3, this voltage can charge the bus capacitor C1 through the anti-parallel diode of IGBT5.

[0057] In loop 3, bus capacitor C1, IGBT2, and IGBT1 provide a freewheeling loop to enable the filter inductor current Io to complete zero crossing as quickly as possible. The voltage on bus capacitor C1 will also slightly decrease due to external output at this stage.

[0058] During this stage, due to the joint action of loop 1, loop 2 and loop 3, the voltages at both ends of VC1 and VC2 are finally restored to Vin / 2, achieving a balance between the midpoint potentials DCN of the upper and lower bus capacitors, preparing for the next stage of inversion to produce a better waveform.

[0059] In this stage, Uo is a positive voltage of Vin / 2.

[0060] The bus capacitor midpoint potential automatic balancing circuit proposed in the present invention is composed of only five devices, namely, a transformer TR1, two capacitors C1 and C2, and two switch devices Q5 and Q6. It is reasonably designed without complex peripheral control circuits and control algorithms. In each PWM modulation working cycle of the I-type three-level inverter device, the bus capacitor midpoint potential is automatically adjusted in real time, so that the voltages of the upper and lower bus capacitors connected in series are automatically balanced, ensuring that the I-type three-level inverter output waveform is more sinusoidal and symmetrical, the DC component is smaller, and the machine output performance is better.

[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An I-type three-level busbar midpoint voltage automatic balancing circuit in a converter, characterized in that: include: An input soft-start device, a series branch consisting of a bus capacitor C1 and a bus capacitor C2 connected in series, an automatic balancing circuit, an I-type NPC three-level bridge arm, and an output filter; the DC input end is connected to the input soft-start device, the series branch is connected in parallel between the DC input ends, the automatic balancing circuit is connected between the DC input ends and connected to the connection point of the bus capacitor C1 and the bus capacitor C2, the I-type NPC three-level bridge arm is connected between the DC input ends and connected to the automatic balancing circuit, and the output filter is connected to the voltage output end of the I-type NPC three-level bridge arm, and connected to the connection point of the bus capacitor C1 and the bus capacitor C2; The automatic balancing circuit includes a power device IGBT5, a power device IGBT6, a transformer TR1, a capacitor C3 and a capacitor C4. The power device IGBT5, the N2 winding of the transformer TR1, the capacitor C3, the capacitor C4, the N3 winding of the transformer TR1 and the power device IGBT6 are sequentially connected in series and connected between the DC input terminals, wherein the power device IGBT5 is connected to the same-name end of the N2 winding of the transformer TR1, the other end of the N2 winding of the transformer TR1 is connected to the capacitor C3, the power device IGBT6 is connected to the same-name end of the N3 winding of the transformer TR1, and the other end of the N3 winding of the transformer TR1 is connected to the capacitor C4; the same-name end of the N1 winding of the transformer TR1 is connected to the connection point of the capacitor C3 and the capacitor C4, the other end of the N1 winding of the transformer TR1 is connected to the I-type NPC three-level bridge arm, and the connection point of the capacitor C3 and the capacitor C4 is connected to the connection point of the bus capacitor C1 and the bus capacitor C2; Among them, the power device IGBT5 and the power device IGBT6 are both provided with anti-parallel freewheeling diodes; Wherein, the inductance of the N1 winding of the transformer TR1 is less than or equal to 1 / 20 of the inductance of the filter inductor in the output filter; Among them, the bus capacitor C1 and the bus capacitor C2 have the same capacitance value, and the capacitor C3 and the capacitor C4 have the same capacitance value; the capacitance value of the capacitor C3 and the capacitor C4 is greater than or equal to 1 / 10 of the capacitance value of the bus capacitor C1 and the bus capacitor C2 and less than or equal to 1 / 5 of the capacitance value of the bus capacitor C1 and the bus capacitor C2.

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