Semiconductor device package and method for manufacturing the same

Abstract

Provided is a semiconductor device package, which includes a substrate, a semiconductor device, and an alignment structure. The semiconductor device and the alignment structure are disposed on the substrate. The alignment structure is in direct contact with the semiconductor device.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same. Background Art

[0002] Techniques (such as placement techniques, bonding techniques, etc.) are used to manufacture semiconductor device packages. In the trend of miniaturization, the accuracy of placement or bonding will become relatively important.

[0003] Due to mechanical tolerances, optical tolerances, etc., deviations occur when placing or bonding components to a semiconductor device onto a carrier.

[0004] In addition, structural limitations (such as size) of manufacturing tools or equipment may impede the miniaturization of semiconductor device packages. Summary of the Invention

[0005] Some embodiments of the present application provide a semiconductor device package, which includes a substrate, a first semiconductor device, and a first alignment structure. The first semiconductor device is disposed on the substrate. The first alignment structure is disposed on the substrate. The first alignment structure is in direct contact with the first semiconductor device.

[0006] Some embodiments of the present application provide a semiconductor device package, which includes a substrate, a first semiconductor device, a first conductive structure disposed on the substrate, a first conductive structure disposed on the semiconductor device, and a connecting element. The connecting element is disposed between the first conductive structure on the substrate and the first conductive structure on the semiconductor device. The first connecting element has a relatively large volume at a first side.

[0007] Some embodiments of the present application provide a method of manufacturing a semiconductor device package. The method includes providing a substrate on which a first conductive structure is disposed. The method further includes forming a first alignment structure on the substrate. The method further includes supplying a fluid onto the substrate. The method further includes placing a first semiconductor device having a first conductive structure on the fluid. Brief Description of the Drawings

[0008] Aspects of the present disclosure can be more readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of discussion.

[0009] Figure 1A Illustrates a top view of a semiconductor device package according to some embodiments of the present application.

[0010] Figure 1BIllustrate a cross-sectional view of a semiconductor device package according to some embodiments of the present application.

[0011] Figure 1C Illustrate a cross-sectional view of a semiconductor device package according to some embodiments of the present application.

[0012] Figure 1D Illustrate a cross-sectional view of a semiconductor device package according to some embodiments of the present application.

[0013] Figure 1E Illustrate a cross-sectional view of a semiconductor device package according to some embodiments of the present application.

[0014] Figure 1F Illustrate a cross-sectional view of a semiconductor device package according to some embodiments of the present application.

[0015] Figure 2A Illustrate a partial enlarged view of a dotted-line circle C1 as shown in Figure 1B according to some embodiments of the present application.

[0016] Figure 2B Illustrate a partial enlarged view of a structure that may replace the structure shown in Figure 2A according to some embodiments of the present application.

[0017] Figure 2C Illustrate a partial enlarged view of a dotted-line circle C2 as shown in Figure 1B according to some embodiments of the present application.

[0018] Figure 2D Illustrate a partial enlarged view of a dotted-line circle C3 as shown in Figure 1B according to some embodiments of the present application.

[0019] Figure 2E Illustrate a partial enlarged view of a dotted-line circle C4 as shown in Figure 1B according to some embodiments of the present application.

[0020] Figure 2F Illustrate a partial enlarged view of a dotted-line circle C4 as shown in Figure 1B according to some embodiments of the present application.

[0021] Figure 2G Illustrate a partial enlarged view of a dotted-line circle C4 as shown in Figure 1B according to some embodiments of the present application.

[0022] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E ,Figure 3F , Figure 3G and Figure 3H describe operations for manufacturing a substrate according to some embodiments of the present application.

[0023] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M , Figure 4N and Figure 4O describe operations for manufacturing a semiconductor device package according to some embodiments of the present application.

[0024] Figure 5A and Figure 5B describe various types of semiconductor device packages according to some embodiments of the present application.

[0025] Figure 6A describe a cross-sectional view of a semiconductor device package according to some embodiments of the present application.

[0026] Figure 6B describe operations for placing a semiconductor device according to some embodiments of the present application.

[0027] Figure 6C describe, according to some embodiments of the present application, an enlarged view of a part of the dotted circle C5 shown in Figure 6B .

[0028] Like reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0029] Embodiments of the present disclosure and their uses are discussed in detail below. However, it should be understood that the embodiments illustrate many applicable concepts that can be embodied in a wide variety of specific contexts. It should be understood that the following disclosure provides many different embodiments or examples for implementing various features of the embodiments. Specific examples of components and arrangements are described below for purposes of discussion. Of course, these are only examples and are not intended to be limiting.

[0030] Spatial descriptions, including terms such as "above", "below", "upward", "left", "right", "downward", "top", "bottom", "vertical", "horizontal", "side", "higher", "lower", "upper", "on top", "beneath", etc., are used herein relative to the orientation shown in the corresponding figures, unless otherwise specified. It should be understood that the spatial descriptions used herein are for illustrative purposes, and the actual implementation of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not prejudiced by such an arrangement.

[0031] Specific language is used below to disclose the embodiments or examples illustrated in the figures. However, it will be understood that the embodiments and examples are not intended to be limiting. As would be commonly thought by those of ordinary skill in the relevant art, any changes and transformations of the disclosed embodiments and any further applications of the principles disclosed in this document fall within the scope of the present disclosure.

[0032] Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed herein.

[0033] Figure 1A Shows a top view of a semiconductor device package according to some embodiments of the present application.

[0034] Reference Figure 1A , the semiconductor device package 1a includes semiconductor devices 151, 152 and alignment structures 161, 162. It is contemplated Figure 1A For simplicity, only the layout of the semiconductor devices and the alignment structures is illustrated, and the structure of the semiconductor device package 1a will be further detailed in the accompanying Figure 1B described below.

[0035] Figure 1A The semiconductor devices not indicated in Figure 1A may be the same as or similar to semiconductor device 151 or semiconductor device 152. The semiconductor devices not indicated in

[0036] Figure 1A may be different from semiconductor device 151 or semiconductor device 152. The semiconductor devices 151 and 152 may include, for example but not limited to, semiconductor dies (or chips) in which circuits are integrated, etc. The size of semiconductor device 151 may be different from the size of semiconductor device 152. Semiconductor device 151 may be different from semiconductor device 152. In some other embodiments of the present application, semiconductor device 151 may be the same as or similar to semiconductor device 152. Figure 1AAlignment structures not indicated in the text may be different from alignment structure 161 or alignment structure 162. An alignment structure (e.g., 161) may define a space, cavity, or chamber for accommodating a semiconductor device (e.g., 151). Some alignment structures may be formed as a single piece. One alignment structure may be separated from another alignment structure by a certain distance or space. One alignment structure may be independent of another alignment structure. One alignment structure (e.g., 161) may be the same as or similar to another alignment structure (e.g., 162). One alignment structure may be different from another alignment structure.

[0037] Alignment structure 161 may have a rectangular shape, etc. Similarly, alignment structure 162 may have a rectangular shape, etc.

[0038] Alignment structure 161 encloses semiconductor device 151. Alignment structure 161 is in direct contact with semiconductor device 151. Side s1 of alignment structure 161 is in direct contact with side s2 of semiconductor device 151. Side s3 of alignment structure 161 is in direct contact with side s4 of semiconductor device 151. Side s1 of alignment structure 161 is adjacent to side s3 of alignment structure 161. Side s2 of semiconductor device 151 is adjacent to side s4 of semiconductor device 151.

[0039] Alignment 161 has corners cor1, cor2, cor3, cor4. Semiconductor device 151 is placed adjacent to corner cor1. Semiconductor device 151 is in direct contact with corner cor1. Corner cor1 is opposed to corner cor2. Corner cor1 is opposed to corner cor3. Corner cor1 is opposed to corner cor4.

[0040] Alignment structure 162 encloses semiconductor device 152. Alignment structure 162 is in direct contact with semiconductor device 152. Side s5 of alignment structure 162 is in direct contact with side s6 of semiconductor device 152. Another side s7 of alignment structure 162 is in direct contact with another side s8 of semiconductor device 152. Side s5 of alignment structure 162 is adjacent to side s7 of alignment structure 162. Side s6 of semiconductor device 152 is adjacent to side s8 of semiconductor device 152.

[0041] Alignment 162 has corners cor5, cor6, cor7, cor8. Semiconductor device 152 is placed adjacent to corner cor5. Semiconductor device 152 is in direct contact with corner cor5. Corner cor5 is opposed to corner cor2. Corner cor5 is opposed to corner cor6. Corner cor5 is opposed to corner cor7. Corner cor5 is opposed to corner cor8. Although not described, it is contemplated that semiconductor device package 1a may include more alignment structures.

[0042] As Figure 1AEach semiconductor device shown therein is disposed at the same corner of the alignment structure (e.g., the lower left corner as shown in Figure 1A ).

[0043] Figure 1B Illustrates a cross-sectional view of a semiconductor device package 1a taken across line AA' as shown in Figure 1A according to some embodiments of the present application.

[0044] Referring to Figure 1B , the semiconductor device package 1a includes connection elements 10 and 131; a substrate 11; conductive structures 12p1 and 141; layers 12m1 and 18v1; seals 17 and 19; semiconductor devices 151, 152, and 153; and alignment structures 161, 162, and 163.

[0045] The substrate 11 may include circuitry therein and / or thereon ( Figure 1B not shown). The substrate 11 may include conductive traces ( Figure 1B not shown). The substrate 11 may include conductive pads ( Figure 1B not shown). The substrate 11 may include semiconductor material. The substrate 11 may include conductive material. The substrate 11 may include insulating material (e.g., dielectric material). The substrate 11 may include a redistribution (RDL) structure. The substrate 11 may include ceramic, bismaleimide triazine (BT), FR4, prepreg (PP), or other suitable material. The substrate 11 may include light-blocking material.

[0046] The substrate 11 may include conductive vias 12v1. The conductive vias 12v1 may include conductive material, such as but not limited to copper or other suitable material.

[0047] The connection element 10 is disposed on the substrate 11. The connection element 10 is disposed on the conductive via 12v1. The connection element 10 may include an alloy of gold and solder. The connection element 10 may include an alloy of silver and solder. The connection element 10 may include solder, copper, or other suitable material.

[0048] The semiconductor device 153 is disposed on the substrate 11. The semiconductor device 153 may include, for example but not limited to, a semiconductor die (or chip) having circuitry integrated therein, and so on.

[0049] The alignment structure 163 is disposed on the substrate 11. The alignment structure 163 is in direct contact with the semiconductor device 153. The side s10 of the alignment structure 163 is in direct contact with the side s9 of the semiconductor device 153. The alignment structure 163 may include, for example but not limited to, an optically curable material.

[0050] The conductive structure 12p1 is disposed on the substrate 11. The conductive structure 12p1 is disposed on the conductive via 12v1. The conductive via 12v1 may be, for example but not limited to, a conductive pad.

[0051] The conductive structure 12p1 is disposed on the conductive via 12v1. The layer 12m1 is disposed on the conductive structure 12p1. The layer 12m1 may include a barrier layer. The conductive structure 141 is disposed under the semiconductor device 153.

[0052] The conductive structure 12p1 may be, for example but not limited to, a conductive pad. The conductive structure 141 may be, for example but not limited to, a conductive pillar.

[0053] The connecting element 131 is disposed between the conductive structure 141 and the layer 12m1. The semiconductor device 153 is electrically connected to the connecting element 10 via the conductive structures 12p1, 141; the connecting element 131; the layer 12m1 and the conductive via 12v1.

[0054] The connecting element 131 has an asymmetric structure. One side of the connecting element 131 has a relatively larger volume. The connecting element 131 has a larger volume on the side relatively closer to or adjacent to the alignment structure 163. The connecting element 131 has a larger volume on the side s10 relatively closer to or adjacent to the alignment structure 163. The connecting element 131 has a larger volume on the side relatively closer to or adjacent to the side ( Figure 1B not indicated in the figure) adjacent to the side s10 of the alignment structure 163. The connecting element 131 has a larger volume on the side relatively closer to or adjacent to the corner ( Figure 1B not indicated in the figure) of the alignment structure 163. The connecting element 131 has a larger volume on the side relatively closer to or adjacent to the corner of the alignment structure 163, and the corner is the intersection of two sides of the alignment structure 163.

[0055] The connecting element 10 may be, for example but not limited to, a ball-shaped connecting element. The connecting element 131 may include an alloy of gold and solder. The connecting element 131 may include an alloy of silver and solder.

[0056] The sealant 17 is disposed on the substrate 11. The sealant 17 covers the semiconductor device 153. The sealant 17 covers the alignment structure 163. The sealant 17 covers the substrate 11. The sealant 17 may include epoxy resin. The sealant 17 may include fillers or particles.

[0057] The layer 18v1 is disposed on the sealant 17. Although not described, it is contemplated that the conductive vias may be patterned to provide electrical connections.

[0058] The semiconductor device 151 is disposed on the seal 17. The semiconductor device 151 may include, for example but not limited to, a semiconductor die (or chip) in which a circuit is integrated, and so on. The conductive layer 151a is disposed on the semiconductor device 151.

[0059] The alignment structure 161 is disposed on the seal 17. The alignment structure 161 is in direct contact with the semiconductor device 151. The side surface s1 of the alignment structure 161 is in direct contact with the side surface s2 of the semiconductor device 151.

[0060] The semiconductor device 152 is disposed on the seal 17. The semiconductor device 152 may include, for example but not limited to, a semiconductor die (or chip) in which a circuit is integrated, and so on.

[0061] The alignment structure 162 is disposed on the seal 17. The alignment structure 162 is in direct contact with the semiconductor device 152. The side surface s5 of the alignment structure 162 is in direct contact with the side surface s6 of the semiconductor device 152. The alignment structure 162 may include, for example but not limited to, an optically curable material.

[0062] The side surface s1 of the alignment structure 161 and the side surface s5 of the alignment structure 162 face the same direction. The side surface s2 of the semiconductor device 151 and the side surface s6 of the semiconductor device 152 face the same direction.

[0063] The connection element ( Figure 1B not indicated in the figure) is disposed between the semiconductor device 151 and the seal 17 and has an asymmetric shape. One side surface of the connection element has a relatively larger volume. The connection element has a larger volume on the side surface relatively close to or adjacent to the alignment structure 161. The connection element has a larger volume on the side surface relatively close to or adjacent to the side surface s1 of the alignment structure 161. The connection element has a larger volume on the side surface relatively close to or adjacent to the side surface s3 (as Figure 1A shown in the figure) adjacent to the side surface s1 of the alignment structure 161 or on the side surface adjacent thereto. The connection element has a larger volume on the side surface relatively close to or adjacent to the corner cor1 (as Figure 1A shown in the figure) of the alignment structure 161 or on the side surface adjacent thereto. The connection element has a larger volume on the side surface relatively close to or adjacent to the corner cor1 of the alignment structure 161, and the corner cor1 is the intersection of the two side surfaces s1 and s3 of the alignment structure 161.

[0064] In some embodiments, the distance D1 between the semiconductor devices 151 and 152 may be less than 2 mm. In some embodiments, the distance D1 between the semiconductor devices 151 and 152 may be less than 1 mm.

[0065] The seal 19 is disposed on the seal 17. The seal 19 covers the seal 17. The seal 19 covers the semiconductor device 151. The seal 19 covers the semiconductor device 152. The seal 19 covers the alignment structure 161. The seal 19 covers the alignment structure 162.

[0066] Figure 1C Illustrate a cross-sectional view of a semiconductor device package 1b according to some embodiments of the present application.

[0067] Reference Figure 1C , the semiconductor device package 1b is similar to the semiconductor device package 1a, except that the connection element 10 of the semiconductor device 1a is replaced by the connection element 10b of the semiconductor device package 1b.

[0068] The connection element 10b may be, for example but not limited to, a bump-type connection element. The connection element 10b is electrically connected to the semiconductor device 153.

[0069] Figure 1D Illustrate a cross-sectional view of a semiconductor device package 1c according to some embodiments of the present application.

[0070] Reference Figure 1D , the semiconductor device package 1c includes a connection element 10; a substrate 11; a conductive via 12v1; a conductive structure 18c; a layer 18m1; an adhesive layer 154a; a conductive layer 154c; semiconductor devices 151, 152, 154; alignment structures 161, 162, 163 and seals 17, 19.

[0071] The substrate 11 may include a circuit therein and / or thereon ( Figure 1D not shown in). The substrate 11 may include conductive traces ( Figure 1D not shown in). The substrate 11 may include conductive pads ( Figure 1D not shown in). The substrate 11 may include semiconductor material. The substrate 11 may include conductive material. The substrate 11 may include insulating material (such as a dielectric material). The substrate 11 may include an RDL structure. The substrate 11 may include ceramic, bismaleimide triazine (BT), FR4, prepreg (PP) or other suitable materials. The substrate 11 may include light-blocking material.

[0072] The substrate 11 may include a conductive via 12v1. The conductive via 12v1 may be filled with a conductive material, such as but not limited to copper or other suitable materials.

[0073] The connection element 10 is disposed under the substrate 11. The connection element 10 is disposed under the conductive via 12v1. The connection element 10 may include an alloy of gold and solder. The connection element 10 may include an alloy of silver and solder. The connection element 10 may include solder, copper or other suitable materials.

[0074] The semiconductor device 154 is disposed on the substrate 11. The semiconductor device 154 is disposed on the adhesive layer 154a. The conductive layer 154c of the semiconductor device 154 is in direct contact with the adhesive layer 154a.

[0075] The semiconductor device 154 may include, for example but not limited to, a semiconductor die (or chip) in which a circuit is integrated, and so on. The connecting element 131 may include solder, copper, or other suitable materials.

[0076] The alignment structure 163 is disposed on the substrate 11. The alignment structure 163 is in direct contact with the semiconductor device 154. The side surface s10 of the alignment structure 163 is in direct contact with the side surface s9 of the semiconductor device 154. The alignment structure 163 may include, for example but not limited to, an optically curable material.

[0077] The sealant 17 is disposed on the substrate 11. The sealant 17 covers the semiconductor device 154. The sealant 17 covers the alignment structure 163. The sealant 17 covers the substrate 11. The sealant 17 may include an epoxy resin. The sealant 17 may include fillers or particles.

[0078] The conductive structure 18c is disposed on the semiconductor device 154. The conductive structure 18c is surrounded by the sealant 17. The layer 18m1 is disposed on the sealant 17. The conductive structure 18c and the layer 18m1 provide electrical connection for the semiconductor device 154.

[0079] The semiconductor device 151 is disposed on the sealant 17. The semiconductor device 151 may include, for example but not limited to, a semiconductor die (or chip) in which a circuit is integrated, and so on. The semiconductor device 151 is electrically connected to the semiconductor device 154.

[0080] The alignment structure 161 is disposed on the sealant 17. The alignment structure 161 is in direct contact with the semiconductor device 151. The side surface s1 of the alignment structure 161 is in direct contact with the side surface s2 of the semiconductor device 151.

[0081] The semiconductor device 152 is disposed on the sealant 17. The semiconductor device 152 may include, for example but not limited to, a semiconductor die (or chip) in which a circuit is integrated, and so on. The semiconductor device 152 is electrically connected to the semiconductor device 154.

[0082] The alignment structure 162 is disposed on the sealant 17. The alignment structure 162 is in direct contact with the semiconductor device 152. The side surface s5 of the alignment structure 162 is in direct contact with the side surface s6 of the semiconductor device 152. The alignment structure 162 may include, for example but not limited to, an optically curable material.

[0083] The side s1 of the alignment structure 161 and the side s5 of the alignment structure 162 face the same direction. The side s2 of the semiconductor device 151 and the side s6 of the semiconductor device 152 face the same direction.

[0084] A connecting element ( Figure 1D not indicated in the figure) is disposed between the semiconductor device 151 and the sealant 17 and has an asymmetric shape. One side of the connecting element has a relatively larger volume. The connecting element has a larger volume on the side relatively closer to or adjacent to the alignment structure 161. The connecting element has a larger volume on the side relatively closer to or adjacent to the side s1 of the alignment structure 161. The connecting element has a larger volume on the side relatively closer to the side s3 (as Figure 1A shown in the figure) adjacent to the side s1 of the alignment structure 161 or on the side adjacent thereto. The connecting element has a larger volume on the side relatively closer to the corner cor1 (as Figure 1A shown in the figure) of the alignment structure 161 or on the side adjacent thereto. The connecting element has a larger volume on the side relatively closer to the corner cor1 of the alignment structure 161 or on the side adjacent thereto, and the corner cor1 is the intersection of the two sides s1 and s3 of the alignment structure 161.

[0085] The distance D1 between the semiconductor devices 151 and 152 may be less than 2 mm.

[0086] A sealant 19 is disposed on the sealant 17. The sealant 19 covers the sealant 17. The sealant 19 covers the semiconductor device 151. The sealant 19 covers the semiconductor device 152. The sealant 19 covers the alignment structure 161. The sealant 19 covers the alignment structure 162.

[0087] Figure 1E A cross-sectional view of a semiconductor device package 1d according to some embodiments of the present application is illustrated.

[0088] Referring Figure 1E to the figure, a semiconductor device package 1d having a single layer is provided. The semiconductor device package 1d includes connecting elements 10, 131; a substrate 11; conductive vias 12v1; conductive structures 12p1, 141; a layer 12m1; semiconductor devices 151, 152; alignment structures 161, 162; and a sealant 17.

[0089] The substrate 11 may include a circuit ( Figure 1E not shown in the figure) therein and / or thereon. The substrate 11 may include conductive traces ( Figure 1B not shown in the figure). The substrate 11 may include conductive pads ( Figure 1E(not described in the text). The substrate 11 may include semiconductor materials. The substrate 11 may include conductive materials. The substrate 11 may include insulating materials (such as dielectric materials). The substrate 11 may include an RDL structure. The substrate 11 may include ceramics, bismaleimide triazine (BT), FR4, prepreg (PP), or other suitable materials. The substrate 11 may include light-blocking materials.

[0090] The substrate 11 may include conductive vias 12v1. The conductive vias 12v1 may be filled with a conductive material, such as but not limited to copper or other suitable materials.

[0091] The connection element 10 is disposed under the substrate 11. The connection element 10 is disposed under the conductive vias 12v1. The connection element 10 may include an alloy of gold and solder. The connection element 10 may include an alloy of silver and solder. The connection element 10 may include solder, copper, or other suitable materials.

[0092] The semiconductor device 151 is disposed on the substrate 11. The semiconductor device 152 is disposed on the substrate 11.

[0093] The semiconductor devices 151 and 152 may include, for example but not limited to, semiconductor dies (or chips) in which circuits are integrated, and so on.

[0094] The alignment structure 161 is disposed on the substrate 11. The alignment structure 161 is in direct contact with the semiconductor device 151. The side surface s1 of the alignment structure 161 is in direct contact with the side surface s2 of the semiconductor device 151. The alignment structure 161 may include, for example but not limited to, optically curable materials.

[0095] The alignment structure 162 is disposed on the substrate 11. The alignment structure 162 is in direct contact with the semiconductor device 152. The side surface s5 of the alignment structure 162 is in direct contact with the side surface s6 of the semiconductor device 152. The alignment structure 162 may include, for example but not limited to, optically curable materials.

[0096] The conductive structure 12p1 is disposed on the substrate 11. The conductive structure 12p1 is disposed on the conductive vias 12v1. The conductive vias 12v1 may be, for example but not limited to, conductive pads.

[0097] The conductive structure 12p1 is disposed on the conductive vias 12v1. The layer 12m1 is disposed on the conductive structure 12p1. The conductive structure 141 is disposed under the semiconductor device 152.

[0098] The conductive structure 12p1 may be, for example but not limited to, conductive pads. The conductive structure 141 may be, for example but not limited to, conductive posts.

[0099] The connecting element 131 is disposed between the conductive structure 141 and the layer 12m1. The semiconductor device 152 is electrically connected to the connecting element 10 via the conductive structures 12p1, 141; the connecting element 131; the layer 12m1; and the conductive via 12v1.

[0100] The connecting element 131 has an asymmetrical shape. One side of the connecting element 131 has a relatively larger volume. The semiconductor device 152 has a larger volume at the side that is relatively closer to or adjacent to the alignment structure 162. The connecting element has a larger volume at the side s5 that is relatively closer to or adjacent to the alignment structure 162. The connecting element has a larger volume at the side that is relatively closer to or adjacent to the side s7 (as shown in Figure 1A ), which is adjacent to the side s5 of the alignment structure 162. The connecting element has a larger volume at the side that is relatively closer to or adjacent to the corner cor5 (as shown in Figure 1A ), which is adjacent to the alignment structure 162. The connecting element has a larger volume at the side that is relatively closer to or adjacent to the corner cor5 of the alignment structure 162, and the corner cor5 is the intersection of the two sides s5 and s7 of the alignment structure 162.

[0101] The connecting element 131 may comprise an alloy of gold and solder. The connecting element 131 may comprise an alloy of silver and solder. The connecting element 131 may comprise solder, copper, or other suitable materials.

[0102] The sealant 17 is disposed on the substrate 11. The sealant 17 covers the semiconductor device 151. The sealant 17 covers the semiconductor device 152. The sealant 17 covers the alignment structure 161. The sealant 17 covers the alignment structure 162. The sealant 17 covers the substrate 11. The sealant 17 may comprise an epoxy resin. The sealant 17 may comprise fillers or particles.

[0103] Figure 1F A cross-sectional view of a semiconductor device package 1e according to some embodiments of the present application is illustrated.

[0104] Referring to Figure 1F , the semiconductor device 1e is similar to the semiconductor device package 1d shown in Figure 1E , except that the sealant 17 of the semiconductor device package 1d is replaced by the sealant 17e of the semiconductor device package 1e.

[0105] The sealant 17e comprises, for example but not limited to, a potting compound. Compared with the sealant 17 described and depicted in the reference Figure 1E , the sealant 17e has a relatively circular upper surface (not indicated in Figure 1F ).

[0106] Figure 2AIllustration of a magnified view of a portion of the dotted - line circle C1 as shown in Figure 1B in accordance with some embodiments of the present application.

[0107] Referring to Figure 2A , a connection element 131 having an asymmetric structure is formed between the layer 12m1 and the conductive structure 141.

[0108] The connection element 131 has an asymmetric shape. One side of the connection element 131 has a relatively larger volume. The connection element 131 has a larger volume at the side relatively closer to or adjacent to the alignment structure 163. The connection element 131 has a larger volume at the side s10 ( Figure 1B shown in

[0109] The conductive structure 141 may be a conductive pillar or a conductive pad.

[0110] Figure 2B Illustration of a magnified view of a structure that may replace the structure as shown in Figure 2A in accordance with some embodiments of the present application.

[0111] Referring to Figure 2B , the conductive structures 14b and 12b are described.

[0112] The conductive structure 12b is disposed on the conductive via - hole 12v1 ( Figure 2B not shown in Figure 2B ). The conductive structure 14b is disposed under the semiconductor device 153 (

[0113] Figure 2C Illustration of a magnified view of a portion of the dotted - line circle C2 as shown in Figure 1B in accordance with some embodiments of the present application.

[0114] Referring to Figure 2C, the semiconductor device 151 is in contact with the alignment structure 161. The side surface s2 of the semiconductor device 151 is in contact with the side surface s1 of the alignment structure 161. A part of the side surface s2 of the semiconductor device 151 is in contact with a part of the side surface s1 of the alignment structure 161. The sealant 19 is between the semiconductor device 151 and the alignment structure 161. The sealant 19 is between the side surface s2 of the semiconductor device 151 and the side surface s1 of the alignment structure 161. The sealant 19 extends between the side surface s2 of the semiconductor device 151 and the side surface s1 of the alignment structure 161.

[0115] Figure 2D Describes a magnified view of a part of the dotted circle C3 as shown in Figure 1B in accordance with some embodiments of the present application.

[0116] Reference Figure 2D , the semiconductor device 152 is in contact with the alignment structure 162. The side surface s6 of the semiconductor device 152 is in contact with the side surface s5 of the alignment structure 162. A part of the side surface s6 of the semiconductor device 152 is in contact with a part of the side surface s5 of the alignment structure 162. The sealant 19 is between the semiconductor device 152 and the alignment structure 162. The sealant 19 is between the side surface s6 of the semiconductor device 152 and the side surface s5 of the alignment structure 162. The sealant 19 extends between the side surface s6 of the semiconductor device 152 and the side surface s5 of the alignment structure 162.

[0117] Figure 2E Describes a magnified view of a part of the dotted circle C4 as shown in Figure 1B in accordance with some embodiments of the present application.

[0118] Reference Figure 2E , the alignment structure 161 is disposed on the sealant 17. The alignment structure 161 is in contact with the sealant 19. The bottom portion of the alignment structure 161 ( Figure 2E not indicated in

[0119] Figure 2F Describes a magnified view of a part of the dotted circle C4 as shown in Figure 1B in accordance with some embodiments of the present application.

[0120] Reference Figure 2F , the alignment structure 161 is disposed on the sealant 17. The alignment structure 161 is in contact with the sealant 19. The bottom portion of the alignment structure 161 ( Figure 2F not indicated in

[0121] Figure 2G Describes a magnified view of a part of the dotted circle C4 as shown in Figure 1B in accordance with some embodiments of the present application.

[0122] Reference Figure 2G , the alignment structure 161 is disposed on the seal 17. The alignment structure 161 contacts the seal 19. The bottom portion of the alignment structure 161 ( Figure 2G not indicated in) extends toward the alignment structure 161 (i.e., inward).

[0123] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H Describe the operations of manufacturing the substrate 30 according to some embodiments of the present application.

[0124] Reference Figure 3A , a substrate 11 is provided. The substrate 11 has a conductive via 12v1. The conductive structure 12p1 is disposed on the conductive via 12v1.

[0125] The conductive via 12v1 may be filled with a conductive material such as but not limited to copper or other suitable materials. The conductive structure 12p1 may be, for example but not limited to, a conductive pad.

[0126] Reference Figure 3B , a layer is formed on the substrate 11. The layer 12m covers the substrate 11. The layer 12m covers the conductive structure 12p1. The layer 12m may be, for example but not limited to, a metal film. The layer 12m may be formed by, for example but not limited to, physical vapor deposition (PVD) operations or electroplating operations.

[0127] Reference Figure 3C , a photosensitive material (e.g., PR material) 31 is formed on the layer 12m. The photosensitive material 31 may be formed by, for example but not limited to, coating, printing, or screening processes. A lithography operation is performed to expose the photosensitive material 31.

[0128] Reference Figure 3D , a photosensitive material 31' is established. A portion of the photosensitive material 31 is removed, and the photosensitive material 31' is formed. A portion of the photosensitive material 31 may be removed by, for example but not limited to, etching operations. A portion of the layer 12m is exposed. A connecting element 131' is formed on the layer 12m. The connecting element 131' is formed within the photosensitive material 31'. The connecting element 131' may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof. The connecting element 131' may be formed by, for example but not limited to, electroplating operations.

[0129] Reference Figure 3E, remove the photosensitive material 31'. Remove a part of the layer 12m. The part of the layer 12m covered by the photosensitive material 31' is removed. Remove a part of the layer 12m by, for example but not limited to, an etching operation. Form a layer 12m1 on the conductive structure 12p1. Form the layer 12m1 under the connection element 131'.

[0130] Reference Figure 3F , form a photosensitive material (e.g., PR material) 16' on the substrate 11. The photosensitive material 16' covers the substrate 11. The photosensitive material 16' covers the connection element 131'. The photosensitive material 16' may be formed by, for example but not limited to, coating, printing, or screening processes. Perform a lithography operation to expose the photosensitive material 16'.

[0131] Reference Figure 3G , remove a part of the photosensitive material 16'. Remove a part of the photosensitive material 16' by, for example but not limited to, an etching operation. Form an alignment structure 163 on the substrate.

[0132] Reference Figure 3H , dispose a fluid 32 on the substrate 11 to form a structure 30. Pour the fluid 32 into the space enclosed by the alignment structure 163. The amount of the fluid 32 may be determined or predetermined based on the height or thickness of each alignment structure 163. The fluid 32 has a density relatively greater than that of the semiconductor device to be placed in the alignment structure 163. The fluid 32 may include, for example but not limited to, a formic acid solution, an iodine solution, a bromine solution, a chlorine solution, a tungstoboric acid solution, or other suitable materials.

[0133] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F 、 Figure 4G 、 Figure 4H 、 Figure 4I 、 Figure 4J 、 Figure 4K 、 Figure 4L 、 Figure 4M 、 Figure 4N and Figure 4O Describe the operations of manufacturing the semiconductor device package 1a according to some embodiments of the present application.

[0134] Reference Figure 4A , provide the structure 30 as shown in Figure 3H . The structure 30 can be provided by referring to Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G and Figure 3HThe structure 30 is manufactured by the operations described and depicted. The placement tool 41 is disposed above the substrate 11. The placement tool 41 holds the semiconductor device 153. The placement tool 41 holds the semiconductor device 153 by, for example but not limited to, vacuum suction. The placement tool 41 may be, for example but not limited to, a vacuum nozzle or the like.

[0135] Reference Figure 4B , the semiconductor device 153 is placed on the fluid 32. The semiconductor device 153 drifts or floats on the fluid 32. The substrate 11 is placed on the carrier 42. Each of some of the semiconductor devices 153 is placed in the alignment structure 163 one at a time. By a pick-and-place technique according to some other embodiments of the present application, each of some of the semiconductor devices 153 can be placed on the substrate 11.

[0136] The fluid 32 has a density greater than the density of the semiconductor device 153.

[0137] For simplicity, only the structure in the dashed box B is described in subsequent operations.

[0138] Reference Figure 4C , tilt the structure as Figure 4B shown. One side of the carrier 42 may be lifted so that the semiconductor device 153 drifting or floating on the fluid 32 floats or drifts or moves by gravity against the alignment structure 163. The semiconductor device 153 is in direct contact with the alignment structure 163. The semiconductor device 153 is blocked by the alignment structure 163. The conductive structure 141 is aligned with the connection element 131'. The conductive structure 141 is aligned with the conductive structure 12p1. The semiconductor device 153 is in direct contact with the alignment structure 163. The side s9 of the semiconductor device 153 is in direct contact with the side s10 of the alignment structure 163.

[0139] The alignment structure 163, which may be manufactured by lithography and has relatively small deviations or tolerances, can help to precisely bond the semiconductor device 153 to the substrate 10. In other words, the misalignment between the conductive structure 141 and the connection element 131' is reduced or minimized. For example, the misalignment between the conductive structure 141 and the connection element 131' can be controlled to be less than 2 μm. For example, the misalignment between the conductive structure 141 and the connection element 131' can be controlled to be less than 1 μm.

[0140] Ultrasonic waves can be applied to remove or eliminate the bubbles in the fluid 32. The ultrasonic waves can help to align or calibrate the semiconductor device 153 and the alignment structure 163.

[0141] Reference Figure 4D , remove the fluid 32. The fluid 32 can be removed by, for example but not limited to, chemical cleaning techniques.

[0142] The presser 43 is disposed on the semiconductor device 153. The presser can perform, for example, a pressing operation. A force is applied from the presser 43 to the semiconductor device 153. A heating operation can be carried out on the substrate 11 to form the connecting element 131. The semiconductor device 153 is bonded to the substrate 11. The conductive structure 141 is bonded to the conductive structure 12p1. During the heating operation, the connecting element 131 may melt and flow towards the alignment structure 163 due to gravity.

[0143] The connecting element 131 has an asymmetric shape. One side of the connecting element 131 has a relatively larger volume. The connecting element 131 has a larger volume at the side relatively closer to or adjacent to the alignment structure 163. The connecting element 131 has a larger volume at the side s10 relatively closer to or adjacent to the alignment structure 163. The connecting element 131 has a larger volume at the side relatively closer to or adjacent to the side ( Figure 4D not indicated in Figure 4D ) adjacent to the side s10 of the alignment structure 163 or at the side adjacent thereto. The connecting element 131 has a larger volume at the side relatively closer to or adjacent to the corner (

[0144] not indicated in Figure 4E ) of the alignment structure 163 or at the side adjacent thereto. The connecting element 131 has a larger volume at the side relatively closer to or adjacent to the corner of the alignment structure 163, and the corner is the intersection of two sides of the alignment structure 163. Figure 4D Refer to

[0145] not indicated in Figure 4F and the carrier 42 is disposed horizontally and the structure as shown in

[0146] Refer to Figure 4G is no longer tilted or lifted. The carrier 42 and the presser 43 are removed. A sealant 17' is formed on the substrate 11 to seal the semiconductor device 153 and the alignment structure 163. The sealant 17' covers the substrate 11. The sealant 17' may contain epoxy resin. The sealant 17' may contain fillers or particles.

[0145] Refer to Figure 4F and a part of the sealant 17' is removed. The sealant 17' can be removed by, for example, but not limited to, an etching operation. A sealant 17 is formed. A layer 18' is formed on the sealant 17. The layer 18' may contain, for example, but not limited to, a metal film or other suitable materials. The layer 18' may be formed by, for example, but not limited to, a PVD operation or an electroplating operation.

[0146] Refer to Figure 4G and a photosensitive material 44 is formed on the layer 18'. The photosensitive material 44 may be formed by, for example, coating, printing, or screening processes. A lithography operation is performed to expose the photosensitive material 44.

[0147] Refer to Figure 4H, a photosensitive material 44' is established. A part of the photosensitive material 44 is removed, and the photosensitive material 44' is formed. A part of the photosensitive material 44 can be removed by, for example, an etching operation. A part of the exposure layer 18' is exposed. A connection element 131' is formed on the layer 18'. The connection element 131' is formed within the photosensitive material 44'. The connection element 131' may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof. The connection element 131' may be formed by, for example, but not limited to, an electroplating operation.

[0148] Reference Figure 4I , the photosensitive material 44' is removed. The photosensitive material 44' can be removed by, for example, but not limited to, an etching operation. A part of the layer 18' is removed. The 18' can be removed by, for example, but not limited to, an etching operation. The layer 18 is formed. The layer 18 can be patterned to provide an electrical connection on the seal 17.

[0149] Reference Figure 4J , a photosensitive material (e.g., PR material) 16" is formed on the seal 17. The photosensitive material 16" covers the seal 17. The photosensitive material 16" covers the layer 18. The photosensitive material 16" may be formed by, for example, but not limited to, coating, printing, or screening processes. A lithography operation is performed to expose the photosensitive material 16".

[0150] Reference Figure 4K , a part of the photosensitive material 16" is removed. A part of the photosensitive material 16" can be removed by, for example, but not limited to, an etching operation. An alignment structure 161 is formed on the substrate. An alignment structure 162 is formed on the substrate.

[0151] The fluid 45 can be arranged on the seal 17. In some embodiments, the fluid 45 can be the same as the fluid 32 described and depicted in the reference Figure 3H description. In some embodiments, the fluid 45 may be different from the fluid 32 described and depicted in the reference Figure 3H description.

[0152] The semiconductor devices 151 and 152 are placed on the fluid 45. The fluid 45 has a density greater than the density of the semiconductor device 151. The fluid 45 has a density greater than the density of the semiconductor device 152. In some embodiments, the semiconductor device 151 drifts or floats on the fluid 45. In some embodiments, the semiconductor device 152 drifts or floats on the fluid 45. In some embodiments, each of some of the semiconductor devices 151 or 152 is placed within the alignment structure 161 or 162 one at a time. By a pick-and-place technique according to some other embodiments of the present application, each of some of the semiconductor devices 151 or 152 can be placed on the fluid 45.

[0153] Reference Figure 4L, the substrate 11 is placed on the carrier 42. The substrate 11 is tilted by the carrier 42. One side of the carrier 42 may be lifted so that the semiconductor devices 151 or 152 floating or drifting on the fluid 45 move or drift or float due to gravity and abut against the alignment structures 161 or 162.

[0154] The semiconductor device 151 is in direct contact with the alignment structure 161. The side s2 of the semiconductor device 151 is in direct contact with the side s1 of the alignment structure 161. The semiconductor device 152 is in direct contact with the alignment structure 162. The side s6 of the semiconductor device 152 is in direct contact with the side s5 of the alignment structure 162.

[0155] The alignment structures 161 or 162, which may be fabricated by lithography and have relatively small deviations or tolerances, can help to precisely bond the semiconductor devices 151 or 152 to the substrate 10. In other words, the misalignment between the conductive structures ( Figure 4L (not indicated in Figure 4L ) and the connection elements (

[0156] ) is reduced or minimized. For example, the misalignment between the conductive structure and the connection element can be controlled to be less than 2 μm. For example, the misalignment between the conductive structure and the connection element can be controlled to be less than 1 μm. Figure 4M , a presser 43 is disposed on the semiconductor devices 151 and 152. An external force is applied to the semiconductor devices 151 and 152 from the presser 43. A heating operation may be performed on the substrate 11. The connection element 131 is formed. The connection element 131 is formed between the semiconductor device 151 and the sealant 17. The connection element 131 is formed between the semiconductor device 152 and the sealant 17. During the heating operation, the connection element 131 may melt and flow towards the alignment structures 161 or 162 due to gravity.

[0157] The connection element 131 has an asymmetric shape. One side of the connection element 131 has a relatively larger volume. The connection element 131 has a larger volume on the side relatively closer to or adjacent to the alignment structure 163. The connection element 131 has a larger volume on the side relatively closer to or adjacent to the alignment structures 161 or 162. The connection element 131 has a larger volume on the side relatively closer to or adjacent to the corner of the alignment structures 161 or 162 ( Figure 4M (not indicated in

[0158] ) or the side adjacent thereto. Figure 4N , the carrier 42 is disposed horizontally, and as Figure 4MThe structure shown is no longer tilted or lifted. The carrier 42 and the presser 43 are removed. The substrate 11 is placed horizontally. A sealant 19 is formed on the substrate 11 to seal the sealant 17, the semiconductor devices 151, 152, and the alignment structures 161, 162. The sealant 19 may comprise an epoxy resin. The sealant 19 may comprise fillers or particles.

[0159] Reference Figure 4O , a connection element 10 is formed under the substrate 11. Forming the connection element 10 may comprise, for example but not limited to, a reflow operation. The connection element 10 may comprise, for example but not limited to, a soldering material or other suitable material.

[0160] Figure 5A and Figure 5B illustrates various types of semiconductor device packages according to some embodiments of the present application. The semiconductor device packages may be bonded to each other, or may be bonded to an external device.

[0161] Reference Figure 5A , a plurality of chips, dies, or semiconductor device packages 5 are placed on a square carrier 51a. In some embodiments, the carrier 51a may comprise, for example, an organic material (such as a molding compound, BT, PI, PBO, solder mask, ABF, PP, epoxy-based material, or a combination of two or more thereof), or an inorganic material (such as silicon, glass, ceramic, quartz, or a combination of two or more thereof), or a combination of two or more thereof.

[0162] Reference Figure 5B , a plurality of chips, dies, or semiconductor device packages 5 are placed on a circular carrier 51b. In some embodiments, the carrier 51b may comprise, for example, an organic material (such as a molding compound, BT, PI, PBO, solder mask, ABF, PP, epoxy-based material, or a combination of two or more thereof), or an inorganic material (such as silicon, glass, ceramic, quartz, or a combination of two or more thereof), or a combination of two or more thereof.

[0163] Figure 6A illustrates a cross-sectional view of a semiconductor device package 6 according to some embodiments of the present application.

[0164] Reference Figure 6A , the semiconductor device package 6 includes connection elements 10 and 53, a substrate 11, conductive vias 12v1, conductive structures 12p1, 141, a layer 12m1, semiconductor devices 151, 152, a spacer bar 66, and a sealant or underfill 67.

[0165] The semiconductor device 152 is disposed on the substrate 11. The semiconductor device 152 is electrically connected to the connection element 10 via the conductive structure 141, the connection element 53, the layer 12m1, the conductive structure 12p1, and the conductive via 12v1.

[0166] The spacer bar 66 is disposed on the substrate 11. The spacer bar 66 does not contact the semiconductor device 151 or the semiconductor device 152. The spacer bar 66 is in direct contact with the sealant or underfill 67.

[0167] Figure 6B Description reference Figure 6A The operation of forming the semiconductor device package 6.

[0168] Reference Figure 6A , the placement tool BH places the semiconductor device 152 on the substrate. The placement tool BH may be, for example but not limited to, an adhesive brush head. The placement tool BH picks up the semiconductor device 152 and places the semiconductor device 152 on the substrate 11 for bonding. The side portion of the placement tool BH ( Figure 6B not indicated in the figure) extends between the semiconductor device 151 and the semiconductor device 152. The distance D2 represents the gap between the semiconductor device 151 and the semiconductor device 152. In order to avoid contact between the placement tool BH and the semiconductor device 151, the distance D2 must be greater than 2 mm. Minimizing the gap between the semiconductor device 151 and the semiconductor device 152 may be impacted or hindered by the size of the placement tool BH.

[0169] Figure 6C Description of a magnified view of a part of the dotted circle C5 as shown in Figure 6B according to some embodiments of the present application.

[0170] To obtain better yield and signal quality, when the placement tool BH places the semiconductor device 152, the conductive structure 141 should be aligned with the connection element 631. The distance D3 represents the distance between the axis passing through the center of the conductive structure 141 and another axis passing through the center of the connection element 631. In other words, the distance D3 represents the misalignment between the conductive structure 141 and the connection element 631, which is approximately 1 - 2 μm. As a result, the semiconductor device package 6 having the semiconductor device 152 placed by the placement tool BH may have relatively greater misalignment and poorer signal quality compared to the semiconductor device package 1a having the semiconductor device 151 placed by the placement tool 41 Figure 4A described and illustrated.

[0171] As used herein, the terms "substantially", "generally", "essentially" and "about" are used to describe and account for minor variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs very nearly. By way of example, when used in connection with a numerical value, the terms can refer to a range of variation that is less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. By way of example, if the difference between two numerical values is less than or equal to ±10% of the average of the values (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1% or less than or equal to ±0.05%), then the two numerical values can be considered to be "substantially" or "about" the same. By way of example, "substantially" parallel can refer to a range of angular variation that is less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. By way of example, "substantially" perpendicular can refer to a range of angular variation that is less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0172] If the displacement between two surfaces does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm or does not exceed 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar. If the displacement of a surface relative to a flat plane between any two points on the surface does not exceed 5 μm, does not exceed 2 μm, does not exceed 1 μm or does not exceed 0.5 μm, then the surface can be considered to be planar or substantially planar.

[0173] As used herein, the terms "conductive", "electrically conductive" and "conductivity" refer to the ability to transfer current. Conductive materials generally denote those materials that present little or no opposition to the flow of current. One measure of conductivity is Siemens (S) / meter (S / m). Generally, conductive materials have a conductivity greater than about 10 4 S / m (e.g., at least 10 5 S / m or at least 10 6A material with a conductivity of [[ID=]]S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0174] As used herein, unless the context clearly dictates otherwise, the singular terms "a / an" and "the" may include plural referents. In the description of some embodiments, a component being provided "on" or "above" another component may cover the case where the former component is directly on the latter component (e.g., in physical contact with the latter component), as well as the case where one or more intermediate components are located between the former component and the latter component.

[0175] Unless otherwise specified, spatial descriptions such as "above", "below", "on", "left", "right", "down", "top", "bottom", "vertical", "horizontal", "side", "higher than", "lower than", "upper", "on top", "below", "downward", etc. are indicated with respect to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and the actual implementations of the structures described herein can be spatially arranged in any orientation or manner, with the proviso that the advantages of the embodiments of the present disclosure are not prejudiced by such an arrangement.

[0176] Although the present disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration do not limit the present disclosure. Those skilled in the art will clearly understand that various changes can be made and equivalent components can be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The figures may not necessarily be drawn to scale. Due to variables in manufacturing processes, etc., there may be differences between the artistic representations and the actual devices in the present disclosure. There may be other embodiments of the present disclosure that are not specifically described. The specification and the drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt the specific circumstances, materials, compositions of matter, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the teachings of the present disclosure to form equivalent methods. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device package, comprising: Providing a substrate on which a first conductive structure is disposed; Forming a first alignment structure on the substrate; Supplying a fluid onto the substrate; Placing a first semiconductor device having a first conductive structure on the fluid; Tilting the substrate after placing the first semiconductor device until the first semiconductor device abuts against the first alignment structure; And Applying ultrasonic waves after abutting the first semiconductor device against the first alignment structure.

2. The method according to claim 1, further comprising performing a heating operation after abutting the first semiconductor device against the first alignment structure.

3. The method according to claim 1, further comprising performing a pressing operation after abutting the first semiconductor device against the first alignment structure.

4. The method according to claim 1, wherein the density of the fluid is greater than the density of the first semiconductor device.

5. The method according to claim 1, further comprising removing the fluid.

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