Organic Light Emitting Diode Display

Abstract

The present disclosure relates to an organic light emitting diode display, comprising: a substrate; a semiconductor layer; a first gate insulating layer, arranged on the semiconductor layer; a first gate layer, arranged on the first gate insulating layer; a first interlayer insulating layer, arranged on the first gate layer; a first data layer, arranged on the first interlayer insulating layer; a second interlayer insulating layer, arranged on the first data layer; a driving voltage line and a driving low voltage line, arranged on the second interlayer insulating layer and separated from each other; an upper insulating layer, covering the driving voltage line and the driving low voltage line; and an anode, arranged on the upper insulating layer and overlapping the driving voltage line or the driving low voltage line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application Nos. 10-2018-0157411 and 10-2018-0166477 filed on December 7, 2018 and December 20, 2018, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] The present disclosure relates to an organic light emitting diode display, and more particularly, to an organic light emitting diode display having a high resolution. Background Art

[0004] A display device is a device that displays images. A flat panel display is a television, monitor, or other display device that uses a thin panel design instead of a traditional cathode ray tube (CRT) design. Examples of flat panel displays include organic light emitting diode (OLED) displays and liquid crystal displays.

[0005] Since the organic light emitting diode display has a self-emitting characteristic and does not require a separate light source, the organic light emitting diode display can be thinner and lighter than a liquid crystal display device. In addition, compared with a liquid crystal display, the organic light emitting diode display can consume less power, have higher brightness, and have a higher response speed.

[0006] However, since an organic light emitting diode (OLED) display has a more complicated pixel structure than a liquid crystal display, and it is difficult to provide a space for forming pixels as the resolution increases. Summary of the invention

[0007] At least one exemplary embodiment of the inventive concept provides an organic light emitting diode display having a high resolution, in which the capacitance of a storage capacitor connected to one terminal of a driving transistor is increased.

[0008] According to an exemplary embodiment of the present invention, an organic light emitting diode display includes: a substrate; a semiconductor layer; a first gate insulating layer, arranged on the semiconductor layer; a first gate layer, arranged on the first gate insulating layer; a first interlayer insulating layer, arranged on the first gate layer; a first data layer, arranged on the first interlayer insulating layer; a second interlayer insulating layer, arranged on the first data layer; a driving voltage line and a driving low voltage line, arranged on the second interlayer insulating layer and separated from each other; an upper insulating layer, covering the driving voltage line and the driving low voltage line; and an anode, arranged on the upper insulating layer and overlapping with the driving voltage line or the driving low voltage line.

[0009] The driving voltage line and the driving low voltage line may extend in a longitudinal direction.

[0010] The anode may be electrically connected to an anode connection portion formed to be separated from the driving voltage line and the driving low voltage line on the same layer.

[0011] In one embodiment, the organic light emitting diode display comprises a plurality of pixels, and the anode is disposed in each of the pixels.

[0012] A portion of the anode may overlap the driving voltage line, and another portion of the anode may overlap the driving low voltage line.

[0013] The anode connection portion may be disposed between the driving voltage line and the driving low voltage line.

[0014] The anode may overlap the driving voltage line.

[0015] The driving voltage line may have an anode connection portion opening corresponding to the anode connection portion, and the anode connection portion is disposed within the anode connection portion opening.

[0016] In an exemplary embodiment, the organic light emitting diode display further includes an overlapping layer disposed between the substrate and the semiconductor layer, the overlapping layer including a channel overlapping portion overlapping with the channel of the first transistor and an extending portion extending from the channel overlapping portion, and the extending portion of the overlapping layer overlaps with the first gate electrode of the first transistor to form an overlapping capacitor.

[0017] The driving voltage line may have a parasitic capacitor opening so that the anode forms a parasitic capacitance with the first gate insulating layer or the first data layer.

[0018] In an exemplary embodiment, the organic light emitting display includes an organic emission layer disposed on the anode and a cathode disposed on the organic emission layer, the cathode being electrically connected to a cathode connecting portion disposed on the same layer as the anode, and the cathode connecting portion being electrically connected to the driving low voltage line.

[0019] In an exemplary embodiment, the driving voltage line has a greater width than the anode, and the driving low voltage line has a width greater than half of the width of the anode.

[0020] In an exemplary embodiment, the first gate layer includes a pair of scan lines receiving the same scan signal, the first data layer includes a pair of data lines connected to a pixel column, and among two adjacent pixels included in the pixel column, one pixel is connected to one scan line of the pair of scan lines and one data line of the pair of data lines, and the other pixel is connected to the other scan line of the pair of scan lines and the other data line of the pair of data lines.

[0021] An organic light emitting diode display according to an exemplary embodiment of the present invention includes: a substrate; a semiconductor layer disposed on the substrate; a first gate insulating layer disposed on the semiconductor layer; a first gate layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the first gate layer; a second gate layer disposed on the second gate insulating layer; a first interlayer insulating layer disposed on the second gate layer; a first data layer disposed on the first interlayer insulating layer and including a data line, an initialization voltage line, a driving voltage line and a driving low voltage line; an upper insulating layer covering the first data layer; an anode disposed on the upper insulating layer, wherein the anode includes an additional capacitor extension portion, and the additional capacitor extension portion overlaps the driving low voltage line.

[0022] In an exemplary embodiment, the organic light emitting diode display further includes an overlapping layer disposed between the substrate and the semiconductor layer, and the overlapping layer overlaps a channel of the first transistor.

[0023] In an exemplary embodiment, the driving voltage line and the driving low voltage line are disposed adjacent to each other, and a width of the driving low voltage line is wider than a width of the driving voltage line.

[0024] The driving low voltage line may also overlap with the driving voltage line.

[0025] In an exemplary embodiment, the organic light emitting diode display includes a second interlayer insulating layer disposed between the first data layer and the upper insulating layer and a second driving low voltage line disposed between the first data layer and the upper insulating layer. In this embodiment, the second interlayer insulating layer is disposed on the first data layer, the second driving low voltage line is disposed on the second interlayer insulating layer, and the driving low voltage line is electrically connected to the second driving low voltage line to transmit a driving low voltage through a dual structure.

[0026] In an exemplary embodiment, the organic light emitting diode display includes a cathode connection portion, which is disposed on the same layer as the anode and is electrically connected to the driving low voltage line, and the additional capacitor extension portion of the anode is disposed to be separated from the cathode connection portion.

[0027] In an exemplary embodiment, the organic light emitting diode display includes a plurality of pixels, the anode is disposed in each of the pixels, and at least one anode does not include the additional capacitor extension portion.

[0028] An organic light emitting diode display according to an exemplary embodiment of the present invention includes: a substrate; a semiconductor layer disposed on the substrate; a first gate insulating layer disposed on the semiconductor layer; a first gate layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the first gate layer; a second gate layer disposed on the second gate insulating layer; an interlayer insulating layer disposed on the second gate layer; a data layer disposed on the interlayer insulating layer and including a data line and a driving voltage line; an upper insulating layer disposed on the data layer; and an anode disposed on the upper insulating layer and completely covering a gate electrode of a first transistor disposed on the first gate layer, wherein the anode overlaps the driving voltage line to form an additional capacitor.

[0029] The driving voltage line may extend in a longitudinal direction.

[0030] One side of the anode extending in the longitudinal direction may overlap the driving voltage line.

[0031] In an exemplary embodiment, the semiconductor layer includes a first semiconductor, a second semiconductor, and a third semiconductor, the first transistor is disposed on the first semiconductor, the second transistor is disposed on the second semiconductor, and the third transistor is disposed on the third semiconductor.

[0032] At least one of the first semiconductor, the second semiconductor, and the third semiconductor may include an opening.

[0033] The first semiconductor may include a channel region, a source region, and a drain region, and the source region may overlap the anode and the driving voltage line.

[0034] The organic light emitting diode display may further include an overlapping layer disposed between the substrate and the semiconductor layer.

[0035] The overlapping layer may include a channel overlapping portion overlapping a channel region of the first semiconductor and an extending portion extending from the channel overlapping portion, and the extending portion of the overlapping portion may overlap the gate electrode of the first transistor.

[0036] The second gate layer may include a storage electrode, the gate electrode of the first transistor and the storage electrode may overlap to form a storage capacitor, and the storage capacitor may completely overlap the anode.

[0037] The overlapping layer may be connected to the storage electrode through the opening, and the storage electrode may be electrically connected to the anode through the anode connection portion formed in the data layer.

[0038] The second semiconductor may include a channel region, a source region, and a drain region, and the source region may overlap the data line to be electrically connected thereto.

[0039] In an exemplary embodiment, the organic light emitting diode display includes a transverse driving voltage line included in the first gate layer and extending in a horizontal direction crossing the driving voltage line.

[0040] In an exemplary embodiment, the light emitting diode display includes a plurality of pixels, and the transverse driving voltage line is electrically connected to at least one pixel among pixels adjacent in a row direction.

[0041] In an exemplary embodiment, the organic light emitting diode display includes an initialization voltage line included in the data layer and extending in a longitudinal direction.

[0042] In an exemplary embodiment, the organic light emitting diode display includes a plurality of pixels and an initialization voltage transfer part disposed in a horizontal direction crossing the initialization voltage line, and the initialization voltage transfer part is electrically connected to at least one pixel among pixels adjacent in the row direction.

[0043] In an exemplary embodiment, the organic light emitting diode display further includes a driving low voltage line included in the data layer and extending in a longitudinal direction.

[0044] In an exemplary embodiment, the semiconductor layer includes a first semiconductor, a second semiconductor, and a third semiconductor, the first transistor is disposed on the first semiconductor, the second transistor is disposed on the second semiconductor, and the third transistor is disposed on the third semiconductor and the anode overlaps the first semiconductor, the second semiconductor, and the third semiconductor.

[0045] The first gate layer may further include a scan line and a previous scan line extending in a horizontal direction.

[0046] The first gate layer may include a gate electrode of the third transistor, and the gate electrode of the third transistor may be electrically connected to the previous scan line through a connection portion included in the second gate layer and a connection portion included in the data layer.

[0047] The organic light emitting diode display may further include an organic emission layer disposed on the anode and a cathode disposed on the organic emission layer.

[0048] According to exemplary embodiments, in an organic light emitting diode display having high resolution, the driving voltage line applying the driving voltage or the driving low voltage line applying the driving low voltage is formed to overlap with the anode to form an additional capacitor, thereby having sufficient capacitance in a narrow area.

[0049] Furthermore, by forming the driving low voltage line with a double-layer structure, a voltage drop generated when the driving low voltage is applied can be eliminated.

[0050] Furthermore, as the capacitance of the storage capacitor connected to one end of the driving transistor increases, the display quality of the display device can be improved.

[0051] According to exemplary embodiments, since the anode does not overlap the data line, crosstalk with the data line due to parasitic capacitance may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0053] Figure 2 is a timing diagram of signals applied to one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0054] Figure 3 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0055] Figure 4 and Figure 5 is along Figure 3 A cross-sectional view taken along lines IV-IV and VV in an exemplary embodiment of the present invention.

[0056] Figure 6 It shows that according to Figure 3 A layout view of an area of ​​a pixel of an organic light emitting diode display of an exemplary embodiment, particularly embodying a specific layer in a pixel.

[0057] Figure 7 is a layout view of a region of a pixel of an organic light emitting diode display according to another exemplary embodiment of the inventive concept.

[0058] Figure 8 It shows that according to Figure 7A layout view of an area of ​​a pixel of an organic light emitting diode display of an exemplary embodiment, particularly embodying a specific layer in a pixel.

[0059] Fig. 9 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0060] Fig.10 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0061] Fig.11 and Fig.12 is along Fig.10 Cross-sectional views taken along lines XI-XI and XII-XII in an exemplary embodiment of the present invention.

[0062] Fig.13 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0063] Fig.14 is along Fig.13 A cross-sectional view taken along line XIV-XIV in an exemplary embodiment of the present invention.

[0064] Fig.15 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0065] Fig.16 is a timing diagram of signals applied to one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0066] Fig.17 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0067] Fig.18 It is along Fig.17 A cross-sectional view taken along line XVIII-XVIII' in an exemplary embodiment of the present invention.

[0068] Fig.19 It is along Fig.17 A cross-sectional view taken along line XIX-XIX' in an exemplary embodiment of the present invention.

[0069] Fig. 20 It is along Fig.17 A cross-sectional view taken along line XX-XX' in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0070] The inventive concept will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0071] To clarify the embodiments of the present inventive concept, like reference numerals refer to like elements throughout the specification.

[0072] In addition, the size and thickness of each configuration shown in the drawings are arbitrarily illustrated for better understanding and ease of description, but the embodiments of the inventive concept are not limited thereto.

[0073] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0074] Furthermore, in this specification, the phrase "on a plane" means viewing a target portion from the top, and the phrase "on a cross section" means viewing a cross section formed by vertically cutting the target portion from the side.

[0075] Now, refer to Figure 1 A pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept is described.

[0076] Figure 1 is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0077] refer to Figure 1 , a pixel PX of the organic light emitting diode display includes a plurality of transistors T1, T2 and T3, a storage capacitor Cst, additional capacitors Ca and Cb, and an organic light emitting diode OLED, which are connected to a plurality of signal lines 151, 152, 171, 172, 173, 155 (195) and 156 (196).

[0078] according to Figure 1 The organic light emitting diode display of the exemplary embodiment shows an organic light emitting diode display used with a high resolution (4K or 8K), and two pixels PX are controlled by two scan lines 151 and two data lines 171 and 172 to which the same signal is applied.

[0079] First, the structure of the pixel PX is described.

[0080] A plurality of transistors T1, T2, and T3 included in one pixel PX include a driving transistor T1 (hereinafter referred to as a first transistor), and include a switching transistor T2 (hereinafter referred to as a second transistor) connected to a scan line 151 and an initialization transistor T3 (hereinafter referred to as a third transistor or a sensing transistor) connected to a previous scan line 152. In an exemplary embodiment, the third transistor T3 is connected to a signal line to which a gate-on voltage is applied at a timing different from that of the previous scan line 152.

[0081] The multiple signal lines 151, 152, 171, 172, 173, 155 (195) and 156 (196) included in one pixel PX may include a scan line 151, a previous scan line 152, data lines 171 and 172, an initialization voltage line 173 (hereinafter referred to as a sensing line), driving voltage lines 155 and 195, and driving low voltage lines 156 and 196.

[0082] The scan line 151 is connected to a gate driver (not shown) to transmit a scan signal Sn to the second transistor T2. The gate driver can be implemented by a gate drive circuit. The scan line 151 is connected to the pixels PX included in two rows, and is separated into two lines from the gate driver in one line in the display area where the pixels PX are provided. The scan line 151 separated into two lines receiving the same scan signal Sn is also referred to as a pair of scan lines 151 hereinafter.

[0083] The previous scan line 152 is connected to the gate driver and transmits the previous scan signal S(n-1) applied to the pixel PX set in the previous stage to the third transistor T3. The previous scan line 152 is separated into two lines like the scan line 151 to be connected to the pixels PX included in two rows. The previous scan line 152 is separated into two lines, the two lines are applied with the same previous scan signal S(n-1), and are also referred to as a pair of previous scan lines 152.

[0084] The data lines 171 and 172 are wirings for transmitting a data voltage Dm generated from a data driver (not shown), and two data lines 171 and 172 are formed for one pixel column. The data driver may be implemented by a data driving circuit. For example, the data line 171 may transmit a first data voltage D1, and the data line 172 may transmit a second data voltage D2. The two data lines 171 and 172 formed for one pixel column are also referred to as a pair of data lines 171 and 172. A pair of data lines 171 and 172 and a pair of scan lines 151 are connected to two pixels PX included in one pixel column. That is, one of the two pixels PX included in the pixel column is connected to the first data line 171 and one of the pair of scan lines 151, and the other of the two pixels PX is connected to the second data line 172 and the other of the pair of scan lines 151. Two adjacent pixels PX included in the pixel column are connected to different data lines 171 and 172 and scan lines 151 of a pair of data lines 171 and 172 and a pair of scan lines 151. The brightness of light emitted from the organic light emitting diode OLED (referred to as an organic light emitting element) varies according to the data voltage Dm supplied to the pixel PX along the data lines 171 and 172 .

[0085] In an exemplary embodiment, the driving voltage lines 155 and 195 apply the driving voltage ELVDD, and the driving low voltage lines 156 and 196 apply the driving low voltage ELVSS. In one embodiment, the driving voltage ELVDD is higher than the driving low voltage ELVSS. The driving voltage lines 155 and 195 and the driving low voltage lines 156 and 196 according to this exemplary embodiment include wiring extending in the horizontal direction and wiring extending in the longitudinal direction, and are formed into a mesh structure. Moreover, the layers of the wiring extending in the horizontal direction are different from the layers of the wiring extending in the longitudinal direction, so that the reference numerals are also given as different numbers. The voltages applied to the driving voltage lines 155 and 195 and the driving low voltage lines 156 and 196 can be predetermined voltages, respectively. The driving voltage ELVDD is used as an input voltage to generate an output current from the driving transistor T1, and when the output current is applied to the anode of the organic light emitting diode OLED, the driving low voltage ELVSS is applied to the cathode electrode of the organic light emitting diode OLED.

[0086] Hereinafter, a plurality of transistors T1 , T2 , and T3 are described.

[0087] First, the driving transistor T1 is a transistor that controls the size of the output current according to the data voltage Dm applied to the gate electrode, and the output driving current Id is applied to the organic light emitting diode OLED, so that the brightness of the organic light emitting diode OLED is controlled according to the data voltage Dm. To this end, the first electrode (input side electrode) of the driving transistor T1 is configured to receive the driving voltage ELVDD, and the second electrode (output side electrode) is connected to the first electrode (hereinafter referred to as the anode or pixel electrode) of the organic light emitting diode OLED. In addition, the gate electrode of the driving transistor T1 is connected to the second electrode (output side electrode) of the second transistor T2 to receive the data voltage Dm.

[0088] In one embodiment, the gate electrode of the driving transistor T1 is connected to one electrode of the storage capacitor Cst. The storage capacitor Cst ensures that the data voltage Dm transmitted to the gate electrode of the driving transistor T1 is maintained for one frame period. Therefore, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and therefore, the driving current Id output from the driving transistor T1 changes during one frame period and is output constantly. In an exemplary embodiment, one frame period is a period during which image data is output to all pixels of the display device.

[0089] The driving transistor T1 includes a semiconductor layer in which a channel is provided. In an exemplary embodiment, the driving transistor T1 further includes an overlapping layer 115, which is provided below a portion of the semiconductor layer in which the channel is provided. The overlapping layer 115 overlaps with the channel and the gate electrode of the driving transistor T1, thereby improving the characteristics of the driving transistor T1 and maintaining the voltage of the gate electrode. Since the overlapping layer 115 overlaps with the gate electrode, the voltage of the gate electrode is maintained, thereby supplementing the capacitance of the storage capacitor Cst. Hereinafter, the capacitor formed by the overlap between the overlapping layer 115 and the gate electrode of the driving transistor T1 is referred to as an overlapping capacitor (not shown). The overlapping layer 115 is electrically connected to the second electrode (output side electrode) of the driving transistor T1, whereby the overlapping layer 115 is also connected to the anode of the resulting organic light emitting diode OLED.

[0090] The second transistor T2 (hereinafter referred to as a switching transistor) is a transistor that receives a data voltage Dm as an input to the pixel PX. The gate electrode of the second transistor T2 is connected to the scan line 151, the first electrode of the second transistor T2 is connected to the data line 171, and the second electrode (output side electrode) of the second transistor T2 is connected to the gate electrode of the driving transistor T1. If the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line connected to the pair of data lines 171 and 172 is transmitted to the gate electrode of the driving transistor T1 and stored in the storage capacitor Cst.

[0091] The third transistor T3 (hereinafter referred to as the initialization transistor or the sensing transistor) plays the role of initializing the second electrode (output side electrode) of the driving transistor T1, one electrode of the storage capacitor Cst, and the anode of the organic light emitting diode OLED. The gate electrode of the third transistor T3 is connected to the previous scanning line 152, and the first electrode of the third transistor T3 is connected to the initialization voltage line 173. The second electrode of the third transistor T3 is electrically connected to the second electrode (output side electrode) of the driving transistor T1, and is thereby also connected to the anode of the organic light emitting diode OLED and the overlapping layer 115.

[0092] The initialization voltage line 173 not only provides an initialization voltage but also serves as a wiring (eg, a sensing line) for sensing a voltage of an anode of the organic light emitting diode OLED connected to a second electrode of the third transistor T3 during a sensing period. Thus, the third transistor T3 is also referred to as a sensing transistor.

[0093] The operation of the third transistor T3 is now described. When the organic light emitting diode OLED emits light (emission period), the voltage of the anode is stored on one electrode of the storage capacitor Cst. At this time, the data voltage Dm is stored in the other electrode of the storage capacitor Cst. At this time, if the gate-on voltage is applied to the gate electrode of the third transistor T3, the initialization voltage line 173 operates as a sensing line, and the voltage of the anode is transmitted to the sensing unit (not shown) through the sensing line. Hereinafter, this is referred to as a sensing period. Next, in the reset period during the period in which the gate-on voltage is applied to the gate electrode of the third transistor T3, the initialization voltage line 173 applies an initialization voltage Vint to initialize the voltage of the anode. Hereinafter, this is referred to as an initialization period.

[0094] If the voltage detected in the sensing period (e.g., the sensing signal SS) is different from the voltage of the anode electrode expected when determined based on the applied data voltage Dm, the data voltage Dm may be modified to be provided to the pixel PX. That is, the characteristics of the driving transistor T1 may be changed, and the organic light emitting diode OLED may emit normal light by sensing the change and providing the data voltage Dm corresponding thereto.

[0095] That is, during one frame period, the two electrodes of the storage capacitor Cst play a role in maintaining the data voltage Dm and the voltage of the anode of the organic light emitting diode OLED (the output side electrode voltage of the driving transistor T1 ).

[0096] However, since an area occupied by a pixel PX of a high-resolution organic light emitting diode display and an area for forming a storage capacitor Cst in the pixel PX are small, the storage capacitance may not be sufficient to maintain one frame period.

[0097] Therefore, the pixel PX of the present exemplary embodiment further includes a first additional capacitor Ca and a second additional capacitor Cb to have sufficient storage capacitance to maintain the voltage of the anode of the organic light emitting diode OLED for one frame period.

[0098] The first additional capacitor Ca has one side electrode connected to the anode of the organic light emitting diode OLED and the other side electrode to which the driving voltage ELVDD is applied. That is, the first additional capacitor Ca plays a role in maintaining the voltage of the anode of the organic light emitting diode OLED.

[0099] Furthermore, since the second additional capacitor Cb has one side electrode connected to the anode of the organic light emitting diode OLED and the other side electrode to which the driving low voltage ELVSS is applied, the second additional capacitor Cb also plays a role in maintaining the voltage of the anode of the organic light emitting diode OLED.

[0100] Therefore, the capacitor included in one pixel PX has a storage capacitor Cst and additional capacitors Ca and Cb (i.e., a first additional capacitor Ca and a second additional capacitor Cb), thereby ensuring sufficient storage capacitance to maintain the voltage of the anode of the organic light emitting diode OLED during one frame period. In addition, according to an exemplary embodiment, an overlapping capacitor formed by the overlapping layer 115 may be further included.

[0101] According to an exemplary embodiment of the inventive concept, the pixel PX also includes only the first additional capacitor Ca or only the second additional capacitor Cb. In addition, adjacent pixels PX may have additional capacitors Ca and Cb of different sizes. In addition, although the capacitance of the first additional capacitor Ca and the capacitance of the second additional capacitor Cb may be different from each other in adjacent pixels PX, the sum of the capacitances of the two additional capacitors Ca and Cb may be set to be substantially constant.

[0102] Reference now Figure 1 and Figure 2 An operation of one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept is described.

[0103] Figure 2 is a timing diagram of signals applied to one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0104] exist Figure 2 , the signal labeled SCAN is a signal applied to the scan line 151 , and the signal labeled SENSING represents a signal applied to the previous scan line 152 .

[0105] First, during the sensing / initial period, a high level previous scan signal S(n-1) is provided to the pixel PX through the previous scan line 152. Then, the third transistor T3 receiving the previous scan signal S(n-1) is turned on. At this time, the voltage stored in the anode of the organic light emitting diode OLED is confirmed through the initialization voltage line 173 (sensing period), and then the voltage of the anode of the organic light emitting diode OLED is changed to the initialization voltage Vint to be initialized (initialization period).

[0106] When the characteristic of the driving transistor T1 changes while the driving transistor T1 provided at each pixel PX has a different threshold voltage Vth due to process dispersion or operates during a long period in a sensing period, the change is sensed so that the organic light emitting diode OLED normally emits light.

[0107] Next, during the data writing period, a high-level scan signal Sn is supplied to the pixel PX through the scan line 151. The second transistor T2 is turned on by the high-level scan signal Sn. If the second transistor T2 is turned on, the data voltage Dm is input to the gate electrode of the driving transistor T1 via the second transistor T2 and stored in one side electrode of the storage capacitor Cst.

[0108] The degree of conduction of the driving transistor T1 is determined according to the data voltage Dm applied to the gate electrode, and the driving transistor T1 outputs the driving voltage ELVDD input to the first electrode to be transmitted to the anode electrode of the organic light emitting diode OLED.

[0109] The voltage of the anode electrode of the organic light emitting diode OLED is stored in the overlapping capacitor or the first and second additional capacitors Ca and Cb and the storage capacitor Cst and is maintained during one frame period.

[0110] Above, through Figure 1 Mainly describes the circuit structure.

[0111] In the following, reference Figures 3 to 5 How to implement the pixel PX according to an exemplary embodiment is described.

[0112] Figure 3 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept, and Figure 4 and Figure 5 is along Figure 3 A cross-sectional view taken along lines IV-IV and VV in an exemplary embodiment of the present invention.

[0113] refer to Figures 3 to 5In an organic light emitting diode display according to an exemplary embodiment of the inventive concept, an overlay layer 115, semiconductor layers (121, 122, and 123), gate layers (151, 152, 154, 155, and 156), a first data layer (171, 172, 173, 174, 175, 176, 177, and 178), a second data layer (191, 195, and 196), a pixel electrode layer (201 and 206), an organic emission layer 350, and a cathode 310 are respectively formed on a substrate 110, and these layers are insulated from each other by an insulating layer therebetween unless they are connected through an opening.

[0114] The substrate 110 may be formed as a glass substrate or a flexible substrate including plastic or polyimide (PI). When the substrate 110 is formed as a flexible substrate, an additional inorganic insulating layer may be further formed unlike the case of a glass substrate.

[0115] The overlapping layer 115 formed on the substrate 110 is now described. The overlapping layer 115 includes a channel overlapping portion overlapping the channel of the driving transistor T1, an extension portion disposed below the storage capacitor Cst, and a connection portion. The extension portion of the overlapping layer 115 overlaps with an extension portion of the gate electrode 154 described later to form an overlapping capacitor. The connection portion of the overlapping layer 115 is connected to the storage electrode 174 described later to receive the voltage of the anode 201. Thus, an overlapping capacitor that maintains the voltage of the anode 201 is configured.

[0116] The buffer layer 11 covers the substrate 110 and the overlapping layer 115. The buffer layer 11 may be formed of an inorganic insulating material.

[0117] The semiconductor layers (121, 122 and 123) are formed on the buffer layer 11. Each semiconductor layer (121, 122 and 123) includes a first semiconductor 121 of a driving transistor T1, a second semiconductor 122 of a second transistor T2 and a third semiconductor 123 of a third transistor T3, and the first semiconductor 121, the second semiconductor 122 and the third semiconductor 123 include channels of the driving transistor T1, the second transistor T2 and the third transistor T3, respectively. The semiconductor layers (121, 122 and 123) according to the present exemplary embodiment are formed of oxide semiconductors. Each semiconductor layer (121, 122 and 123) includes a channel of each transistor T1, T2 and T3 and a source region / drain region disposed on both sides of the channel. The source region / drain region of each semiconductor layer (121, 122 and 123) extends respectively and is electrically connected to different layers through an opening. The third semiconductor 123 including the channel of the third transistor T3 includes an extension portion extending in a first direction (lateral direction). The third semiconductor 123 of the third transistor T3 also includes a protrusion protruding from the extension portion. That is, the extension portion of the third semiconductor 123 protrudes to connect to the third semiconductor 123 of the third transistor T3 of the adjacent pixel PX, and extends to the position where the initialization voltage line 173 is formed. In the present exemplary embodiment, one initialization voltage line 173 is formed for three pixels PX, and the third semiconductors 123 of the third transistors T3 of the three pixels PX are connected to each other to receive the initialization voltage Vint. Here, the extension portion of the third semiconductor 123 may be doped to have the same characteristics as a conductor. On the other hand, according to an exemplary embodiment, the extension portion of the third semiconductor 123 may be formed by a conductive layer such as a gate layer other than a semiconductor layer.

[0118] The gate insulating layer 12 covers the semiconductor layers (121, 122, and 123) and the buffer layer 11. The gate insulating layer 12 may be formed of an inorganic insulating material.

[0119] The gate layer (151, 152, 154, 155 and 156) is formed on the gate insulating layer 12. The gate layer (151, 152, 154, 155 and 156) includes a scan line 151, a previous scan line 152, a gate electrode 154 of the driving transistor T1, a first driving voltage line 155 and a first driving low voltage line 156.

[0120] The scan line 151 extends in a first direction (lateral direction) and includes a protrusion protruding toward the second semiconductor 122 in which the channel of the second transistor T2 is provided. The protrusion of the scan line 151 is a gate electrode of the second transistor T2.

[0121] The previous scan line 152 extends in the first direction (lateral direction) and passes through a portion of the third semiconductor 123 in which the channel of the third transistor T3 is disposed. A portion where the previous scan line 152 intersects the third semiconductor 123 is a gate electrode of the third transistor T3. However, according to an exemplary embodiment, the previous scan line 152 may further include a structure protruding toward the third semiconductor 123.

[0122] The first driving voltage line 155 and the first driving low voltage line 156 extend in the first direction (lateral direction) as wiring for applying the driving voltage ELVDD and the driving low voltage ELVSS respectively. The first driving voltage line 155 and the first driving low voltage line 156 respectively play the role of transmitting the driving voltage ELVDD and the driving low voltage ELVSS in the first direction. Hereinafter, the first driving voltage line 155 and the first driving low voltage line 156 are also referred to as the lateral driving voltage line and the lateral driving low voltage line, respectively.

[0123] The gate electrode 154 of the driving transistor T1 includes an overlapping portion overlapping with the first semiconductor 121 in which the channel of the driving transistor T1 is disposed and an extending portion extending from the overlapping portion. The overlapping portion of the gate electrode 154 of the driving transistor T1 functions as a gate electrode, and the extending portion forms one side electrode of the storage capacitor Cst. The extending portion of the gate electrode 154 overlaps with the extending portion of the overlapping layer 115 to form an overlapping capacitor. The gate electrode 154 also includes an extending portion extending from the extending portion, and receives the data voltage Dm from the second electrode of the second transistor T2 through the extending portion.

[0124] The first interlayer insulating layer 13 covers the gate layers (151, 152, 154, 155, and 156) and the gate insulating layer 12. The first interlayer insulating layer 13 may be formed of an inorganic insulating material.

[0125] A first data layer (171, 172, 173, 174, 175, 176, 177 and 178) is formed on the first interlayer insulating layer 13. The first data layer (171, 172, 173, 174, 175, 176, 177 and 178) includes a pair of data lines 171 and 172, an initialization voltage line 173, a storage electrode 174, a driving voltage connection part 175, a driving low voltage connection part 176, a gate electrode connection part 177 and a step removal part 178.

[0126] A pair of data lines 171 and 172 are formed for each pixel column and extend in a second direction (longitudinal direction) perpendicular to the first direction. The pair of data lines 171 and 172 are arranged on both sides relative to the positions where the transistors T1, T2 and T3 are formed. One of the pair of data lines 171 and 172 is connected to the second semiconductor 122 of the second transistor T2 through the opening 64, and the data voltage Dm is applied to the second transistor T2.

[0127] The initialization voltage line 173 extends to the second direction like a pair of data lines 171 and 172, and applies an initialization voltage Vint. In the present exemplary embodiment, the initialization voltage line 173 is not formed for each pixel column, and one initialization voltage line 173 is formed for every three pixel columns. The initialization voltage line 173 is connected to the extended portion of the third semiconductor 123 through the opening 69. The third semiconductor 123 is connected to the third transistor T3 of each pixel PX through a protrusion to sense or initialize the voltage of the second electrode of the third transistor T3 of each pixel PX (i.e., the voltage of the anode 201).

[0128] The storage electrode 174 has an extension portion overlapping the extension portion of the gate electrode 154 and includes an extension portion extending from the extension portion. The extension portion of the storage electrode 174 is connected to the second electrode (output side electrode) of the driving transistor T1, the overlapping layer 115, and the second electrode of the third transistor T3 through the openings 63, 61, and 66, respectively. The extension portion of the storage electrode 174 overlaps with the gate electrode 154 to form a storage capacitor Cst. Figure 3 As shown, the extension of the storage electrode 174 and the extension of the gate electrode 154 occupy a large area within the pixel PX, but the area in which the pixel PX is formed is reduced while increasing the resolution, and therefore, the capacitance of the storage capacitor Cst may be insufficient. To prevent this problem, an overlapping capacitor may be formed by adding an extension of the overlapping layer 115 that overlaps the extension of the gate electrode 154. In addition, at least one of the additional capacitors Ca and Cb to be discussed below is additionally formed. In an exemplary embodiment, the storage electrode 174 is also electrically connected to the anode 201 described later, so that the voltage of the storage electrode 174 is equal to the voltage of the anode 201 and is initialized at each frame period.

[0129] The driving voltage connection portion 175, which is a connection portion for applying the driving voltage ELVDD to the first semiconductor 121 of the driving transistor T1, has an island structure. The driving voltage connection portion 175 is connected to the first driving voltage line 155 through the opening 83, and is connected to the first semiconductor 121 through the opening 62. Moreover, the driving voltage connection portion 175 extends upward and is connected to the second driving voltage line 195 described later through the opening 82.

[0130] In an exemplary embodiment, the driving low voltage connection portion 176 has a linear structure and facilitates the connection between the second driving low voltage line 196 and the first driving low voltage line 156, which will be described later. That is, the gate layer (151, 152, 154, 155 and 156) includes the first driving low voltage line 156, the second data layer (191, 195 and 196) includes the second driving low voltage line 196, and the first data layer (171, 172, 173, 174, 175, 176, 177 and 178) includes the driving low voltage connection portion 176 disposed between the gate layer (151, 152, 154, 155 and 156) and the second data layer (191, 195 and 196). This structure improves the contact characteristics. According to an exemplary embodiment, the driving low voltage connection portion 176 is omitted.

[0131] The gate electrode connection portion 177 plays a role of electrically connecting the second electrode of the second transistor T2 and the gate electrode 154 of the driving transistor T1. That is, the gate electrode connection portion 177 is connected to the second semiconductor 122 of the second transistor T2 through the opening 65, and is connected to the extended portion of the gate electrode 154 through the opening 67. According to an exemplary embodiment, since the gate electrode 154 and the second semiconductor 122 can be directly connected, the gate electrode connection portion 177 can be omitted.

[0132] The step-removed portion 178 has an island structure and is electrically connected to the extension portion of the third semiconductor 123 through the opening 68. The step-removed portion 178 is formed to prevent the superimposed second driving voltage line 195 or the second driving low voltage line 196 from being disconnected by the step. According to an exemplary embodiment, the step-removed portion 178 may be in a floating state, but in the present exemplary embodiment, the step-removed portion 178 receives the initialization voltage Vint.

[0133] The second interlayer insulating layer 14 covers the first data layers (171, 172, 173, 174, 175, 176, 177, and 178) and the first interlayer insulating layer 13. The second interlayer insulating layer 14 may be formed of an inorganic insulating material.

[0134] The second data layer (191, 195 and 196) is formed on the second interlayer insulating layer 14. The second data layer (191, 195 and 196) includes an anode connection portion 191, a second driving voltage line 195 and a second driving low voltage line 196.

[0135] The anode connection portion 191 has an island structure and is connected to the storage electrode 174 through the opening 81. Since the storage electrode 174 is connected to the second electrode (output side electrode) of the driving transistor T1, the second electrode (output side electrode) of the driving transistor T1 is to be electrically connected to the anode 201 which is one side electrode of the organic light emitting diode OLED, and the anode connection portion 191 is formed for this purpose.

[0136] The second driving voltage line 195 extends in the second direction (longitudinal direction) to transmit the driving voltage ELVDD in the second direction. In one embodiment, the second driving voltage line 195 is wider than the width of one pixel PX. The second driving voltage line 195 is connected to the driving voltage connection portion 175 through the opening 82, and is connected to the first driving voltage line 155 through the driving voltage connection portion 175. Hereinafter, the second driving voltage line 195 is referred to as a longitudinal driving voltage line. In an exemplary embodiment, the second driving voltage line 195 is formed outside the region where the anode connection portion 191 is formed according to the position, and has an opening 197 (hereinafter also referred to as an anode connection portion opening) corresponding to the anode connection portion 191. The second driving voltage line 195 has a structure in which the width is reduced at a portion where the anode connection portion 191 is provided. In one embodiment, the width of the second driving voltage line 195 is greater than the width of the anode 201 formed thereon.

[0137] In an exemplary embodiment, the driving voltage ELVDD has a constant voltage applied through the first driving voltage line 155 in a horizontal direction and through the second driving voltage line 195 in a longitudinal direction, so that a constant voltage is applied to each pixel PX.

[0138] The second driving low voltage line 196 extends in the second direction (longitudinal direction) to transmit the driving low voltage ELVSS in the second direction, and is spaced apart from the second driving voltage line 195 by a certain distance. Hereinafter, the second driving low voltage line 196 is also referred to as a longitudinal driving low voltage line. The second driving low voltage line 196 is connected to the driving low voltage connection portion 176 and the first driving low voltage line 156 through the opening 87. Figure 4 , the openings 87 are collectively referred to as two openings formed at the same position, at which the first opening 87 connects the first driving low voltage line 156 and the driving low voltage connection portion 176 , and the second opening 87 connects the driving low voltage connection portion 176 and the second driving low voltage line 196 .

[0139] In an exemplary embodiment, the width of the second driving low voltage line 196 is equal to the width of one anode 201. In an exemplary embodiment, the width of the second driving low voltage line 196 is greater than at least half the width of the anode 201. In addition, the second driving low voltage line 196 has a structure in which the width is partially reduced at a portion where the anode connection portion 191 is provided.

[0140] In an exemplary embodiment, the driving low voltage ELVSS has a constant voltage applied through the first driving low voltage line 156 in a horizontal direction and through the second driving low voltage line 196 in a longitudinal direction, so that a constant voltage may be applied at each pixel PX.

[0141] The upper insulating layer 15 is formed on the second data layer (191, 195, and 196) and the second interlayer insulating layer 14. The upper insulating layer 15 may be formed of an organic insulating material, and has a feature of removing and planarizing steps.

[0142] The pixel electrode layer ( 201 and 206 ) is disposed on the upper insulating layer 15 , and the pixel electrode layer ( 201 and 206 ) includes an anode 201 and a cathode connection portion 206 .

[0143] The anode 201, which is one side electrode of the organic light emitting diode OLED, transfers the current output from the driving transistor T1 to the organic emission layer 350. In order to receive the output current from the driving transistor T1, the anode 201 is connected to the anode connection portion 191 through the opening 91, and is connected to the storage electrode 174 through the opening 81. The size and shape of the anode 201 may be different for each adjacent pixel PX.

[0144] The cathode connection portion 206 is a connection portion that allows the driving low voltage ELVSS to be applied to the cathode 310, which is the other side electrode of the organic light emitting diode OLED. The cathode connection portion 206 is electrically connected to the second driving low voltage line 196 through the opening 92, and is also electrically connected to the cathode 310 described later.

[0145] The partition 300 is formed between adjacent anodes 201 . The partition 300 has an opening 301 exposing the anode 201 , and the organic emission layer 350 may be disposed within the opening 301 .

[0146] The cathode 310 is disposed on the organic emission layer 350 and the partition 300. The partition 300 further includes an opening 302 exposing the cathode connection portion 206. The cathode 310 is connected to the cathode connection portion 206 through the opening 302 and receives the driving low voltage ELVSS.

[0147] According to the above structure, the second driving voltage line 195 and the second driving low voltage line 196 are formed under the anode 201 and overlap the anode 201. The portion where the anode 201 overlaps with the second driving voltage line 195 forms a first additional capacitor Ca, and the portion where the anode 201 overlaps with the second driving low voltage line 196 forms a second additional capacitor Cb.

[0148] Due to the different components, Figures 3 to 5is complex, so by Figure 6 The structure of the additional capacitors Ca and Cb is described.

[0149] Figure 6 It only shows the Figure 3 A layout view of an area of ​​a pixel of an organic light emitting diode display of an exemplary embodiment, particularly embodying a specific layer in a pixel.

[0150] Figure 6 The second data layer (191, 195 and 196) and the pixel electrode layer (201 and 206) are mainly shown, and a first driving voltage line 155 to which a driving voltage ELVDD is applied and a first driving low voltage line 156 to which a driving low voltage ELVSS is applied are additionally shown.

[0151] refer to Figure 6 , the anode 201 has different areas for adjacent pixels PX. The first pixel PX shown on the far left has an anode 201a whose edge width is reduced due to the cathode connection part 206, and the third pixel PX shown on the far right has an anode 201c whose edge width is reduced due to the cathode connection part 206. On the other hand, the anode 201b of the second pixel PX disposed in the middle has an angular structure of a corner portion. However, according to an exemplary embodiment, the central portions of the anodes 201a and 201c of the first pixel PX and the third pixel PX are narrower than the anode 201b of the second pixel PX. As a result, the capacitances of the additional capacitors Ca and Cb of all pixels PX can be the same.

[0152] In addition, the second pixel PX disposed at the center of the three pixels PX has only the first additional capacitor Ca as an additional capacitor. That is, the anode 201b of the second pixel PX overlaps only the second driving voltage line 195, thereby forming only the first additional capacitor Ca. In an exemplary embodiment, anodes 201a and 201c of the first pixel PX and the third pixel PX partially overlap the second driving low voltage line 196, and partially overlap the second driving voltage line 195, thereby having the first additional capacitor Ca and the second additional capacitor Cb.

[0153] However, all three pixels PX may have additional capacitors Ca and Cb to compensate for the problem of reducing the capacity of the storage capacitor Cst when the organic light emitting diode display is adjusted to a high resolution.

[0154] refer to Figure 6, the driving voltage ELVDD is applied in a mesh shape through the first driving voltage line 155 and the second driving voltage line 195, and the driving low voltage ELVSS is applied in a mesh shape through the first driving low voltage line 156 and the second driving low voltage line 196. Thus, even if the pixel PX is far away from the portion to which the driving voltage ELVDD and the driving low voltage ELVSS are applied due to the large size of the organic light emitting diode display, a constant voltage can be applied.

[0155] In the following, reference Figure 7 and Figure 8 describe Figure 3 A variant exemplary embodiment of .

[0156] exist Figure 7 and Figure 8 In an exemplary embodiment of Figure 3 Differently, it has such a feature that an additional opening 198 (hereinafter also referred to as an opening for parasitic capacitance) is formed in the second driving voltage line 195 .

[0157] Figure 7 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept, and Figure 8 It only shows the Figure 7 A layout view of an area of ​​a pixel of an organic light emitting diode display of an exemplary embodiment, particularly embodying a specific layer in a pixel.

[0158] refer to Figure 8 , an additional opening 198 is formed in the second driving voltage line 195, so that the overlapping area of ​​the anode 201 and the second driving voltage line 195 is reduced. In this case, there may be a disadvantage that the capacitance of the first additional capacitor Ca is reduced. However, since the anode 201 overlaps with the first data layer (171, 172, 173, 174, 175, 176, 177 and 178) or the gate layer (151, 152, 154, 155 and 156), a parasitic capacitance can be formed to compensate for the insufficient capacitance of the storage capacitor Cst. In addition, in this case, the second driving voltage line 195 can reduce the signal delay problem caused by the parasitic capacitance caused by overlapping with the first data layer (171, 172, 173, 174, 175, 176, 177 and 178) or the gate layer (151, 152, 154, 155 and 156).

[0159] According to an exemplary embodiment, the additional opening 198 formed in the second driving voltage line 195 may be replaced with a plurality of openings.

[0160] Furthermore, according to an exemplary embodiment, an additional opening 198 is also formed in the second driving low voltage line 196 .

[0161] As described above, the pixel PX of the organic light emitting diode display according to an exemplary embodiment of the inventive concept has the additional capacitors Ca and Cb, and can overcome the insufficient capacitance of the storage capacitor Cst due to the reduction in pixel size due to the increase in overlapping capacitors.

[0162] Hereinafter, an additional capacitor and an overlapping capacitor in another pixel structure will be described.

[0163] Fig. 9 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0164] refer to Fig. 9 , a pixel PX of the organic light emitting diode display includes a plurality of transistors T1 , T2 and T3 , a storage capacitor Cst, additional capacitors Ca and Cb, and an organic light emitting diode OLED, which are connected to a plurality of signal lines 151 , 152 , 171 , 173 , 155 and 156 .

[0165] according to Fig. 9 The organic light emitting diode display of the exemplary embodiment of FIG. 1 shows an organic light emitting diode display that can be used at a high resolution of 4K. Figure 1 Unlike the exemplary embodiment of FIG. 1 , only one data line 171 is formed for one pixel row. In addition, the scan lines 151 do not constitute a pair of scan lines receiving the same signal, so only one scan line receives the signal.

[0166] The plurality of transistors T1, T2, and T3 included in one pixel PX include a driving transistor T1 (i.e., a first transistor), a switching transistor T2 (i.e., a second transistor) connected to the scan line 151, and an initialization transistor T3 (i.e., a third transistor or a sensing transistor) connected to the previous scan line 152. The third transistor T3 may be connected to a signal line to which a gate-on voltage is applied at a timing different from that of the previous scan line 152.

[0167] The plurality of signal lines 151 , 152 , 171 , 173 , 155 and 156 included in one pixel PX may include a scan line 151 , a previous scan line 152 , a data line 171 , an initialization voltage line 173 (referred to as a sensing line), a driving voltage line 155 and a driving low voltage line 156 .

[0168] The scan line 151 is connected to a gate driver (not shown) to transmit the scan signal Sn to the second transistor T2.

[0169] The previous scan line 152 is connected to the gate driver, and transmits a previous scan signal S(n−1) applied to the pixel PX disposed at a previous stage to the third transistor T3 .

[0170] The data line 171 is a wiring for transmitting a data voltage Dm generated from a data driver (not shown), and one data line 171 is formed for one pixel column. One data line 171 and one scan line 151 select one pixel to input the data voltage Dm. The brightness of light emitted by an organic light emitting diode OLED (referred to as an organic light emitting element) varies according to the data voltage Dm supplied to the pixel PX.

[0171] The driving voltage line 155 applies a driving voltage ELVDD, and the driving low voltage line 156 applies a driving low voltage ELVSS. The driving voltage line 155 and the driving low voltage line 156 according to the present exemplary embodiment are wirings extending in the longitudinal direction, and are respectively referred to as a longitudinal driving voltage line and a longitudinal driving low voltage line. In an exemplary embodiment, the voltage applied to the driving voltage line 155 and the driving low voltage line 156 is a constant voltage. The driving voltage ELVDD acts as an input voltage to generate an output current in the driving transistor T1, and when the output current is applied to the anode of the organic light emitting diode OLED, the driving low voltage ELVSS is applied to the cathode electrode of the organic light emitting diode OLED.

[0172] Hereinafter, a plurality of transistors T1 , T2 , and T3 will be described.

[0173] First, the driving transistor T1 is a transistor that controls the size of the current output according to the data voltage Dm applied to the gate electrode, so that the output driving current Id is applied to the organic light emitting diode OLED and controls the brightness of the organic light emitting diode OLED according to the data voltage Dm. To this end, the first electrode (input side electrode) of the driving transistor T1 is configured to receive the driving voltage ELVDD, and the second electrode (output side electrode) is connected to the first electrode (hereinafter referred to as the anode or pixel electrode) of the organic light emitting diode OLED. In addition, the gate electrode of the driving transistor T1 is connected to the second electrode (output side electrode) of the second transistor T2 to receive the data voltage Dm.

[0174] In an exemplary embodiment, the gate electrode of the driving transistor T1 is connected to one electrode of the storage capacitor Cst. The storage capacitor Cst ensures that the data voltage Dm transmitted to the gate electrode of the driving transistor T1 is maintained for one frame period. Therefore, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and therefore, the driving current Id output from the driving transistor T1 changes and is constantly output for one frame period.

[0175] In addition, the driving transistor T1 according to the exemplary embodiment also includes an overlapping layer 115 below the semiconductor layer in which the channel is provided. The overlapping layer 115 overlaps the channel and the gate electrode of the driving transistor T1, thereby improving the characteristics of the driving transistor T1 and maintaining the voltage of the gate electrode. Since the overlapping layer 115 overlaps with the gate electrode, the voltage of the gate electrode is maintained, thereby supplementing the capacitance of the storage capacitor Cst. Hereinafter, the capacitor formed by the overlap between the overlapping layer 115 and the gate electrode of the driving transistor T1 is referred to as an overlapping capacitor (not shown). The overlapping layer 115 is electrically connected to the second electrode (output side electrode) of the driving transistor T1, whereby the overlapping layer 115 is also connected to the anode of the resulting organic light emitting diode OLED.

[0176] The second transistor T2 (hereinafter referred to as a switching transistor) is a transistor that receives a data voltage Dm as an input to the pixel PX. The gate electrode of the second transistor T2 is connected to the scan line 151, the first electrode of the second transistor T2 is connected to the data line 171, and the second electrode (output side electrode) of the second transistor T2 is connected to the gate electrode of the driving transistor T1. If the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the gate electrode of the driving transistor T1 and stored in the storage capacitor Cst.

[0177] The third transistor T3 (hereinafter referred to as the initialization transistor or the sensing transistor) plays the role of initializing the second electrode (output side electrode) of the driving transistor T1, one electrode of the storage capacitor Cst, and the anode of the organic light emitting diode OLED. The gate electrode of the third transistor T3 is connected to the previous scanning line 152, and the first electrode of the third transistor T3 is connected to the initialization voltage line 173. The second electrode of the third transistor T3 is electrically connected to the second electrode (output side electrode) of the driving transistor T1, and is thereby also connected to the anode of the organic light emitting diode OLED and the overlapping layer 115.

[0178] The initialization voltage line 173 not only provides an initialization voltage but also serves as a wiring (eg, a sensing line) for sensing a voltage of an anode of the organic light emitting diode OLED connected to a second electrode of the third transistor T3 during a sensing period. Thus, the third transistor T3 is also referred to as a sensing transistor.

[0179] The operation of the third transistor T3 is now described. The voltage of the anode of the organic light emitting diode OLED when the organic light emitting diode OLED emits light during the light emission period is stored on one electrode of the storage capacitor Cst. At this time, the data voltage Dm is stored in the other electrode of the storage capacitor Cst. At this time, if the gate-on voltage is applied to the gate electrode of the third transistor T3, the initialization voltage line 173 operates as a sensing line, and the voltage of the anode is transmitted to the sensing unit (not shown) through the sensing line. Hereinafter, this is referred to as a sensing period. Next, during the reset period in which the gate-on voltage is applied to the gate electrode of the third transistor T3, the initialization voltage line 173 applies an initialization voltage Vint to initialize the voltage of the anode. Hereinafter, this is referred to as an initialization period.

[0180] If the voltage detected in the sensing period is different from the voltage of the anode electrode expected when determined based on the applied data voltage Dm, the data voltage Dm can be modified to be provided to the pixel PX. That is, the characteristics of the driving transistor T1 can be changed, and the organic light emitting diode OLED can emit normal light by sensing the change and providing the data voltage Dm corresponding thereto.

[0181] That is, during one frame period, the two electrodes of the storage capacitor Cst may play a role in maintaining the data voltage Dm and the voltage of the anode of the organic light emitting diode OLED (the output side electrode voltage of the driving transistor T1 ).

[0182] Since an area occupied by a pixel PX and an area for forming a storage capacitor Cst in the pixel PX are small in a high-resolution organic light emitting diode display, insufficient storage capacitance may be maintained for one frame period.

[0183] Therefore, the pixel PX of at least one exemplary embodiment of the inventive concept further includes the first additional capacitor Ca and the second additional capacitor Cb so as to have sufficient storage capacitance to maintain the voltage of the anode of the organic light emitting diode OLED for one frame period.

[0184] The first additional capacitor Ca has one side electrode connected to the anode of the organic light emitting diode OLED and the other side electrode to which the driving voltage ELVDD is applied, thereby maintaining the voltage of the anode of the organic light emitting diode OLED.

[0185] Furthermore, since the second additional capacitor Cb has one side electrode connected to the anode of the organic light emitting diode OLED and the other side electrode to which the driving low voltage ELVSS is applied, the second additional capacitor Cb also functions to maintain the voltage of the anode of the organic light emitting diode OLED.

[0186] Therefore, the capacitor included in one pixel PX has a storage capacitor Cst and additional capacitors Ca and Cb, thereby ensuring sufficient storage capacitance to maintain the voltage of the anode of the organic light emitting diode OLED during one frame period. In addition, according to an exemplary embodiment of the inventive concept, an overlapping capacitor formed by the overlapping layer 115 is further included.

[0187] according to Fig. 9 The organic light emitting diode display of the exemplary embodiment may receive Figure 2 The same signal in .

[0188] Reference now Figure 2 describe Fig. 9 Pixel operations.

[0189] First, during the sensing / initial period, a high level previous scan signal S(n-1) is supplied to the pixel PX through the previous scan line 152. Then, the third transistor T3 receiving the previous scan signal S(n-1) is turned on. At this time, the voltage stored in the anode of the organic light emitting diode OLED is confirmed through the initialization voltage line 173 (sensing period), and then the voltage of the anode of the organic light emitting diode OLED is changed to the initialization voltage Vint to be initialized (initialization period).

[0190] When the characteristic of the driving transistor T1 changes while the driving transistor T1 provided at each pixel PX has a different threshold voltage Vth due to process dispersion or operates during a long period in a sensing period, the change is sensed so that the organic light emitting diode OLED normally emits light.

[0191] Next, during the data writing period, a high-level scan signal Sn is supplied to the pixel PX through the scan line 151. The second transistor T2 is turned on by the high-level scan signal Sn. If the second transistor T2 is turned on, the data voltage Dm is input to the gate electrode of the driving transistor T1 via the second transistor T2 and stored in one side electrode of the storage capacitor Cst.

[0192] The turn-on degree of the driving transistor T1 is determined according to the data voltage Dm applied to the gate electrode, and the driving transistor T1 outputs the driving voltage ELVDD input to the first electrode to be transmitted to the anode electrode of the organic light emitting diode OLED.

[0193] The voltage of the anode electrode of the organic light emitting diode OLED is stored in the additional capacitors Ca and Cb or the overlap capacitor and the storage capacitor Cst, and is maintained during one frame period.

[0194] In the above, through Fig. 9 Mainly describes the circuit structure.

[0195] In the following, reference Figures 10 to 12 How to implement the pixel PX according to an exemplary embodiment is described.

[0196] Fig.10 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept, and Fig.11 and Fig.12 is along Fig.10 Cross-sectional views taken along lines XI-XI and XII-XII in an exemplary embodiment of the present invention.

[0197] refer to Figures 10 to 12 In the organic light emitting diode display according to an exemplary embodiment, an overlapping layer 115, a semiconductor layer (121, 122 and 123), a gate layer (151, 152, 153, 154, 157 and 158), a second gate layer (storage electrode 161), a first data layer (171, 173, 155, 156, 182, 183, 184 and 185), a pixel electrode layer (192, 192-1 and 207), an organic light emitting layer (not shown) and a common electrode (not shown) are respectively formed on a substrate 110, and these layers are insulated from each other by an insulating layer therebetween unless they are connected through an opening.

[0198] The substrate 110 may be formed as a glass substrate or a flexible substrate including plastic or polyimide (PI). When the substrate 110 is formed as a flexible substrate, an additional inorganic insulating layer may be further formed unlike the case of a glass substrate.

[0199] The overlapping layer 115 formed on the substrate 110 is now described. The overlapping layer 115 includes an overlapping portion overlapping the channel of the driving transistor T1 and a connecting portion. The connecting portion of the overlapping layer 115 is connected to the storage electrode 161 described later. Since the storage electrode 161 has the voltage of the anode (192 and 192-1) of the organic light emitting diode OLED, the overlapping layer 115 also has the voltage of the anode (192 and 192-1).

[0200] The buffer layer 11 covers the substrate 110 and the overlapping layer 115. The buffer layer 11 may be formed of an inorganic insulating material.

[0201] The semiconductor layers (121, 122, and 123) are formed on the buffer layer 11. Each semiconductor layer (121, 122, and 123) includes a channel of a driving transistor T1, a second transistor T2, and a third transistor T3. The semiconductor layers (121, 122, and 123) according to an exemplary embodiment are formed of an oxide semiconductor. Each semiconductor layer (121, 122, and 123) includes a channel of each transistor T1, T2, and T3 and a source region / drain region disposed on both sides of the channel. The source region / drain region of each semiconductor layer (121, 122, and 123) extends and is electrically connected to different layers through an opening, respectively.

[0202] The gate insulating layer 12 covers the semiconductor layers (121, 122, and 123) and the buffer layer 11. The gate insulating layer 12 may be formed of an inorganic insulating material.

[0203] The gate layer (151, 152, 153, 154, 157 and 158) is formed on the gate insulating layer 12. The gate layer (151, 152, 153, 154, 157 and 158) includes a scan line 151, a previous scan line 152, an initialization voltage transfer part 153, a gate electrode 154 of the driving transistor T1, a gate electrode 157 of the second transistor T2 and a gate electrode 158 of the third transistor T3.

[0204] The scan line 151 extends in a first direction (lateral direction), and the preceding scan line 152 also extends in the first direction (lateral direction).

[0205] The initialization voltage transmission portion 153 has a long island shape in the first direction. The initialization voltage transmission portion 153 is a structure for connecting the initialization voltage line 173 formed for a predetermined number of pixel columns and a plurality of pixels PX. That is, the initialization voltage transmission portion 153 passes through adjacent pixels PX and extends to a position where the initialization voltage line 173 is formed. In the present exemplary embodiment, one initialization voltage line 173 is formed for every three pixels PX.

[0206] The gate electrode 154 of the driving transistor T1 includes an overlapping portion overlapping the first semiconductor 121 in which the channel of the driving transistor T1 is disposed, an extending portion extending from the overlapping portion, and an extending portion connected to the second semiconductor 122 of the second transistor T2. In an exemplary embodiment, only the overlapping portion of the gate electrode 154 of the driving transistor T1 performs the role of the gate electrode, and the extending portion forms one side electrode of the storage capacitor Cst. The extending portion of the gate electrode 154 overlaps with the extending portion of the overlapping layer 115 to form an overlapping capacitor. The extending portion of the gate electrode 154 is connected to the second semiconductor 122 of the second transistor T2 through the opening 74, and receives the data voltage Dm from the second electrode of the second transistor T2.

[0207] The gate electrode 157 of the second transistor T2 has an island structure and overlaps the second semiconductor 122 of the second transistor T2. The channel of the second transistor T2 is formed at a position where the second semiconductor 122 and the gate electrode 157 overlap. The gate electrode 157 is electrically connected to the scan line 151 through the second gate electrode connection portion 182.

[0208] The gate electrode 158 of the third transistor T3 has an island structure and overlaps the third semiconductor 123 of the third transistor T3. The channel of the third transistor T3 is formed at a position where the third semiconductor 123 and the gate electrode 158 overlap. The gate electrode 158 is electrically connected to the previous scan line 152 through the third gate electrode connection portion 183.

[0209] The second gate insulating layer 12-1 covers the gate layers (151, 152, 153, 154, 157, and 158) and the gate insulating layer 12. The second gate insulating layer 12-1 may be formed of an inorganic insulating material.

[0210] The second gate layer (storage electrode 161 ) is disposed on the second gate insulating layer 12 - 1 , and the second gate layer (storage electrode 161 ) includes the storage electrode 161 .

[0211] The storage electrode 161 has an extending portion overlapping with the extending portion of the gate electrode 154 of the driving transistor T1, and includes a first extending portion and a second extending portion extending upward and downward from the extending portion, respectively. The first extending portion extending downward from the extending portion of the storage electrode 161 is connected to the second electrode (output side electrode) of the driving transistor T1 and the overlapping layer 115 through openings 61 and 71. The second extending portion extending upward from the extending portion of the storage electrode 161 is connected to the anode connecting portion 185 through an opening 84. The extending portion of the storage electrode 161 overlaps with the gate electrode 154 to form a storage capacitor Cst. The extending portion of the storage electrode 161 and the extending portion of the gate electrode 154 occupy a large area in the pixel PX, but reduce the area in which the pixel PX is formed with high resolution, thereby causing a problem of insufficient capacitance of the storage capacitor Cst. In order to prevent this problem, additional capacitors Ca and Cb are further formed, and Fig.10 An additional capacitor Cb is formed in the pixels provided on both sides of . This will be described later.

[0212] The first interlayer insulating layer 13 covers the second gate layer (storage electrode 161) and the second gate insulating layer 12-1. The first interlayer insulating layer 13 may be formed of an inorganic insulating material.

[0213] A first data layer (171, 173, 155, 156, 182, 183, 184 and 185) is formed on the first interlayer insulating layer 13. The first data layer (171, 173, 155, 156, 182, 183, 184 and 185) includes a data line 171, an initialization voltage line 173, a driving voltage line 155, a driving low voltage line 156, a second gate electrode connection part 182, a third gate electrode connection part 183, an initialization voltage second transmission part 184 and an anode connection part 185.

[0214] The data line 171 is formed for each pixel column and extends in a second direction (longitudinal direction) perpendicular to the first direction. The data line 171 is connected to the second semiconductor 122 of the second transistor T2 through the opening 60 and applies the data voltage Dm to the second transistor T2.

[0215] The initialization voltage line 173 extends in the second direction and applies the initialization voltage Vint. The initialization voltage line 173 is not formed for each pixel column, and in the present exemplary embodiment, one initialization voltage line 173 is formed for three pixel columns. The initialization voltage line 173 is connected to the initialization voltage transmission part 153 through the opening 63, and the initialization voltage transmission part 153 is connected to the initialization voltage second transmission part 184 through the opening 79. The initialization voltage second transmission part 184 is connected to the third semiconductor 123 of the third transistor T3 via the opening 78. Thus, the initialization voltage Vint is applied to the first electrode of the third transistor T3 of each pixel.

[0216] The driving voltage line 155 and the driving low voltage line 156 extend in the second direction. The driving voltage line 155 is set for each pixel column, but the driving low voltage line 156 is set for three pixel columns. The driving voltage line 155 transmits the driving voltage ELVDD and is connected to the first semiconductor 121 of the driving transistor T1 through the opening 75 to transmit the driving voltage ELVDD to the first electrode of the driving transistor T1. In an exemplary embodiment, the driving voltage line 155 has a narrower width than the driving low voltage line 156. In addition, the driving low voltage line 156 may have a narrower width in an area overlapping with a wiring set in another layer. Fig.10 In the embodiment, the driving voltage line 155 has a narrow width at a portion overlapping the scan line 151. The driving low voltage line 156 having a wide width is used to form an electrical connection to transmit the driving low voltage ELVSS to the structure overlapping the cathode electrode. That is, a certain degree of width is required for electrical connection by forming a contact using a laser or the like.

[0217] Although not in Fig.10As shown in FIG. 1 , the driving voltage line 155 may further include a lateral driving low voltage line (not shown). The lateral driving low voltage line is disposed between vertically adjacent pixels and may be electrically connected to the driving voltage line 155 .

[0218] The second gate electrode connection portion 182 has an island shape and overlaps the scan line 151 and the gate electrode 157 of the second transistor T2. The second gate electrode connection portion 182 is connected to the scan line 151 and the gate electrode 157 of the second transistor T2 through the openings 72 and 73, respectively, and transmits the scan signal Sn applied to the scan line 151 to the gate electrode 157 of the second transistor T2.

[0219] The third gate electrode connection portion 183 has an island shape and overlaps the previous scan line 152 and the gate electrode 158 of the third transistor T3. The third gate electrode connection portion 183 is connected to the gate electrode 158 of the third transistor T3 and the previous scan line 152 through the openings 76 and 77, respectively, and transmits the previous scan signal S(n-1) applied to the previous scan line 152 to the gate electrode 158 of the third transistor T3.

[0220] The anode connection portion 185 is connected to the second extension portion of the storage electrode 161 through the opening 84, and is connected to the anode (192 and 192-1) through the opening 81. Thus, the output current of the driving transistor T1 is transferred to the anode (192 and 192-1).

[0221] The upper insulating layer 15 is disposed on the first data layer (171, 173, 155, 156, 182, 183, 184, and 185) and the first interlayer insulating layer 13. The upper insulating layer 15 is formed of an organic insulating material and has a feature of removing and planarizing steps.

[0222] The pixel electrode layer ( 192 , 192 - 1 , and 207 ) is disposed on the upper insulating layer 15 , and the pixel electrode layer ( 192 , 192 - 1 , and 207 ) includes an anode ( 192 and 192 - 1 ) and a cathode connection portion 207 .

[0223] The anode (192 and 192-1) as one side electrode of the organic light emitting diode OLED transmits the current output from the driving transistor T1 to the organic emission layer. In order to receive the output current from the driving transistor T1, the anode (192 and 192-1) is connected to the anode connection portion 185 through the opening 81, and the anode connection portion 185 is connected to the storage electrode 161 through the opening 84.

[0224] refer to Fig.10The anode (192 and 192-1) includes an anode portion 192 overlapping the organic emission layer and an extension portion 192-1 (hereinafter referred to as an additional capacitor extension portion) passing over the driving voltage line 155 and extending over the driving low voltage line 156. The extension portion 192-1 of the anode (192 and 192-1) is formed outside the region where the cathode connection portion 207 is provided, overlaps the driving voltage line 155 to form a first additional capacitor Ca, and overlaps the driving low voltage line 156 to form a second additional capacitor Cb.

[0225] exist Fig.10 , it is clearly shown that for each adjacent pixel PX, the anode (192 and 192-1) has a different area. The first pixel PX shown on the far left has an extension portion 192-1 of the anode (192 and 192-1), whose edge width is reduced due to the cathode connection portion 207, and the third pixel PX shown on the far right has an extension portion 192-1 of the anode (192 and 192-1), whose edge width is reduced due to the cathode connection portion 207. In an exemplary embodiment, the second pixel PX disposed in the middle has an anode portion 192 but does not include an extension portion 192-1 of the anode (192 and 192-1). However, according to an exemplary embodiment, the central portion of the anode (192 and 192-1) of the first pixel PX and the third pixel PX is narrower than the anode (192 and 192-1) of the second pixel PX. Thus, the capacitances of the additional capacitors Ca and Cb of all pixels PX may be the same.

[0226] However, since the driving low voltage line 156 is formed every three pixel columns, some pixels may not include the extension portion 192-1 that forms the anode of the additional capacitors Ca and Cb. In addition, according to an exemplary embodiment, the driving low voltage line 156 is not disposed at a portion adjacent to the anode portion 192, and the anode portion 192 may extend only over the driving voltage line 155 to form only the first additional capacitor Ca in the pixel PX in which only the driving voltage line 155 is disposed.

[0227] According to an exemplary embodiment, the anode portion 192 extends over the initialization voltage line 173 to form an additional capacitor.

[0228] The cathode connection portion 207 is a connection portion so that the driving low voltage ELVSS can be applied to the cathode electrode which is the other side electrode of the organic light emitting diode OLED. The cathode connection portion 207 is electrically connected to the driving low voltage line 156 through the opening 86 .

[0229] Although not shown, a partition is formed between the adjacent anode portions 192 and the extension portions 192-1. The partition has an opening exposing the anode (192 and 192-1), and the organic emission layer may be disposed within the opening.

[0230] In one embodiment, the cathode electrode of the organic light emitting diode OLED is disposed on the organic emission layer and the partition. The partition further includes an opening exposing the cathode connection portion 207. The cathode is connected to the exposed cathode connection portion 207 to receive the driving low voltage ELVSS.

[0231] According to the above structure, the extension portion 192-1 of the anode (192 and 192-1) and the driving low voltage line 156 overlap to form additional capacitors Ca and Cb. According to an exemplary embodiment, a capacitor may be formed by overlapping the extension portion 192-1 of the anode (192 and 192-1) and the initialization voltage line 173. Thus, the voltage of the anode (192 and 192-1) may be maintained.

[0232] Next, refer to Fig.13 and Fig.14 right Fig.10 Exemplary variations of the exemplary embodiments of are described. Fig.13 In an exemplary embodiment of Fig.10 Differently, the driving low voltage line is formed as a double layer.

[0233] Fig.13 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept, and Fig.14 It is along Fig.13 A cross-sectional view taken along line XIV-XIV in an exemplary embodiment of the present invention.

[0234] and Fig.10 The exemplary embodiments are different. Fig.13 The exemplary embodiment of the present invention further includes a second data layer, and it further includes a second interlayer insulating layer 14 to insulate the second data layer from other layers.

[0235] That is, the second interlayer insulating layer 14 covers the first data layer (171, 173, 155, 156, 182, 183, 184, and 185). The second interlayer insulating layer 14 may be formed of an inorganic insulating material.

[0236] The second data layer ( 176 - 1 ) is formed on the second interlayer insulating layer 14 , and the second data layer ( 176 - 1 ) includes a second driving low voltage line 176 - 1 .

[0237] The second driving low voltage line 176-1 overlaps with the driving low voltage line 156 and extends in the second direction. The second driving low voltage line 176-1 and the driving low voltage line 156 are connected through the opening 86-1. Like the driving low voltage line 156, the second driving low voltage line 176-1 is also provided for every three pixel columns. The second driving low voltage line 176-1 also transmits the driving voltage ELVDD, and various problems when the driving voltage ELVDD is transmitted only through the driving low voltage line 156 are eliminated. That is, when only the driving low voltage line 156 is formed, the second driving low voltage line 176-1 is connected to the driving low voltage line 156 through the opening 86-1. Figure 3 Unlike the exemplary embodiment of , its width is reduced, so the voltage drop due to resistance can be eliminated. Fig.13 In an exemplary embodiment of Figure 3 Unlike the exemplary embodiment of the present invention, the driving low voltage line 156 is not formed by a mesh structure including horizontal direction wiring and vertical direction wiring, but is formed only in the vertical direction. In this case, even if a voltage drop occurs in the driving low voltage ELVSS, the voltage drop can be reduced by the double-layer structure. Moreover, even if a set of wirings of a single layer is disconnected, the driving low voltage ELVSS can be applied through other layers.

[0238] The upper insulating layer 15 is formed on the second data layer 176-1 and the second interlayer insulating layer 14, as in Figures 10 to 12 Like in.

[0239] and Fig.10 Compared to the exemplary embodiment, Fig.13 The exemplary embodiment not only stably transmits the driving low voltage ELVSS, but also includes a second additional capacitor Cb, like in Fig.10 As in , therefore, the insufficient capacitance of the storage capacitor Cst in the high-resolution pixel can be compensated.

[0240] Next, refer to Fig.15 A pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept is described.

[0241] Fig.15 is an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0242] refer to Fig.15 , a pixel PX of the organic light emitting diode display includes a plurality of transistors T1 , T2 and T3 , a storage capacitor Cst, an additional capacitor Ca and an organic light emitting diode OLED, which are connected to a plurality of signal lines 151 , 152 , 171 , 173 , 155 and 156 .

[0243] according to Fig.15The organic light emitting diode display of the exemplary embodiment is an organic light emitting diode display used in a high-resolution display, and one pixel PX is controlled by one data line 171 and one scan line 151 .

[0244] First, the structure of one pixel PX is described.

[0245] The plurality of transistors T1, T2, and T3 included in one pixel PX include a driving transistor T1 (hereinafter referred to as a first transistor), a switching transistor T2 (e.g., a second transistor) connected to the scan line 151, and an initialization transistor T3 (e.g., a third transistor or a sensing transistor) connected to the previous scan line 152. The third transistor T3 may be connected to a signal line to which a gate-on voltage is applied at a timing different from that of the previous scan line 152.

[0246] The scan line 151 is connected to a gate driver (not shown) to transmit the scan signal Sn to the second transistor T2.

[0247] The previous scan line 152 is connected to the gate driver, and transmits a previous scan signal S(n−1) applied to the pixel PX disposed at a previous stage to the third transistor T3 .

[0248] The data line 171 is a wiring for transmitting a data voltage Dm generated by a data driver (not shown), and one data line 171 is formed for one pixel PX. One data line 171 and one scan line 151 select one pixel PX to input the data voltage Dm. The brightness of light emitted by the organic light emitting diode OLED varies according to the data voltage Dm provided in the pixel PX.

[0249] The driving voltage line 155 applies a driving voltage ELVDD, and the driving low voltage line 156 applies a driving low voltage ELVSS. The driving voltage line 155 and the driving low voltage line 156 according to the present exemplary embodiment are wirings extending in the longitudinal direction, and are respectively referred to as a longitudinal driving voltage line and a longitudinal driving low voltage line. In an exemplary embodiment, the voltage applied to the driving voltage line 155 and the driving low voltage line 156 is a constant voltage. The driving voltage ELVDD acts as an input voltage to generate an output current in the driving transistor T1, and when the output current is applied to the anode of the organic light emitting diode OLED, the driving low voltage ELVSS is applied to the cathode electrode of the organic light emitting diode OLED.

[0250] Hereinafter, a plurality of transistors T1 , T2 , and T3 will be described.

[0251] First, the driving transistor T1 is a transistor that controls the size of the current output according to the data voltage Dm applied to the gate electrode, so that the output driving current Id is applied to the organic light emitting diode OLED and controls the brightness of the organic light emitting diode OLED according to the data voltage Dm. To this end, the first electrode (input side electrode) of the driving transistor T1 is configured to receive the driving voltage ELVDD, and the second electrode (output side electrode) of the driving transistor T2 is connected to the first electrode (hereinafter referred to as the anode or pixel electrode) of the organic light emitting diode OLED. In addition, the gate electrode of the driving transistor T1 is connected to the second electrode (output side electrode) of the second transistor T2 to receive the data voltage Dm.

[0252] In an exemplary embodiment, the gate electrode of the driving transistor T1 is connected to one electrode of the storage capacitor Cst. The storage capacitor Cst ensures that the data voltage Dm transmitted to the gate electrode of the driving transistor T1 is maintained for one frame period. Therefore, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and therefore, the driving current Id output from the driving transistor T1 changes and is constantly output for one frame period.

[0253] In addition, the driving transistor T1 according to the exemplary embodiment further includes an overlapping layer 115 below the semiconductor layer in which the channel is provided. The overlapping layer 115 overlaps the channel and the gate electrode of the driving transistor T1, thereby improving the characteristics of the driving transistor T1 and maintaining the voltage of the gate electrode. Since the overlapping layer 115 overlaps the gate electrode, the voltage of the gate electrode is maintained, thereby supplementing the capacitance of the storage capacitor Cst. Hereinafter, the capacitor formed by the overlap between the overlapping layer 115 and the gate electrode of the driving transistor T1 is referred to as an overlapping capacitor (not shown). The overlapping layer 115 is electrically connected to the second electrode (output side electrode) of the driving transistor T1, whereby the overlapping layer 115 is also connected to the anode of the resulting organic light emitting diode OLED.

[0254] The second transistor T2 (hereinafter referred to as a switching transistor) is a transistor that receives a data voltage Dm as an input to the pixel PX. The gate electrode of the second transistor T2 is connected to the scan line 151, the first electrode of the second transistor T2 is connected to the data line 171, and the second electrode (output side electrode) of the second transistor T2 is connected to the gate electrode of the driving transistor T1. If the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the gate electrode of the driving transistor T1 and stored in the storage capacitor Cst.

[0255] The third transistor T3 (hereinafter referred to as the initialization transistor or the sensing transistor) plays the role of initializing the second electrode (output side electrode) of the driving transistor T1, one electrode of the storage capacitor Cst, and the anode of the organic light emitting diode OLED. The gate electrode of the third transistor T3 is connected to the previous scanning line 152, and the first electrode is connected to the initialization voltage line 173. The second electrode (output side electrode) of the third transistor T3 is electrically connected to the second electrode (output side electrode) of the driving transistor T1, and is thereby also connected to the anode of the organic light emitting diode OLED and the overlapping layer 115.

[0256] The initialization voltage line 173 not only provides an initialization voltage but also serves as a wiring (eg, a sensing line) for sensing a voltage of an anode of the organic light emitting diode OLED connected to a second electrode of the third transistor T3 during a sensing period. Thus, the third transistor T3 is also referred to as a sensing transistor.

[0257] The operation of the third transistor T3 is now described. The voltage of the anode of the organic light emitting diode OLED when the organic light emitting diode OLED emits light (emission period) is stored in one electrode of the storage capacitor Cst. The data voltage Dm is stored in the other electrode of the storage capacitor Cst. At this time, if the gate-on voltage is applied to the gate electrode of the third transistor T3, the initialization voltage line 173 operates as a sensing line, and the voltage of the anode is transmitted to the sensing unit (not shown) through the sensing line. Hereinafter, this is referred to as a sensing period. Next, in the reset period during which the gate-on voltage is applied to the gate electrode of the third transistor T3, the initialization voltage line 173 applies an initialization voltage Vint to initialize the voltage of the anode. Hereinafter, this is referred to as an initialization period.

[0258] If the voltage detected in the sensing period is different from the expected voltage of the anode when determined based on the applied data voltage Dm, the data voltage Dm can be modified to be provided to the pixel PX. That is, the characteristics of the driving transistor T1 can be changed, and the organic light emitting diode OLED can emit normal light by sensing the change and providing the data voltage Dm corresponding thereto.

[0259] That is, during one frame period, the two electrodes of the storage capacitor Cst may play a role in maintaining the data voltage Dm and the voltage of the anode of the organic light emitting diode OLED (the output side electrode voltage of the driving transistor T1 ).

[0260] Since the area occupied by the pixel PX of the organic light emitting diode display having a high resolution is small and the area for forming the storage capacitor Cst in the pixel PX is also small, sufficient storage capacitance may not be maintained for one frame period.

[0261] Therefore, the pixel PX of the present exemplary embodiment further includes an additional capacitor Ca so as to have sufficient storage capacitance to maintain the voltage of the anode electrode of the organic light emitting diode OLED for one frame period.

[0262] The first additional capacitor Ca has one side electrode connected to the anode of the organic light emitting diode OLED and the other side electrode to which the driving voltage ELVDD is applied, thereby maintaining the voltage of the anode of the organic light emitting diode OLED.

[0263] That is, the capacitor included in one pixel PX has the storage capacitor Cst and the first additional capacitor Ca, thereby ensuring storage capacitance for maintaining the voltage of the anode of the organic light emitting diode OLED during one frame period. In addition, according to an exemplary embodiment, an overlapping capacitor formed by the overlapping layer 115 may be further included.

[0264] Next, refer to Fig.15 and Fig.16 An operation of one pixel of an organic light emitting diode display according to an exemplary embodiment is described.

[0265] Fig.16 is a timing diagram of signals applied to one pixel of an organic light emitting diode display according to an exemplary embodiment of the inventive concept.

[0266] exist Fig.16 , the signal indicated by SCAN is a signal applied to the scan line 151, and the signal indicated by SENSING is a signal applied to the previous scan line 152.

[0267] First, during the sensing / initial period, a high level previous scan signal S(n-1) is supplied to the pixel PX through the previous scan line 152. Then, the third transistor T3 receiving the previous scan signal S(n-1) is turned on. At this time, the voltage stored in the anode of the organic light emitting diode OLED is confirmed through the initialization voltage line 173 (sensing period), and then the voltage of the anode of the organic light emitting diode OLED is changed to the initialization voltage Vint to be initialized (initialization period).

[0268] When the characteristic of the driving transistor T1 changes while the driving transistor T1 provided at each pixel PX has a different threshold voltage Vth due to process dispersion or operates during a long period in a sensing period, the change is sensed so that the organic light emitting diode OLED normally emits light.

[0269] Next, during the data writing period, a high-level scan signal Sn is supplied to the pixel PX through the scan line 151. The second transistor T2 is turned on by the high-level scan signal Sn. If the second transistor T2 is turned on, the data voltage Dm is input to the gate electrode of the driving transistor T1 via the second transistor T2 and stored in one side electrode of the storage capacitor Cst.

[0270] The turn-on degree of the driving transistor T1 is determined according to the data voltage Dm applied to the gate electrode, and the driving transistor T1 outputs the driving voltage ELVDD input to the first electrode to be transmitted to the anode electrode of the organic light emitting diode OLED.

[0271] The voltage of the anode electrode of the organic light emitting diode OLED is stored in the additional capacitors Ca and Cb or the overlap capacitor and the storage capacitor Cst, and is maintained during one frame period.

[0272] In the above, through Fig.15 and Fig.16 Mainly describes the circuit structure.

[0273] In the following, reference Figures 17 to 20 How to implement the pixel PX according to an exemplary embodiment is described.

[0274] Fig.17 is a layout view of a region of a pixel of an organic light emitting diode display according to an exemplary embodiment, and Fig.18 , Fig.19 and Fig. 20 It is along Fig.17 Cross-sectional views taken along lines XVIII-XVIII', XIX-XIX' and XX-XX' in an exemplary embodiment of FIG.

[0275] refer to Figures 17 to 20 In the organic light emitting diode display according to an exemplary embodiment, an overlay layer 115, semiconductor layers (121, 122 and 123), gate layers (151, 152, 153, 154, 157, 158 and 159), a second gate layer (161, 162, 163, 164, 165, 166 and 167), a first data layer (171, 173, 155, 156, 182, 183, 184 and 185), an anode 192, an organic light emitting layer (not shown) and a common electrode (not shown) are respectively formed on a substrate 110, and these layers are insulated from each other by an insulating layer therebetween unless they are connected through an opening.

[0276] The substrate 110 may be formed as a glass substrate or a flexible substrate including plastic or polyimide (PI). When the substrate 110 is formed as a flexible substrate, an additional inorganic insulating layer may be formed unlike the case of a glass substrate.

[0277] An overlapping layer 115 formed on the substrate 110 is described. The overlapping layer 115 includes an overlapping portion overlapping the channel of the driving transistor T1 and a connecting portion. The connecting portion of the overlapping layer 115 is connected to the storage electrode 161 described later. Since the storage electrode 161 receives the voltage of the anode 192, the overlapping layer 115 also receives the voltage of the anode 192. The overlapping layer 115 may form an overlapping capacitor in a region overlapping with the gate electrode 154 of the driving transistor T1.

[0278] The buffer layer 11 covers the substrate 110 and the overlapping layer 115. The buffer layer 11 may be formed of an inorganic insulating material.

[0279] The semiconductor layers (121, 122, and 123) are formed on the buffer layer 11. Each semiconductor layer (121, 122, and 123) includes a channel of a driving transistor T1, a second transistor T2, and a third transistor T3. The semiconductor layers (121, 122, and 123) according to the exemplary embodiment are formed of an oxide semiconductor. The first semiconductor 121 as the semiconductor layer of the driving transistor T1 includes a channel region and a source / drain region disposed on both sides of the channel region. The second semiconductor 122 as the semiconductor layer of the second transistor T2 includes a channel region and a source / drain region disposed on both sides of the channel region, and the third semiconductor 123 as the semiconductor layer of the third transistor T3 includes a channel region and a source / drain region disposed on both sides of the channel region.

[0280] The channel region of each semiconductor layer ( 121 , 122 , and 123 ) may be formed as two lines including an opening at the center of a quadrangle, or may be formed as one line connecting source / drain regions.

[0281] The source region / drain region of each semiconductor layer (121, 122, and 123) is electrically connected to the first electrode / second electrode (output side electrode), respectively. Also, the source region / drain region extends to be electrically connected to another layer through the opening.

[0282] The first gate insulating layer 12 covers the semiconductor layer (121, 122, and 123) and the buffer layer 11. The first gate insulating layer 12 may be formed of an inorganic insulating material.

[0283] The gate layer (151, 152, 153, 154, 157, 158 and 159) is formed on the first gate insulating layer 12. The gate layer (151, 152, 153, 154, 157, 158 and 159) includes a scan line 151, a previous scan line 152, an initialization voltage transfer part 153, a gate electrode 154 of the driving transistor T1, a gate electrode 157 of the second transistor T2, a gate electrode 158 of the third transistor T3 and a lateral driving voltage line 159.

[0284] The scan line 151 extends in a first direction (lateral direction), and the preceding scan line 152 also extends in the first direction (lateral direction).

[0285] The initialization voltage transmission portion 153 has a long island shape formed in the first direction (lateral direction). The initialization voltage transmission portion 153 is a structure for connecting the initialization voltage line 173 formed for a predetermined number of pixel columns and a plurality of pixels PX. That is, the initialization voltage transmission portion 153 passes through the pixels PX adjacent in the first direction (lateral direction) and extends to a position where the initialization voltage line 173 is formed. In the present exemplary embodiment, one initialization voltage line 173 is formed for three pixels PX1, PX2, and PX3.

[0286] The transverse driving voltage line 159 extends in the first direction (transverse direction) and crosses the driving voltage line 155 extending in the second direction (longitudinal direction). The transverse driving voltage line 159 is disposed between pixels PX adjacent in the second direction (longitudinal direction) and is electrically connected to the driving voltage line 155 through the opening 57 for each of the pixels PX1, PX2, and PX3 adjacent in the first direction (transverse direction).

[0287] The gate electrode 154 of the driving transistor T1 includes an overlapping portion overlapping the first semiconductor 121 in which the channel of the driving transistor T1 is disposed, an extending portion extending from the overlapping portion, and an extending portion connected to the second semiconductor 122 of the second transistor T2. In one embodiment, only the overlapping portion of the gate electrode 154 of the driving transistor T1 performs the role of the gate electrode, and the extending portion forms one side electrode of the storage capacitor Cst. The extending portion of the gate electrode 154 overlaps with the extending portion of the overlapping layer 115 to form an overlapping capacitor. The extending portion of the gate electrode 154 is connected to the second semiconductor 122 of the second transistor T2 through the openings 43, 44 and 58 and the second gate layer connecting portion 163, and receives the data voltage Dm from the second electrode of the second transistor T2.

[0288] Fig.17 Three pixels PX1, PX2 and PX3 are shown, and the gate electrode 154 of the driving transistor T1 of each of the pixels PX1, PX2 and PX3 can be formed into various sizes. Here, the three pixels PX1, PX2 and PX3 can respectively display one color of the three primary colors. For example, the pixel PX1 can display red, the pixel PX2 can display green, and the pixel PX3 can display blue.

[0289] The gate electrode 157 of the second transistor T2 has an island structure and overlaps the second semiconductor 122 of the second transistor T2. The channel of the second transistor T2 is formed at a position where the second semiconductor 122 and the gate electrode 157 overlap. The gate electrode 157 is electrically connected to the scan line 151 through the second gate electrode connection part 182 and the second gate layer connection part 162.

[0290] The gate electrode 158 of the third transistor T3 has an island structure and overlaps the third semiconductor 123 of the third transistor T3. The channel of the third transistor T3 is formed at a position where the third semiconductor 123 and the gate electrode 158 overlap. The gate electrode 158 is electrically connected to the previous scan line 152 through the third gate electrode connection part 183 and the second gate layer connection part 167.

[0291] The second gate insulating layer 12-1 covers the gate layers (151, 152, 153, 154, 157, 158, and 159) and the first gate insulating layer 12. The second gate insulating layer 12-1 may be formed of an inorganic insulating material.

[0292] The second gate layer (161, 162, 163, 164, 165, 166 and 167) is disposed on the second gate insulating layer 12-1, and the second gate layer (161, 162, 163, 164, 165, 166 and 167) includes a storage electrode 161 and second gate layer connection portions 162, 163, 164, 165, 166 and 167.

[0293] The storage electrode 161 has an extension portion overlapping the extension portion of the gate electrode 154 of the driving transistor T1, and includes a first extension portion and a second extension portion extending upward and downward from the extension portion, respectively. The first extension portion extending downward from the extension portion of the storage electrode 161 is connected to the second electrode (output side electrode) of the driving transistor T1 through the openings 49 and 50, and is connected to the overlapping layer 115 through the opening 71. The second extension portion extending upward from the extension portion of the storage electrode 161 is connected to the anode connection portion 185 through the opening 84. The extension portion of the storage electrode 161 overlaps with the gate electrode 154 to form a storage capacitor Cst.

[0294] The extension of the storage electrode 161 and the extension of the gate electrode 154 occupy a large area in the pixel PX, but the area in which the pixel PX is formed with high resolution is reduced, thereby causing a problem of insufficient capacitance of the storage capacitor Cst. In order to prevent this problem, an additional capacitor Ca is further formed, which will be described later.

[0295] The second gate layer connection portion 162 has an island structure and overlaps with the second gate electrode connection portion 182 and the gate electrode 157 of the second transistor T2. The second gate layer connection portion 162 is connected to the second gate electrode connection portion 182 and the gate electrode 157 of the second transistor T2 through the openings 46 and 45, respectively.

[0296] The second gate layer connection portion 163 has an island structure and overlaps the second electrode (output side electrode) in the region of the second semiconductor 122 of the second transistor T2 and the gate electrode 154 of the driving transistor T1. The second gate layer connection portion 163 is connected to the second electrode (output side electrode) in the region of the second semiconductor 122 of the second transistor T2 through the two openings 43 and 44, and is connected to the gate electrode 154 of the driving transistor T1 through the opening 58.

[0297] The second gate layer connection portion 164 has an island structure and overlaps the data line 171 and the first electrode in the region of the second semiconductor 122 of the second transistor T2. The second gate layer connection portion 164 is connected to the first electrode in the region of the second semiconductor 122 of the second transistor T2 through the two openings 41 and 42, and is connected to the data line 171 through the opening 59.

[0298] The second gate layer connection portion 165 has an island structure and overlaps the driving voltage line 155 and the second electrode (output side electrode) in the region of the first semiconductor 121 of the driving transistor T1. The second gate layer connection portion 165 is connected to the second electrode of the driving transistor T1 through the two openings 51 and 52, and is connected to the driving voltage line 155 through the two openings 53.

[0299] The second gate layer connection portion 166 has an island structure and overlaps the initialization voltage second transfer portion 184 and the first electrode in the region of the third semiconductor 123 of the third transistor T3. The second gate layer connection portion 166 is connected to the first electrode of the third transistor T3 through the two openings 47 and 48, and is connected to the initialization voltage second transfer portion 184 through the opening 78.

[0300] The second gate layer connection portion 167 has an island structure and overlaps the third gate electrode connection portion 183 and the gate electrode 158 of the third transistor T3. The second gate layer connection portion 167 is connected to the gate electrode 158 of the third transistor T3 through the opening 54 and is connected to the third gate electrode connection portion 183 through the opening 55.

[0301] The interlayer insulating layer 13 covers the second gate layer (161, 162, 163, 164, 165, 166, and 167) and the second gate insulating layer 12-1. The interlayer insulating layer 13 may be formed of an inorganic insulating material.

[0302] The first data layer (171, 173, 155, 156, 182, 183, 184 and 185) is formed on the interlayer insulating layer 13. The first data layer (171, 173, 155, 156, 182, 183, 184 and 185) includes a data line 171, an initialization voltage line 173, a driving voltage line 155, a driving low voltage line 156, a second gate electrode connection part 182, a third gate electrode connection part 183, an initialization voltage second transmission part 184 and an anode connection part 185.

[0303] The data line 171 is formed for each pixel and extends in a second direction (longitudinal direction) perpendicular to the first direction (lateral direction). The data line 171 is connected to the second gate layer connecting portion 164 and the second semiconductor 122 of the second transistor T2 through the opening 59, and applies the data voltage Dm to the second transistor T2.

[0304] The initialization voltage line 173 extends in the second direction (longitudinal direction) and applies the initialization voltage Vint. The initialization voltage line 173 is not formed for each pixel, but in an exemplary embodiment, one initialization voltage line 173 may be formed for each of the three pixels PX1, PX2, and PX3. The initialization voltage line 173 is connected to the initialization voltage transmission part 153 through the opening 63, and the initialization voltage transmission part 153 is connected to the initialization voltage second transmission part 184 through the opening 79. The initialization voltage second transmission part 184 is connected to the second gate layer connection part 166 and the third semiconductor 123 of the third transistor T3 through the opening 78. Thus, the initialization voltage Vint is applied to the first electrode of the third transistor T3 of each pixel.

[0305] The driving voltage line 155 and the driving low voltage line 156 extend in the second direction (longitudinal direction). The driving voltage line 155 is provided for each pixel, but the driving low voltage line 156 is provided for every three pixels PX1, PX2 and PX3. The driving voltage line 155 transmits the driving voltage ELVDD, and is connected to the second gate layer connecting portion 165 and the first semiconductor 121 of the driving transistor T1 through two openings 53 to transmit the driving voltage ELVDD to the first electrode of the driving transistor T1. In one embodiment, the driving voltage line 155 has a narrow width compared to the driving low voltage line 156. The driving low voltage line 156 may have a narrow width in an area overlapping with a wiring provided on another layer, and may have a narrow width in an area overlapping with a wiring provided on another layer. Fig.17 The portion where the scanning line 151 overlaps has a narrow width. The driving low voltage line 156 having a wide width is used to form an electrical connection to transmit the driving low voltage ELVSS to the structure of the upward cathode. That is, this is because a predetermined degree of width is required to form an electrical connection by forming a contact using a laser or the like.

[0306] The second gate electrode connection portion 182 has an island structure and overlaps the scan line 151 and the second gate layer connection portion 162. The second gate layer connection portion 162 overlaps the gate electrode 157 of the second transistor T2. The second gate electrode connection portion 182 is connected to the scan line 151 and the second gate layer connection portion 162 through the openings 72 and 46, respectively, and the second gate layer connection portion 162 is connected to the gate electrode 157 of the second transistor T2 through the opening 45, thereby transmitting the scan signal Sn applied to the scan line 151 to the gate electrode 157 of the second transistor T2.

[0307] The third gate electrode connection portion 183 has an island structure and overlaps the previous scan line 152 and the second gate layer connection portion 167. The second gate layer connection portion 167 overlaps the gate electrode 158 of the third transistor T3. The third gate electrode connection portion 183 is connected to the second gate layer connection portion 167 and the previous scan line 152 through the openings 77 and 55, respectively, and the second gate layer connection portion 167 is connected to the gate electrode 158 of the third transistor T3 through the opening 54, thereby transmitting the previous scan signal S(n-1) applied to the previous scan line 152 to the gate electrode 158 of the third transistor T3.

[0308] The anode connection portion 185 is connected to the second extension portion of the storage electrode 161 through the two lower openings 84, and is connected to the anode 192 through the upper opening 81. Thus, the output current of the driving transistor T1 is transferred to the anode 192.

[0309] The upper insulating layer 15 is disposed on the first data layer (171, 173, 155, 156, 182, 183, 184, and 185) and the first interlayer insulating layer 13. The upper insulating layer 15 is formed of an organic insulating material and has features of removing and planarizing steps.

[0310] The anode 192 is formed on the upper insulating layer 15 .

[0311] Anode 192, which is one side electrode of organic light emitting diode OLED, transmits current outputted from driving transistor T1 to organic emission layer. Anode 192 is connected to anode connection portion 185 through opening 81 to receive current outputted from driving transistor T1, and anode connection portion 185 is connected to storage electrode 161 through opening 84.

[0312] refer to Fig.17 The anode 192 is disposed over the entire surfaces of the pixels PX1 , PX2 , and PX3 to overlap the driving transistor T1 , the second transistor T2 , and the third transistor T3 , and one side of the driving voltage line 155 overlaps one side of the anode 192 .

[0313] Here, the area where the anode 192 overlaps the driving voltage line 155 forms an additional capacitor Ca. Fig.18 , Fig.19 and Fig. 20 The cross-sectional view of FIG. 1 describes in detail the region where the additional capacitor Ca is formed.

[0314] refer to Fig.18 , an overlapping layer 115 is formed on the substrate 110, a buffer layer 11 covers the overlapping layer 115, and a first semiconductor 121 of the driving transistor T1 is formed on the buffer layer 11. A first gate insulating layer 12 is formed to cover the first semiconductor 121, and a gate electrode 154 of the driving transistor T1 is formed on the first gate insulating layer 12. A second gate insulating layer 12-1 is formed to cover the gate electrode 154, and a second gate layer connecting portion 165 formed on the second gate insulating layer 12-1 is connected to the first semiconductor 121 through an opening 51. An interlayer insulating layer 13 is formed to cover the second gate layer connecting portion 165, and a driving voltage line 155 is formed on the interlayer insulating layer 13. An upper insulating layer 15 is formed on the driving voltage line 155, and an anode 192 is formed on the upper insulating layer 15 to overlap the overlapping layer 115, the first semiconductor 121 of the driving transistor T1, the gate electrode 154, the storage electrode 161, the second gate layer connecting portion 165, and the driving voltage line 155.

[0315] Here, one end of the driving voltage line 155 is disposed on the same line as one end of the anode 192 on the virtual extension line. The area where the driving voltage line 155 and the anode 192 overlap forms an additional capacitor Ca, which can have sufficient capacitance in a narrow area of ​​a high-resolution organic light emitting diode OLED display.

[0316] refer to Fig.19 The anode 192 is formed upward to overlap the second semiconductor 122, the gate electrode 157 of the second transistor T2, the scan line 151, the second gate layer connection portion 162, the second gate electrode connection portion 182, and the driving voltage line 155. Figure 5 , it can be confirmed that one end of the driving voltage line 155 is disposed on the same line as one end of the anode 192 on the virtual extension line.

[0317] refer to Fig. 20 , a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 12-1, and an interlayer insulating layer 13 are sequentially formed on a substrate 110, and a driving low voltage line 156, a driving voltage line 155, and an anode connection portion 185 are formed on the interlayer insulating layer 13. An upper insulating layer 15 covers the driving low voltage line 156, the driving voltage line 155, and the anode connection portion 185, and an anode 192 is formed on the upper insulating layer 15.

[0318] Anode 192 is formed only in an upper region overlapping driving voltage line 155 and anode connection portion 185 and does not overlap driving low voltage line 156. Anode 192 is connected to anode connection portion 185 through opening 81 and transmits output current of driving transistor T1 to anode 192.

[0319] Although not shown, a partition may be formed between the anodes 192 of adjacent pixels. The partition has an opening exposing the anode 192, and an organic emission layer may be formed in the opening.

[0320] The cathode is disposed on the organic emission layer and the partition. The partition further includes an opening exposing the cathode connection portion. The cathode is connected to the exposed cathode connection portion to receive the driving low voltage ELVSS.

[0321] According to the above structure, the anode 192 and the driving voltage line 155 overlap to form an additional capacitor Ca. According to an exemplary embodiment, the capacitor may be formed by a region where the anode 192 extends to overlap the driving low voltage line 156. Thus, the voltage of the anode 192 may be additionally maintained.

[0322] Reference again Fig.17 , the anode 192 and the driving voltage line 155 overlap with the second electrode (output side electrode) of the driving transistor T1, i.e., the source region. In one embodiment, the driving voltage line 155 does not overlap with the second electrode (output side electrode) of the second transistor T2, i.e., the source region. The source region of the second transistor T2 overlaps only with the data line 171, and the anode 192 does not overlap with the data line 171, thereby preventing crosstalk caused by parasitic capacitance between the data line 171 and the anode 192.

[0323] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. An organic light emitting diode display, wherein: The organic light emitting diode display comprises: substrate; Semiconductor layer; A first gate insulating layer, disposed on the semiconductor layer; A first gate layer, disposed on the first gate insulating layer; A first interlayer insulating layer, disposed on the first gate layer; A first data layer, disposed on the first interlayer insulating layer; A second interlayer insulating layer, disposed on the first data layer; A driving voltage line and a driving low voltage line, which are arranged on the second interlayer insulating layer and separated from each other; an upper insulating layer, covering the driving voltage line and the driving low voltage line; and an anode, disposed on the upper insulating layer and overlapping at least a portion of the driving voltage line or at least a portion of the driving low voltage line, The driving low voltage line provides a first voltage to the cathode, and the driving voltage line provides a second voltage different from the first voltage.

2. The organic light emitting diode display according to claim 1, wherein: The driving voltage line and the driving low voltage line extend in a longitudinal direction.

3. The organic light emitting diode display according to claim 2, wherein: The anode is electrically connected to an anode connection portion, and the anode connection portion is formed to be separated from the driving voltage line and the driving low voltage line on the same layer.

4. The organic light emitting diode display according to claim 3, wherein: The organic light emitting diode display comprises a plurality of pixels, wherein: The anode is provided in each of the pixels.

5. The organic light emitting diode display according to claim 4, wherein: A portion of the anode overlaps the driving voltage line, and another portion of the anode overlaps the driving low voltage line, and The anode connection portion is disposed between the driving voltage line and the driving low voltage line.

6. The organic light emitting diode display according to claim 4, wherein: The anode overlaps the driving voltage line, and The driving voltage line has an anode connection portion opening corresponding to the anode connection portion, and the anode connection portion is disposed within the anode connection portion opening.

7. The organic light emitting diode display according to claim 1, wherein: The organic light emitting diode display further comprises: an overlapping layer disposed between the substrate and the semiconductor layer, The overlapping layer includes a channel overlapping portion overlapping with a channel of the first transistor and an extending portion extending from the channel overlapping portion, and The extending portion of the overlapping layer overlaps the first gate electrode of the first transistor to form an overlapping capacitor.

8. The organic light emitting diode display according to claim 1, wherein: The driving voltage line has a parasitic capacitor opening so that the anode forms a parasitic capacitor with the first gate insulating layer or the first data layer.

9. The organic light emitting diode display according to claim 1, wherein: The organic light emitting diode display further comprises: an organic emission layer disposed on the anode; and The cathode is disposed on the organic emission layer, wherein the cathode is electrically connected to a cathode connection portion located on the same layer as the anode, and The cathode connection portion is electrically connected to the driving low voltage line.

10. The organic light emitting diode display according to claim 1, wherein: The driving voltage line has a greater width than the anode, and The driving low voltage line has a width greater than half of a width of the anode.

11. The organic light emitting diode display according to claim 1, wherein: The first gate layer includes a pair of scan lines receiving the same scan signal, The first data layer includes a pair of data lines connected to a pixel column, Among two adjacent pixels included in the one pixel column, one pixel is connected to one scan line of the pair of scan lines and one data line of the pair of data lines, and the other pixel is connected to the other scan line of the pair of scan lines and the other data line of the pair of data lines.

12. An organic light emitting diode display, wherein: The organic light emitting diode display comprises: substrate; A semiconductor layer is disposed on the substrate; A first gate insulating layer, disposed on the semiconductor layer; A first gate layer, disposed on the first gate insulating layer; a second gate insulating layer, disposed on the first gate layer; A second gate layer, disposed on the second gate insulating layer; A first interlayer insulating layer, disposed on the second gate layer; A first data layer, disposed on the first interlayer insulating layer and comprising a data line, an initialization voltage line, a driving voltage line and a driving low voltage line; an upper insulating layer, covering the first data layer; and an anode, disposed on the upper insulating layer; wherein the anode includes an additional capacitor extension portion, and the additional capacitor extension portion overlaps the driving low voltage line, The driving low voltage line provides a first voltage to the cathode, and the driving voltage line provides a second voltage different from the first voltage.

13. The organic light emitting diode display according to claim 12, wherein: The organic light emitting diode display further comprises: an overlapping layer disposed between the substrate and the semiconductor layer, and The overlapping layer overlaps with a channel of the first transistor.

14. The organic light emitting diode display according to claim 12, wherein: The driving voltage line and the driving low voltage line are arranged adjacent to each other, The width of the driving low voltage line is wider than the width of the driving voltage line, and The driving low voltage line also overlaps with the driving voltage line.

15. The organic light emitting diode display according to claim 12, wherein: The organic light emitting diode display further comprises: a second interlayer insulating layer disposed between the first data layer and the upper insulating layer, the second interlayer insulating layer being disposed on the first data layer; and A second driving low voltage line is arranged between the first data layer and the upper insulating layer, the second driving low voltage line is arranged on the second interlayer insulating layer, and The driving low voltage line is electrically connected to the second driving low voltage line to transmit a driving low voltage through a dual structure.

16. The organic light emitting diode display according to claim 12, wherein: The organic light emitting diode display further comprises: a cathode connection portion disposed on the same layer as the anode, and the cathode connection portion being electrically connected to the driving low voltage line, and The additional capacitor extension portion of the anode is disposed separate from the cathode connection portion.

17. The organic light emitting diode display according to claim 12, wherein: The organic light emitting diode display further comprises a plurality of pixels, wherein: The anode is disposed in each of the pixels, and at least one of the anodes does not include the additional capacitor extension portion.

18. An organic light emitting diode display, wherein: The organic light emitting diode display comprises: substrate; A semiconductor layer is disposed on the substrate; A first gate insulating layer, disposed on the semiconductor layer; A first gate layer, disposed on the first gate insulating layer; a second gate insulating layer, disposed on the first gate layer; A second gate layer, disposed on the second gate insulating layer; an interlayer insulating layer, disposed on the second gate layer; A data layer, disposed on the interlayer insulating layer and comprising a data line and a driving voltage line; an upper insulating layer, disposed on the data layer; and an anode disposed on the upper insulating layer and completely covering a gate electrode of a first transistor included in the first gate layer; wherein the anode overlaps the driving voltage line to form an additional capacitor, The second gate layer includes a storage electrode, The gate electrode and the storage electrode of the first transistor overlap to form a storage capacitor; Wherein, the organic light emitting diode display further comprises: an overlapping layer disposed between the substrate and the semiconductor layer, The overlapping layer includes a channel overlapping portion overlapping with a channel of the first transistor and an extending portion extending from the channel overlapping portion, and The extending portion of the overlapping layer overlaps the gate electrode of the first transistor to form an overlapping capacitor.

19. The organic light emitting diode display according to claim 18, wherein: The driving voltage line extends along a longitudinal direction.

20. The organic light emitting diode display according to claim 19, wherein: One side of the anode extending in the longitudinal direction overlaps the driving voltage line.

21. The organic light emitting diode display according to claim 18, wherein: The semiconductor layer includes a first semiconductor, a second semiconductor and a third semiconductor, The first transistor is arranged on the first semiconductor, the second transistor is arranged on the second semiconductor, and the third transistor is arranged on the third semiconductor.

22. The organic light emitting diode display according to claim 21, wherein: The first semiconductor includes a channel region, a source region and a drain region, and The source region overlaps the anode and the driving voltage line.

23. The organic light emitting diode display according to claim 18, wherein: The storage capacitor completely overlaps the anode.

24. The organic light emitting diode display according to claim 23, wherein: The overlapping layer is connected to the storage electrode through the opening, and The storage electrode is electrically connected to the anode through a connection portion included in the data layer.

25. The organic light emitting diode display according to claim 21, wherein: The second semiconductor includes a channel region, a source region and a drain region, and The source region overlaps the data line to be electrically connected thereto.

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