Output Buffer Control Circuit

Abstract

The present invention discloses an output buffer control circuit, and the control circuit includes: an operational amplifier; a feedback resistor R F ; a voltage dividing resistor; a floating switch, including a first floating switch SW1 and a second floating switch SW2. One end of the first floating switch SW1 is electrically connected to a first voltage dividing resistor R1 and a second voltage dividing resistor R2, and the other end is electrically connected to a second input terminal of the operational amplifier. One end of the second floating switch SW2 is electrically connected to the second voltage dividing resistor R2 and the feedback resistor R F and the other end is electrically connected to the second input terminal of the operational amplifier; a MOS transistor switch, including a first MOS transistor switch SW3 and a second MOS transistor switch SW4 connected in common gate. The first MOS transistor switch SW3 and the second MOS transistor switch SW4 are respectively electrically connected to the first voltage dividing resistor R1. The output buffer control circuit of the present invention controls the switching between voltage domains through the floating switch, and the leakage current of the MOS transistor switch does not flow through the resistor, greatly improving the linearity of the output voltage.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an output buffer control circuit. Background Art

[0002] The output buffer needs to support the output of several voltage domains at the same time, including switching between the output positive voltage and negative voltage, for example, switching between the four voltage domains of +VA / +VB / -VA / -VB. Switching the voltage domain needs to be controlled by a switch.

[0003] Ginseng Figure 1 As shown, the control circuit in the prior art includes an amplifier, voltage divider resistors R1 and R2 (R2 = aR1), a feedback resistor R F And four MOS tube switches (NMOS tube SW1', PMOS tube SW2', NMOS tube SW3', PMOS tube SW4'), the four MOS tube switches control the switching of the four voltage domains +VA / +VB / -VA / -VB, and only one of the four switches can be turned on at the same time. The advantage of this control circuit is that the switch control is convenient and does not require a level shifter. However, the leakage current (Leakage) of the MOS tube of this control circuit at high temperature will affect the output accuracy. For example, when the +VA voltage domain output is selected, the NMOS tube SW1' is turned on and the other MOS tubes are turned off. At this time, the leakage current of the NMOS tube SW3' and the PMOS tube SW4' will flow through the voltage divider resistor. When the leakage current is 1nA, a 100k ohm resistor will generate a voltage of 0.1mV, which will be amplified to the output and will have a great impact on the linearity of the output voltage.

[0004] Therefore, in view of the above technical problems, it is necessary to provide an output buffer control circuit. Summary of the invention

[0005] The object of the present invention is to provide an output buffer control circuit to improve the linearity of the output buffer.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] An output buffer control circuit, the control circuit comprising:

[0008] An operational amplifier, comprising a first input terminal, a second input terminal and an output terminal;

[0009] Feedback resistor R F , electrically connected to the output terminal of the operational amplifier;

[0010] The voltage-dividing resistors include a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, and a feedback resistor R FSeries setting;

[0011] The floating switch includes a first floating switch SW1 and a second floating switch SW2. One end of the first floating switch SW1 is electrically connected to the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the other end is electrically connected to the second input end of the operational amplifier. One end of the second floating switch SW2 is electrically connected to the second voltage-dividing resistor R2 and the feedback resistor R F electrically connected to the second input terminal of the operational amplifier; and the other end is electrically connected to the second input terminal of the operational amplifier;

[0012] The MOS transistor switch includes a first MOS transistor switch SW3 and a second MOS transistor switch SW4 connected in common gate connection. The first MOS transistor switch SW3 and the second MOS transistor SW4 are electrically connected to the first voltage-dividing resistor R1 respectively.

[0013] In one embodiment, the first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS transistor switch SW3 is an NMOS transistor, and the second MOS transistor switch SW4 is a PMOS transistor.

[0014] In one embodiment, in the control circuit:

[0015] The drain of the first floating switch SW1 is electrically connected to the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the source is electrically connected to the second input terminal of the operational amplifier. The drain of the second floating switch SW2 is electrically connected to the second voltage-dividing resistor R2 and the feedback resistor R F The source is electrically connected to the second input terminal of the operational amplifier, the drain voltage of the second floating switch SW2 is V1, and the source voltage is V IM , the gate control voltage of the second floating switch SW2 is V G , Bulk voltage is V B ;

[0016] The source voltage of the first MOS switch SW3 is 0, and the source voltage of the second MOS switch SW4 is V R The drain of the first MOS switch SW3 and the drain of the second MOS switch SW4 are electrically connected to the first voltage-dividing resistor R1, and the drain voltage is V RI The gate of the first MOS switch SW3 and the gate of the second MOS switch SW4 are connected to the control signal VSEL.

[0017] In one embodiment, the input voltage of the first input terminal of the operational amplifier is V IP , satisfying 0≤V IP ≤V I , V I is a preset voltage threshold, and the source voltage V R Greater than the preset voltage threshold V I .

[0018] In one embodiment, the control circuit includes:

[0019] In the first state, the first floating switch SW1 is turned on and the second floating switch SW2 is turned off. RI = 0 and V IM =0, V1 = 0, when V RI =V R And V IM =0, V1 = -aV R , when V RI = 0 and V IM =V I When V1=(1+a)V I , when V RI =V R And V IM =V I When V1 = -aV R +(1+a)V I , where a=R2 / R1;

[0020] In the second state, the first floating switch SW1 is closed, the second floating switch SW2 is turned on, V1 = V IM , 0≤V1≤V I .

[0021] In one embodiment, the control circuit further includes a voltage generating unit for generating a voltage following V1 or V IM voltage.

[0022] In one embodiment, the voltage follower unit includes:

[0023] The first voltage comparison unit is used to obtain V1 and V IM The lower voltage min(V1,V IM );

[0024] The second voltage comparison unit is used to obtain V1 and V IM The higher voltage max(V1,V IM );

[0025] The third resistor and the first control switch are electrically connected between the first voltage comparison unit and the second voltage comparison unit in sequence;

[0026] The first level converter and the second control switch are electrically connected between the third resistor and the first control switch.

[0027] In one embodiment, in the first state of the voltage following unit, the first level converter is short-circuited by the second control switch, and the min(V1, V IM) as the gate control voltage V of the second floating switch SW2 G , and V B =V G In the second state, the max(V1,V IM ) and is raised by the first level converter as the gate control voltage V of the second floating switch SW2 G , and V B =min(V1,V IM ); the voltage follower unit is in the second state, V G -max(V1,V IM )≥bV TH , where b≥1, V TH is the threshold voltage of the second floating switch SW2.

[0028] In one embodiment, the voltage following unit further includes a second level converter electrically connected to the first voltage comparing unit, and the second level converter is used to convert the min(V1, V IM ) after stepping down as V B Output.

[0029] In one embodiment, the first voltage comparison unit includes a first differential pair consisting of two PMOS transistors, and the second voltage comparison unit includes a second differential pair consisting of two NMOS transistors.

[0030] Compared with the prior art, the present invention has the following advantages:

[0031] The output buffer control circuit of the present invention controls the switching between voltage domains through a floating switch, and the leakage current of the MOS tube switch will not flow through the resistor, thereby greatly improving the linearity of the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 is a schematic diagram of an output buffer control circuit in the prior art;

[0034] Figure 2 is a schematic diagram of an output buffer control circuit in a specific embodiment of the present invention;

[0035] Figure 3a , 3bare equivalent circuit diagrams of an output buffer control circuit in a first state and a second state in a specific embodiment of the present invention;

[0036] Figure 4 It is a module schematic diagram of a voltage follower unit in a specific embodiment of the present invention;

[0037] Figure 5 It is a specific implementation circuit diagram of a voltage follower unit in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be described in detail below in conjunction with the various embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0039] Ginseng Figure 2 As shown, an output buffer control circuit in a specific embodiment of the present invention includes:

[0040] An operational amplifier, comprising a first input terminal (non-inverting input terminal +), a second input terminal (inverting input terminal -) and an output terminal;

[0041] Feedback resistor R F , electrically connected to the output terminal of the operational amplifier;

[0042] The voltage-dividing resistors include a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, and a feedback resistor R F Series setting;

[0043] The floating switch includes a first floating switch SW1 and a second floating switch SW2. One end of the first floating switch SW1 is electrically connected to the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the other end is electrically connected to the second input end of the operational amplifier. One end of the second floating switch SW2 is electrically connected to the second voltage-dividing resistor R2 and the feedback resistor R F The other end is electrically connected to the second input terminal of the operational amplifier;

[0044] The MOS transistor switch includes a first MOS transistor switch SW3 and a second MOS transistor switch SW4 connected in common gate connection. The first MOS transistor switch SW3 and the second MOS transistor SW4 are electrically connected to the first voltage-dividing resistor R1 respectively.

[0045] Specifically, the drain of the first floating switch SW1 is electrically connected to the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, the source is electrically connected to the second input terminal of the operational amplifier, and the drain of the second floating switch SW2 is electrically connected to the second voltage-dividing resistor R2 and the feedback resistor R FThe source is electrically connected to the second input terminal of the operational amplifier, the drain voltage of the second floating switch SW2 is V1, and the source voltage is V IM , the gate control voltage of the second floating switch SW2 is V G , Bulk voltage is V B ;

[0046] The source voltage of the first MOS switch SW3 is 0, and the source voltage of the second MOS switch SW4 is V R The drain of the first MOS switch SW3 and the drain of the second MOS switch SW4 are electrically connected to the first voltage-dividing resistor R1, and the drain voltage is V RI The gate of the first MOS switch SW3 and the gate of the second MOS switch SW4 are connected to the control signal VSEL.

[0047] The input voltage of the first input terminal of the operational amplifier is V IP , satisfying 0≤V IP ≤V I , V I is a preset voltage threshold, and the source voltage V R Greater than the preset voltage threshold V I .

[0048] In this embodiment, the first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS switch SW3 is an NMOS transistor, and the second MOS switch SW4 is a PMOS transistor. Among them, SW1, SW3, and SW4 can all be controlled by low-voltage logic. According to the control of SW1, the control circuit includes the following two states:

[0049] The first state, Figure 3a As shown, the first floating switch SW1 is turned on and the second floating switch SW2 is turned off. RI = 0 and V IM =0, V1 = 0, when V RI =V R And V IM =0, V1 = -aV R , when V RI = 0 and V IM =V I When V1=(1+a)V I , when V RI =V R And V IM =V I When V1 = -aV R +(1+a)V I , where a=R2 / R1;

[0050] The second state, Figure 3b As shown, the first floating switch SW1 is closed, the second floating switch SW2 is turned on, V1 = V IM , 0≤V1≤V I .

[0051] In the first state, when the first floating switch SW1 is turned on, a negative voltage will appear at one end (V1 end) of the second floating switch SW2. This situation is described as follows:

[0052] Assume a = 1, when VSEL selects the second MOS switch SW4 (PMOS) to turn on, that is, V RI =V R When SW1 is turned on and SW2 is turned off, V IP =0V, then V1 = -V R , if the gate voltage of SW2 is V G = 0V, SW2 cannot be completely turned off, and a voltage higher than -V is required. R The lower voltage controls the gate of SW2 to turn SW2 off. In addition, the substrate of SW2 also needs to switch to a more negative voltage between the source and drain. At this time, V IM >V1.

[0053] When V RI =0V, the voltage of V1 can reach up to 2*V I , at this time V IM <V1。

[0054] In both cases, V RI , V1, V IM The relationship is shown in the following table:

[0055] <![CDATA[V RI ]]> <![CDATA[V1(V IM =0)]]> <![CDATA[V1(V IM =V I )]]> 0V 0 <![CDATA[(1+a)V I ]]> <![CDATA[V R ]]> <![CDATA[-aV R ]]> <![CDATA[-aV R +(1+a)V I ]]>

[0056] Therefore, in each case, SW2 needs to generate a voltage to control the gate, which needs to be switched lower than the source and drain to turn SW2 off.

[0057] In the first state, when SW1 is off and SW2 is on, V1 = V IM , that is, V1 needs to be between 0 and V I At this time, the gate of SW2 needs to be greater than V1 / V IM The terminal is at least 1 V high TH In order to ensure a sufficiently small on-resistance, it is best to use 2 V TH above.

[0058] In this embodiment, VSEL is used to control the output of the positive voltage domain or the negative voltage domain, and the SW1 and SW2 switches are used to control the switching between the voltage domains. The leakage current of the MOS tube switches SW3 and SW4 will not flow through the resistor, so it will not affect the output accuracy. Since the floating switches SW1 and SW2 do not need to flow current during operation, the switches can be made very small and their leakage current can be ignored.

[0059] According to the above description, in order to control the gate voltage V of SW2 G And generate the corresponding Bulk voltage V B , a follower V1 or V needs to be generated according to different application situations IM voltage.

[0060] Ginseng Figure 4 As shown, the voltage follower unit in this embodiment includes:

[0061] The first voltage comparison unit (smaller) is used to obtain V1 and V IM The lower voltage min(V1,V IM );

[0062] The second voltage comparison unit (larger) is used to obtain V1 and V IM The higher voltage max(V1,V IM );

[0063] The third resistor R3 and the first control switch are electrically connected between the first voltage comparison unit (smaller) and the second voltage comparison unit (larger) in sequence;

[0064] The first level shifter and the second control switch are electrically connected between the third resistor R3 and the first control switch.

[0065] In the first state of the voltage following unit, the first level converter is short-circuited by the second control switch, and the min(V1, V IM ) as the gate control voltage V of the second floating switch SW2 G , and V B =V G ;

[0066] In the second state, the voltage follower unit uses the max(V1,V IM ) and is raised by the first level converter as the gate control voltage V of the second floating switch SW2 G , and V B =min(V1,V IM ). At this time, V G -max(V1,VIM )≥bV TH , where b≥1, V TH is the threshold voltage of the second floating switch SW2.

[0067] Specifically, when VSW is at a high level, SW2 needs to be turned off, and V1 / V IM The lower one is used as the gate control signal V of SW2 G , at this time the second control switch in the middle short-circuits the first level converter, making V G =V B .

[0068] When VSW is low ( is high), SW2 needs to be turned on to select V1 / V IM The higher of the two, and then through the first level converter to make V G than max(V1,V IM ) 2 V high TH , which can ensure that SW2 has a smaller on-resistance.

[0069] Since the Bulk voltage V B Always use V1 / V IM Therefore, the Bulk voltage can be guaranteed to be the lowest voltage of the NMOS tube.

[0070] Ginseng Figure 5 The figure shows a specific implementation circuit of the voltage follower unit in this embodiment, wherein the first voltage comparison unit (smaller) includes a first differential pair consisting of two PMOS tubes, and the second voltage comparison unit (larger) includes a second differential pair consisting of two NMOS tubes.

[0071] Specifically, the first voltage comparison unit (smaller) includes a first differential pair consisting of two PMOS transistors P1 and P2, and the gate voltages of the PMOS transistors P1 and P2 are V1 and V2, respectively. IM , the source is connected to the current source I1, the drain is connected in series with the resistors R5 and R6 and then connected to the current source I2, the voltage between the resistor R5 and the current source I2 is V B .

[0072] The second voltage comparison unit (larger) includes a second differential pair consisting of two NMOS transistors N1 and N2, and the gate voltages of the NMOS transistors N1 and N2 are V1 and V2, respectively. IMThe source is connected to the resistor R3 and then electrically connected to the current source I2. The drain is connected in series with the resistors R7 and R8 and then electrically connected to the switch S1 and the current source I3. The switch S1 is a PMOS tube. The switch S1 is used to control whether the second voltage comparison unit works. Its gate drive signal is VSW. The voltage between the second voltage comparison unit and the resistor R3 is V B .

[0073] The first level converter includes two NMOS transistors N3 and N4 connected in series, which are used to convert the acquired max(V1, V IM ) is raised as V G Output. The source of N4 is connected to V A , the gate and drain are electrically connected to the source of N3, and the gate and drain voltage of N3 is V G , and the resistor R4 is electrically connected to the resistor R3, N3 and N4 are electrically connected to the current source I4 through the switch S2, the switch S2 is a PMOS tube, used to control whether the first level converter works, and its gate drive signal is

[0074] The second level converter includes two NMOS transistors N5 and N6 connected in series, which are used to convert the min (V1, V IM ) after stepping down as V B Output.

[0075] Specifically, in this embodiment, the NMOS and PMOS differential pairs are used as the first voltage comparison unit (smaller) and the second voltage comparison unit (larger), respectively, and min (V1, V IM ) and max(V1,V IM ) are selected respectively. Among them, min(V1,V IM ) Drop two V GS Then, as the Bulk voltage V B .

[0076] Switch S1 controls whether the second voltage comparison unit (larger) works. When S1 is closed, current does not flow through the second voltage comparison unit (larger), and the unit does not work. At this time, S2 is turned on. Since no current flows through R3 and R4, V A =V G =V B , switch SW2 is turned on.

[0077] When S1 is turned on and S2 is turned off, the second voltage comparison unit (larger) can work normally, V A =max(V1,V IM ), the current flows through S2 for several V GS The first level converter generates a higher voltage VG Turn on SW2.

[0078] It should be understood that the voltage follower unit in the above embodiment is only a specific implementation circuit of the present invention, and other voltage follower circuits can also be used in other embodiments to implement the voltage V1 or V IM Following, I will not give examples one by one here.

[0079] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0080] The output buffer control circuit of the present invention controls the switching between voltage domains through a floating switch, and the leakage current of the MOS tube switch will not flow through the resistor, thereby greatly improving the linearity of the output voltage.

[0081] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0082] In addition, it should be understood that although the present specification is described according to embodiments, not every embodiment contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation methods that those skilled in the art can understand.

Claims

1. An output buffer control circuit, characterized in that: The control circuit comprises: An operational amplifier, comprising a first input terminal, a second input terminal and an output terminal; Feedback resistor R F , electrically connected to the output terminal of the operational amplifier; The voltage-dividing resistors include a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, and a feedback resistor R F Series setting; The floating switch includes a first floating switch SW1 and a second floating switch SW2. One end of the first floating switch SW1 is electrically connected to the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the other end is electrically connected to the second input end of the operational amplifier. One end of the second floating switch SW2 is electrically connected to the second voltage-dividing resistor R2 and the feedback resistor R F The first floating switch SW1 is electrically connected to the second input terminal of the operational amplifier, and the other end is electrically connected to the second input terminal of the operational amplifier, the control end signal of the first floating switch SW1 and the control end signal of the second floating switch SW2 are reverse signals to each other, and the floating switch is used to control the switching between voltage domains; The MOS transistor switch includes a first MOS transistor switch SW3 and a second MOS transistor switch SW4 connected in common gate connection. The first MOS transistor switch SW3 and the second MOS transistor SW4 are electrically connected to the first voltage-dividing resistor R1 respectively.

2. The output buffer control circuit according to claim 1, characterized in that: The first floating switch SW1 and the second floating switch SW2 are NMOS transistors, the first MOS transistor switch SW3 is an NMOS transistor, and the second MOS transistor switch SW4 is a PMOS transistor.

3. The output buffer control circuit according to claim 2, characterized in that: In the control circuit: The drain of the first floating switch SW1 is electrically connected to the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the source is electrically connected to the second input terminal of the operational amplifier. The drain of the second floating switch SW2 is electrically connected to the second voltage-dividing resistor R2 and the feedback resistor R F The source is electrically connected to the second input terminal of the operational amplifier, the drain voltage of the second floating switch SW2 is V1, and the source voltage is V IM , the gate control voltage of the second floating switch SW2 is V G , Bulk voltage is V B ; The source voltage of the first MOS switch SW3 is 0, and the source voltage of the second MOS switch SW4 is V R The drain of the first MOS switch SW3 and the drain of the second MOS switch SW4 are electrically connected to the first voltage-dividing resistor R1, and the drain voltage is V RI The gate of the first MOS switch SW3 and the gate of the second MOS switch SW4 are connected to the control signal VSEL.

4. The output buffer control circuit according to claim 3, characterized in that: The input voltage of the first input terminal of the operational amplifier is V IP , satisfying 0≤V IP ≤V I , V I is a preset voltage threshold, and the source voltage V R Greater than the preset voltage threshold V I .

5. The output buffer control circuit according to claim 4, characterized in that: The control circuit comprises: In the first state, the first floating switch SW1 is turned on and the second floating switch SW2 is turned off. RI = 0 and V IM =0, V1 = 0, when V RI =V R And V IM =0, V1 = -aV R , when V RI = 0 and V IM =V I When V1=(1+a)V I , when V RI =V R And V IM =V I When V1 = -aV R +(1+a)V I , where a=R2 / R1; In the second state, the first floating switch SW1 is closed, the second floating switch SW2 is turned on, V1 = V IM , 0≤V1≤V I .

6. The output buffer control circuit according to claim 5, characterized in that: The control circuit also includes a voltage following unit for generating a voltage following V1 or V IM voltage.

7. The output buffer control circuit according to claim 6, characterized in that: The voltage follower unit comprises: The first voltage comparison unit is used to obtain V1 and V IM The lower voltage min(V1,V IM ); The second voltage comparison unit is used to obtain V1 and V IM The higher voltage max(V1,V IM ); The third resistor and the first control switch are electrically connected between the first voltage comparison unit and the second voltage comparison unit in sequence; The first level converter and the second control switch are electrically connected between the third resistor and the first control switch.

8. The output buffer control circuit according to claim 7, characterized in that: In the first state, the voltage follower unit has the first level converter short-circuited by the second control switch, and the min(V1, V IM ) as the gate control voltage V of the second floating switch SW2 G , and V B =V G In the second state, the max(V1,V IM ) and is raised by the first level converter as the gate control voltage V of the second floating switch SW2 G , and V B =min(V1,V IM ); the voltage follower unit is in the second state, V G -max(V1,V IM )≥bV TH , where b≥1, V TH is the threshold voltage of the second floating switch SW2.

9. The output buffer control circuit according to claim 8, characterized in that: The voltage following unit further includes a second level converter electrically connected to the first voltage comparison unit, and the second level converter is used to convert the min(V1, V IM ) is stepped down to become V B Output.

10. The output buffer control circuit according to claim 7, characterized in that: The first voltage comparison unit includes a first differential pair consisting of two PMOS transistors, and the second voltage comparison unit includes a second differential pair consisting of two NMOS transistors.

Images