A stepless delay circuit with adjustable pulse width and multi-channel ground penetrating radar

Abstract

The present invention provides a stepless delay circuit with adjustable pulse width and a multi-channel ground penetrating radar. The circuit includes: a coupling capacitor, a first high-speed D flip-flop, a fifth resistor, a first adjustable resistor, and a seventh capacitor. The coupling capacitor is connected to the clock input of the first high-speed D flip-flop, the data input and the set input of the first high-speed D flip-flop are connected to the power supply VCC, the inverting output of the first high-speed D flip-flop is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to a fixed pin of the first adjustable resistor, another fixed pin of the first adjustable resistor is connected to the moving pin of the first adjustable resistor and the reset input of the first high-speed D flip-flop, and another fixed pin is also connected to one end of the seventh capacitor. The stepless delay circuit with adjustable pulse width and the multi-channel ground penetrating radar provided by the present invention can overcome the problems of low precision, high complexity, and high power consumption of the existing delay circuit made based on digital chips.

Description

Technical Field

[0001] The invention relates to the technical field of ground penetrating radar, and in particular to a stepless delay circuit with adjustable pulse width and a multi-channel ground penetrating radar. Background Art

[0002] Ultra-wideband radar technology is a non-destructive detection method that uses wide-band narrow pulse electromagnetic waves to detect medium stratification or target information hidden behind obstacles or in medium layers. It has the characteristics of strong penetration, strong anti-interference ability, high resolution, and simple structure. It has very wide applications in various civil and military fields such as geological exploration, road quality inspection and evaluation, through-wall imaging, and anti-terrorism. Among them, multi-channel ground penetrating radar has an incomparable advantage in detection efficiency, especially in the detection of urban road diseases, which can greatly improve the operation efficiency. The trigger signal delayer is an important part of the ultra-wideband radar system. To a certain extent, the different delay amounts of the trigger signals between different channels affect the consistency between the signals of different channels. Therefore, the selection and design of the trigger signal delayer is crucial for the multi-channel ground penetrating radar system.

[0003] At present, the methods of using semiconductor devices to generate trigger pulse signal delays can be roughly divided into several categories: one is to use digital chips such as MCU or FPGA to generate narrow pulse trigger signals with different delay amounts; the other is to adjust the delay amount of the trigger signal based on high-precision precision delay chips; the other is to use analog chips to use the different charging and discharging times of capacitors or inductors to generate narrow pulse trigger signals with different delay amounts. This circuit uses the different time constants generated by different RC or RL combinations to achieve the delay of the trigger signal.

[0004] The trigger signal delay of different channels of the existing multi-channel ground penetrating radar is mostly realized by the narrow pulse signal delay generated by the digital chip. By increasing the working clock of the digital chip, a more precise clock signal can be generated, thereby improving the accuracy of the trigger signal delay. However, the increase in the working clock of the digital chip will increase the power consumption of the system on the one hand, and on the other hand, the increase in the working clock of the digital chip will also have a limit. The delay accuracy of the trigger signal generated by the general digital chip is basically in the nanosecond level, which is used for coarse delay adjustment; and although the trigger signal with different delay amounts generated by the high-precision precision delay chip can improve the delay accuracy, generally accurate to 5 picoseconds, this will increase the complexity of the system, and the high-precision precision delay chip is required to achieve different delay amounts. The digital chip needs to cooperate to generate the control word for controlling the delay amount, and there is a limit resolution. The power consumption of the high-precision delay chip is generally high. The time point of generating the transmission signal is inconsistent due to the inconsistent wiring length and different device parameters between different channels. These factors will cause the arrival time of the direct wave signal of the echo signal received by different channels to be inconsistent, thereby affecting the consistency of the signal between different channels. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a stepless delay circuit with adjustable pulse width and a multi-channel ground penetrating radar, which can overcome the problems of low precision, high complexity and high power consumption of existing delay circuits made based on digital chips.

[0006] In order to solve the above technical problems, the present invention provides a stepless delay circuit with adjustable pulse width, the circuit comprising: a pulse signal stepless delay adjustment circuit, wherein the pulse signal stepless delay adjustment circuit comprises: a coupling capacitor C6, a first high-speed D flip-flop U3, a fifth resistor R5, a first adjustable resistor RP1, and a seventh capacitor C7, the coupling capacitor C6 is connected to the clock input end of the first high-speed D flip-flop U3, the data input end and the set input end of the first high-speed D flip-flop U3 are connected to the power supply VCC, the inverting output end of the first high-speed D flip-flop U3 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to a fixed pin of the first adjustable resistor RP1, the other fixed pin of the first adjustable resistor RP1 is connected to the moving pin of the first adjustable resistor RP1 and the reset input end of the first high-speed D flip-flop U3, the other fixed pin is also connected to one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.

[0007] In some embodiments, it also includes: a pulse width stepless adjustment circuit, which includes: a second high-speed D trigger U4, a sixth resistor R6, a second adjustable resistor RP2, an eighth capacitor C8, a ninth capacitor C9 and a first inductor L1, a clock input terminal of the second high-speed D trigger U4 is connected to the inverting output terminal of the first high-speed D trigger U3, a data input terminal and a set input terminal of the second high-speed D trigger U4 are connected to the power supply VCC, a positive phase output terminal of the second high-speed D trigger U4 is connected to one end of the ninth capacitor C9, the other end of the ninth capacitor C9 is connected to one end of the first inductor L1, the other end of the first inductor L1 is connected to the high-voltage power supply HV, an inverting output terminal of the second high-speed D trigger U4 is connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to a fixed pin of the second adjustable resistor RP2, another fixed pin of the second adjustable resistor RP2 is connected to the moving pin of the second adjustable resistor RP2 and the reset input terminal of the second high-speed D trigger U4, another fixed pin is also connected to one end of the eighth capacitor C8, and the other end of the eighth capacitor C8 is grounded.

[0008] In some embodiments, it also includes: a pulse signal shaping circuit, the pulse signal shaping circuit includes: a first inverter U1, a first high-speed diode D3, a second inverter U2, a fourth resistor R4, a fourth capacitor C4, a fifth capacitor C5, a fourth diode D4, and a fifth diode D5, wherein the output end of the first inverter U1 is connected to the cathode of the first high-speed diode D3, the anode of the first high-speed diode D3 is connected to the input end of the second inverter U2, the output end of the second inverter U2 is respectively connected to the anode of the fourth diode D4, the cathode of the fifth diode D5 and the coupling capacitor C6, the cathode of the fourth diode D4 is connected to the fifth capacitor C5 and one end of the fourth resistor R4, the other end of the fifth capacitor C5 is grounded, the other end of the fourth resistor R4 is connected to the power supply VCC and to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and the anode of the fifth diode D5 is grounded.

[0009] In some embodiments, it also includes: a filtering and protection circuit, which includes: a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1 and a second diode D2, wherein one end of the first capacitor C1 is connected to the input signal, and the other end is connected to one end of the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is grounded, the other end of the second resistor R2 is connected to the positive electrode of the first diode D1 and the negative electrode of the second diode D2, the negative electrode of the first diode D1 is connected to one end of the third capacitor C3 and the third resistor R3, the other end of the third capacitor C3 is grounded, the other end of the third resistor R3 is connected to the power supply VCC, and is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the positive electrode of the second diode D2 is grounded, and the other end of the second resistor R2 is also connected to the input end of the first inverter U1.

[0010] In some embodiments, both the first inverter U1 and the second inverter U2 are Schmitt inverters.

[0011] In some implementations, the amplitude of the input trigger signal is between 1.8V and 5V, the pulse width is between 50ns and 500ns, and the signal repetition frequency is between 20kHz and 400kHz.

[0012] In addition, the present invention also provides a multi-channel ground penetrating radar, which includes: a stepless delay circuit with adjustable pulse width as described above.

[0013] After adopting such a design, the present invention has at least the following advantages:

[0014] (1) The pulse signal stepless delay adjustment circuit constructed by high-speed D flip-flop can realize stepless adjustment of delay amount compared with the circuit constructed by ordinary digital chip or delay chip. It has simple structure and can realize precise adjustment of delay amount between different channels, thus improving the consistency between channels.

[0015] (2) The pulse signal shaping circuit constructed using a high-speed D flip-flop has a higher adjustment accuracy than the pulse width adjustment circuit constructed using an ordinary digital chip, can achieve stepless adjustment of the pulse signal duty cycle, and has a simpler structure and higher reliability.

[0016] (3) Through the shaping of high-speed diodes and Schmidt inverters, the rising and falling edges of the output signal are steeper and the jitter is smaller, making the trigger signal of higher quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0018] Figure 1 It is a circuit structure block diagram of a stepless delay circuit with adjustable pulse width applicable to a multi-channel ground penetrating radar provided by an embodiment of the present invention;

[0019] Figure 2 The invention provides a circuit schematic diagram of a stepless delay circuit with adjustable pulse width applicable to a multi-channel ground penetrating radar according to an embodiment of the invention. DETAILED DESCRIPTION

[0020] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0021] Please refer to Figure 1 and Figure 2 In this embodiment, a stepless delay circuit with adjustable pulse width applicable to a multi-channel ground penetrating radar includes:

[0022] The filtering and protection circuit 101 is used for input signal filtering and back-end circuit protection to prevent the back-end circuit from being damaged due to excessive input signal; the pulse signal shaping circuit 102, whose front end is electrically connected to the input signal filtering and protection circuit, is used to shape the edge of the pulse signal; the pulse signal stepless delay adjustment circuit 103, whose front end is electrically connected to the pulse signal shaping circuit, is used to achieve stepless adjustment of the delay of the pulse signal, to achieve precise adjustment of the trigger delay of different channels, and ensure consistency between channels; the pulse width stepless adjustment circuit 104, whose front end is electrically connected to the pulse signal stepless delay adjustment circuit, is used to steplessly adjust the width (duty cycle) of the pulse signal to meet the trigger requirements of different transmitters or receivers.

[0023] The following describes in detail the various components of the stepless delay circuit with adjustable pulse width applicable to a multi-channel ground penetrating radar according to the present embodiment.

[0024] First, the circuit structure of the filtering and protection circuit 101 is described.

[0025] In this embodiment, the input trigger pulse signal is a square wave signal with an amplitude of 3.3V, a pulse width of 200ns, and a signal repetition frequency of 200kHz. The present invention is not limited to this. The amplitude of the trigger signal can be between 1.8V and 5V, the pulse width can be between 50ns and 500ns, and the signal repetition frequency can be between 20kHz and 400kHz.

[0026] Please refer to Figure 2The filtering and protection circuit 101 includes: a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1 and a second diode D2, wherein a first end of the first capacitor C1 is connected to a trigger pulse signal input end, a second end of the first capacitor C1 is connected to a first end of the first resistor R1 and a first end of the second resistor R2, a second end of the first resistor R1 is grounded, a second end of the second resistor R2 is connected to a first end of the first diode D1 and a second end of the second diode D2, a first end of the second diode D2 is grounded, a second end of the first diode D1 is connected to a first end of the third resistor R3 and a first end of the second capacitor C2, a second end of the second capacitor C2 is grounded, a second end of the third resistor R3 is connected to a power supply VCC and a first end of the third capacitor C3, and a second end of the third capacitor C3 is grounded.

[0027] In the filtering and protection circuit 101, the high-pass filter network composed of the first resistor R1 and the first capacitor C1 performs preliminary filtering on the input signal, isolates interference signals such as DC components, and allows signals within the designed repetition frequency range (20kHz~400kHz) to pass. The second resistor R2 serves as a matching input resistor of the pulse shaping circuit. The first diode D1, the second diode D2, the third resistor R3, the second capacitor C2, and the third capacitor C3 together form an input protection circuit, which clamps the input signal between 0 and VCC to prevent the input signal from being too large and causing damage to the back-end circuit.

[0028] Next, the circuit structure of the pulse signal shaping circuit 102 will be described.

[0029] Please refer to Figure 2 The pulse signal shaping circuit 102 includes: a first inverter U1, a first high-speed diode D3, a second inverter U2, a fourth resistor R4, a fourth capacitor C4, a fifth capacitor C5, a fourth diode D4, and a fifth diode D5, wherein a first end of the first inverter U1 is connected to a second end of the second resistor R2 of the input signal filtering and protection circuit, a second end of the first inverter U1 is connected to a second end of the first high-speed diode D3, a first end of the first high-speed diode D3 is connected to a first end of the second inverter U2, a second end of the second inverter U2 is connected to a first end of the fourth diode D4 and a second end of the fifth diode D5, a first end of the fifth diode D5 is grounded, a second end of the fourth diode D4 is connected to a first end of the fourth resistor R4 and a first end of the fifth capacitor, a second end of the fourth resistor R4 and a first end of the fourth capacitor C4 are commonly connected to a power supply VCC, and a second end of the fourth capacitor C4 and a second end of the fifth capacitor C5 are commonly grounded.

[0030] In the pulse signal shaping circuit 102, the first and second inverters U1 and U2 shape the edge of the pulse signal, convert the pulse signal with a slowly changing edge into a rectangular pulse signal with a steep edge, and prevent the change of the output signal caused by a slight change in the input voltage (below a certain threshold). The first high-speed diode D3 shapes the negative pulse signal output by U1 to make the edge of the pulse signal steeper and improve the quality of the trigger pulse signal. The first high-speed diode D3, the fourth diode D4, the fourth resistor R4, the fourth capacitor C4 and the fifth capacitor C5 together constitute an output protection device of the pulse shaping circuit, which clamps the output signal between 0 and VCC to prevent the output signal from being too large and causing damage to the back-end circuit.

[0031] Next, the circuit structure of the pulse signal stepless delay adjustment circuit 103 is described.

[0032] Please refer to Figure 2 The pulse signal stepless delay adjustment circuit 103 includes: a coupling capacitor C6, a first high-speed D flip-flop U3, a fifth resistor R5, a first adjustable resistor RP1, and a seventh capacitor C7, wherein the first end of the coupling capacitor C6 is connected to the output end of the shaping circuit, i.e., the second end of the second inverter, the second section of the sixth capacitor C6 is connected to the clock input end, i.e., the third end, of the first high-speed D flip-flop U3, the second end of the data input end and the fourth section of the set input end of the first high-speed D flip-flop are connected to the power supply VCC, the fifth output end of the positive phase output end of the first high-speed D flip-flop U3 is not connected, the sixth end of the inverting output end of the first high-speed D flip-flop U3 is connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the second end of the adjustable resistor RP1, the first end of the adjustable resistor RP1 is connected to the reset input end of the first high-speed D flip-flop U3 and its third end, the third end of the first adjustable resistor RP1 is connected to the first end of the seventh capacitor C7, and the second end of the seventh capacitor C7 is connected to the ground.

[0033] In the pulse signal stepless delay adjustment circuit 103, the coupling capacitor C6 shapes the input trigger square wave signal, and uses the differential effect of the capacitor on the square wave signal to sharpen the trigger signal and use it as the input clock signal of the first high-speed D trigger U3. The input signal and the set end of the first high-speed D trigger U3 are connected to the high level VCC, so that the output signal of the trigger is only determined by the rising edge of the clock and the reset (clear) end. The positive phase output end of the first high-speed D trigger U3 is not used. The present invention only uses the negative phase output end of the first high-speed D trigger U3. The negative phase output end of the first high-speed D trigger U3 is connected to the fifth resistor R5, the first adjustable resistor RP1 and the seventh resistor R6. The fifth resistor R5, the first adjustable resistor RP1 and the seventh capacitor C7 form an RC network, and the output signal is fed back to the reset terminal of the first high-speed D flip-flop U3 through the first end of the first adjustable resistor RP1. The time constant of the RC network composed of them is adjusted by adjusting the parameter values ​​of the fifth resistor R5, the first adjustable resistor RP1 and the seventh capacitor C7, so that the length of the pulse signal delay is realized by the length of the arrival time of the low level of the feedback signal fed back to the reset terminal. The approximate length of the pulse signal delay can be determined by adjusting the parameter values ​​of the fifth resistor R5 and the seventh capacitor C7, and the precise stepless adjustment of the pulse signal delay can be realized by adjusting the parameter value of the first adjustable resistor RP1 (precision adjustable resistor).

[0034] Finally, the circuit structure of the pulse width stepless adjustment circuit 104 is described.

[0035] Please refer to Figure 2 The pulse signal stepless delay adjustment circuit 104 includes: a second high-speed D trigger U4, a sixth resistor R6, a second adjustable resistor RP2, an eighth capacitor C8, a ninth capacitor C9, and a first inductor L1, wherein the clock input terminal of the first high-speed D trigger U3, i.e., the third terminal, is connected to the output terminal of the pulse signal stepless delay adjustment circuit, i.e., the sixth terminal of the inverting output terminal of the first high-speed D trigger, the second terminal of the data input terminal and the fourth section of the set input terminal of the second high-speed D trigger are connected to the power supply VCC, the sixth terminal of the inverting output terminal of the second high-speed D trigger is connected to the first terminal of the sixth resistor R6, and the sixth capacitor C9 is connected to the first terminal of the sixth resistor R6. The second end of the resistor R6 is connected to the second end of the adjustable resistor RP2, the first end of the adjustable resistor RP2 is connected to the reset input terminal of the second high-speed D flip-flop U4 and its own third end, the third end of the adjustable resistor RP2 is connected to the first end of the eighth capacitor C8, the second end of the eighth capacitor C8 is connected to the ground, the fifth end of the positive phase output terminal of the second high-speed D flip-flop U4 is connected to the first end of the ninth capacitor C9, the second end of the ninth capacitor C9 is connected to the first end of the first inductor L1 as the output end of the entire circuit, and the second end of the first inductor L1 is connected to a high voltage power supply (100V~500V).

[0036] In the pulse width stepless adjustment circuit 104, the output signal of the previous stage circuit is used as the input clock signal of the second high-speed D flip-flop U4. The input signal and the set end of the second high-speed D flip-flop U4 are connected to the high level VCC, so that the output signal of the flip-flop is only determined by the rising edge of the clock and the reset (clear) end. The negative phase output end of the second high-speed D flip-flop U4 is connected to the RC network composed of the sixth resistor R6, the second adjustable resistor RP2 and the eighth capacitor C8, and the output signal is fed back to the reset end of the second high-speed D flip-flop U4 through the first end of the second adjustable resistor RP2. The time constant of the RC network composed of the sixth resistor R6, the second adjustable resistor RP2 and the eighth capacitor C8 is adjusted by adjusting the values ​​of the parameters of the sixth resistor R6, the second adjustable resistor RP2 and the eighth capacitor C8. Thereby, the width of the output pulse signal is adjusted according to the time when the low level of the feedback signal fed back to the reset terminal arrives. The approximate width of the pulse signal can be determined by adjusting the parameter values ​​of the sixth resistor R6 and the eighth capacitor C8. The precise stepless adjustment of the pulse signal width can be achieved by adjusting the parameter value of the second adjustable resistor RP2 (precision adjustable resistor). The signal is output through the positive phase output terminal of the second high-speed D-type flip-flop U4. The coupling capacitor C9 couples the final adjusted signal to the output terminal. If it is used as a trigger signal for some transmitters, the high-voltage power supply can be sent to the transmitter as an output through the first inductor L1. At this time, the coupling capacitor C9 needs to adopt a high-voltage resistant capacitor to prevent the DC high voltage from breaking down and damaging the second high-speed D-type flip-flop.

[0037] The working process of the stepless delay circuit with adjustable pulse width applicable to the multi-channel ground penetrating radar in this embodiment is as follows:

[0038] Step 1: When the trigger signal is in a low level state, the first diode D1, the second diode D2, the first high-speed diode D3, the fourth diode D4, and the fifth diode D5 are in a reverse cut-off state, the sixth inverting output end of the first high-speed D flip-flop U3 is in a high level state, the first reset end is in a high level state, the sixth inverting output end of the second high-speed D flip-flop U4 is in a high level state, the first reset end is in a high level state, the fifth resistor R5 and the first adjustable resistor RP1 charge the seventh charge and discharge capacitor C7, and the sixth resistor R6 and the second adjustable resistor RP2 charge the eighth charge and discharge capacitor C8.

[0039] Step 2: When the rising edge of the trigger signal arrives, the trigger signal becomes a high level, and the pulse is sharpened by the action of the first capacitor C1, and the DC component in the trigger signal is isolated with the action of the first resistor R1, and high-pass filtering is performed, and the pulse is input to the pulse shaping circuit through the input matching resistor second resistor R2. The third resistor R3, the second capacitor C2 and the third capacitor C3 form a power supply filter network for VCC filtering, filter out some clutter, and clamp the input pulse signal between 0 and VCC through the first diode D1 and the second diode D2. If the amplitude of the input signal is higher than VCC+Uth, the first diode D1 is turned on to stabilize the voltage at VCC+Uth. If the voltage amplitude of the input signal is lower than -Uth, the second diode D2 is turned on to stabilize the voltage at -Uth. Generally, Uth is relatively small, between 0.2 and 0.7V, so that the input voltage can be clamped in a safe range to ensure the safety of the subsequent circuit.

[0040] Step three: The filtered trigger signal is shaped for the first time by the first inverter U1, from a rising edge to a falling edge, and the edge signal is sharpened. The output state of the first inverter U1 is converted from a high level to a low level. At this time, the first high-speed diode D3 is turned on, and the input end of the second inverter U2 is converted from a high level state to a low level state. The rapid conduction of the first high-speed diode D3 will also sharpen and shape the edge of the trigger signal. Then, the trigger signal is input into the second inverter U2 for a third shaping, from a falling edge to a rising edge, and the edge signal is sharpened. The output state of the second inverter U2 is also quickly converted from a low level to a high level. The fourth resistor R4, the fourth capacitor C4, the fifth capacitor C5, the fourth diode D4 and the fifth diode D5 together form a protection network to clamp the output signal within a safe range to ensure the safe operation of the subsequent circuit.

[0041] Step 4: The shaped trigger signal is output to the clock input terminal of the first high-speed D flip-flop U3 through the coupling capacitor C6. When the rising edge of the trigger signal at the clock input terminal arrives, the state of the sixth terminal inverting output terminal changes from a high level to a low level, and the seventh capacitor C7 starts to discharge through the fifth resistor R5 and the first adjustable resistor RP1. The voltage at the first terminal of the seventh capacitor C7 cannot suddenly change to a low level immediately, but slowly decreases to a low level (0V) through discharge. At the same time, the voltage at the first terminal of the first adjustable resistor RP1 will also slowly decrease from a high level to a low level, and is fed back to the reset terminal of the first high-speed D flip-flop U3. When it is reduced to a low level, the first high-speed D flip-flop U3 is reset, and its sixth terminal inverting output terminal becomes a high level, and the seventh capacitor C7 is discharged through the fifth resistor R5 and the first adjustable resistor RP1. 7 is charged to make the input voltage of the reset end high level, wherein the time for the input level of the reset end to change from high level to low level is related to the time constant τ1 of the RC network composed of the fifth resistor R5, the first adjustable resistor RP1 and the seventh capacitor C7. If τ1 is relatively large, the level changes slowly, the reset time of the first high-speed D trigger U3 becomes longer, and the delay time of the output trigger signal becomes longer. On the contrary, if the time constant τ1 is relatively small, the level changes quickly, the reset time of the first high-speed D trigger U3 becomes shorter, and the delay time of the output trigger signal becomes shorter. The approximate length of the delay time can be preliminarily determined by the values ​​of the fifth resistor R5 and the seventh capacitor C7, and the delay of the trigger signal can be precisely and steplessly adjusted by adjusting the value of the precision adjustable resistor RP1.

[0042] Step 5: The delayed trigger signal is used as the clock input of the second high-speed D flip-flop U4. At this time, the phase of the delayed trigger signal changes, the rising edge becomes the falling edge, and the falling edge becomes the rising edge. The rising edge of the delayed signal output by the first high-speed D flip-flop U3 after reset is used as the input trigger signal of the second high-speed D flip-flop U4. When its state changes from a low level to a high level, the state of the sixth inverting output terminal of the second high-speed D flip-flop U4 changes from a high level to a low level, and the eighth capacitor C7 starts to discharge through the sixth resistor R6 and the second adjustable resistor RP2. The voltage at the first end of the eighth capacitor C8 cannot suddenly change to a low level, but slowly decreases to a low level (0V) through discharge. At the same time, the voltage at the first end of the second adjustable resistor RP2 will also slowly decrease from a high level to a low level, and is fed back to the reset end of the second high-speed D flip-flop U4. When it is reduced to a low level, the second high-speed D flip-flop U4 is reset, and its sixth inverting output terminal becomes a high level, and is transmitted through the sixth resistor R6 and the second adjustable resistor RP2. The second adjustable resistor RP2 charges the eighth capacitor C8, so that the input voltage of the reset end is a high level, wherein the time for the input level of the reset end to change from a high level to a low level is related to the time constant τ2 of the RC network composed of the sixth resistor R6, the first adjustable resistor RP2, and the eighth capacitor C8. If τ2 is relatively large, the level changes slowly, the reset time of the second high-speed D trigger U4 becomes longer, the high level maintenance time of the trigger signal output from the fifth end becomes longer, and the pulse width becomes wider. On the contrary, if the time constant τ2 is relatively small, the level changes quickly, the reset time of the second high-speed D trigger U4 becomes shorter, the high level maintenance time of the trigger signal output from the fifth end becomes shorter, and the pulse width becomes narrower. An approximate pulse width can be preliminarily determined by the values ​​of the sixth resistor R6 and the eighth capacitor C8, and the output trigger signal pulse width can be precisely and steplessly adjusted by adjusting the value of the precision adjustable resistor RP2, thereby adapting to different requirements of different transmitters or receivers for trigger pulse width.

[0043] Step six: The trigger signal after delay and pulse width adjustment is output from the fifth positive phase output terminal of the second high-speed D trigger U4 to the output terminal through the coupling capacitor ninth capacitor C9. If it is used as a trigger signal for some transmitters, the high-voltage DC power supply HV (100-500V) needs to be coupled into the output trigger signal through the first inductor L1. At the same time, the first inductor L1 can also filter out high-frequency AC signals, and can effectively filter out the ripple and some harmonic AC noise components in the high voltage HV, reducing the impact of noise on the back-end circuit. If the trigger signal does not require a high-voltage DC component, the first inductor L1 and the high-voltage power supply are not required.

[0044] Practical tests have proved that the pulse trigger signal after the delay adjustment of this embodiment can be delayed steplessly between 0 and 1000ps, the pulse width can be adjusted steplessly between 1ns and 500ns, the signal repetition frequency can be between 20kHz and 400kHz, and the processed signal has a steep rising edge, small jitter, and high trigger quality. It can meet the triggering requirements of different transmitters and receivers, and can accurately adjust the radar echo signals of different channels in the multi-channel ground penetrating radar to have consistent delays, fully ensuring the consistency between channels.

[0045] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Those skilled in the art may make some simple modifications, equivalent changes or modifications using the technical contents disclosed above, which all fall within the protection scope of the present invention.

Claims

1. A stepless delay circuit with adjustable pulse width, characterized in that: include: A pulse signal stepless delay adjustment circuit, wherein the pulse signal stepless delay adjustment circuit comprises: a coupling capacitor C6, a first high-speed D flip-flop U3, a fifth resistor R5, a first adjustable resistor RP1, and a seventh capacitor C7, wherein the coupling capacitor C6 is connected to a clock input terminal of the first high-speed D flip-flop U3, a data input terminal and a set input terminal of the first high-speed D flip-flop U3 are connected to a power supply VCC, an inverting output terminal of the first high-speed D flip-flop U3 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to a fixed pin of the first adjustable resistor RP1, another fixed pin of the first adjustable resistor RP1 is connected to a moving pin of the first adjustable resistor RP1 and a reset input terminal of the first high-speed D flip-flop U3, another fixed pin is also connected to one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded; It also includes: a pulse width stepless adjustment circuit, which includes: a second high-speed D flip-flop U4, a sixth resistor R6, a second adjustable resistor RP2, an eighth capacitor C8, a ninth capacitor C9 and a first inductor L1, a clock input terminal of the second high-speed D flip-flop U4 is connected to the inverting output terminal of the first high-speed D flip-flop U3, a data input terminal and a set input terminal of the second high-speed D flip-flop U4 are connected to the power supply VCC, a positive phase output terminal of the second high-speed D flip-flop U4 is connected to one end of the ninth capacitor C9, the other end of the ninth capacitor C9 is connected to one end of the first inductor L1, the other end of the first inductor L1 is connected to the high-voltage power supply HV, an inverting output terminal of the second high-speed D flip-flop U4 is connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to a fixed pin of the second adjustable resistor RP2, another fixed pin of the second adjustable resistor RP2 is connected to the moving pin of the second adjustable resistor RP2 and the reset input terminal of the second high-speed D flip-flop U4, another fixed pin is also connected to one end of the eighth capacitor C8, and the other end of the eighth capacitor C8 is grounded; It also includes: a pulse signal shaping circuit, which includes: a first inverter U1, a first high-speed diode D3, a second inverter U2, a fourth resistor R4, a fourth capacitor C4, a fifth capacitor C5, a fourth diode D4, and a fifth diode D5, wherein the output end of the first inverter U1 is connected to the cathode of the first high-speed diode D3, the anode of the first high-speed diode D3 is connected to the input end of the second inverter U2, the output end of the second inverter U2 is respectively connected to the anode of the fourth diode D4, the cathode of the fifth diode D5 and the coupling capacitor C6, the cathode of the fourth diode D4 is connected to the fifth capacitor C5 and one end of the fourth resistor R4, the other end of the fifth capacitor C5 is grounded, the other end of the fourth resistor R4 is connected to the power supply VCC and is connected to one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and the anode of the fifth diode D5 is grounded; It also includes: a filtering and protection circuit, which includes: a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1 and a second diode D2, wherein one end of the first capacitor C1 is connected to the input signal, and the other end is connected to one end of the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is grounded, the other end of the second resistor R2 is connected to the positive electrode of the first diode D1 and the negative electrode of the second diode D2, the negative electrode of the first diode D1 is connected to one end of the third capacitor C3 and the third resistor R3, the other end of the third capacitor C3 is grounded, the other end of the third resistor R3 is connected to the power supply VCC, and is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the positive electrode of the second diode D2 is grounded, and the other end of the second resistor R2 is also connected to the input end of the first inverter U1.

2. The stepless delay circuit with adjustable pulse width according to claim 1, characterized in that: The first inverter U1 and the second inverter U2 are both Schmitt inverters.

3. The stepless delay circuit with adjustable pulse width according to claim 1, characterized in that: The amplitude of the input trigger signal is between 1.8V and 5V, the pulse width is between 50ns and 500ns, and the signal repetition frequency is between 20kHz and 400kHz.

4. A multi-channel ground penetrating radar, characterized in that: include: A stepless delay circuit with adjustable pulse width according to any one of claims 1 to 3.

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