Data buffering method, device and computer readable storage medium

Abstract

The present invention provides a data buffering method, device and computer-readable storage medium, the method comprising the following steps: when writing data to be written to a memory through a cache area, obtaining target load information, wherein the target load information is used to represent data processing performance, and the cache capacity of the cache area is determined according to the write block size when the memory write speed meets a preset condition; adjusting the cache area according to the target load information, so as to write data to the memory through the adjusted cache area. The present invention dynamically adjusts the cache area according to actual usage, so that the actual buffering capacity of the system is adapted to the actual usage, improves the adaptability of data buffering, and meets different data writing requirements.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data buffering method, device and computer-readable storage medium. Background Art

[0002] At present, the implementation method of data buffering is basically to use a fixed area in the memory as a cache area, and write data to the built-in or external memory through the fixed cache area; this method does not take into account the actual usage conditions of the cache area, and thus cannot adapt to different usage environments, reducing writing efficiency. Summary of the invention

[0003] The main purpose of the present invention is to provide a data buffering method, a terminal device and a computer-readable storage medium, aiming to solve the problem of low adaptability of the current data buffering method.

[0004] To achieve the above object, an embodiment of the present invention proposes a data buffering method, comprising the following steps:

[0005] When writing data to be written to the memory through the cache area, obtaining target load information, wherein the target load information is used to indicate data processing performance, and the cache capacity of the cache area is determined according to the write block size when the memory write speed meets a preset condition;

[0006] The buffer area is adjusted according to the target load information so as to write data to the memory through the adjusted buffer area.

[0007] Optionally, the cache area includes a first cache area and a second cache area.

[0008] Accordingly, when writing the data to be written into the memory through the buffer area, the step of obtaining the target load information includes:

[0009] When writing the data to be written into the memory through the first buffer area, obtaining target load information;

[0010] Correspondingly, the step of adjusting the buffer area according to the target load information to obtain the adjusted buffer area, and writing data to the memory through the adjusted buffer area includes:

[0011] The second buffer area is adjusted according to the target load information, so as to write data to the memory through the adjusted second buffer area.

[0012] Optionally, when writing the data to be written into the memory through the first buffer area, before the step of acquiring the target load information, the step further includes:

[0013] Get the data capacity of the data to be written;

[0014] When the data capacity is greater than or equal to the first cache capacity of the first cache area, the data to be written is written to the memory through the first cache area.

[0015] Optionally, the step of obtaining the data capacity of the data to be written includes:

[0016] Acquire an input rate of data to be written in a first cycle, and determine a data capacity of the data to be written in the first cycle according to the input rate;

[0017] Correspondingly, when the data capacity is greater than or equal to the first cache capacity of the first cache area, the step of writing the to-be-written data to the memory through the first cache area includes:

[0018] When the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity, writing the data to be written to the memory through the first cache area in the first cycle;

[0019] Correspondingly, the step of acquiring the second cache capacity according to the target load information, and adjusting the second cache area according to the second cache capacity to write data to the memory through the adjusted second cache area includes:

[0020] A second cache capacity is acquired according to the target load information, and the second cache area is adjusted according to the second cache capacity, so as to write data to the memory through the adjusted second cache area in a second cycle.

[0021] Optionally, when the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity, the step of writing the data to be written to the memory through the first cache area in the first cycle includes:

[0022] When the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity, determining a first write count according to the data capacity and the first cache capacity, wherein the first write count is the number of writes to the memory in the first cycle;

[0023] The data to be written is written into the memory through the first buffer area within the first cycle according to the first writing number.

[0024] Optionally, the first cache capacity is determined according to the write block size and a first coefficient, and the first coefficient is a positive integer;

[0025] Correspondingly, the step of determining the first number of write times according to the data capacity and the first cache capacity includes:

[0026] A first write count is determined according to the data capacity, the write block size, and a first coefficient.

[0027] Optionally, the step of determining the first number of write times according to the data capacity, the write block size and the first coefficient includes:

[0028] The first number of write times is determined according to the data capacity, the write block size, the first coefficient and a preset formula, where the preset formula is:

[0029] M1*time1=BLK*Nu1*P1

[0030] Wherein, M1*time1 is the data capacity;

[0031] BLK is the write block size;

[0032] Nu1 is the first coefficient;

[0033] P1 is the first writing number.

[0034] Optionally, the target load information includes memory occupancy rate.

[0035] Correspondingly, the step of acquiring the second cache capacity according to the target load information includes:

[0036] When the memory occupancy rate is greater than a preset occupancy threshold, a second cache capacity is obtained, where the second cache capacity is smaller than the first cache capacity.

[0037] Optionally, when the memory occupancy rate is greater than a preset occupancy threshold, the step of acquiring the second cache capacity includes:

[0038] When the memory occupancy rate is greater than a preset occupancy threshold, determining a second coefficient according to the first coefficient, and obtaining a second cache capacity according to the write block size and the second coefficient, wherein the second coefficient is less than the first coefficient and is a positive integer; or,

[0039] When the memory occupancy rate is greater than a preset occupancy threshold, the second write number is determined based on the first write number, and the second storage capacity is obtained based on the second write number, the data capacity and the write block size, wherein the second write number is the number of writes to the memory in the second cycle, and the second write number is greater than the first write number.

[0040] Optionally, the target load information includes processor utilization,

[0041] Correspondingly, the step of acquiring the second cache capacity according to the target load information includes:

[0042] When the processor utilization is greater than a preset utilization threshold, a second cache capacity is acquired, wherein the second cache capacity is greater than the first cache capacity.

[0043] Optionally, when the processor utilization is greater than a preset utilization threshold, the step of acquiring the second cache capacity includes:

[0044] When the processor occupancy rate is greater than a preset occupancy threshold, determining a second coefficient according to the first coefficient, and obtaining a second cache capacity according to the write block size and the second coefficient, wherein the second coefficient is greater than the first coefficient and is a positive integer; or,

[0045] When the processor occupancy rate is greater than a preset occupancy threshold, a second write number is determined based on the first write number, and a second storage capacity is obtained based on the second write number, the data capacity and the write block size, wherein the second write number is the number of writes to the memory in the second cycle, and the second write number is less than the first write number.

[0046] Optionally, when writing the data to be written into the memory through the buffer area, before the step of acquiring the target load information, the step further includes:

[0047] Obtaining an input rate of data to be written, and obtaining a maximum write rate of the memory;

[0048] When the input rate is less than or equal to the maximum write rate, the data to be written is written to the memory through the buffer area.

[0049] In addition, to achieve the above-mentioned purpose, an embodiment of the present invention further proposes a data buffering device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program implements the steps of the data buffering method as described above when executed by the processor.

[0050] In addition, to achieve the above purpose, an embodiment of the present invention further proposes a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the data buffering method as described above are implemented.

[0051] When writing data to a memory through a cache area, the embodiment of the present invention obtains target load information to determine the data processing performance of the system, and then adjusts the cache area according to the target load information, thereby dynamically adjusting the cache area according to actual usage, so that the actual buffering capacity of the system is adapted to the actual usage, improving the adaptability of data buffering, meeting different data writing requirements, and helping to avoid buffering waste and improve data writing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic diagram of the structure of a data buffer device involved in an embodiment of the present invention;

[0053] Figure 2 FIG. 1 is a flow chart of a first embodiment of a data buffering method according to the present invention.

[0054] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0057] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0058] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0059] The data buffering method involved in the embodiment of the present invention is mainly applied to a data buffering device, which may be a server, a personal computer (PC), a notebook computer, a mobile phone, etc.

[0060] Reference Figure 1 , Figure 1It is a schematic diagram of the hardware architecture of the data buffer device involved in the embodiment of the present invention. In the embodiment of the present invention, the audio processing device includes a processor 1001 (such as a central processing unit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components; the user interface 1003 may include a display screen (Display), an input unit such as a key (Keyboard); the network interface 1004 may optionally include a standard wired interface, a wireless interface (such as wireless fidelity WIreless-FIdelity, WI-FI interface); the memory 1005 may be a high-speed random access memory (random access memory, RAM), or a stable memory (non-volatile memory), such as a disk storage, and the memory 1005 may optionally be a storage device independent of the aforementioned processor 1001. Of course, those skilled in the art will understand that Figure 1 The hardware structure shown in the figure does not constitute a limitation of the present invention.

[0061] Continue to refer to Figure 1 , Figure 1 The memory 1005 as a readable storage medium may include an operating system, a network communication module, and a computer program. Figure 1 In the embodiment, the network communication module can be used to connect to the database and perform data interaction with the database; and the processor 1001 can call the computer program stored in the memory 1005 and implement the data buffering method of the embodiment of the present invention.

[0062] An embodiment of the present invention provides a data buffering method.

[0063] Reference Figure 2 , Figure 2 FIG. 1 is a flow chart of a first embodiment of a data buffering method according to the present invention.

[0064] In this embodiment, the data buffering method includes the following steps:

[0065] Step S10, when writing the data to be written into the memory through the cache area, obtaining target load information, wherein the target load information is used to indicate the data processing performance, and the cache capacity of the cache area is determined according to the write block size when the memory write speed meets the preset condition;

[0066] At present, the implementation method of data buffering is basically to use part of the fixed area in the memory as a cache area, and write data to the built-in or external memory through the fixed cache area. For example, the digital television broadcasting system applies this method; this method does not take into account the actual use conditions of the cache area, so it cannot adapt to different use environments, reducing the writing efficiency. In this regard, an embodiment of the present invention proposes a data buffering method. When writing data to the memory through the cache area, the target load information is obtained to determine the data processing performance of the system, and then the cache area is adjusted according to the target load information, so as to dynamically adjust the cache area according to the actual use situation, so that the actual buffering capacity of the system is adapted to the actual use situation, the adaptability of the data buffer is improved, and different data writing requirements are met, which is conducive to avoiding buffer waste and improving data writing efficiency.

[0067] The data buffering method of this embodiment can be applied to a data buffering device, which is an independent physical device, such as a server, a personal computer (PC), a laptop, a mobile phone, etc.; it can also be applied to a device, which is an abstract functional device composed of one (such as a CPU) or multiple different physical functional modules. For the convenience of explanation, this embodiment takes the data buffering processing of a "device" as an example for explanation. In this embodiment, the device is connected to a memory, which can be a built-in memory of the device or an external memory, and the memory is a non-volatile memory (NVM). When the memory is powered off, the stored data will not disappear; and the device's memory (sometimes also called "running memory") is a volatile memory (Random Access Memory, RAM), or called random access memory, which is a temporary storage medium for the operating system or other running programs. When the power is off, the memory cannot retain data; part of the memory area will be set as a cache area; when external input data needs to be written to the memory, these data must first be stored in the cache area of ​​the memory, and then the data are written to the memory through the cache area. For the convenience of explanation, these data can be called data to be written.

[0068] It is worth noting that, in this embodiment, when setting the cache area, the cache capacity of the cache area (i.e., the size of the cache area) can be determined according to the write block size when the memory write speed meets the preset adjustment. Specifically, it can be determined according to the write block size of the memory at the highest write speed. The write block size can be recorded as BLK, and the cache capacity of the cache area is the product of BLK and a coefficient. The coefficient can be recorded as Nu, and Nu is a positive integer. For example, BLK is 2MB, Nu is 32, and the cache capacity is 64MB; of course, if the write block size of the memory at the highest write speed is not a fixed value, it can be the write block size of the memory at the highest write speed in a certain cycle. Get several values, and then calculate the average value to represent the write block size. Through the above settings, the data to be written into the memory through the cache area can just occupy several storage blocks of the memory, which is conducive to improving the efficiency of data writing and improving the utilization of memory storage space.

[0069] In this embodiment, when the device writes the data to be written to the memory through the cache area, the device will detect and obtain the current target load information, wherein the target load information is used to indicate the data processing performance, and may specifically include various types of information, such as memory occupancy, processor (such as CPU) utilization, processor temperature, etc. By obtaining the target load information, the data processing performance of the device can be determined so that the cache area can be adjusted in time later. Of course, when the device writes the data to be written to the memory through the cache area, it can be done through a specific thread, which can be called a write thread.

[0070] Step S20: adjusting the buffer area according to the target load information, so as to write data to the memory through the adjusted buffer area.

[0071] In this embodiment, after obtaining the target load information, the device can adjust the cache area according to the target load information; when adjusting the cache area, the cache capacity of the cache area is mainly adjusted, such as increasing the cache capacity, reducing the cache capacity, etc., and in subsequent use, data will be written to the memory through the adjusted cache area, so that the buffering capacity of the device (or system) is adapted to the actual usage.

[0072] It is worth noting that the cache area of ​​the device memory can be set as one area or two or more (here "or more" includes the number itself, the same below) relatively independent areas. For example, the cache area of ​​the device memory is an area with a cache capacity of; when writing data, the data is written to the memory through the only cache area, and then the only cache area is adjusted according to the target load information, and then the next data is written through the adjusted cache area. Of course, this dynamic adjustment process can be executed in a loop). For another example, the cache area of ​​the device memory is two relatively independent areas, which can be respectively referred to as the first cache area and the second cache area. The two cache areas can be pre-created, and then data is first written to the memory through the first cache area (or the second cache area), and then the second cache area (or the first cache area) is adjusted according to the target load information, and then the next data is written through the adjusted second cache area (or the first cache area), and then the first cache area is adjusted according to the target load information of the next data write, and the next data is written through the adjusted first cache area, and so on; of course, the cache area of ​​the device memory is two relatively independent areas, which can be respectively referred to as the first cache area and the second cache area. The first cache area is pre-created, and the second cache area is created and adjusted according to the target load information. The specific adjustment process is similar to the above and will not be repeated here.

[0073] In this embodiment, when writing data to be written to the memory through the cache area, target load information is obtained, wherein the target load information is used to indicate data processing performance, and the cache capacity of the cache area is determined according to the write block size when the memory write speed meets the preset conditions; the cache area is adjusted according to the target load information to write data to the memory through the adjusted cache area. In this embodiment, when writing data to the memory through the cache area, target load information is obtained to determine the data processing performance of the system, and then the cache area is adjusted according to the target load information, so that the cache area is dynamically adjusted according to the actual usage, so that the actual buffering capacity of the system is adapted to the actual usage, the adaptability of the data buffer is improved, and different data writing requirements are met, which is conducive to avoiding buffer waste and improving data writing efficiency.

[0074] Based on the above first embodiment of the data buffering method, a second embodiment of the data buffering method of the present invention is proposed.

[0075] In this embodiment, before step S10, the following steps are further included:

[0076] Step A30, obtaining an input rate of data to be written, and obtaining a maximum write rate of the memory;

[0077] In this embodiment, when the device obtains the data to be written, it will first obtain the input rate of the data to be written, and obtain the maximum write rate of the memory, and then compare the two; wherein the data to be written can be data manually input by the user, or data transmitted from the network or other devices, or other input forms.

[0078] Step A40: when the input rate is less than or equal to the maximum write rate, write the data to be written into the memory through the buffer area.

[0079] In this embodiment, when the input rate of the data to be written is less than or equal to the maximum write rate of the memory, it means that the data write speed (storage speed) of the memory can keep up with the input rate, that is, the input data can be stored in the memory in time, so the data to be written can be written to the memory through the cache area. When the input rate of the data to be written is greater than the maximum write of the memory, it means that the data write speed (storage speed) of the memory may not be able to keep up with the input rate, that is, the process of storing the input data to the memory has a lag. At this time, in order to avoid other risks that may be caused by the lag of data storage (such as data loss, thread blocking, etc.), relevant prompt information can be output to prompt the user to replace the memory with a higher write rate.

[0080] Through the above method, before writing the data to be written through the cache, this embodiment can first determine the relationship between the data input rate and the maximum write rate of the memory. When the input rate is less than or equal to the maximum write rate, the data to be written is written to the memory through the cache area, thereby ensuring the timeliness of data storage; and when the input rate is greater than the maximum write rate, relevant prompt information is output to prompt the user to replace the memory with a higher write rate, thereby avoiding other risks that may be caused by data storage lags.

[0081] Based on the above first embodiment of the data buffering method, a third embodiment of the data buffering method of the present invention is proposed.

[0082] In this embodiment, the cache area includes a first cache area and a second cache area. Accordingly, step S10 includes:

[0083] Step A11, when writing the data to be written into the memory through the first buffer area, obtaining target load information;

[0084] In this embodiment, the cache area of ​​the device memory is two relatively independent areas, which can be respectively referred to as the first cache area and the second cache area. The two cache areas can be pre-created. For example, the block write size is 2MB, the first cache capacity of the first cache area is 64MB, and the second cache capacity of the second cache area is 64MB; then data is written to the memory through the first cache area (or the second cache area), and the target load information is obtained when writing.

[0085] Accordingly, the step S20 includes:

[0086] Step A21, adjusting the second buffer area according to the target load information, so as to write data to the memory through the adjusted second buffer area.

[0087] After obtaining the target load information, the second cache area can be adjusted according to the target load information, and then the next data writing can be performed through the adjusted second cache area (or the first cache area), so that the cache area can be dynamically adjusted according to the actual usage, so that the actual buffering capacity of the system is adapted to the actual usage, and the adaptability of the data buffering is improved; of course, when the next data writing is performed through the adjusted second cache area (or the first cache area), the target load information can be obtained again, and then the first cache area can be adjusted according to the target load information, and the next data writing can be performed through the adjusted first cache area, and so on. It is worth noting that the first cache area and the second cache area in the above example are both pre-created, and in practice, only the first cache area can be pre-created, and the second cache area is newly created and adjusted according to the target load information. The specific adjustment process is similar to the above, and will not be repeated here.

[0088] Through the above method, the cache area is dynamically adjusted according to actual usage, so that the actual buffering capacity of the system is adapted to the actual usage, the adaptability of data buffering is improved, and different data writing requirements are met, which is conducive to avoiding buffer waste and improving data writing efficiency.

[0089] Based on the third embodiment of the data buffering method described above, a fourth embodiment of the data buffering method of the present invention is proposed.

[0090] In this embodiment, before step A11, the following steps are further included:

[0091] Step A01, obtaining the data capacity of the data to be written;

[0092] In this embodiment, when the device obtains the data to be written, it will obtain the data capacity of the data to be written, that is, determine the data amount of the data to be written.

[0093] Step A02: when the data capacity is greater than or equal to the first cache capacity of the first cache area, write the data to be written into the memory through the first cache area.

[0094] In this embodiment, when the data capacity of the data to be written is greater than or equal to the first cache capacity of the first cache area, the device can create a write thread, and then write the data to be written to the memory through the first cache area based on the write thread; of course, the write thread can also exist all the time, and when the data capacity of the data to be written is greater than or equal to the first cache capacity of the first cache area, the data to be written is written to the memory through the first cache area based on the write thread.

[0095] Through the above method, when the capacity of the data to be written is greater than or equal to the first cache capacity of the first cache area, the data to be written is written to the memory through the first cache area, thereby reducing the resource loss caused by multiple writes; and because the first cache capacity of the first cache area is determined based on the write block size, the data to be written written to the memory through the first cache area just occupies a number of storage blocks of the memory, which is beneficial to improving the efficiency of data writing and improving the utilization rate of the memory storage space.

[0096] Based on the fourth embodiment of the data buffering method described above, a fifth embodiment of the data buffering method of the present invention is proposed.

[0097] In this embodiment, the step A01 includes:

[0098] Step A011, obtaining an input rate of data to be written in a first cycle, and determining a data capacity of the data to be written in the first cycle according to the input rate;

[0099] In this embodiment, in order to effectively manage the data writing process, the natural time period can be divided into several continuous or discontinuous cycles, and data is written to the memory through different buffer areas in each cycle; for example, the cycle length of each cycle is 5s, 0-5s is recorded as the first cycle, 6-10s is recorded as the second cycle, 11-15s is recorded as the third cycle, and so on; and in the first cycle, data is written to the memory through the first buffer area, in the second cycle, data is written to the memory through the second buffer area, and in the third cycle, data is written to the memory through the first buffer area, and so on. Before writing in the first cycle, the input rate of the data to be written in the first cycle can be obtained first, and the data capacity of the data to be written in the first cycle can be determined according to the input rate. For example, if the input rate of the data to be written in the first cycle is M1, and the cycle length of the first cycle is time1, then the data capacity of the data to be written in the first cycle can be calculated to be M1*time1.

[0100] Accordingly, the step A02 includes:

[0101] Step A021, when the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity, writing the data to be written into the memory through the first cache area in the first cycle;

[0102] In this embodiment, when the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity of the first cache area, the data to be written can be written to the memory through the first cache area in the first cycle.

[0103] The step A21 comprises:

[0104] Step A211, obtaining a second cache capacity according to the target load information, and adjusting the second cache area according to the second cache capacity, so as to write data to the memory through the adjusted second cache area in a second cycle.

[0105] In this embodiment, when writing data to the memory through the first buffer area in the first cycle, the target load information of the writing process will be obtained. After obtaining the target load information, the second buffer area can be adjusted according to the target load information, and then the data is written to the memory through the adjusted second buffer area in the second cycle, so that the buffering capacity of the device (or system) is adapted to the actual usage. Of course, when writing data to the memory through the second buffer area in the second cycle, the target load information of the second cycle can also be continuously obtained, and then the first buffer area is adjusted according to the target load information of the second cycle, and then the data is written to the memory through the adjusted first buffer area in the third cycle, and so on.

[0106] Through the above method, data is written through different cache areas in different cycles, and unused cache areas are dynamically adjusted according to target load information, so that the actual buffering capacity of the system is adapted to the actual usage, improving the adaptability of data buffering and meeting different data writing requirements.

[0107] Based on the fifth embodiment of the data buffering method described above, a sixth embodiment of the data buffering method of the present invention is proposed.

[0108] In this embodiment, the step A021 includes:

[0109] Step A0211, when the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity, determining a first write count according to the data capacity and the first cache capacity, wherein the first write count is the number of writes to the memory in the first cycle;

[0110] In this embodiment, when the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity of the first cache area, the first number of writes can be determined according to the data capacity of the data to be written in the first cycle and the first cache capacity, wherein the first number of writes is the number of writes to the memory in the first cycle; for example, the first number of writes P1 is 2 times (2=128 / 64), that is, the memory must be written 2 times in the first week to write all the data to be written into the memory; of course, if the data capacity cannot be divided by the first cache capacity, the result can be rounded up to get the first number.

[0111] Furthermore, the first cache capacity of the first cache area is determined according to the write block size BLK. For example, the product of the write block size BLK and the first coefficient is taken as the cache capacity, and the first coefficient is recorded as Nu1, which is a positive integer. That is, the first cache capacity can be expressed as BLK*Nu1, then there is a preset formula:

[0112] M1*time1=BLK*Nu1*P1

[0113] Wherein, M1*time1 is the data capacity; BLK is the write block size; Nu1 is the first coefficient; P1 is the first write number. The first write number can be determined based on the obtained data capacity M1*time1, the write block size BLK, the first coefficient Nu1 and the preset formula. For example, if the data capacity M1*time1 of the data to be written in the first cycle is 128MB, the write block size is 2MB, and the first coefficient is 32, then the first write number P1 is 2 times.

[0114] Step A0212, writing the data to be written into the memory through the first cache area within the first cycle according to the first write number.

[0115] In this embodiment, when the first writing number is obtained, the data to be written can be written into the memory through the first buffer area within the first cycle according to the first writing number.

[0116] In the above manner, when writing the data to be written to the memory through the first cache area, the first write count can be obtained according to the data capacity of the data to be written and the first cache capacity, and the data is written according to the first write count to ensure that all the data to be written in the first cycle can be written into the memory.

[0117] Based on the sixth embodiment of the data buffering method described above, a seventh embodiment of the data buffering method of the present invention is proposed.

[0118] In this embodiment, the target load information includes memory occupancy rate; accordingly, in step A211, the step of acquiring the second cache capacity according to the target load information includes:

[0119] Step A2111: when the memory occupancy rate is greater than a preset occupancy threshold, a second cache capacity is obtained, and the second cache capacity is smaller than the first cache capacity.

[0120] In this embodiment, the target load information includes memory occupancy rate; that is, in the process of writing data to the memory through the first cache area, the memory occupancy rate will be obtained, and the memory occupancy rate can represent the data processing capacity of the device (or system). Among them, the larger the memory occupancy rate, the more memory space is used at this time, the higher the memory load is, and the data processing capacity will be negatively affected; when the memory occupancy rate is greater than the preset occupancy threshold, it means that the memory load is too high and the data processing capacity is relatively poor. At this time, in order to improve the data processing capacity, the second cache capacity can be obtained, and the second cache capacity is smaller than the first cache capacity. Then, the second cache area is adjusted by the second cache capacity, and the cache capacity of the second cache area is set to the second cache capacity, thereby reducing the overall cache area's memory occupancy and improving the data processing capacity.

[0121] Specifically, when the memory occupancy rate is greater than a preset occupancy threshold, the process of obtaining the second cache capacity can be calculated directly on the basis of the first cache capacity; since the first cache capacity is obtained by multiplying the block write size BLK by the first coefficient Nu1, and since the block write size BLK is related to the memory, a smaller second coefficient Nu2 can be determined based on the first coefficient Nu1, and then the second cache capacity is obtained by multiplying the block write size BLK and the second coefficient Nu2; for example, BLK is 2MB, Nu1 is 32, the first buffer capacity is 64MB, and Nu2 can be determined to be 30 based on Nu1, then the second cache capacity is 60MB (60=2*30). Secondly, the second capacity can also be obtained based on the relationship between data capacity, write times and cache capacity; in M1*time1=BLK*Nu1*P1, BLK*Nu1 is the first cache capacity, and when the data capacity M1*time1 remains unchanged, when the write times increase, the cache capacity will decrease accordingly; therefore, the second write times P2 can be obtained based on the first write times P1 (the second write times are the write times of the memory in the second cycle), and then the second cache capacity can be obtained based on the data capacity M1*time1 and the second write times P2; for example, the data capacity is 128MB, the first cache capacity BLK*Nu1 is 64MB, and the first write times P1 is 2. The second write times P2 can be determined to be 4 based on the first write times P1, and then the second cache capacity is determined to be 32MB (of course, when obtaining the second cache capacity, it is necessary to ensure that the second cache capacity is a positive integer multiple of the block write size).

[0122] Through the above method, when the memory utilization is high, the cache capacity of the cache area can be reduced, thereby reducing the memory load and improving the data processing capability.

[0123] Based on the sixth embodiment of the data buffering method described above, an eighth embodiment of the data buffering method of the present invention is proposed.

[0124] In this embodiment, the target load information includes processor utilization; accordingly, in step A211, the step of acquiring the second cache capacity according to the target load information further includes:

[0125] Step A2112: when the processor utilization is greater than a preset utilization threshold, obtain a second cache capacity, where the second cache capacity is greater than the first cache capacity.

[0126] In this embodiment, the target load information includes processor utilization; that is, in the process of writing data to the memory through the first cache area, the processor utilization will be obtained, and the processor utilization can represent the data processing capability of the device (or system). Among them, the greater the processor utilization, the higher the processor load, and the data processing capability will be negatively affected; when the processor utilization is greater than the preset utilization threshold, it means that the processor load is too high and the data processing capability is relatively poor. At this time, in order to improve the data processing capability, the second cache capacity can be obtained, and the second cache capacity is greater than the first cache capacity. Then, the second cache area is adjusted by the second cache capacity, and the cache capacity of the second cache area is set to the second cache capacity, thereby reducing the number of writes to the memory per cycle, reducing the amount of tasks of the processor, reducing the processor load, and improving the data processing capability.

[0127] Specifically, when the processor utilization is greater than a preset utilization threshold, the process of obtaining the second cache capacity can be calculated directly on the basis of the first cache capacity; since the first cache capacity is obtained by multiplying the block write size BLK by the first coefficient Nu1, and since the block write size BLK is related to the memory, a larger second coefficient Nu2 can be determined based on the first coefficient Nu1, and then the second cache capacity is obtained based on the multiplication of the block write size BLK and the second coefficient Nu2; for example, BLK is 2MB, Nu1 is 32, and the first buffer capacity is 64MB. According to Nu1, it can be determined that Nu2 is 64, then the second cache capacity is 128MB (60=2*64). Secondly, the second capacity can also be obtained based on the relationship between data capacity, write times and cache capacity; in M1*time1=BLK*Nu1*P1, BLK*Nu1 is the first cache capacity, and when the data capacity M1*time1 remains unchanged, when the write times decrease, the cache capacity will increase accordingly; therefore, the second write times P2 can be obtained based on the first write times P1 (the second write times are the write times of the memory in the second cycle), and then the second cache capacity can be obtained based on the data capacity M1*time1 and the second write times P2; for example, the data capacity is 128MB, the first cache capacity BLK*Nu1 is 64MB, and the first write times P1 is 2. The second write times P2 can be determined to be 1 based on the first write times P1, and then the second cache capacity is determined to be 128MB (of course, when obtaining the second cache capacity, it is necessary to ensure that the second cache capacity is a positive integer multiple of the block write size).

[0128] Through the above method, when the processor utilization is high, the cache capacity of the cache area can be increased, thereby reducing the processor load and improving data processing capabilities.

[0129] It is worth noting that when both the memory occupancy rate and the processor utilization rate are high, adjustments can be made based on the memory and processor priorities. For example, if the memory priority is higher, the second cache capacity can be obtained based on the memory occupancy rate, as shown in the above step A2111; and if the processor priority is higher, the second cache capacity can be obtained based on the processor utilization rate, as shown in the above step A2112; of course, at this time, there may also be a prompt that the input load is too high and the data processing capacity is insufficient, so as to prompt the user to take timely processing, such as reducing the input rate, replacing high-speed memory, etc.

[0130] In addition, an embodiment of the present invention further provides a readable storage medium.

[0131] The readable storage medium of the present invention stores a computer program, wherein when the computer program is executed by a processor, the steps of the above-mentioned data buffering method are implemented.

[0132] The method implemented when the computer program is executed may refer to the various embodiments of the data buffering method of the present invention, and will not be described in detail here.

[0133] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0134] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0135] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A data buffering method, characterized in that: The data buffering method comprises the following steps: When writing data to be written to the memory through the cache area, obtaining target load information, wherein the target load information is used to indicate data processing performance, the cache capacity of the cache area is determined according to the write block size when the memory write speed meets a preset condition, and the cache area includes a first cache area and a second cache area; adjusting the buffer area according to the target load information so as to write data to the memory through the adjusted buffer area; When writing the data to be written into the memory through the buffer area, the step of obtaining the target load information includes: When writing the data to be written into the memory through the first buffer area, obtaining target load information; adjusting the second buffer area based on the target load information; When writing data again to the memory through the adjusted second buffer area, obtaining target load information of the re-writing data; Based on the target load information of the second data writing, the first buffer area is adjusted.

2. The data buffering method according to claim 1, characterized in that: Accordingly, when writing the data to be written into the memory through the first buffer area, before the step of acquiring the target load information, it also includes: Get the data capacity of the data to be written; When the data capacity is greater than or equal to the first cache capacity of the first cache area, the data to be written is written to the memory through the first cache area.

3. The data buffering method according to claim 2, characterized in that: The step of obtaining the data capacity of the data to be written comprises: Acquire an input rate of data to be written in a first cycle, and determine a data capacity of the data to be written in the first cycle according to the input rate; Correspondingly, when the data capacity is greater than or equal to the first cache capacity of the first cache area, the step of writing the to-be-written data to the memory through the first cache area includes: When the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity, writing the data to be written to the memory through the first cache area in the first cycle; Correspondingly, the step of acquiring the second cache capacity according to the target load information, and adjusting the second cache area according to the second cache capacity to write data to the memory through the adjusted second cache area includes: A second cache capacity is acquired according to the target load information, and the second cache area is adjusted according to the second cache capacity, so as to write data to the memory through the adjusted second cache area in a second cycle.

4. The data buffering method according to claim 3, characterized in that: When the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity, the step of writing the data to be written into the memory through the first cache area in the first cycle includes: When the data capacity of the data to be written in the first cycle is greater than or equal to the first cache capacity, determining a first write count according to the data capacity and the first cache capacity, wherein the first write count is the number of writes to the memory in the first cycle; The data to be written is written into the memory through the first buffer area within the first cycle according to the first writing number.

5. The data buffering method according to claim 4, characterized in that: The first cache capacity is determined according to the write block size and a first coefficient, and the first coefficient is a positive integer; Correspondingly, the step of determining the first number of write times according to the data capacity and the first cache capacity includes: A first write count is determined according to the data capacity, the write block size, and a first coefficient.

6. The data buffering method according to claim 5, characterized in that: The step of determining the first number of write times according to the data capacity, the write block size and the first coefficient comprises: The first number of write times is determined according to the data capacity, the write block size, the first coefficient and a preset formula, where the preset formula is: M1*time1=BLK*Nu1*P1 Wherein, M1*time1 is the data capacity; BLK is the write block size; Nu1 is the first coefficient; P1 is the first writing number.

7. The data buffering method according to claim 5, characterized in that: The target load information includes a memory occupancy rate. Accordingly, the step of acquiring the second cache capacity according to the target load information includes: When the memory occupancy rate is greater than a preset occupancy threshold, a second cache capacity is obtained, where the second cache capacity is smaller than the first cache capacity.

8. The data buffering method according to claim 7, characterized in that: When the memory occupancy rate is greater than a preset occupancy threshold, the step of obtaining the second cache capacity includes: When the memory occupancy rate is greater than a preset occupancy threshold, determining a second coefficient according to the first coefficient, and obtaining a second cache capacity according to the write block size and the second coefficient, wherein the second coefficient is less than the first coefficient and is a positive integer; or, When the memory occupancy rate is greater than a preset occupancy threshold, the second write number is determined based on the first write number, and the second storage capacity is obtained based on the second write number, the data capacity and the write block size, wherein the second write number is the number of writes to the memory in the second cycle, and the second write number is greater than the first write number.

9. The data buffering method according to claim 5, characterized in that: The target load information includes processor utilization, and accordingly, the step of acquiring the second cache capacity according to the target load information includes: When the processor utilization is greater than a preset utilization threshold, a second cache capacity is acquired, wherein the second cache capacity is greater than the first cache capacity.

10. The data buffering method according to claim 9, characterized in that: When the processor utilization is greater than a preset utilization threshold, the step of obtaining the second cache capacity includes: When the processor utilization is greater than a preset occupancy threshold, determining a second coefficient according to the first coefficient, and obtaining a second cache capacity according to the write block size and the second coefficient, wherein the second coefficient is greater than the first coefficient and is a positive integer; or, When the processor utilization is greater than a preset occupancy threshold, the second write number is determined based on the first write number, and the second storage capacity is obtained based on the second write number, the data capacity and the write block size, wherein the second write number is the number of writes to the memory in the second cycle, and the second write number is less than the first write number.

11. The data buffering method according to claim 1, characterized in that: When writing the data to be written into the memory through the buffer area, before the step of obtaining the target load information, the method further includes: Obtaining an input rate of data to be written, and obtaining a maximum write rate of the memory; When the input rate is less than or equal to the maximum write rate, the data to be written is written to the memory through the buffer area.

12. A data buffer device, characterized in that: The data buffering device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the data buffering method according to any one of claims 1 to 11 when executed by the processor.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data buffering method according to any one of claims 1 to 11 are implemented.

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