Non-volatile memory devices

Abstract

A nonvolatile memory device includes a first memory cell array, a first bidirectional multiplexer, a first register, a second register, a first I / O pad, and a second I / O pad. The first memory cell array stores first data. The first bidirectional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The first register stores the first sub-data from the first bidirectional multiplexer. The second register stores the second sub-data from the second bidirectional multiplexer. The first I / O pad outputs the first sub-data from the first register to the outside. The second I / O pad outputs the second sub-data from the second register to the outside.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2019-0015298 filed in the Korean Intellectual Property Office on February 11, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to non-volatile memory devices. Background Art

[0003] Semiconductor memory devices are memory devices that can store data so that the data can be read when necessary. Semiconductor memory devices can be roughly divided into random access memory (RAM) devices and read-only memory (ROM) devices. RAM devices are volatile memory devices in which the stored data disappears when the power is turned off. ROM devices are non-volatile memory devices in which the stored data does not disappear even when the power is turned off. RAM devices include dynamic RAM (DRAM), static RAM (SRAM), etc. ROM devices include programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), flash memory devices, etc.

[0004] As the speed of microprocessors increases, semiconductor memory devices also need to increase their speed. For this reason, semiconductor memory devices incorporating pipeline technology have been introduced. Pipeline technology divides a series of processes performed in a semiconductor memory device so that different processes are performed in parallel by different parts of the processor. The series of processes may, for example, include: first, input of an address; second, decoding of an address; third, output of data from a memory cell; fourth, data transmission to an output circuit; and fifth, output of data in / from a semiconductor memory device. In pipeline technology, a first process is first performed on a first command, and then a second process is performed on the first command when the first process is started on the second command, so that the second process on the first command and the first process on the second command are performed simultaneously. Therefore, a semiconductor memory device using pipeline technology can effectively increase the processing speed of commands. A semiconductor memory device may use a wave pipeline system that uses a known or predictable propagation delay of a logic circuit and controls the waiting time of data output by using a final register connected to an output terminal.

[0005] However, when operating at a high frequency (HF), a deviation occurs in a path between an output terminal and a final register connected to the output terminal, and thus performance characteristics are degraded. As a result, high-speed operation of the semiconductor memory device may be difficult. Summary of the invention

[0006] Aspects of the present disclosure provide a nonvolatile memory device that operates at high speed.

[0007] Aspects of the present disclosure also provide a nonvolatile memory device that reduces a skew between output data and a clock signal.

[0008] However, the aspects of the present disclosure are not limited to the contents set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0009] According to an exemplary embodiment of the present disclosure, a nonvolatile memory device includes a first memory cell array, a first bidirectional multiplexer, a second bidirectional multiplexer, a first register, a second register, a first I / O pad, and a second I / O pad. The first memory cell array stores first data. The first bidirectional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The second bidirectional multiplexer receives the second sub-data from the first bidirectional multiplexer. The first register stores the first sub-data from the first bidirectional multiplexer. The second register stores the second sub-data from the second bidirectional multiplexer. The first I / O pad outputs the first sub-data from the first register to the outside. The second I / O pad outputs the second sub-data from the second register to the outside.

[0010] According to another exemplary embodiment of the present disclosure, a nonvolatile memory device includes a first I / O pad, a first register, a first bidirectional multiplexer, a second bidirectional multiplexer, a first memory cell array, and a second memory cell array. The first I / O pad receives first data. The first register stores the first data and sends the first data to the first I / O pad. The first bidirectional multiplexer sends the first data to the first register. The first data includes first sub-data and second sub-data. The second bidirectional multiplexer sends the second sub-data. The first memory cell array stores the first sub-data and sends the first sub-data to the first bidirectional multiplexer, and the second memory cell array stores the second sub-data and sends the second sub-data to the second bidirectional multiplexer.

[0011] According to another exemplary embodiment of the present disclosure, a nonvolatile memory device includes a first memory cell array, a second memory cell array, a first bidirectional multiplexer, a second bidirectional multiplexer, a first register, a second register, a first I / O pad, and a second I / O pad. The first memory cell array stores first data and the second memory cell array stores second data. The first bidirectional multiplexer receives the first data. The first data includes first sub-data and second sub-data. The second bidirectional multiplexer receives the second data. The second data includes third sub-data and fourth sub-data. The second bidirectional multiplexer receives the second sub-data from the first bidirectional multiplexer and sends the fourth sub-data to the first bidirectional multiplexer. The first register receives the first sub-data and the third sub-data from the first bidirectional multiplexer. The second register receives the second sub-data and the fourth sub-data from the second bidirectional multiplexer. The first I / O pad outputs the first sub-data and the third sub-data from the first register to the outside, and the second I / O pad outputs the second sub-data and the fourth sub-data from the second register to the outside. The frequency of the first clock applied to the first bidirectional multiplexer and the second bidirectional multiplexer is lower than the frequency of the second clock applied to the first register and the second register.

[0012] These and / or other aspects will become more apparent and more easily understood through the following description of the embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is an exemplary block diagram illustrating a memory device including a nonvolatile memory device.

[0014] Figure 2 It shows Figure 1 An exemplary block diagram of a non-volatile memory device.

[0015] Figure 3 It shows Figure 2 An exemplary block diagram of the first plane of FIG.

[0016] Figure 4 It shows Figure 2 An exemplary block diagram of the second plane of FIG.

[0017] Figure 5 is another exemplary block diagram illustrating a nonvolatile memory device according to some embodiments of the present disclosure.

[0018] Figure 6 is another exemplary block diagram illustrating a nonvolatile memory device according to some embodiments of the present disclosure.

[0019] Figure 7 It shows Figure 1 Another exemplary block diagram of a non-volatile memory device.

[0020] Figure 8 It shows Figure 7 An exemplary block diagram of the third plane of FIG.

[0021] Fig. 9 is another exemplary block diagram illustrating a nonvolatile memory device according to some embodiments of the present disclosure.

[0022] Fig.10 is another exemplary block diagram illustrating a nonvolatile memory device according to some embodiments of the present disclosure.

[0023] Fig.11 is a block diagram illustrating a computing system including a non-volatile memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] Figure 1 is an exemplary block diagram illustrating a memory device including a nonvolatile memory device.

[0025] refer to Figure 1 , the memory device 1 includes a nonvolatile memory device 100 and a controller 3 .

[0026] The controller 3 may be connected to the host 2 and the nonvolatile memory device 100. The controller 3 may access the nonvolatile memory device 100 in response to a request from the host 2. For example, the controller 3 may be configured to control read, program, erase, and background operations of the nonvolatile memory device 100.

[0027] The controller 3 may include an interface. In addition, the controller 3 may drive firmware to control the non-volatile memory device 100. Before continuing, it should be clear that the non-volatile memory device 100 is included in this document. Figure 1 and Fig.11The figure shows and refers to a circuit system with a label "controller". Such a circuit system can be or include a processor, which includes a microprocessor or an application-specific integrated circuit (ASIC) and other elements with other labels. As is common in the field of the inventive concept described herein, examples can be described and illustrated according to blocks (such as circuits and other elements) that perform one or more functions described. These blocks, which may be referred to as controllers, etc. in this article, are physically implemented by analog and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and can be optionally driven by firmware and / or software. For example, the circuit can be specifically implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuits constituting the blocks can be implemented by dedicated hardware or processors (for example, one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware used to perform some functions of the block and a processor used to perform other functions of the block. Without departing from the scope of the present disclosure, each block of the example can be physically divided into two or more interactive and discrete blocks. Similarly, the illustrated blocks may be physically combined into more complex blocks without departing from the scope of the present disclosure.

[0028] Figure 2 It shows Figure 1 An exemplary block diagram of a non-volatile memory device. Figure 3 It shows Figure 2 An exemplary block diagram of the first plane of FIG. Figure 4 It shows Figure 2 An exemplary block diagram of the second plane of FIG.

[0029] refer to Figure 2 , the nonvolatile memory device 100 includes a first plane 600, a second plane 700, and a final stage 800 of the nonvolatile memory device. The clock generator 190 and / or the delay clock generator 195 may be provided outside the nonvolatile memory device 100, or may be included as a component of the nonvolatile memory device 100. It is worth noting that the delay clock generator 195 may be physically and / or logically separated from the clock generator 190. The final stage 800 of the nonvolatile memory device includes a first bidirectional multiplexer 150, a second bidirectional multiplexer 160, a third register 155, a fourth register 165, a first I / O pad 161, a second I / O pad 171, a clock multiplexer 170, a third delay trimming 137, a third clock input terminal 139, and a third clock delay input terminal 140.

[0030] The non-volatile memory device 100 may operate synchronously with an external clock such as a clock generator 190 and / or a delay clock generator 195. Incidentally, when the frequency of the clock generator 190 rises, the delay may continue to increase. In this article, the delay is the number of cycles of the clock generator 190 required until the first data is output after the output command is input from the outside to the non-volatile memory device 100. "External" may be external to the non-volatile memory device 100, or external to a device or system including the non-volatile memory device 100. In addition, the output command may be received by / at such a device or system via an electronic communication network, or the output command may be received as input via other input mechanisms such as a touch screen, a keypad, or for inputting commands. The non-volatile memory device 100 may use a wave pipeline system utilizing a delay clock generator 195 in order to effectively control the increase in delay, but the structure of the wave pipeline system is not limited thereto.

[0031] refer to Figure 2 and Figure 3 The first plane 600 includes a first memory cell array 101 , a first page buffer driver 103 , a first delay trimming 107 , a first clock input terminal 109 , a first clock delay input terminal 110 and a first register 105 .

[0032] The first plane 600 is an exemplary block diagram using a wave pipeline system, but the configuration of the first plane 600 is not limited thereto.

[0033] When an output command of the first data in the first memory cell array 101 is input, the first data is transmitted from the first memory cell array 101 to the first register 105 via the first page buffer driver 103. The first data may be parallel data transmitted or otherwise processed in parallel with other data such as the second data. The transmission scheme of the first data is not limited thereto.

[0034] The first data output from the first memory cell array 101 is synchronized with the first clock signal CLK1 generated by the clock generator 190 and can be stored in the first register 105. The first clock signal CLK1 can be transmitted to the first register 105 via the first delay trimming 107 and the first clock input terminal 109, but the transmission scheme is not limited thereto. In addition, the first delayed clock signal L_CLK1 for delay control transmitted by the delay clock generator 195 can be transferred (transmitted) to the first register 105. The first delayed clock signal L_CLK1 can be transmitted to the first register 105 through the first clock delay input terminal 110. The first clock delay input terminal 110 can transmit the first clock multiplexer signal CLKM1 to the clock multiplexer 170.

[0035] refer to Figure 2 and Figure 4 The second plane 700 includes a second memory cell array 111 , a second page buffer driver 113 , a second delay trimming 117 , a second clock input terminal 119 , a second clock delay input terminal 120 and a second register 115 .

[0036] The second plane 700 is an exemplary block diagram using a wave pipeline system, but the configuration of the second plane 700 is not limited thereto.

[0037] When an output command of the second data in the second memory cell array 111 is input, the second data is transmitted from the second memory cell array 111 to the second register 115 via the second page buffer driver 113. The second data may be parallel data transmitted or otherwise processed in parallel with other data such as the first data. The transmission scheme of the second data is not limited thereto.

[0038] The second data output from the second memory cell array 111 is synchronized with the second clock signal CLK2 generated by the clock generator 190 and can be stored in the second register 115. The second clock signal CLK2 can be transmitted to the second register 115 via the second delay trimming 117 and the second clock input terminal 119, but the transmission scheme is not limited thereto. In addition, the second delayed clock signal L_CLK2 for delay control transmitted by the delay clock generator 195 can be transferred (transmitted) to the second register 115. The second delayed clock signal L_CLK2 can be transmitted to the second register 115 through the second clock delay input terminal 120. The second clock delay input terminal 120 can transmit the second clock multiplexer signal CLKM2 to the clock multiplexer 170.

[0039] Will refer to it again Figure 2 A path for outputting the first data in the first plane 600 is described.

[0040] When the first data in the first plane 600 is output, the first clock multiplexer signal CLKM1 can be sent from the clock multiplexer 170 to the third register 155 and the fourth register 165 through the third delay trimming 137 and the third clock input terminal 139. The transmission scheme of the first clock multiplexer signal CLKM1 is not limited to this. In addition, the delay signal can be sent from the delay clock generator 195 to the third register 155 and the fourth register 165 through the third clock delay input terminal 140 for delay control. The clock input system according to the wave pipeline structure is not limited to this.

[0041] The first sub-data of the first data in the first plane 600 may be sent to the third register 155 via the first bidirectional multiplexer 150. The first sub-data of the first data may be sent to the first I / O pad 161 through the third register 155. The first I / O pad 161 may include but is not limited to the first to fourth I / O registers IO0 to IO3.

[0042] In addition, the second sub-data of the first data in the first plane 600 can be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The second sub-data of the first data can be sent to the fourth register 165 through the second bidirectional multiplexer 160. The second sub-data of the first data can be sent to the second I / O pad 171 through the fourth register 165. The second I / O pad 171 may include, but is not limited to, the fifth I / O register IO4 to the eighth I / O register IO7.

[0043] The third register 155 and the fourth register 165 may operate in a high frequency (HF) region, and a deviation may occur between the first data and the clock signal transmitted through the third clock input terminal 139 and / or the third clock delay input terminal 140. Therefore, the possibility of occurrence of the deviation or the magnitude of the deviation may be reduced by shortening the data transmission distance between the first I / O pad 161 and the second I / O pad 171 and the third register 155 and the fourth register 165, thereby realizing high-speed operation of the nonvolatile memory device 100.

[0044] For example, the case of outputting the first data to the first I / O pad 161 and the second I / O pad 171 using one multiplexer and one register can be easily compared with the case based on Figure 3 In this case, the path of the first data traveling to the first I / O pad 161 and the second I / O pad 171 arranged on the left and right through the single register operating in HF is smaller than Figure 2 The final stage is 800 meters long.

[0045] That is, by arranging the third register 155 and the fourth register 165 in a one-to-one relationship with each of the first I / O pad 161 and the second I / O pad 171, the path of the first data operated in HF can be shortened, thereby reducing the possibility of deviation or the magnitude of deviation, and achieving high-speed operation of the non-volatile memory device 100.

[0046] A path for outputting the second data in the second plane 700 will be described.

[0047] When the second data in the second plane 700 is output, the second clock multiplexer signal CLKM2 can be sent from the clock multiplexer 170 to the third register 155 and the fourth register 165 through the third delay adjustment 137 and the third clock input terminal 139. The sending scheme of the second clock multiplexer signal CLKM2 is not limited to this. In addition, the delay signal can be sent from the delay clock generator 195 to the third register 155 and the fourth register 165 through the third clock delay input terminal 140 for delay control. The clock input system according to the wave pipeline structure is not limited to this.

[0048] The first sub-data of the second data in the second plane 700 may be sent to the fourth register 165 through the second bidirectional multiplexer 160. The first sub-data of the second data may be sent to the second I / O pad 171 through the fourth register 165. The second I / O pad 171 may include but is not limited to the fifth I / O register IO4 to the eighth I / O register IO7.

[0049] In addition, the second sub-data of the second data in the second plane 700 can be sent to the first bidirectional multiplexer 150 through the second bidirectional multiplexer 160. The second sub-data of the second data can be sent to the third register 155 through the first bidirectional multiplexer 150. The second sub-data of the second data can be sent to the first I / O pad 161 through the third register 155. The first I / O pad 161 may include, but is not limited to, the first I / O register IO0 to the fourth I / O register IO3.

[0050] The third register and the fourth register may operate in a high frequency (HF) region, and a deviation may occur between the second data and the clock signal transmitted through the third clock input terminal 139 and / or the third clock delay input terminal 140. Therefore, the possibility of occurrence of the deviation or the magnitude of the deviation may be reduced by shortening the data transmission distance between the first I / O pad 161 and the second I / O pad 171 and the third register 155 and the fourth register 165, thereby realizing high-speed operation of the nonvolatile memory device 100.

[0051] For example, the case of outputting the second data to the first I / O pad 161 and the second I / O pad 171 using one multiplexer and one register can be easily compared with the case based on Figure 4 In this case, the path of the second data traveling to the first I / O pad 161 and the second I / O pad 171 arranged on the left and right through the single register operating in HF is smaller than Figure 2 The final stage is 800 meters long.

[0052] That is, by arranging the third register 155 and the fourth register 165 in a one-to-one relationship with each of the first I / O pad 161 and the second I / O pad 171, the path of the second data operated in HF can be shortened, thereby reducing the possibility of deviation or the magnitude of deviation, and achieving high-speed operation of the non-volatile memory device 100.

[0053] Figure 5 is another exemplary block diagram illustrating a nonvolatile memory device according to some embodiments of the present disclosure.

[0054] refer to Figure 2 and Figure 5 , the last stage 800 of the nonvolatile memory device 100 includes a first bidirectional multiplexer 150, a second bidirectional multiplexer 160, a third register 213, a fourth register 215, a fifth register 223 and a sixth register 225, and a first I / O pad 230, a second I / O pad 240, a third I / O pad 250 and a fourth I / O pad 260.

[0055] For reference, blocks associated with a clock sent to each register are omitted in the drawing for convenience.

[0056] The third register 213 and the fourth register 215 may be connected to the first bidirectional multiplexer 150. The first I / O pad 230 may be connected to the third register 213. The second I / O pad 240 may be connected to the fourth register 215 (or a sub-register of the third register 213). The fifth register 223 and the sixth register 225 may be connected to the second bidirectional multiplexer 160. The third I / O pad 250 may be connected to the fifth register 223. The fourth I / O pad 260 may be connected to the sixth register 225 (or a sub-register of the fifth register 223).

[0057] In an alternative embodiment, third register 213 and fourth register 215 may be considered together as a first register, which includes third register 213 as a first sub-register and fourth register 215 as a second sub-register. In this alternative embodiment, first I / O pad 230 and second I / O pad 240 may be considered together as a single first I / O pad, such that third register 213 as a first sub-register is connected to a portion of the single first I / O pad, and such that fourth register 215 as a second sub-register is connected to the remaining portion of the single first I / O pad.

[0058] Based on Figure 5 , Figure 6 , Figure 7 , Fig. 9 and / or Fig.10In an embodiment, the number of registers is the same as the number of I / O pads, and the registers and I / O pads are arranged in a one-to-one relationship. Figure 5 In the embodiment, the third register 213 and the fourth register 215 can be considered as a first register together, and the first I / O pad 230 and the second I / O pad 240 can be considered as a first I / O pad together. Figure 5 The number of the first register and the first I / O pad are the same, and for direct based Figure 6 , Figure 7 , Fig. 9 and Fig.10 Therefore, in some embodiments of the present invention, such a first register and such a first I / O pad are arranged in a one-to-one relationship. Similarly, in Figure 6 In the embodiment, the fifth register 223 and the sixth register 225 can be considered together as the second register, and the third I / O pad 250 and the fourth I / O pad 260 can be considered together as the second I / O pad. Figure 5 The number of second registers and second I / O pads is the same, and for direct-based Figure 6 , Figure 7 , Fig. 9 and Fig.10 The similar arrangement in the embodiment of can be visually confirmed to be the same. Therefore, in some embodiments of this article, such a second register and such a second I / O pad are set in a one-to-one relationship.

[0059] In the above alternative embodiment, the fifth register 223 and the sixth register 225 can be considered together as a second register, which includes the fifth register 223 as a third sub-register and the sixth register 225 as a fourth sub-register. In this alternative embodiment, the third I / O pad 250 and the fourth I / O pad 260 can be considered together as a single second I / O pad, so that the fifth register 223 as the third sub-register is connected to a portion of the single second I / O pad, and the sixth register 225 as the fourth sub-register is connected to the remaining portion of the single second I / O pad. It is to be recognized that this alternative embodiment is not limited to the first register and the second register each having two sub-registers, or the first I / O pad and the second I / O pad each having a portion and a remaining portion. On the contrary, more than two registers can be provided with sub-register relationships, for example in a configuration based on Fig. 9 and Fig.10In an alternative embodiment of the present invention, the three groups of registers can be divided into sub-registers. Similarly, any grouped "registers" are not limited to two sub-registers. Instead, more than two registers can be grouped into sub-registers of a single "register", for example in a Figure 6 In alternatives to the embodiments of the present invention, groups of four registers may be grouped as sub-registers of a single "register," and groups of four I / O pads may be grouped as portions of a single I / O pad.

[0060] A path for outputting the first data in the first plane 600 will be described.

[0061] The first sub-data of the first data in the first plane 600 may be sent to the third register 213 through the first bidirectional multiplexer 150. The first sub-data of the first data may be sent to the first I / O pad 230 through the third register 213. The first I / O pad 230 may include, but is not limited to, a first I / O register IO0 and a second I / O register IO1.

[0062] The second sub-data of the first data in the first plane 600 may be transmitted to the fourth register 215 via the first bidirectional multiplexer 150. The second sub-data of the first data may be transmitted to the second I / O pad 240 via the fourth register 215. The second I / O pad 240 may include but is not limited to the third I / O register IO2 to the fourth I / O register IO3.

[0063] The third sub-data of the first data in the first plane 600 may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The third sub-data of the first data may be sent to the fifth register 223 via the second bidirectional multiplexer 160. The third sub-data of the first data may be sent to the third I / O pad 250 through the fifth register 223. The third I / O pad 250 may include, but is not limited to, the fifth I / O register IO4 to the sixth I / O register IO5.

[0064] The fourth sub-data of the first data in the first plane 600 may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The fourth sub-data of the first data may be sent to the sixth register 225 through the second bidirectional multiplexer 160. The fourth sub-data of the first data may be sent to the fourth I / O pad 260 through the sixth register 225. The fourth I / O pad 260 may include, but is not limited to, the seventh I / O register IO6 to the eighth I / O register IO7.

[0065] The third register 213, the fourth register 215, the fifth register 223, and the sixth register 225 may operate in a high frequency (HF) region, and a deviation may occur between the first data and the clock signal to be input to the third register 213, the fourth register 215, the fifth register 223, and the sixth register 225. Therefore, by shortening the data transmission distance between the first I / O pad 230, the second I / O pad 240, the third I / O pad 250, and the fourth I / O pad 260 and the third register 213, the fourth register 215, the fifth register 223, and the sixth register 225, the possibility of the occurrence of the deviation or the magnitude of the deviation may be reduced, thereby realizing high-speed operation of the nonvolatile memory device 100.

[0066] For example, the case of outputting the first data to the first I / O pad 230, the second I / O pad 240, the third I / O pad 250, and the fourth I / O pad 260 using one multiplexer and one register can be easily compared with the case of outputting the first data to the first I / O pad 230, the second I / O pad 240, the third I / O pad 250, and the fourth I / O pad 260 based on Figure 5 In this case, the path of the first data traveling to the first I / O pad 230, the second I / O pad 240, the third I / O pad 250, and the fourth I / O pad 260 arranged on the left and right through the single register operating in HF is smaller than that of the first data. Figure 5 The final stage is 800 meters long.

[0067] That is, by arranging the third register 213, the fourth register 215, the fifth register 223 and the sixth register 225 in a one-to-one relationship with each of the first I / O pad 230, the second I / O pad 240, the third I / O pad 250 and the fourth I / O pad 260, the path of the first data operated in HF can be shortened, thereby reducing the possibility of deviation or the magnitude of deviation, and achieving high-speed operation of the non-volatile memory device 100.

[0068] A path for outputting the second data in the second plane 700 will be described.

[0069] The first sub-data of the second data in the second plane 700 may be sent to the sixth register 225 through the second bidirectional multiplexer 160. The first sub-data of the second data may be sent to the fourth I / O pad 260 through the sixth register 225. The fourth I / O pad 260 may include but is not limited to the seventh I / O register IO6 to the eighth I / O register IO7.

[0070] The second sub-data of the second data in the second plane 700 may be sent to the fifth register 223 through the second bidirectional multiplexer 160. The second sub-data of the second data may be sent to the third I / O pad 250 through the fifth register 223. The third I / O pad 250 may include but is not limited to the fifth I / O register IO4 to the sixth I / O register IO5.

[0071] The third sub-data of the second data in the second plane 700 may be sent to the first bidirectional multiplexer 150 through the second bidirectional multiplexer 160. The third sub-data of the second data may be sent to the fourth register 215 through the first bidirectional multiplexer 150. The third sub-data of the second data may be sent to the second I / O pad 240 through the fourth register 215. The second I / O pad 240 may include, but is not limited to, the third I / O register IO3 to the fourth I / O register IO4.

[0072] The fourth sub-data of the second data in the second plane 700 may be sent to the first bidirectional multiplexer 150 through the second bidirectional multiplexer 160. The fourth sub-data of the second data may be sent to the third register 213 through the first bidirectional multiplexer 150. The fourth sub-data of the second data may be sent to the first I / O pad 230 through the third register 213. The first I / O pad 230 may include, but is not limited to, the first I / O register IO1 to the second I / O register IO2.

[0073] The third register 213, the fourth register 215, the fifth register 223, and the sixth register 225 may operate in a high frequency (HF) region, and a deviation may occur between the second data and the clock signal to be input to the third register 213, the fourth register 215, the fifth register 223, and the sixth register 225. Therefore, by shortening the data transmission distance between the first I / O pad 230, the second I / O pad 240, the third I / O pad 250, and the fourth I / O pad 260 and the third register 213, the fourth register 215, the fifth register 223, and the sixth register 225, the possibility of the occurrence of the deviation or the magnitude of the deviation may be reduced, thereby realizing high-speed operation of the nonvolatile memory device 100.

[0074] For example, the case of outputting the second data to the first I / O pad 230, the second I / O pad 240, the third I / O pad 250, and the fourth I / O pad 260 using one multiplexer and one register can be easily compared with the case based on Figure 5 In this case, the second data travels to the first I / O pad 230, the second I / O pad 240, the third I / O pad 250, and the fourth I / O pad 260 arranged on the left and right via a single register operating in HF. Figure 5 The final stage is 800 meters long.

[0075] That is, by arranging the third register 213, the fourth register 215, the fifth register 223 and the sixth register 225 in a one-to-one relationship with each of the first I / O pad 230, the second I / O pad 240, the third I / O pad 250 and the fourth I / O pad 260, the path of the second data operated in HF can be shortened, thereby reducing the possibility of deviation or the magnitude of deviation, and achieving high-speed operation of the non-volatile memory device 100.

[0076] Figure 6 is another exemplary block diagram illustrating a nonvolatile memory device according to some embodiments of the present disclosure.

[0077] refer to Figure 2 and Figure 6 , the last stage 800 of the nonvolatile memory device 100 includes a first bidirectional multiplexer 150, a second bidirectional multiplexer 160, a third register 313, a fourth register 315, a fifth register 317, a sixth register 319, a seventh register 323, an eighth register 325, a ninth register 327 and a tenth register 329, as well as a first I / O pad 330, a second I / O pad 340, a third I / O pad 350, a fourth I / O pad 360, a fifth I / O pad 370, a sixth I / O pad 380, a seventh I / O pad 390 and an eighth I / O pad 395.

[0078] For reference, blocks associated with a clock sent to each register are omitted in the drawing for convenience.

[0079] The third register 313, the fourth register 315, the fifth register 317, and the sixth register 319 may be connected to the first bidirectional multiplexer 150. The first I / O pad 330 may be connected to the third register 313. The second I / O pad 340 may be connected to the fourth register 315. The third I / O pad 350 may be connected to the fifth register 317. The fourth I / O pad 360 may be connected to the sixth register 319. The seventh register 323, the eighth register 325, the ninth register 327, and the tenth register 329 may be connected to the second bidirectional multiplexer 160. The fifth I / O pad 370 may be connected to the seventh register 323. The sixth I / O pad 380 may be connected to the eighth register 325. The seventh I / O pad 390 may be connected to the ninth register 327. The eighth I / O pad 395 may be connected to the tenth register 329.

[0080] A path for outputting the first data in the first plane 600 will be described.

[0081] The first sub-data of the first data in the first plane 600 may be sent to the third register 313 through the first bidirectional multiplexer 150. The first sub-data of the first data may be sent to the first I / O pad 330 through the third register 313. The first I / O pad 330 may include but is not limited to the first I / O register IO0.

[0082] The second sub-data of the first data in the first plane 600 may be sent to the fourth register 315 through the first bidirectional multiplexer 150. The second sub-data of the first data may be sent to the second I / O pad 340 through the fourth register 315. The second I / O pad 340 may include but is not limited to the second I / O register IO1.

[0083] The third sub-data of the first data in the first plane 600 may be sent to the fifth register 317 through the first bidirectional multiplexer 150. The third sub-data of the first data may be sent to the third I / O pad 350 through the fifth register 317. The third I / O pad 350 may include but is not limited to the third I / O register IO2.

[0084] The fourth sub-data of the first data in the first plane 600 may be sent to the sixth register 319 through the first bidirectional multiplexer 150. The fourth sub-data of the first data may be sent to the fourth I / O pad 360 through the sixth register 319. The fourth I / O pad 360 may include but is not limited to the fourth I / O register IO3.

[0085] The fifth sub-data of the first data in the first plane 600 may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The fifth sub-data of the first data may be sent to the seventh register 323 through the second bidirectional multiplexer 160. The fifth sub-data of the first data may be sent to the fifth I / O pad 370 through the seventh register 323. The fifth I / O pad 370 may include, but is not limited to, the fifth I / O register IO4.

[0086] The sixth sub-data of the first data in the first plane 600 may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The sixth sub-data of the first data may be sent to the eighth register 325 through the second bidirectional multiplexer 160. The sixth sub-data of the first data may be sent to the sixth I / O pad 380 through the eighth register 325. The sixth I / O pad 380 may include, but is not limited to, the sixth I / O register IO5.

[0087] The seventh sub-data of the first data in the first plane 600 may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The seventh sub-data of the first data may be sent to the ninth register 327 through the second bidirectional multiplexer 160. The seventh sub-data of the first data may be sent to the seventh I / O pad 390 through the ninth register 327. The seventh I / O pad 390 may include, but is not limited to, the seventh I / O register IO6.

[0088] The eighth sub-data of the first data in the first plane 600 may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The eighth sub-data may be sent to the tenth register 329 through the second bidirectional multiplexer 160. The eighth sub-data may be sent to the eighth I / O pad 395 through the tenth register 329. The eighth I / O pad 395 may include, but is not limited to, the eighth I / O register IO7.

[0089] The third register 313, the fourth register 315, the fifth register 317, the sixth register 319, the seventh register 323, the eighth register 325, the ninth register 327 and the tenth register 329 can operate in a high frequency (HF) region, and a deviation may occur between the first data and the clock signal to be input to the third register 313, the fourth register 315, the fifth register 317, the sixth register 319, the seventh register 323, the eighth register 325, the ninth register 327 and the tenth register 329. Therefore, by shortening the data transmission distance between the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, the sixth I / O pad 380, the seventh I / O pad 390 and the eighth I / O pad 395 and the third register 313, the fourth register 315, the fifth register 317, the sixth register 319, the seventh register 323, the eighth register 325, the ninth register 327 and the tenth register 329, the possibility of deviation or the magnitude of deviation can be reduced, thereby achieving high-speed operation of the non-volatile memory device 100.

[0090] For example, the case where the first data is output to the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, the sixth I / O pad 380, the seventh I / O pad 390, and the eighth I / O pad 395 using one multiplexer and one register can be easily compared with the case where the first data is output to the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, the sixth I / O pad 380, the seventh I / O pad 390, and the eighth I / O pad 395 based on Figure 6In this case, the first data travels through a single register operating in HF to the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, the sixth I / O pad 380, the seventh I / O pad 390, and the eighth I / O pad 395 arranged on the left and right. Figure 6 The final stage is 800 meters long.

[0091] That is, by arranging the third register 313, the fourth register 315, the fifth register 317, the sixth register 319, the seventh register 323, the eighth register 325, the ninth register 327 and the tenth register 329 in a one-to-one relationship with each of the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, the sixth I / O pad 380, the seventh I / O pad 390 and the eighth I / O pad 395, the path of the first data operated with HF can be shortened, thereby reducing the possibility of deviation or the magnitude of deviation, and achieving high-speed operation of the non-volatile memory device 100.

[0092] Since a path for outputting the second data in the second plane 700 is symmetrical to a path for outputting the first data in the first plane 600 , a description thereof will not be provided.

[0093] Figure 7 It shows Figure 1 Another exemplary block diagram of a non-volatile memory device. Figure 8 It shows Figure 7 An exemplary block diagram of the third plane of FIG.

[0094] For reference, the Figure 2 The repeated parts of the description are omitted, and the third plane 900 will be mainly described.

[0095] refer to Figure 7 and Figure 8 ,and Figure 2 Compared with the nonvolatile memory device 100, the nonvolatile memory device 100 further includes a third plane 900, a third bidirectional multiplexer 180, a fifth register 185, and a third I / O pad 181. The third plane 900 includes a third memory cell array 121, a third page buffer driver 123, a third delay trimming 127, a third clock input terminal 129, a third clock delay input terminal 130, and a third register 125.

[0096] Although the third plane 900 is an exemplary block diagram using a wave pipeline system, the configuration of the third plane 900 is not limited thereto.

[0097] When an output command of the third data in the third memory cell array 121 is input, the third data is transmitted from the third memory cell array 121 to the third register 125 via the third page buffer driver 123. The third data may be parallel data transmitted or otherwise processed in parallel with other data such as the first data and / or the second data. The transmission scheme of the third data is not limited thereto.

[0098] The third data output from the third memory cell array 121 may be stored in the third register 125 in synchronization with the third clock signal CLK3 generated by the clock generator 190. The third clock signal CLK3 may be transmitted to the third register 125 via the third delay adjustment 127 and the third clock input terminal 129, but the transmission scheme is not limited thereto. In addition, the third delayed clock signal L_CLK3 for delay control transmitted by the delay clock generator 195 may be transferred (transmitted) to the third register 125. The third delayed clock signal L_CLK3 may be transmitted to the third register 125 via the third clock delay input terminal 130. The third clock delay input terminal 130 may transmit the third clock multiplexer signal CLKM3 to the clock multiplexer 170.

[0099] Will refer to it again Figure 7 Describes the path for outputting the third data in the third plane 900.

[0100] When the third data in the third plane 900 is output, the third clock multiplexer signal CLKM3 can be sent from the clock multiplexer 170 to the third register 155, the fourth register 165 and the fifth register 185 through the third delay trimming 137 and the third clock input terminal 139. The transmission scheme of the third clock multiplexer signal CLKM3 is not limited to this. In addition, the delay signal can be sent from the delay clock generator 195 to the third register 155, the fourth register 165 and the fifth register 185 through the third clock delay input terminal 140 for delay control. The clock input scheme according to the wave pipeline structure is not limited to this.

[0101] The first sub-data of the third data in the third plane 900 may be sent to the fifth register 185 through the third bidirectional multiplexer 180. The first sub-data of the third data may be sent to the third I / O pad 181 through the fifth register 185. The third I / O pad 181 may include, but is not limited to, the seventh I / O register IO6, the eighth I / O register IO7, and the ninth I / O register IO8.

[0102] In addition, the second sub-data of the third data in the third plane 900 can be sent to the second bidirectional multiplexer 160 through the third bidirectional multiplexer 180. The second sub-data of the third data can be sent to the fourth register 165 through the second bidirectional multiplexer 160. The second sub-data of the third data can be sent to the second I / O pad 171 through the fourth register 165. The second I / O pad 171 may include, but is not limited to, the fourth I / O register I / O3 to the sixth I / O register IO5.

[0103] Finally, the third sub-data of the third data in the third plane 900 may be sent to the second bidirectional multiplexer 160 through the third bidirectional multiplexer 180. Thereafter, the third sub-data of the third data may be sent to the first bidirectional multiplexer 150 through the second bidirectional multiplexer 160. The third sub-data of the third data may be sent to the third register 155 through the first bidirectional multiplexer 150. The third sub-data of the third data may be sent to the first I / O pad 161 through the third register 155. The first I / O pad 161 may include, but is not limited to, the first I / O register IO0 to the third I / O register IO2.

[0104] The third register 155, the fourth register 165, and the fifth register 185 may operate in a high frequency (HF) region, and a deviation may occur between the third data and the clock signal transmitted through the third clock input terminal 139 and / or the third clock delay input terminal 140. Therefore, by shortening the data transmission distance between the first I / O pad 161, the second I / O pad 171, and the third I / O pad 181 and the third register 155, the fourth register 165, and the fifth register 185, the possibility of occurrence of the deviation or the magnitude of the deviation may be reduced, thereby achieving high-speed operation of the nonvolatile memory device 100.

[0105] For example, the case of outputting the third data to the first I / O pad 161, the second I / O pad 171, and the third I / O pad 181 using one multiplexer and one register can be easily compared with the case based on Figure 7 and Figure 8 In this case, the path of the third data traveling to the first I / O pad 161, the second I / O pad 171, and the third I / O pad 181 arranged on the left and right through a single register operating in HF is smaller than Figure 7 The final stage is 800 meters long.

[0106] That is, by arranging the third register 155, the fourth register 165 and the fifth register 185 in a one-to-one relationship with each of the first I / O pad 161, the second I / O pad 171 and the third I / O pad 181, the path of the third data operated in HF can be shortened, thereby reducing the possibility of deviation or the magnitude of deviation, and achieving high-speed operation of the non-volatile memory device 100.

[0107] Fig. 9 is an exemplary block diagram illustrating a nonvolatile memory device according to some embodiments of the present disclosure.

[0108] refer to Figure 7 and Fig. 9 , the last stage 800 of the nonvolatile memory device 100 includes a first bidirectional multiplexer 150, a second bidirectional multiplexer 160, a third bidirectional multiplexer 180, a fourth register 315, a fifth register 317, a sixth register 319, a seventh register 323, an eighth register 325 and a ninth register 327 as well as a first I / O pad 330, a second I / O pad 340, a third I / O pad 350, a fourth I / O pad 360, a fifth I / O pad 370 and a sixth I / O pad 380.

[0109] For reference, blocks associated with a clock sent to each register are omitted in the drawing for convenience.

[0110] 14. The fourth register 315 and the fifth register 317 may be connected to the first bidirectional multiplexer 150. The first I / O pad 330 may be connected to the fourth register 315. The second I / O pad 340 may be connected to the fifth register 317. The sixth register 319 and the seventh register 323 may be connected to the second bidirectional multiplexer 160. The third I / O pad 350 may be connected to the sixth register 319. The fourth I / O pad 360 may be connected to the seventh register 323. The eighth register 325 and the ninth register 328 may be connected to the third bidirectional multiplexer 180. The fifth I / O pad 370 may be connected to the eighth register 325. The sixth I / O pad 380 may be connected to the ninth register 327.

[0111] A path for outputting the first data in the first plane 600 will be described.

[0112] The first sub-data of the first data in the first plane 600 may be sent to the fourth register 315 through the first bidirectional multiplexer 150. The first sub-data of the first data may be sent to the first I / O pad 330 through the fourth register 315. The first I / O pad 330 may include but is not limited to the first I / O register IO0.

[0113] The second sub-data of the first data in the first plane 600 may be sent to the fifth register 317 through the first bidirectional multiplexer 150. The second sub-data of the first data may be sent to the second I / O pad 340 through the fifth register 317. The second I / O pad 340 may include but is not limited to the second I / O register IO1 and the third I / O register IO2.

[0114] The third sub-data of the first data in the first plane 600 may be sent to the first bidirectional multiplexer 150. Thereafter, the third sub-data of the first data may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The third sub-data of the first data may be sent from the second bidirectional multiplexer 160 to the sixth register 319. The third sub-data of the first data may be sent to the third I / O pad 350 through the sixth register 319. The third I / O pad 350 may include, but is not limited to, the fourth I / O register IO3.

[0115] The fourth sub-data of the first data in the first plane 600 may be sent to the first bidirectional multiplexer 150. Thereafter, the fourth sub-data of the first data may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The fourth sub-data of the first data may be sent from the second bidirectional multiplexer 160 to the seventh register 323. The fourth sub-data of the first data may be sent to the fourth I / O pad 360 through the seventh register 323. The fourth I / O pad 360 may include, but is not limited to, the fifth I / O register IO4 and the sixth I / O register IO5.

[0116] The fifth sub-data of the first data in the first plane 600 may be sent to the first bidirectional multiplexer 150. Thereafter, the fifth sub-data of the first data may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. In addition, the fifth sub-data of the first data may be sent to the third bidirectional multiplexer 180 through the second bidirectional multiplexer 160. The fifth sub-data of the first data may be sent from the third bidirectional multiplexer 180 to the eighth register 325. The fifth sub-data of the first data may be sent to the fifth I / O pad 370 through the eighth register 325. The fifth I / O pad 370 may include, but is not limited to, the seventh I / O register IO6.

[0117] The sixth sub-data of the first data in the first plane 600 may be sent to the first bidirectional multiplexer 150. Thereafter, the sixth sub-data of the first data may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. In addition, the sixth sub-data of the first data may be sent to the third bidirectional multiplexer 180 through the second bidirectional multiplexer 160. The sixth sub-data of the first data may be sent from the third bidirectional multiplexer 180 to the ninth register 327. The sixth sub-data of the first data may be sent to the sixth I / O pad 380 through the ninth register 327. The sixth I / O pad 380 may include, but is not limited to, the eighth I / O register IO7 and the ninth I / O register IO8.

[0118] The fourth register 315, the fifth register 317, the sixth register 319, the seventh register 323, the eighth register 325, and the ninth register 327 may operate in a high frequency (HF) region, and a deviation may occur between the first data and the clock signal to be input to the fourth register 315, the fifth register 317, the sixth register 319, the seventh register 323, the eighth register 325, and the ninth register 327. Therefore, by shortening the data transmission distance between the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, and the sixth I / O pad 380 and the fourth register 315, the fifth register 317, the sixth register 319, the seventh register 323, the eighth register 325, and the ninth register 327, the possibility of the occurrence of the deviation or the magnitude of the deviation may be reduced, thereby achieving high-speed operation of the nonvolatile memory device 100.

[0119] For example, the case where the first data is output to the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, and the sixth I / O pad 380 using one multiplexer and one register can be easily compared with the case where the first data is output to the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, and the sixth I / O pad 380 based on Fig. 9 In this case, the first data travels through a single register operating in HF to the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370, and the sixth I / O pad 380 arranged on the left and right. Figure 7 The final stage is 800 meters long.

[0120] That is, by arranging the fourth register 315, the fifth register 317, the sixth register 319, the seventh register 323, the eighth register 325 and the ninth register 327 in a one-to-one relationship with each of the first I / O pad 330, the second I / O pad 340, the third I / O pad 350, the fourth I / O pad 360, the fifth I / O pad 370 and the sixth I / O pad 380, the path of the first data operated in HF can be shortened, thereby reducing the possibility of deviation or the magnitude of deviation, and achieving high-speed operation of the non-volatile memory device 100.

[0121] Since the output paths of the second data in the second plane 700 and the third data in the third plane 900 are symmetrical to the output path of the first data in the first plane 600 , a description thereof will not be provided.

[0122] In relation to the above Figure 5In an alternative embodiment similar to the alternative embodiment described above, the fourth register 315 and the fifth register 317 may be considered together as a first register, which includes the fourth register 315 as a first sub-register and the fifth register 317 as a second sub-register. The sixth register 319 and the seventh register 323 may be considered together as a second register, which includes the sixth register 319 as a third sub-register and the seventh register 323 as a fourth sub-register. The eighth register 325 and the ninth register 327 may be considered together as a third register, which includes the eighth register 325 as a fifth sub-register and the ninth register 327 as a sixth sub-register. In this alternative embodiment, the first I / O pad 330 and the second I / O pad 340 may be considered together as a single first I / O pad, such that the fourth register 315 as a first sub-register is connected to a portion of the first I / O pad, and the fifth register 317 as a second sub-register is connected to the remaining portion of the single first I / O pad. The third I / O pad 350 and the fourth I / O pad 360 can be considered together as a single second I / O pad, so that the sixth register 319 as the third sub-register is connected to a part of the single second I / O pad, and the seventh register 323 as the fourth sub-register is connected to the remainder of the single second I / O pad. The fifth I / O pad 370 and the sixth I / O pad 380 can be considered together as a single third I / O pad, so that the eighth register 325 as the fifth sub-register is connected to a part of the single third I / O pad, and the ninth register 327 as the sixth sub-register is connected to the remainder of the single third I / O pad. This alternative embodiment is also not limited to three registers each having two sub-registers, or three I / O pads each having a part and a remainder. On the contrary, more than two registers can be provided with a sub-register relationship, and more than two I / O pads can be provided. Similarly, any grouping of sub-registers of a "register" is not limited to two sub-registers. On the contrary, more than two registers can be grouped into sub-registers of a single "register".

[0123] Fig.10 is another exemplary block diagram illustrating a nonvolatile memory device according to some embodiments of the present disclosure.

[0124] refer to Figure 7 and Fig.10, the last stage 800 of the non-volatile memory device 100 includes a first bidirectional multiplexer 150, a second bidirectional multiplexer 160, a third bidirectional multiplexer 180, a fourth register 401, a fifth register 403, a sixth register 405, a seventh register 407, an eighth register 409, a ninth register 411, a tenth register 413, an eleventh register 415 and a twelfth register 417, and a first I / O pad 421, a second I / O pad 423, a third I / O pad 425, a fourth I / O pad 427, a fifth I / O pad 429, a sixth I / O pad 431, a seventh I / O pad 433, an eighth I / O pad 435 and a ninth I / O pad 437.

[0125] For reference, blocks associated with a clock sent to each register are omitted in the drawing for convenience.

[0126] The fourth register 401, the fifth register 403 and the sixth register 405 may be connected to the first bidirectional multiplexer 150. The first I / O pad 421 may be connected to the fourth register 401. The second I / O pad 423 may be connected to the fifth register 403. The third I / O pad 425 may be connected to the sixth register 404. The seventh register 407, the eighth register 409 and the ninth register 411 may be connected to the second bidirectional multiplexer 160. The fourth I / O pad 427 may be connected to the seventh register 407. The fifth I / O pad 429 may be connected to the eighth register 409. The sixth I / O pad 431 may be connected to the ninth register 411. The tenth register 413, the eleventh register 415 and the twelfth register 417 may be connected to the third bidirectional multiplexer 180. The seventh I / O pad 433 may be connected to the tenth register 413. The eighth I / O pad 435 may be connected to the eleventh register 415. The ninth I / O pad 437 may be connected to the twelfth register 417 .

[0127] A path for outputting the first data in the first plane 600 will be described.

[0128] The first sub-data of the first data in the first plane 600 may be sent to the fourth register 401 through the first bidirectional multiplexer 150. The first sub-data of the first data may be sent to the first I / O pad 421 via the fourth register 401. The first I / O pad 421 may include but is not limited to the first I / O register IO0.

[0129] The second sub-data of the first data in the first plane 600 may be sent to the fifth register 403 through the first bidirectional multiplexer 150. The second sub-data of the first data may be sent to the second I / O pad 423 through the fifth register 403. The second I / O pad 423 may include but is not limited to the second I / O register IO1.

[0130] The third sub-data of the first data in the first plane 600 may be sent to the sixth register 405 through the first bidirectional multiplexer 150. The third sub-data of the first data may be sent to the third I / O pad 425 through the sixth register 405. The third I / O pad 425 may include but is not limited to the third I / O register IO2.

[0131] The fourth to sixth sub-data of the first data in the first plane 600 may be sent to the first bidirectional multiplexer 150. Thereafter, the fourth to sixth sub-data of the first data may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. The fourth sub-data of the first data may be sent from the second bidirectional multiplexer 160 to the seventh register 407. The fourth sub-data of the first data may be sent to the fourth I / O pad 427 through the seventh register 407. The fourth I / O pad 427 may include, but is not limited to, the fourth I / O register IO3. The fifth sub-data of the first data may be sent from the second bidirectional multiplexer 160 to the eighth register 409. The fifth sub-data of the first data may be sent to the fifth I / O pad 429 through the eighth register 409. The fifth I / O pad 429 may include, but is not limited to, the fifth I / O register IO4. The sixth sub-data of the first data may be sent from the second bidirectional multiplexer 160 to the ninth register 411. The sixth sub-data of the first data may be sent to the sixth I / O pad 431 through the ninth register 411. The sixth I / O pad 431 may include, but is not limited to, a sixth I / O register IO5.

[0132] The seventh to ninth sub-data of the first data in the first plane 600 may be sent to the first bidirectional multiplexer 150. Thereafter, the seventh, eighth, and ninth sub-data of the first data may be sent to the second bidirectional multiplexer 160 through the first bidirectional multiplexer 150. In addition, the seventh to ninth sub-data of the first data may be sent to the third bidirectional multiplexer 180 through the second bidirectional multiplexer 160. The seventh sub-data of the first data may be sent from the third bidirectional multiplexer 180 to the tenth register 413. The seventh sub-data of the first data may be sent to the seventh I / O pad 433 through the tenth register 413. The seventh I / O pad 433 may include, but is not limited to, the seventh I / O register IO6. The eighth sub-data of the first data may be sent from the third bidirectional multiplexer 180 to the eleventh register 415. The eighth sub-data of the first data may be sent to the eighth I / O pad 435 through the eleventh register 415. The eighth I / O pad 435 may include, but is not limited to, the eighth I / O register IO7. The ninth sub-data of the first data may be sent from the third bidirectional multiplexer 180 to the twelfth register 417. The ninth sub-data of the first data may be transmitted to the ninth I / O pad 437 through the twelfth register 417. The ninth I / O pad 437 may include, but is not limited to, a ninth I / O register IO8.

[0133] The fourth register 401, the fifth register 403, the sixth register 405, the seventh register 407, the eighth register 409, the ninth register 411, the tenth register 413, the eleventh register 415 and the twelfth register 417 can operate in a high frequency (HF) region, and deviations may occur between clock signals to be input to the fourth register 401, the fifth register 403, the sixth register 405, the seventh register 407, the eighth register 409, the ninth register 411, the tenth register 413, the eleventh register 415 and the twelfth register 417. Therefore, by shortening the data transmission distance between the first I / O pad 421, the second I / O pad 423, the third I / O pad 425, the fourth I / O pad 427, the fifth I / O pad 429, the sixth I / O pad 431, the seventh I / O pad 433, the eighth I / O pad 435 and the ninth I / O pad 437 and the fourth register 401, the fifth register 403, the sixth register 405, the seventh register 407, the eighth register 409, the ninth register 411, the tenth register 413, the eleventh register 415 and the twelfth register 417, the possibility of deviation or the magnitude of deviation can be reduced, thereby achieving high-speed operation of the non-volatile memory device 100.

[0134] For example, a case where the first data is output to the first I / O pad 421, the second I / O pad 423, the third I / O pad 425, the fourth I / O pad 427, the fifth I / O pad 429, the sixth I / O pad 431, the seventh I / O pad 433, the eighth I / O pad 435, and the ninth I / O pad 437 using one multiplexer and one register will be described. In this case, the first data travels to the first I / O pad 421, the second I / O pad 423, the third I / O pad 425, the fourth I / O pad 427, the fifth I / O pad 429, the sixth I / O pad 431, the seventh I / O pad 433, the eighth I / O pad 435, and the ninth I / O pad 437 arranged on the left and right through a single register operating in HF. Figure 7 The final stage is 800 meters long.

[0135] That is, by arranging the fourth register 401, the fifth register 403, the sixth register 405, the seventh register 407, the eighth register 409, the ninth register 411, the tenth register 413, the eleventh register 415 and the twelfth register 417 in a one-to-one relationship with each of the first I / O pad 421, the second I / O pad 423, the third I / O pad 425, the fourth I / O pad 427, the fifth I / O pad 429, the sixth I / O pad 431, the seventh I / O pad 433, the eighth I / O pad 435 and the ninth I / O pad 437, the path of the first data operated with HF can be shortened, thereby reducing the possibility of deviation or the magnitude of deviation, and achieving high-speed operation of the non-volatile memory device 100.

[0136] Since the output paths of the second data in the second plane 700 and the third data in the third plane 900 are symmetrical to the output path of the first data in the first plane 600 , a description thereof will not be provided.

[0137] Fig.11 is a block diagram illustrating a computing system including a non-volatile memory device according to some embodiments of the present disclosure.

[0138] refer to Fig.11 , the computing system 1000 includes a central processing unit (CPU) 1100 , a random access memory (RAM) 1200 , a user interface 1300 , a power supply 1400 , and a storage device 1 .

[0139] Data processed by the CPU 1100 may be stored in the memory device 1 via the system bus 1500 .

[0140] The computing system 1000 may be provided as one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a device capable of sending and receiving information in a wireless environment, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a telematics network, an RFID device, or one of the various components constituting a computing system, but the present disclosure is not limited to such examples.

[0141] Summarizing the above detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present disclosure. Therefore, the preferred embodiments of the present disclosure disclosed are only for general and descriptive purposes, and not for purposes of limitation.

Claims

1. A non-volatile memory device, comprising: A first memory cell array storing first data; a first bidirectional multiplexer, receiving the first data and distributing the first data into first sub-data and second sub-data; a second bidirectional multiplexer, receiving the second sub-data from the first bidirectional multiplexer; a first register, storing the first sub-data from the first bidirectional multiplexer; a second register, storing the second sub-data from the second bidirectional multiplexer; a first I / O pad, outputting the first sub-data from the first register to the outside; as well as The second I / O pad outputs the second sub-data from the second register to the outside.

2. The nonvolatile memory device according to claim 1, further comprising: A second memory cell array stores second data, wherein the second bidirectional multiplexer receives the second data and distributes the second data into third sub-data and fourth sub-data, The first bidirectional multiplexer receives the third sub-data, The first register receives and stores the third sub-data from the first bidirectional multiplexer, The second register receives and stores the fourth sub-data from the second bidirectional multiplexer, and The first I / O pad and the second I / O pad output the third sub-data and the fourth sub-data to the outside, respectively.

3. The nonvolatile memory device according to claim 2, wherein: The first register includes a first sub-register and a second sub-register, The first sub-register is connected to a portion of the first I / O pad, and The second sub-register is connected to a remaining portion of the first I / O pad.

4. The nonvolatile memory device according to claim 3, wherein: The first register is one of the first registers, and the first I / O pad is one of the first I / O pads that are arranged in a one-to-one relationship with the first register.

5. The nonvolatile memory device according to claim 4, wherein: The second register includes a third sub-register and a fourth sub-register, The third sub-register is connected to a portion of the second I / O pad, and The fourth sub-register is connected to a remaining portion of the second I / O pad.

6. The nonvolatile memory device according to claim 2, further comprising: a second memory cell array storing third data; a third bidirectional multiplexer, receiving the third data and distributing the third data into fifth sub-data, sixth sub-data and seventh sub-data; a third register storing the seventh sub-data from the third bidirectional multiplexer, and a third I / O pad, outputting the seventh sub-data from the third register to the outside, wherein the third bidirectional multiplexer sends the fifth sub-data and the sixth sub-data to the second bidirectional multiplexer, The second bidirectional multiplexer sends the sixth sub-data to the second register, The second bidirectional multiplexer sends the fifth sub-data to the first bidirectional multiplexer, The first bidirectional multiplexer sends the fifth sub-data to the first register, The first I / O pad outputs the fifth sub-data from the first bidirectional multiplexer to the outside, and The second I / O pad outputs the sixth sub-data from the second bidirectional multiplexer to the outside.

7. The nonvolatile memory device according to claim 6, wherein: The third register includes a fifth sub-register and a sixth sub-register, The fifth sub-register is connected to a portion of the third I / O pad, and The sixth sub-register is connected to a remaining portion of the third I / O pad.

8. The nonvolatile memory device according to claim 7, wherein: The third register and the third I / O pad have a one-to-one relationship.

9. The nonvolatile memory device according to claim 2, wherein: The first memory cell array includes a first page buffer driver, The second memory cell array includes a second page buffer driver, The first bidirectional multiplexer receives the first data from the first page buffer driver, and The second bidirectional multiplexer receives the second data from the second page buffer driver.

10. A non-volatile memory device comprising: A first I / O pad receives first data; a first register, storing the first data and sending the first data to the first I / O pad; a first bidirectional multiplexer, sending the first data to the first register, the first data including first sub-data and second sub-data; a second bidirectional multiplexer, for sending the second sub-data; a first memory cell array storing the first sub-data and sending the first sub-data to the first bidirectional multiplexer; as well as The second memory cell array stores the second sub-data and sends the second sub-data to the second bidirectional multiplexer.

11. The nonvolatile memory device according to claim 10, further comprising: A second I / O pad receives second data; as well as a second register storing the second data and sending the second data to the second I / O pad, The second data includes third sub-data and fourth sub-data. The first bidirectional multiplexer sends the third sub-data to the second bidirectional multiplexer, The first memory cell array stores the third sub-data and sends the third sub-data to the first bidirectional multiplexer, and The second memory cell array stores the fourth sub-data and transmits the fourth sub-data to the second bidirectional multiplexer.

12. The nonvolatile memory device according to claim 11, wherein: The first register includes a first sub-register and a second sub-register, The first sub-register is connected to a portion of the first I / O pad, and The second sub-register is connected to a remaining portion of the first I / O pad.

13. The nonvolatile memory device according to claim 12, wherein: The first register is one of the first registers, and the first I / O pad is one of the first I / O pads that are arranged in a one-to-one relationship with the first register.

14. The nonvolatile memory device according to claim 13, wherein: The second register includes a third sub-register and a fourth sub-register, The third sub-register is connected to a portion of the second I / O pad, and The fourth sub-register is connected to a remaining portion of the second I / O pad.

15. The nonvolatile memory device according to claim 11, further comprising: A third I / O pad receives third data; a third register, storing the third data and sending the third data to the third I / O pad; a third bidirectional multiplexer, sending the third data to the third register, the third data including fifth sub-data, sixth sub-data and seventh sub-data; as well as The third memory cell array stores seventh sub-data. wherein the second bidirectional multiplexer sends the fifth sub-data and the sixth sub-data to the third bidirectional multiplexer, The first bidirectional multiplexer sends the fifth sub-data to the second bidirectional multiplexer, The first memory cell array stores the fifth sub-data and sends the fifth sub-data to the first bidirectional multiplexer, and The second memory cell array stores the sixth sub-data and transmits the sixth sub-data to the second bidirectional multiplexer.

16. The nonvolatile memory device according to claim 15, wherein: The first register includes a first sub-register and a second sub-register, The first sub-register is connected to a portion of the first I / O pad, and The second sub-register is connected to a remaining portion of the first I / O pad.

17. The nonvolatile memory device according to claim 16, wherein: The first register is one of the first registers, and the first I / O pad is one of the first I / O pads that are arranged in a one-to-one relationship with the first register.

18. The nonvolatile memory device according to claim 17, wherein: The second register includes a third sub-register and a fourth sub-register, The third sub-register is connected to a portion of the second I / O pad, and The fourth sub-register is connected to a remaining portion of the second I / O pad.

19. The nonvolatile memory device according to claim 18, wherein: The third register includes a fifth sub-register and a sixth sub-register, The fifth sub-register is connected to a portion of the third I / O pad, and The sixth sub-register is connected to a remaining portion of the third I / O pad.

20. A non-volatile memory device comprising: A first memory cell array and a second memory cell array store first data and second data, respectively; a first bidirectional multiplexer, receiving the first data, wherein the first data includes first sub-data and second sub-data; a second bidirectional multiplexer, receiving the second data, the second data including third sub-data and fourth sub-data, the second bidirectional multiplexer receiving the second sub-data from the first bidirectional multiplexer, and sending the fourth sub-data to the first bidirectional multiplexer; a first register, receiving the first sub-data and the third sub-data from the first bidirectional multiplexer; a second register, receiving the second sub-data and the fourth sub-data from the second bidirectional multiplexer; a first I / O pad, outputting the first sub-data and the third sub-data from the first register to the outside; as well as a second I / O pad, outputting the second sub-data and the fourth sub-data from the second register to the outside, The frequency of a first clock applied to the first bidirectional multiplexer and the second bidirectional multiplexer is lower than the frequency of a second clock applied to the first register and the second register.

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