Conductive trace design for smart cards

Abstract

A lead frame for assembling a smart card is formed by a substrate having a first main surface and a second main surface that are opposite. A die receiving area is formed in the first main surface of the substrate and is surrounded by a conductive through hole. A conductive coating is formed on the second main surface of the substrate and is patterned to form an electrical contact pad on the conductive through hole. A conductive trace is formed on the first main surface of the substrate. The conductive trace extends between at least two adjacent through holes and partially surrounds the at least two adjacent conductive through holes, thereby forming a gap in the portion of the trace surrounding the through hole. An electrical connection between an integrated circuit chip and the conductive through hole extends over the gap. The gap prevents the electrical connection from accidentally contacting the conductive trace.

Description

Technical Field

[0001] The present invention relates generally to smart cards and, more particularly, to conductive trace designs for smart cards. Background Art

[0002] refer to Figure 1A , shows a smart card 10 having a credit card-sized body 12 having a first major surface 14 including an integrated circuit (IC) module receiving area 16 for receiving an IC module 18 and an antenna 20. Figure 1B is a top plan view of the IC module 18 before it is separated from the carrier 22. The IC module 18 includes an IC 24, which may be a microcontroller with some memory mounted on a substrate or lead frame 26, which is part of the carrier 22. The substrate 26 includes a plurality of through holes 28 that electrically connect conductive pads on the active surface of the IC 24 to contact pads on the opposite side of the substrate 26 through bonding wires 30. By including both the antenna 20 and the contact pads, the smart card enables both contact and contactless connections.

[0003] Through hole 28 typically comprises a plated through hole. One or more conductive traces 32 and 33 are formed on the surface of substrate 26 and form a connection between IC 24 and antenna 20. Figure 1B As shown, conductive traces 32 and 33 run from one through hole to an adjacent through hole and so on. Conductive traces 32 and 33 are also shown as Figure 1C The enclosed through hole 28 is shown. Figure 1C is a greatly enlarged plan view of via 28 , bonding wire 30 connecting IC 24 to via 28 , and conductive trace 32 .

[0004] Also like Figure 1C As shown, a problem with the smart card package is that one of the bonding wires 30 sometimes sags and makes accidental contact with the conductive trace 32, causing a short circuit condition that may cause the smart card to operate incorrectly. Therefore, it would be desirable to be able to assemble a smart card that does not cause an accidental short circuit due to accidental contact between the bonding wire and the conductive trace 32. Summary of the invention

[0005] A lead frame for assembling a smart card, comprising:

[0006] a substrate having opposing first and second major surfaces;

[0007] a die receiving area formed in the first major surface of the substrate;

[0008] a plurality of conductive vias, the plurality of conductive vias generally surrounding the die receiving area;

[0009] a conductive coating formed on the second major surface of the substrate, wherein the conductive coating is patterned to form a plurality of electrical contact pads on the plurality of conductive vias; and

[0010] At least one conductive trace is formed on the first major surface of the substrate, wherein the conductive trace extends between at least two adjacent vias, and wherein the conductive trace does not completely surround the at least two adjacent conductive vias.

[0011] Optionally, the conductive through hole is one of circular, elliptical, rectangular and triangular.

[0012] Optionally, the at least one conductive trace extends approximately half way around the at least two adjacent conductive vias.

[0013] Optionally, the at least one conductive trace extends more than half way around the at least two adjacent conductive vias.

[0014] Optionally, the portion of the conductive trace partially surrounding the at least two adjacent conductive vias is configured such that a bonding wire extending from the integrated circuit chip to the at least two adjacent conductive vias extends over the portion of the conductive via not surrounded by the conductive trace.

[0015] Optionally:

[0016] The plurality of conductive vias include two groups of conductive vias disposed on opposite sides of the die receiving area; and the at least one conductive trace includes a first conductive trace extending between and partially surrounding each of the conductive vias in the first group and a second conductive trace extending between and partially surrounding each of the conductive vias in the second group.

[0017] Optionally, the die receiving area comprises a cavity having a depth less than about half the thickness of the substrate.

[0018] Optionally, the conductive coating formed on the second major surface of the substrate extends over the cavity such that a major surface of an integrated circuit chip disposed within the cavity rests on the conductive coating.

[0019] Optionally, the conductive coating further extends over the conductive via and includes a gap between a portion extending over the conductive via and a portion over the cavity.

[0020] Optionally, the conductive coating comprises a copper foil attached to the second major surface of the substrate with an adhesive.

[0021] Optionally, the conductive coating comprises an anti-corrosion coating for preventing oxidation of the copper.

[0022] A smart card comprising:

[0023] a substrate having opposing first and second major surfaces;

[0024] a die receiving area formed in the first major surface of the substrate;

[0025] a plurality of conductive vias, the plurality of conductive vias generally surrounding the die-receiving area, wherein the conductive vias extend from the first major surface to the second major surface;

[0026] a conductive coating formed on the second major surface of the substrate, wherein the conductive coating is patterned to form a plurality of electrical contact pads on the plurality of conductive vias;

[0027] at least one conductive trace formed on the first major surface of the substrate, wherein the conductive trace extends between at least two adjacent vias, and wherein the conductive trace does not completely surround the at least two adjacent conductive vias;

[0028] an integrated circuit chip, the integrated circuit chip being disposed in the die receiving area; and

[0029] A plurality of electrical connections electrically connect the integrated circuit chip to corresponding ones of the conductive vias.

[0030] Optionally, the at least one conductive trace extends approximately half way around the at least two adjacent conductive vias.

[0031] Optionally, the at least one conductive trace extends more than half way around the at least two adjacent conductive vias.

[0032] Optionally, the conductive through hole is one of circular, elliptical, rectangular and triangular.

[0033] Optionally, the portion of the at least one conductive trace partially surrounding the at least two adjacent conductive vias is configured such that the electrical connection extending from the integrated circuit chip to the at least two adjacent conductive vias extends over the portion of the at least two adjacent conductive vias not surrounded by the conductive trace.

[0034] Optionally:

[0035] The plurality of conductive vias includes two groups of conductive vias disposed on opposite sides of the die-receiving area; and

[0036] The at least one conductive trace includes a first conductive trace extending between and only partially surrounding each of the conductive vias in the first group, and a second conductive trace extending between and only partially surrounding each of the conductive vias in the second group.

[0037] Optionally, the die receiving area comprises a cavity having a depth less than about half the thickness of the substrate.

[0038] Optionally, the conductive coating formed on the second major surface of the substrate extends over the cavity such that a bottom surface of the integrated circuit chip disposed within the cavity rests on the conductive coating.

[0039] Optionally, an encapsulant is further included formed on the first major surface of the substrate, the encapsulant covering the integrated circuit chip, the plurality of conductive vias, the at least one conductive trace, and the electrical connection between the integrated circuit chip and the plurality of conductive vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order that the features of the present invention can be understood in detail, a detailed description of the present invention is provided below with reference to embodiments, some of which are shown in the accompanying drawings. The accompanying drawings only show typical embodiments of the present invention and should not be regarded as limiting the scope of the present invention, as the present invention may admit other embodiments with equivalent effects. In addition, the accompanying drawings are for the purpose of facilitating the understanding of the present invention and are therefore not necessarily drawn to scale, and some features may be omitted in order to highlight other features of the present invention, so that the present invention can be more clearly understood. When reading this description in conjunction with the accompanying drawings, the advantages of the claimed subject matter will become apparent to those skilled in the art, in which similar reference numerals are used to refer to similar elements, and in the accompanying drawings:

[0041] Figure 1Ais a perspective view showing a conventional smart card assembly and its IC module, Figure 1B yes Figure 1A An enlarged plan view of one side of the IC module, and Figure 1C yes Figure 1B a greatly enlarged view of a portion of an IC module having a bonding wire in contact with its conductive trace;

[0042] Figure 2A is a cross-sectional side view of a lead frame carrier according to an embodiment of the present invention, Figure 2B yes Figure 2A a bottom plan view of a portion of a lead frame carrier, and Figure 2C yes Figure 2B a top plan view of the portion of the carrier;

[0043] Figure 3A Shows Figure 2B the top side of the carrier and lead frame after attaching the IC thereto and electrically connecting the IC to its through-holes with bonding wires, and Figure 3B yes Figure 3A a significantly magnified view of through-holes, conductive traces, and bonding wires of an assembly;

[0044] Figure 4A , 4B 4C and 4D show vias and conductive traces according to various embodiments of the present invention; and

[0045] Figure 5 is a flow chart showing various steps in a smart card assembly process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In one embodiment, the present invention provides a lead frame for assembling a smart card. The lead frame is formed by a substrate having a first main surface and a second main surface relative to each other. A die receiving area is formed in the first main surface of the substrate and is surrounded by a conductive through hole. A conductive coating is formed on the second main surface of the substrate and is patterned to form an electrical contact pad on the conductive through hole. A conductive trace is formed on the first main surface of the substrate. The conductive trace extends between at least two adjacent through holes and partially surrounds the at least two adjacent conductive through holes, thereby forming a gap in the portion of the trace surrounding the through hole. An electrical connection between an integrated circuit chip and the conductive through hole extends over the gap. The gap prevents the electrical connection from accidentally contacting the conductive trace.

[0047] In another embodiment, the present invention provides a smart card, the smart card comprising a substrate having a first main surface and a second main surface opposite to each other and a die receiving area formed in the first main surface. A plurality of conductive vias are provided, the plurality of conductive vias generally surrounding the die receiving area and extending from the first main surface to the second main surface. A conductive coating is formed on the second main surface of the substrate and patterned to form a plurality of electrical contact pads on the plurality of conductive vias. At least one conductive trace is formed on the first main surface of the substrate, and the at least one conductive trace extends between at least two adjacent vias. The conductive trace only partially surrounds the at least two adjacent conductive vias. An integrated circuit chip is placed in the die receiving area, and the integrated circuit chip is electrically connected to the vias using a plurality of electrical connections extending between bonding pads on the active surface of the chip and the vias. The portion of the conductive trace that partially surrounds the adjacent conductive vias is configured so that the electrical connection extending from the chip to the two adjacent conductive vias extends over the portion of the conductive vias that is not surrounded by the conductive trace.

[0048] Therefore, the present invention provides a smart card with an improved conductive trace design for avoiding and preventing electrical shorting between bonding wires and conductive traces. The present invention provides the advantage of preventing bonding wires from contacting conductive traces even in the case of wire sagging. The present invention also makes it easier to control the wire loop shape.

[0049] Reference now Figure 2A , 2B and 2C, Figure 2A is a cross-sectional side view of a lead frame carrier 100 according to an embodiment of the present invention, Figure 2B is a bottom plan view of the portion of the lead frame carrier 100 , and Figure 2C 1 is a top plan view of the portion of the lead frame carrier 100. The portion of the lead frame carrier 100 includes lead frames 102 and rails 104 including a plurality of aligned holes 106 for moving the carrier 100 using a sprocket (not shown). The carrier 100 may include a lead frame strip or a strip having more than one row of lead frames and another track having holes on the opposite side of the carrier. The lead frame strip 100 is of a type well known in the art, and therefore, those elements of the lead frame strip 100 that are not particularly relevant to an understanding of the present invention will not be described in detail to avoid obscuring the present invention. Figure 2C An outline 108 of the lead frame 102 is shown in FIG. The lead frame 102 may be used in a smart card assembly process, as will be discussed in detail below. The lead frame 102 may be separated from the carrier 100 by punching or cutting, as is also known in the art.

[0050] The lead frame 102 includes a substrate 110 having a first major surface 112 ( Figure 2B) and the opposite second major surface 114 ( Figure 2C ). As used herein, substrate refers to an underlying substance or layer or a primary material or underlying material onto which other materials (e.g., conductive ink, conductive metal, molding compound, etc.) are applied. Substrate 110 is made of a non-conductive material such as glass reinforced epoxy laminate (i.e., FR4).

[0051] like Figure 2B As shown, a die receiving area 116 is formed in the first major surface 112 of the substrate 110, as are a plurality of conductive vias 118 that generally surround the die receiving area 116. The die receiving area 116 includes a cavity formed at a location substantially centered on the lead frame 102. The depth of the die receiving area 116 may be less than about half the thickness of the substrate 110. Alternatively, the depth of the cavity may be greater than half the thickness of the substrate 110, and in a preferred embodiment, the cavity extends completely through the substrate 110. The conductive vias 118 also extend completely through the substrate 110. As is known in the art, the vias 118 may be plated through holes or through holes filled with a conductive material such as solder.

[0052] In the currently preferred embodiment and as Figure 2B As shown, the conductive vias 118 include two sets of conductive vias disposed on opposite sides of the die receiving area 116. For example, Figure 2B Two groups of through holes 118 are shown, where each group includes four (4) through holes 118. As discussed below, the groups are defined by the through holes associated with the conductive traces. As will be appreciated by those skilled in the art, the number of through holes 118 in each group, as well as the number of through holes 118 as a whole, will depend on the number of bond pads used to assemble the integrated circuit of the smart card that needs to be accessed.

[0053] A conductive coating 120 is formed on the second major surface 114 of the substrate 110. The conductive coating 120 is patterned to form a plurality of electrical contact pads 122(1) to 122(8) on corresponding ones of the conductive vias 118. The conductive coating 120 also covers the cavity of the die receiving area 116 to form a die pad or die flag 124 so that the major surface of the integrated circuit chip disposed in the cavity rests on the conductive coating 120. The die pad or flag 124 is typically sized and shaped to accommodate the IC chip, i.e., to accommodate the chip based on the size and shape of the chip. However, the size and shape of the die pad 124 and the size and type of the IC chip are not part of the present invention and will not be described in further detail herein.

[0054] As will be appreciated by those skilled in the art, a gap exists between the portion of the conductive coating 120 extending over the conductive via 118 and the portion extending over the cavity 116 such that the contact pads 122 are electrically isolated from each other and from the die pad 124 .

[0055] In one embodiment, conductive coating 120 includes a copper foil attached to second major surface 114 of substrate 110 with an adhesive (not shown). Conductive coating or copper foil 120 may include an anti-corrosion coating such as Ni, Pd, and / or Au to prevent copper oxidation.

[0056] At least one conductive trace 126 is formed on the first major surface 112 of the substrate 110, and in a preferred embodiment, there are first conductive traces 126 and second conductive traces 128 (see Figure 2B ). Each of the conductive traces 126 , 128 extends between at least two adjacent through-holes 118 and partially surrounds the through-hole 118 , but the conductive traces 126 , 128 do not completely surround the through-hole 118 .

[0057] As previously discussed, the vias 118 can be divided into two groups, and the groups are defined as those vias associated with one or the other of the two conductive traces 126 and 128. Thus, a first conductive trace 126 extends between and partially surrounds each of the conductive vias 118 in the first group, and a second conductive trace 128 extends between and partially surrounds each of the conductive vias 118 in the second group. As will be apparent to one skilled in the art, the first group of vias is associated with contact pads 122(1) through 122(4), and the second group of vias is associated with contact pads 122(5) through 122(8).

[0058] Brief reference Figure 3A and 3B , Figure 3A The first surface 112 of the substrate 110 is shown with an integrated circuit (IC) chip 130 disposed within the cavity of the die receiving area 116 and attached to the inner surface of the die flag 124 with a die attach adhesive or die attach tape. The IC chip 130 (which may include any type of integrated circuit, such as a simple microprocessor with relatively small memory) has bonding pads (not shown) on its active surface that are electrically connected to the contact pads 122 via vias 118 with electrical connection means 132. In a preferred embodiment, the electrical connection means include bonding wires, but in alternative embodiments, other electrical connection means may be used, such as conductive inks.

[0059] A plastic molding compound or encapsulant 134 may be formed on the first major surface 112 of the substrate 110 , wherein the encapsulant covers the IC chip 130 , the conductive vias 118 , the first and second conductive traces 126 , 128 , and the electrical connections 132 between the IC chip 130 and the conductive vias 118 .

[0060] Figure 3B yes Figure 3A A significantly enlarged view of the through hole 118, a portion of the first conductive trace 126, and the bonding wire 132 of the assembly shown. As shown, the conductive trace 126 extends from one through hole 118 to another through hole 118 and also partially surrounds each of the through holes 118. In one embodiment, the conductive trace extends about half the distance around the through hole 118, and in another embodiment, the conductive trace extends more than half the distance around the through hole. However, in each embodiment, there is a gap or portion of the outer perimeter of the through hole that the conductive trace does not extend around. The portion of the conductive traces 126 and 128 that partially surround the conductive through hole 118 is configured so that the bonding wire 132 extending from the IC chip 130 to the through hole 118 does not extend on the conductive trace. That is, the bonding wire 132 extends over the portion of the conductive through hole 118 that is not surrounded by the conductive trace 126 or 128. Therefore, if the bonding wire 132 happens to sag or the loop height is particularly low, the bonding wire 132 still does not accidentally contact the conductive trace.

[0061] Figure 4A , 4B 4C and 4D show vias and conductive traces according to various embodiments of the present invention. Figure 4A A circular via 142 and a conductive trace 144 are shown that extends over more than half of the diameter of the via 142 but still has clearance for accommodating a bonding wire 132 . Figure 4B A triangular via 146 and a conductive trace 148 extending along two sides of the triangular via 146 are shown, but the trace 148 does not extend along a third side of the triangular via 146 so that the bonding wire 132 does not make accidental contact with the bonding wire 132 . Figure 4C A rectangular or square via 150 and a conductive trace 152 are shown that extends completely along one side of the rectangle and partially along two sides of the rectangle and provides clearance along the two sides and toward portions of the middle side thereof for accommodating a bonding wire 132 . Figure 4D A circular or annular via 154 and a conductive trace 156 are shown that extend along only about half of the diameter of the via 154 and leave clearance for accommodating the bonding wire 132. Thus, as will be apparent to one skilled in the art, the present invention is not limited by the via shape.

[0062] Figure 5 1 is a flow chart showing the steps in a smart card assembly process 160 according to an embodiment of the present invention. Figure 5 Starting from the upper left side of the , in a first step 162, a lead frame for assembling a smart card is provided. The lead frame is similar to a conventional smart card lead frame ( Figure 1B ) and formed in sub-step 163. However, in sub-step 164, conductive traces according to embodiments of the present invention are added to the leadframe, wherein one or more traces extend between the vias and partially but not completely surround the vias, thereby leaving gaps where bond wires will pass from the integrated circuit to the vias.

[0063] At step 166, an adhesive or die attach film (DAF) is placed in the die receiving area of ​​the encapsulation side of the lead frame, and at step 168, the die is attached in the die receiving area using the adhesive or DAF. The adhesive is cured so that the die is securely attached to the lead frame. At step 170, the die is electrically connected to the through holes in the lead frame. In a currently preferred embodiment, the bonding wires are attached to the die bond pads and the corresponding lead frame through holes using a standard wire bonding process. At step 172, an encapsulant is formed over the die, bonding wires, and through holes (see Figure 3A ). For example, a ball-top encapsulation process may be performed, whereby a liquid encapsulant is dispensed onto the die, bond wires, and vias. The mold compound / encapsulant may be removed at step 174, which is optional. Finally, at step 176, the finished device is inspected.

[0064] The conductive traces of the present invention can be formed using a variety of known methods, such as by printing and etching. The conductive traces only partially surround the vias to which the bonding wires are attached, thereby preventing accidental shorting of the bonding wires to the conductive traces.

[0065] The integrated circuit chip and electrical connection (bonding wire) are covered with molding compound to form an assembled device. The molding compound provides electrical and mechanical protection for the integrated circuit chip, lead frame and the electrical connection between the chip and the through hole. In one embodiment, the molding compound includes an epoxy resin composition, such as a C-grade plastic material (propene-resin). The molding compound is then cured to be physically hard, so that the chip, through hole, conductive traces and bonding wire covered by the molding compound are protected from potential environmental (such as moisture and dust) influences and mechanical damage. The molding compound can be formed on the chip using known methods (such as transfer molding or ball top process).

[0066] The present invention can be applied to any smart card package or MEMS package and will adapt to any die size and shape, number of dies, and stacked dies.

[0067] The use of the terms "a," "an," and "the" and similar referents in the context of describing subject matter (especially in the context of the following claims) should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values ​​herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein.

[0068] In addition, the foregoing description is for illustrative purposes only and is not intended to be limiting, because the protection scope sought is limited by the claims as set forth below together with any equivalents to which it is entitled. Unless otherwise stated, the use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the subject matter and does not constitute a limitation on the scope of the subject matter. The term "based on" and other similar phrases used in both the claims and the written description to indicate the conditions for producing the result are not intended to exclude any other conditions for producing the result. Any language in the specification should not be interpreted as indicating any unclaimed element as necessary for practicing the invention as claimed.

[0069] Preferred embodiments are described herein, including the best mode known to the inventor for performing the claimed subject matter. Of course, variations of these preferred embodiments will become apparent to those of ordinary skill in the art after reading the foregoing description. The inventor expects the skilled person to adopt these variations as needed, and the inventor wishes to practice the claimed subject matter in a manner different from that specifically described herein. Therefore, where permitted by applicable law, the claimed subject matter includes all modifications and equivalents of the subject matter listed in the appended claims. In addition, unless otherwise indicated herein or clearly contradicted by the context, any combination of the above elements in all possible variations thereof is included.

Claims

1. A lead frame for assembling a smart card, characterized in that: The lead frame comprises: a substrate having opposing first and second major surfaces; a die receiving area formed in the first major surface of the substrate; a plurality of conductive vias, the plurality of conductive vias generally surrounding the die receiving area; a conductive coating formed on the second major surface of the substrate, wherein the conductive coating is patterned to form a plurality of electrical contact pads on the plurality of conductive vias; and at least one conductive trace formed on the first major surface of the substrate, wherein the conductive trace extends between at least two adjacent vias, and wherein the conductive trace does not completely surround the at least two adjacent conductive vias; The portion of the conductive trace partially surrounding the at least two adjacent conductive vias is configured such that a bonding wire extending from the integrated circuit chip to the at least two adjacent conductive vias extends over the portion of the conductive vias not surrounded by the conductive trace.

2. The lead frame according to claim 1, characterized in that: The at least one conductive trace extends around the at least two adjacent conductive vias a distance half of the outer perimeter of the conductive vias.

3. The lead frame according to claim 1, wherein: The plurality of conductive vias include two groups of conductive vias disposed on opposite sides of the die receiving area; and the at least one conductive trace includes a first conductive trace extending between and partially surrounding each of the conductive vias in a first group of the two groups of conductive vias and a second conductive trace extending between and partially surrounding each of the conductive vias in a second group of the two groups of conductive vias.

4. The lead frame according to claim 1, wherein: The die receiving area includes a cavity having a depth less than half the thickness of the substrate.

5. The lead frame according to claim 4, characterized in that: The conductive coating formed on the second major surface of the substrate extends over the cavity such that a major surface of an integrated circuit chip disposed within the cavity rests on the conductive coating.

6. A smart card, characterized in that: include: a substrate having opposing first and second major surfaces; a die receiving area formed in the first major surface of the substrate; a plurality of conductive vias, the plurality of conductive vias generally surrounding the die-receiving area, wherein the conductive vias extend from the first major surface to the second major surface; a conductive coating formed on the second major surface of the substrate, wherein the conductive coating is patterned to form a plurality of electrical contact pads on the plurality of conductive vias; at least one conductive trace formed on the first major surface of the substrate, wherein the conductive trace extends between at least two adjacent vias, and wherein the conductive trace does not completely surround the at least two adjacent conductive vias; an integrated circuit chip, the integrated circuit chip being placed in the die receiving area; as well as a plurality of electrical connections electrically connecting the integrated circuit chip to corresponding ones of the conductive vias; The portion of the at least one conductive trace partially surrounding the at least two adjacent conductive vias is configured such that the electrical connection extending from the integrated circuit chip to the at least two adjacent conductive vias extends over the portion of the at least two adjacent conductive vias not surrounded by the conductive trace.

7. The smart card according to claim 6, characterized in that: The plurality of conductive vias includes two groups of conductive vias disposed on opposite sides of the die-receiving area; and The at least one conductive trace includes a first conductive trace extending between each of the conductive vias in a first group of the two groups of conductive vias and only partially surrounding each of the conductive vias in the first group, and a second conductive trace extending between each of the conductive vias in a second group of the two groups of conductive vias and only partially surrounding each of the conductive vias in the second group.

8. The smart card according to claim 6, characterized in that: Also included is an encapsulant formed on the first major surface of the substrate, the encapsulant covering the integrated circuit chip, the plurality of conductive vias, the at least one conductive trace, and the electrical connections between the integrated circuit chip and the plurality of conductive vias.

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