Memory structure

Abstract

The present disclosure provides a memory structure and a method for forming the same. The memory structure of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stacked structure, and a dielectric layer extending between the gate structure and the stacked structure. The stacked structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first silicide layer and the second silicide layer, a channel region covering the oxide layer and extending between the first and second silicide layers, and an isolation layer covering the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

Description

Technical Field

[0001] The present disclosure relates to a memory structure, and in particular to a flash memory structure and a forming method thereof. Background Art

[0002] Semiconductor integrated circuits (ICs) have experienced exponential growth. Technological advances in the materials and design of integrated circuits have produced generations of ICs, each smaller and more complex than the previous generation. In the evolution of ICs, functional density (e.g., the number of interconnects per chip area) has generally increased, while geometric size (e.g., the smallest component (or line segment) that can be manufactured using a manufacturing process) has decreased. Such downsizing generally provides the benefit of increased production efficiency and reduced associated process costs. Such downsizing also increases the complexity of handling and manufacturing the ICs. To achieve the above advances, new developments in IC processing and manufacturing are needed.

[0003] For example, flash memory devices have been developed to include three-dimensional stackable structures formed by thin film stacks. Tungsten has been used in the above-mentioned thin film stacks due to its ability to adapt to high temperatures. Because tungsten can be oxidized at high process temperatures, the use of tungsten in thin film stacks requires various barrier layers and protective layers to protect the tungsten layer from oxidation. The use of the above-mentioned various barrier layers and protective layers, while being an appropriate solution to the oxidation of the tungsten layer, also increases the complexity of the thin film stack layers and manufacturing processes used to form the flash memory device. Therefore, although common semiconductor devices have been widely used for their intended purposes, they are not satisfactory in all aspects. Summary of the invention

[0004] A memory structure according to the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure including a plurality of memory thin film stack layers, and a dielectric layer extending between the gate structure and the stack structure. Each of the memory thin film stack layers includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers along a first direction, a channel region covering the oxide layer and extending between the first and second silicide layers along the first direction, and an isolation layer covering the second silicide layer along the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a cross-sectional view of a stacking structure according to an embodiment of the present disclosure.

[0006] Figure 2 is a cross-sectional view of another stacking structure according to an embodiment of the present disclosure.

[0007] Figure 3 A flow chart of a method for fabricating a semiconductor device on a workpiece is disclosed.

[0008] FIG. 4A to FIG. 10A Reveal when artifacts include similar Figure 1 The stack structure of a stack structure is an operation of the method.

[0009] FIG. 4B to FIG. 10B Reveal when the artifact includes similar Figure 2 The stack structure of a stack structure is an operation of the method.

[0010] The reference numerals are described as follows:

[0011] 10: Stacked structure

[0012] 11: Alternative stacking structure

[0013] 102: Bottom dielectric layer

[0014] 104A-1: first silicide layer

[0015] 104A-2: Second silicide layer

[0016] 104B-1: Third silicide layer

[0017] 104B-2: Fourth silicide layer

[0018] 104C-1: Fifth silicide layer

[0019] 104C-2: Sixth silicide layer

[0020] 104D-1: Seventh silicide layer

[0021] 104D-2: Eighth silicide layer

[0022] 106A-1: first polycrystalline semiconductor layer

[0023] 106A-2: Second polycrystalline semiconductor layer

[0024] 106B-1: third polycrystalline semiconductor layer

[0025] 106B-2: Fourth polycrystalline semiconductor layer

[0026] 108A: First oxide layer

[0027] 108B: Second oxide layer

[0028] 108C: Third oxide layer

[0029] 108D: Fourth oxide layer

[0030] 108A′: first recessed oxide layer

[0031] 108B': second recessed oxide layer

[0032] 108C': third recessed oxide layer

[0033] 108D': fourth recessed oxide layer

[0034] 110A: First isolation layer

[0035] 110B: Second isolation layer

[0036] 110C: The third isolation layer

[0037] 110D: Fourth isolation layer

[0038] A: First Film Stack

[0039] B: Second film stack

[0040] C: Third film stack

[0041] D: Fourth film stack

[0042] 120: First groove

[0043] 125: Notch

[0044] W1,W2: Width

[0045] T:Thickness

[0046] 130: Polycrystalline semiconductor materials

[0047] 132: Channel characteristics

[0048] 135: Second groove

[0049] 137: Side wall

[0050] 140: Dielectric layer

[0051] 145: Gate material

[0052] 150: Vertical isolation feature

[0053] 160: Channel Bar

[0054] 170: Fence

[0055] 180: Isolation Fence

[0056] P: Contact spacing

[0057] 200: Method

[0058] 202,204,206,208,210: Operation

[0059] 212,214,216,218: Operation DETAILED DESCRIPTION

[0060] The following disclosure provides many different embodiments or examples to implement the different features of the present application. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the specification describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, different examples in the following specification may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0061] In addition, spatially relative terms, such as "below," "below," "lower," "above," "higher," and the like, are used to facilitate description of the relationship between one element or feature and another element or feature in the diagram. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be rotated 90 degrees or in other orientations, and the spatially relative terms used herein may be interpreted accordingly. In addition, the term "made of" may include "comprising" or "consisting of." Furthermore, in the following process, there may be one or more additional operations within / between the described operations, and the order of the operations may be changed.

[0062] Furthermore, when "about," "approximately," etc. are used to describe a number or a range of numbers, the word is intended to encompass numbers within a reasonable range including the number, such as within + / -10% of the number or other values ​​understood by those skilled in the art. For example, the word "about 5 nanometers" encompasses a size range from 4.5 nanometers to 5.5 nanometers.

[0063] The present disclosure generally relates to semiconductor devices and methods of forming the same. More specifically, the present disclosure relates to memory devices and three-dimensional memory structures, such as structures used in NOR flash memory. In some common memory structures, a tungsten (W) metal layer is used in the thin film stack of the memory to reduce the resistive load of the source line and the bit line, and to form an oxide-nitride-oxide (ONO, such as silicon oxide-silicon nitride-silicon oxide) layer through a subsequent high temperature budget. When the tungsten metal layer is used, the tungsten metal line is exposed to an oxygen-containing process to form silicon dioxide (SiO2), which may cause the tungsten metal line to fail due to oxidation. In order to prevent oxidation of the tungsten metal line, a barrier layer such as a titanium nitride layer is deposited to surround the tungsten metal layer. In addition, when the tungsten metal layer and the barrier layer are used, a polysilicon sidewall protection layer is required. Further, in order to create a space to accommodate the polysilicon sidewall protection layer, a recess process in the barrier layer is necessary. Therefore, the use of tungsten metal lines requires an additional barrier layer (such as titanium nitride or tantalum nitride) and an additional barrier metal recess process (W / barrier metal recess process) for the sidewall protection layer and the polysilicon sidewall protection layer, thereby increasing the complexity of the process.

[0064] The present disclosure provides a memory device formed by a stacked structure, the stacked structure including a metal silicide having a conductivity comparable to that of tungsten and allowing a thermal budget. However, compared with tungsten, the oxidation of the metal silicide is self-limiting, which reduces the reactivity of the metal silicide to oxygen at high temperatures (approximately 800° C.). Due to the above reasons, the metal silicide does not need the protection of the above-mentioned barrier layer and protective layer to avoid the oxidation of the metal silicide. The stacked structure in the embodiment of the present disclosure has a simpler structure by replacing the tungsten layer with the metal silicide layer, and can be manufactured using a less complicated process, thereby improving the stability of the process.

[0065] Now refer to Figure 1 , Figure 1is a cross-sectional view of a stacking structure 10 according to one embodiment of the present disclosure. The stacking structure 10 can be used as a basic structure for forming a memory device, such as a three-dimensional stackable (3D stackable) memory structure. In some embodiments, the stacking structure 10 includes an even number of thin film stacks, such as 2, 4, 8, 16, 24, and 32 thin film stacks. For ease of illustration, only two thin film stacks of the stacking structure 10 are shown, namely a first thin film stack A and a second thin film stack B. Each thin film stack can serve as the basis for a field effect transistor (FET). In some embodiments, the memory device formed by the stacking structure 10 or the alternative stacking structure 11 may include an N-type field effect transistor or a P-type field effect transistor. In some examples, the memory device may include an N-type field effect transistor. When the stacking structure 10 includes more thin film stacks, the additional thin film stacks may be in Figure 1In some embodiments, the stack structure 10 is formed on a bottom dielectric layer 102. In some embodiments, the bottom dielectric layer 102 is formed on a substrate or an interconnect structure. In some cases, the bottom dielectric layer 102 may be formed of a suitable dielectric material, such as zirconium oxide, aluminum oxide, aluminum nitride, silicon carbide, and silicon nitride. When silicon nitride or silicon carbide is used for the bottom dielectric layer 102, it may be doped with carbon or nitrogen to impart different etching selectivities. In one embodiment, the first film stack A includes a first silicide layer 104A-1 on the bottom dielectric layer 102, a first polycrystalline semiconductor layer 106A-1 on the first silicide layer 104A-1, a first oxide layer 108A on the first polycrystalline semiconductor layer 106A-1, a second polycrystalline semiconductor layer 106A-2 on the first oxide layer 108A, a second silicide layer 104A-2 on the second polycrystalline semiconductor layer 106A-2, and a first isolation layer 110A on the second silicide layer 104A-2. In some embodiments, the first silicide layer 104A-1 and the second silicide layer 104A-2 include a metal silicide whose conductivity and allowed thermal budget (or thermal budget tolerance) are comparable to tungsten. In some cases, the metal silicide may be titanium silicide (TiSi2), cobalt silicide (CoSi2, C54 phase), tungsten silicide (WSi), palladium silicide (PdSi), other suitable silicides, or combinations thereof. The first polycrystalline semiconductor layer 106A-1 and the second polycrystalline semiconductor layer 106A-2 include doped or undoped polycrystalline silicon. When the first polycrystalline semiconductor layer 106A-1 and the second polycrystalline semiconductor layer 106A-2 are doped, they may be doped with an N-type dopant (e.g., phosphorus or arsenic), or a P-type dopant. In some embodiments, the first oxide layer 108A may be a semiconductor oxide, such as silicon oxide. In some embodiments, the first isolation layer 110A may be formed of a dielectric material different from the dielectric material forming the bottom dielectric layer 102. In some cases, the first isolation layer 110A may be formed of silicon nitride doped with carbon or oxygen to impart different etching selectivities.

[0066] In some embodiments, the layers in the stacked structure, such as the layers in the first film stack A and the second film stack B, can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition techniques. As described above, approximately 2 to 32 identical thin film stacks are formed on the bottom dielectric layer 102. For example, Figure 1 As shown, a second film stack B identical to the first film stack A is formed on the first film stack A. The second film stack B includes a third silicide layer 104B-1 on the first isolation layer 110A, a third polycrystalline semiconductor layer 106B-1 on the third silicide layer 104B-1, a second oxide layer 108B on the third polycrystalline semiconductor layer 106B-1, a fourth silicide layer 104B-2 on the second oxide layer 108B, and a second isolation layer 110B on the fourth silicide layer 104B-2. Figure 1 The second isolation layer 110B is shown as the top layer of the stack structure 10. This is for illustration purposes only, and the stack structure 10 may include additional thin film stacks on the second isolation layer 110B. In some examples, the thickness of the top isolation layer of the stack structure 10 is greater than the thickness of other isolation layers, so that the top isolation layer can withstand a reactive ion etching (RIE) process in the process of forming a memory device.

[0067] Now refer to Figure 2 , Figure 21 is a cross-sectional view of an alternative stack structure 11 according to an embodiment of the present disclosure. The difference between the alternative stack structure 11 and the stack structure 10 is that the alternative stack structure 11 does not include any polycrystalline semiconductor layer, such as the first polycrystalline semiconductor layer 106A-1, the second polycrystalline semiconductor layer 106A-2, the third polycrystalline semiconductor layer 106B-1, and the fourth polycrystalline semiconductor layer 106B-2 in the stack structure 10. The omission of the above-mentioned polycrystalline semiconductor layer can increase the height of the Schottky barrier between the silicide layer and the polycrystalline semiconductor channel. For the above reasons, the memory device formed by the alternative stack structure 11 can have a different read and write driving mechanism (scheme) from the memory device formed by the stack structure 10. In some embodiments, the alternative stack structure 11 also includes an even number of film stacks, such as 2, 4, 8, 16, 24, and 32 film stacks. For the convenience of explanation, only two film stacks of the stack structure 11 are shown, namely a third film stack C and a fourth film stack D. Each film stack will form a field effect transistor. When the alternative stack structure 11 includes more film stacks, the additional film stacks are formed at Figure 2 In some embodiments, the replacement stack structure 11 is formed on a bottom dielectric layer 102. In some embodiments, the bottom dielectric layer 102 may be formed on a substrate or an interconnect structure, and may be formed of a dielectric material, such as zirconium oxide, aluminum oxide, aluminum nitride, silicon carbide, and silicon nitride. When silicon nitride or silicon carbide is used for the bottom dielectric layer 102, it may be doped with carbon or nitrogen to impart different etching selectivities. In one embodiment, the third film stack C includes a fifth silicide layer 104C-1 on the bottom dielectric layer 102, a third oxide layer 108C on the fifth silicide layer 104C-1, a sixth silicide layer 104C-2 on the third oxide layer 108C, and a third isolation layer 110C on the sixth silicide layer 104C-2. In some embodiments, the fifth silicide layer 104C-1 and the sixth silicide layer 104C-2 include a metal silicide whose conductivity and allowed thermal budget (or thermal budget tolerance) are comparable to tungsten. In some cases, the metal silicide can be titanium silicide (TiSi2), cobalt silicide (CoSi2, C54 phase), tungsten silicide (WSi), palladium silicide (PdSi), other suitable silicides, or combinations thereof. In some embodiments, the third oxide layer 108C can be a semiconductor oxide, such as silicon oxide. In some embodiments, the third isolation layer 110C can be formed of a dielectric material different from the dielectric material forming the bottom dielectric layer 102. In some cases, the third isolation layer 110C can be formed of silicon nitride doped with carbon or oxygen to impart different etching selectivities.

[0068] In some embodiments, the layers in the stack structure, such as the layers in the third film stack C and the fourth film stack D, can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition techniques. As described above, approximately 2 to 32 identical thin film stacks are formed on the bottom dielectric layer 102. For example, Figure 2 As shown, a fourth film stack D identical to the third film stack C is formed on the third film stack C. The fourth film stack D includes a seventh silicide layer 104D-1 on the third isolation layer 110C, a fourth oxide layer 108D on the seventh silicide layer 104D-1, an eighth silicide layer 104D-2 on the fourth oxide layer 108D, and a fourth isolation layer 110D on the eighth silicide layer 104D-2. Although the fourth isolation layer 110D is shown as the topmost layer of the stack structure 11 in FIG. 2 , such description is only for illustrative purposes, and the stack structure 11 may include additional film stacks on the fourth isolation layer 110D. In some examples, the thickness of the topmost isolation layer of the stack structure 11 is formed greater than the thickness of other isolation layers, so that the topmost isolation layer can withstand a reactive ion etching process in a process of forming a memory device.

[0069] Compared to tungsten, the metal silicides used for the first, second, third, fourth, fifth, sixth, seventh, and eighth silicide layers have resistivities and allowable thermal budgets (or thermal budget tolerances) comparable to those of tungsten when there is a low oxidation rate. The resistivity of tungsten is about 10-30 μΩ-cm and the allowable thermal budget (or thermal budget tolerance) is about between 700°C and 900°C. For example, the resistivity of titanium silicide is about 10-15 μΩ-cm and the allowable thermal budget (or thermal budget tolerance) is about 800°C and 900°C. For example, the resistivity of cobalt silicide (CoSi2, C54 phase) is about 18-20 μΩ-cm and the allowable thermal budget (or thermal budget tolerance) is about between 750°C and 850°C. It can be observed that the oxidation of metal silicides, such as titanium silicide (TiSi2) and cobalt silicide (CoSi2, C54 phase), at 800°C is self-limiting. That is, after a thin oxide film is formed at the interface between the metal silicide and the oxygen source, the oxidation rate of the metal silicide is greatly reduced. However, the oxidation of tungsten is not self-limiting, and its oxidation may continue until most of the tungsten layer is oxidized. Due to the above reasons, metal silicide exhibits a slower oxidation rate than tungsten. When tungsten is used in a general stacking structure, a barrier layer, such as a barrier layer formed by a metal nitride (such as titanium nitride or tantalum nitride), must be formed between the tungsten layer and the bottom dielectric layer and between the tungsten layer and the oxide layer to protect the tungsten from oxidation. In addition, in order to prevent the sidewalls of the tungsten layer from being oxidized, the tungsten layer and the barrier layer must also be recessed to accommodate the polysilicon sidewall protection layer. The implementation of the barrier layer, the recess of the tungsten layer, and the formation of the polysilicon sidewall protection layer complicate the process, reduce the stability of the process, and reduce the yield. The present disclosure provides a stacking structure without a tungsten layer and the accompanying barrier layer and sidewall protection layer, thereby reducing the complexity of the process and increasing the stability and yield of the process.

[0070] Figure 3A flow chart of a method 200 for fabricating a semiconductor device (e.g., a memory device) on a workpiece is shown. In operation 202 of method 200, a workpiece is provided. The workpiece includes a stack structure, and the stack structure includes a plurality of thin film stacks on a bottom dielectric layer. In operation 204 of method 200, a plurality of first trenches are formed through the stack structure to expose the bottom dielectric layer. In operation 206 of method 200, the oxide layer within the plurality of stack structures is recessed. In operation 208 of method 200, a polycrystalline semiconductor material is deposited in the plurality of first trenches. In operation 210 of method 200, the polycrystalline semiconductor material deposited in the plurality of first trenches is recessed to form a plurality of second trenches. In operation 212 of method 200, a dielectric layer is deposited on the plurality of second trenches. In operation 214 of method 200, a gate material is deposited on the dielectric layer deposited on the sidewalls of the plurality of second trenches. In operation 216 of method 200, a plurality of vertical isolation features are formed. In operation 218 of method 200 , a plurality of subsequent processes are performed to complete the fabrication of the semiconductor device. Other steps may be provided before, during, and after method 200 , and some steps described may be replaced or eliminated in other embodiments of method 200 .

[0071] Reference now Figure 3 , Figure 4A and Figure 4B The method 200 includes an operation 202 of providing a workpiece 100. The workpiece 100 may include a stacked structure, for example, the stacked structure may be similar to Figure 1 The stacking structure 10, or a similar alternative stacking structure 11. FIG. 4A to FIG. 10A It is disclosed that when the workpiece 100 includes a Figure 1 The stacked structure 10 is the stacked structure of the method 200, and FIG. 4B to FIG. 10B When the workpiece 100 includes a Figure 2 The stack structure 11 is an operation of the method 200. The stack structure 10 includes an even number of film stacks, such as 2, 4, 8, 16, 24, and 32 film stacks. FIG. 4A to FIG. 10A Only two film stacks are shown, namely a first film stack A and a second film stack B. Likewise, the alternative stack structure 11 includes an even number of film stacks, such as 2, 4, 8, 16, 24, and 32 film stacks. FIG. 4B to FIG. 10B Only two film stacks are shown, namely the first film stack C and the second film stack D. The details of the film stacks in the stack structure 10 and the alternative film stack 11 have been described above and will not be repeated here. It should be noted that, unless otherwise specified, the reference numerals A, B, C, and D in the drawings do not represent a necessary order of stacking.

[0072] Reference now Figure 3 , Figure 5A , Figure 5B The method 200 includes an operation 204 in which a plurality of first trenches 120 are formed through the plurality of thin film stacks of the stack structure 10 or the alternative stack structure 11 to expose the bottom dielectric layer 102. Figure 5A , Figure 5B For the stack structure of two film stacks shown, each first trench 120 may have a high aspect ratio (depth / width) between about 5 and 25, and when the stack structure includes more film stacks, the aspect ratio of each first trench 120 may be about 5 to 100. In some examples, each first trench 120 may have a depth of about 400nm to 1μm and a width of about 40nm to 80nm. In some embodiments, the plurality of first trenches 120 may be formed by a reactive ion etching (RIE) process until the bottom dielectric layer 102 is exposed. In some cases, the plurality of film stacks of the stack structure 10 or the alternative stack structure 11 may be selectively etched, while the bottom dielectric layer is substantially not etched. As described above, the material of the bottom dielectric layer 102 and the material of the isolation layer (e.g., the first isolation layer 110A, the second isolation layer 110B, the third isolation layer 110C, and the fourth isolation layer 110D) are different, so that the isolation layer can be etched while the bottom dielectric layer 102 is not substantially etched. In this case, the bottom dielectric layer 102 serves as an etching stop layer for forming the plurality of first trenches 120. Although not shown, each first trench 120 may have a rectangular cross-section when viewed from a direction perpendicular to the bottom dielectric layer 102.

[0073] Reference now Figure 3 , Fig. 6A , Figure 6BThe method 200 includes an operation 206, in which the oxide layers (e.g., the first oxide layer 108A, the second oxide layer 108B, the third oxide layer 108C, and the fourth oxide layer 108D) in the plurality of thin film stacks are recessed to obtain recesses 125. In some embodiments, dry etching, wet etching, a combination thereof, or other suitable etching techniques may be used to selectively etch the oxide layers. In these embodiments, the silicide layers (104A-1, 104A-2, 104B-1, 104B-2, 104C-1, 104C-2, 104D-1, and 104D-2), the polycrystalline semiconductor layers (106A-1, 106A-2, 106B-1, and 106B-2), and the isolation layers (e.g., the first isolation layer 110A, the second isolation layer 110B, the third isolation layer 110C, and the fourth isolation layer 110D) are not substantially etched, while the oxide layers (e.g., the first oxide layer 108A, the second oxide layer 108B, the third oxide layer 108C, and the fourth oxide layer 108D) are etched so that their widths are reduced from W1 to W2. W2 is the width of each recessed oxide layer (eg, first recessed oxide layer 108A', second recessed oxide layer 108B', third recessed oxide layer 108C', and fourth recessed oxide layer 108D'). Each notch may be defined by the difference between W1 and W2 and the thickness T of the oxide layer.

[0074] Reference now Figure 3 , Fig. 7A and Figure 7B The method 200 includes an operation 208, in which a polycrystalline semiconductor material 130 is deposited in the plurality of first trenches 120. In some embodiments, the polycrystalline semiconductor material 130 may be deposited on the workpiece 100 using chemical vapor deposition, atomic layer deposition, or other suitable deposition techniques with good hole filling capability to fill the plurality of first trenches 120 and the recesses 125. In some cases, the polycrystalline semiconductor material 130 is first deposited using atomic layer deposition to fill the recesses 125; and then the polycrystalline semiconductor material 130 is deposited using chemical vapor deposition to increase throughput. In some embodiments, the polycrystalline semiconductor material 130 may be undoped or lightly doped polysilicon. In some examples, after the polycrystalline semiconductor material 130 is deposited in operation 208, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to provide a flat top surface for the upcoming process.

[0075] Reference now Figure 3 , Fig. 8A and Figure 8B The method 200 includes an operation 210 in which the polycrystalline semiconductor material 130 deposited in the plurality of first trenches 120 is recessed to form a plurality of second trenches 135. In some embodiments, the polycrystalline semiconductor material 130 deposited in operation 208 is anisotropically etched using a directional etching technique, such as reactive ion etching. In some embodiments, in operation 210, the recesses 125 are filled with the polycrystalline semiconductor material 130 after forming the plurality of second trenches 135 because the recesses 125 may protect the deposited polycrystalline semiconductor material 130 from anisotropic corrosion. The polycrystalline semiconductor material 130 deposited in the recesses 125 serves as a channel region of a memory device to be formed on the workpiece 100 and may serve as a channel feature 132. Fig. 8A and Figure 8B In the illustrated embodiment, each channel feature 132 is formed on the sidewalls of a recessed oxide layer (eg, first recessed oxide layer 108A', second recessed oxide layer 108B', third recessed oxide layer 108C', and fourth recessed oxide layer 108D'). Fig. 8A , Figure 8B As shown, in some cases, each first trench 120 can have substantially the same size as each second trench 135. Each second trench 135 is defined by two sidewalls 137 and a bottom surface above the bottom dielectric layer 102. It is worth noting that operation 210 of method 200 removes the polycrystalline semiconductor material 130 on the sidewalls of the isolation layers (e.g., the first isolation layer 110A, the second isolation layer 110B, the third isolation layer 110C, and the fourth isolation layer 110D) to prevent short circuits or device failures.

[0076] Reference now Figure 3 , Fig.9A and Fig. 9B The method 200 includes an operation 212 in which a dielectric layer 140 is deposited on the sidewalls 137 of the plurality of second trenches 135. In some embodiments, the dielectric layer 140 may include multiple layers of different dielectric materials. In some cases, the dielectric layer 140 includes a semiconductor nitride layer sandwiched between two semiconductor oxide layers, which may be implemented as an oxide-nitride-oxide (ONO) layer. In these cases, the semiconductor nitride layer may be a silicon nitride (SiN). x N y) layer, and the semiconductor oxide layer can be a silicon monoxide layer. Because the function of the dielectric layer 140 is to capture charges, it can also serve as a storage layer, and the current difference detected in the memory cell (such as the drain current) provides a memory effect. The performance of the storage layer can be adjusted using the ratio of silicon to nitrogen in the silicon nitride layer in the ONO layer. In some embodiments, a deposition technology with good step coverage capability, such as low pressure chemical vapor deposition (LPCVD) and low pressure atomic layer deposition (LPALD) at a temperature between about 750°C and 850°C, can be used to form the semiconductor oxide layer in the dielectric layer 140 to ensure good film quality. A deposition technology with good step coverage capability, such as low pressure chemical vapor deposition and low pressure atomic layer deposition at a temperature between about 650°C and 700°C, can be used to form the semiconductor nitride layer in the dielectric layer 140. In Fig.9A and Fig. 9B In the illustrated embodiment, the deposition of the dielectric layer 140 does not fill the plurality of second trenches 135 and leaves a vertical opening for the gate material 145, which will be described below. In some embodiments, the high temperature during the formation of the dielectric layer 140 in operation 212 may promote phase transformation or recrystallization of the silicide layers (e.g., the first silicide layer 104A-1, the second silicide layer 104A-2, the third silicide layer 104B-1, the fourth silicide layer 104B-2, the fifth silicide layer 104C-1, the sixth silicide layer 104C-2, the seventh silicide layer 104D-1, and the eighth silicide layer 104D-2) to form a phase having an electrical conductivity comparable to that of tungsten. For example, the high temperature in operation 212 may cause titanium silicide to form a C54 phase.

[0077] Reference now Figure 3 , Fig.9A and Fig. 9BThe method 200 includes an operation 214 in which a gate material 145 is deposited on the dielectric layer 140 deposited on the sidewalls of the plurality of second trenches 135. In some embodiments, the gate material 145 is deposited on the workpiece 100 to fill the vertical openings in the plurality of second trenches 135 that are not completely filled by the dielectric layer 140. In some embodiments, the gate material 145 may be polysilicon heavily doped with a P-type dopant (e.g., boron), or an N-type dopant (e.g., phosphorus), or a metal (e.g., tungsten, cobalt, nickel, copper, titanium nitride, tantalum nitride, ruthenium, or the like). In some embodiments, after the dielectric layer 140 and the gate material 145 are formed in operations 212 and 214, a planarization process, such as a chemical mechanical planarization (CMP) process, is performed to provide a planar top surface for the upcoming process.

[0078] Reference now Figure 3 , Fig. 10A and Fig. 10B The method 200 includes an operation 216 in which a plurality of vertical isolation features 150 are formed. In some embodiments, lithography techniques are used to form a plurality of holes in the gate material 145 deposited in at least one second trench 135. In some cases, the plurality of holes may expose the bottom dielectric layer 102 and separate the gate material 145 into a plurality of segments. Fig. 10A and Fig. 10B1 represents a cross section through one of the plurality of vertical isolation features 150. In those embodiments, a photoresist layer is formed in a blanket manner on the workpiece 100. The photoresist layer can then be exposed to radiation reflected or through a mask. The exposed photoresist layer is baked in a post-bake process to undergo a chemical change to allow for selective removal of the exposed / unexposed photoresist layer during development. At this point, the photoresist layer is patterned. The gate material 145 deposited in at least one second trench 135 is etched using a patterned photoresist layer as an etch mask to form the plurality of holes. Thereafter, an insulating material is deposited on the workpiece 100 using chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques to fill the plurality of holes through the gate material 145, thereby forming the vertical isolation features 150. In some embodiments, the insulating material can include a dielectric material, such as a low-k dielectric material. In some cases, the insulating material includes silicon, oxygen, nitrogen, and carbon. In some examples, the insulating material may be silicon oxide, silicon oxy-carbonitride, silicon carbonitride, or silicon oxycarbide. Although not separately identified as another operation in method 200, method 200 may include a planarization process, such as a chemical mechanical planarization (CMP) process, to planarize the Fig. 10A The stacking structure 10 and Fig. 10B The top surface of the replacement stack structure 11 is planarized.

[0079] Now refer to Figure 3 , the method 200 includes an operation 218, in which subsequent processes are performed. For example, a contact via may be formed on the stack structure 10 or the alternative stack structure 11. As another example, an interconnect structure may be formed on the stack structure 10 or the alternative stack structure 11 to electrically couple to the stack structure 10 or the alternative stack structure 11 through the contact via. As another example, an additional stack structure may be formed on the stack structure 10 or the alternative stack structure 11 to form a memory device with a larger capacity.

[0080] The stack structure 10 and the alternative stack structure 11 do not have tungsten, a barrier layer, and a protective layer in a conventional stack structure. Fig. 10AAs shown, the channel feature 132 extends between two polycrystalline semiconductor layers (e.g., the first polycrystalline semiconductor layer 106A-1 and the second polycrystalline semiconductor layer 106A-2, or the third polycrystalline semiconductor layer 106B-1 and the fourth polycrystalline semiconductor layer 106B-2). In addition, the sidewalls of the channel feature 132 in the stacked structure 10 are directly in contact with the dielectric layer 140 without any protective layer in between. Each of the first silicide layer 104A-1, the second silicide layer 104A-2, the third silicide layer 104B-1, and the fourth silicide layer 104B-2 is directly in contact with an isolation layer (e.g., the first isolation layer 110A or the second isolation layer 110B), and is directly in contact with a polycrystalline semiconductor layer (e.g., the first polycrystalline semiconductor layer 106A-1, the second polycrystalline semiconductor layer 106A-2, the third polycrystalline semiconductor layer 106B-1, and the fourth polycrystalline semiconductor layer 106B-2), without any barrier layer in between. In addition, the first silicide layer 104A-1 in the stacked structure 10 is directly in contact with the bottom dielectric layer 102.

[0081] Back to Fig. 10B In the alternative stack structure 11, the channel feature 132 extends between two silicide layers (e.g., the fifth silicide layer 104C-1 and the sixth silicide layer 104C-2, or the seventh silicide layer 104D-1 and the eighth silicide layer 104D-2). In addition, the sidewalls of the channel feature 132 in the alternative stack structure 11 are directly in contact with the dielectric layer 140 without any protective layer in between. Each of the fifth silicide layer 104C-1, the sixth silicide layer 104C-2, the seventh silicide layer 104D-1, and the eighth silicide layer 104D-2 is directly in contact with an isolation layer (e.g., the third isolation layer 110C, or the fourth isolation layer 110D), and is directly in contact with a recessed oxide layer (e.g., the third recessed oxide layer 110C' and the fourth recessed oxide layer 110D'), without any barrier layer in between. In addition, the fifth silicide layer 104C- 1 in the replacement stack structure 11 is in direct contact with the bottom dielectric layer 102 .

[0082] Fig. 10A Each stacking structure 10 and Fig. 10BEach alternative stack structure 11 has a plurality of channel columns 160 and a plurality of gate columns 170. Each gate column 170 includes a dielectric layer 140 and a gate material 145. Each channel column 160 includes a carved thin film stack sandwiched between two gate columns 170 or sandwiched between a gate column 170 and an isolation column 180. In some embodiments, the plurality of channel columns 160 include a contact pitch P of about 80 nm to 160 nm along the X direction. In some cases, the width of the channel columns 160 along the X direction occupies half of the contact pitch P, and the width of the gate columns 170 (or the width of the isolation structure 180) along the X direction occupies the other half. That is, in these cases, each channel column 160 has a width of about 40 nm to 80 nm; each gate column 170 has a width of about 40 nm to 80 nm; and each isolation column 180 has a width of about 40 nm to 80 nm. In some examples, the dielectric layer 140 has a thickness of approximately 10 nm to 15 nm along the X direction, and the gate material 145 (or vertical isolation feature 150 ) has a width of approximately 10 nm to 60 nm along the X direction.

[0083] Therefore, in one embodiment, the present disclosure provides a memory structure. The structure includes a bottom dielectric layer, a gate structure, a stacked structure and a dielectric layer. The gate structure extends vertically from the bottom dielectric layer along a first direction, and the dielectric layer extends along the first direction between the gate structure and the stacked structure. The stacked structure includes a plurality of memory film stacks. Each memory film stack includes a first silicide layer, a second silicide layer, an oxide layer extending along the first direction between the first silicide layer and the second silicide layer, a channel region extending along the first direction above the oxide layer and between the first silicide layer and the second silicide layer, and an isolation layer above the second silicide layer along the first direction.

[0084] In some embodiments, the first silicide layer and the second silicide layer include titanium, tungsten, palladium, or cobalt. In some embodiments, the stacked structure does not have a metal nitride, and the metal nitride is directly in contact with the first silicide layer or the second silicide layer. In some cases, the isolation layer and the bottom dielectric layer have different compositions. In some embodiments, the isolation layer includes silicon nitride. In some embodiments, the first silicide layer and the second silicide layer are in direct contact with the dielectric layer. In some embodiments, the memory structure may also include a first polycrystalline semiconductor layer between the first silicide layer and the oxide layer, and a second polycrystalline semiconductor layer between the second silicide layer and the oxide layer.

[0085] In another embodiment, a memory device is provided. The memory device includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer along a first direction, a stacked structure, and a dielectric layer extending along the first direction between the gate structure and the stacked structure. The stacked structure includes a first silicide layer, a second silicide layer, an oxide layer extending along the first direction between the first silicide layer and the second silicide layer, a channel region extending along the first direction between the first silicide layer and the second silicide layer on the oxide layer, and an isolation layer on the second silicide layer along the first direction. The first silicide layer and the second silicide layer include cobalt, titanium, tungsten, or palladium.

[0086] In some embodiments, the isolation layer is formed of silicon nitride, and the bottom dielectric layer is formed of aluminum oxide or aluminum nitride. In some embodiments, the stacked structure does not have a metal nitride, and the metal nitride is between the first silicide layer and the oxide layer, and between the second silicide layer and the oxide layer. In some embodiments, the memory device may further include a first polysilicon layer between the first silicide layer and the oxide layer, and a second polysilicon layer between the second silicide layer and the oxide layer. In some embodiments, the first silicide layer and the second silicide layer are directly in contact with the dielectric layer.

[0087] In another embodiment, a method for manufacturing a semiconductor device is provided. The method includes forming a stack structure on a bottom dielectric layer by performing multiple film stacking cycles. Each film stacking cycle includes depositing a first silicide layer, depositing an oxide layer on the first silicide layer, depositing a second silicide layer on the oxide layer, and depositing an isolation layer on the second silicide layer. The method also includes: forming multiple first trenches through the stack structure to expose the oxide layer and the bottom dielectric layer; etching the oxide layer exposed in the first trench to form a recess; depositing a semiconductor material in the first trench; recessing the semiconductor material to form multiple second trenches through the stack structure, so that part of the semiconductor material remains deposited in the recess; depositing a dielectric layer on the sidewalls in the second trench; and depositing a conductive material on the dielectric layer in the second trench.

[0088] In some embodiments, the deposition of the dielectric layer includes: depositing the dielectric layer using low pressure chemical vapor deposition (LPCVD) or low pressure atomic layer deposition (LPALD). In some embodiments, the first silicide layer and the second silicide layer include titanium, cobalt, tungsten, or palladium. In some cases, each film stacking cycle further includes: depositing a first polycrystalline semiconductor layer on the first silicide layer before depositing the oxide layer; and depositing a second polycrystalline semiconductor layer on the oxide layer before depositing the second silicide layer. In some embodiments, the isolation layer and the bottom dielectric layer have different compositions. In some embodiments, the isolation layer includes silicon nitride. In some embodiments, the deposition of the dielectric layer includes: depositing a first silicon oxide layer on the sidewalls in the second trench; depositing a silicon nitride layer on the first silicon oxide layer, and depositing a second silicon oxide layer on the silicon nitride layer. In some embodiments, the method further includes forming a plurality of vertical isolation features to separate the conductive material into a plurality of segments.

[0089] The features of several embodiments are summarized above so that those skilled in the art can better understand the content of the present disclosure. It should be understood by those skilled in the art that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to implement the same purpose and / or achieve the same advantages as the embodiments introduced in the present disclosure. It should be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and the above-mentioned equivalent constructions can be variously changed, replaced and altered herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory structure comprising: a bottom dielectric layer; A gate structure vertically extending from the bottom dielectric layer along a first direction; A stack structure includes a plurality of memory film stacks, each memory film stack including: a first silicide layer; a second silicide layer; an oxide layer extending along the first direction between the first silicide layer and the second silicide layer; a channel region extending along the first direction above the oxide layer and between the first silicide layer and the second silicide layer; and an isolation layer on the second silicide layer along the first direction; and A dielectric layer extends along the first direction between the gate structure and the stack structure. 2 . The memory structure of claim 1 , wherein the first silicide layer and the second silicide layer comprise titanium, tungsten, palladium or cobalt. 3 . The memory structure of claim 1 , wherein the stacked structure does not have a metal nitride directly contacting the first silicide layer or the second silicide layer. 4 . The memory structure of claim 1 , wherein the isolation layer and the bottom dielectric layer have different compositions. The memory structure of claim 1 , wherein the isolation layer comprises silicon nitride. 6 . The memory structure as claimed in claim 1 , wherein the first silicide layer and the second silicide layer are directly in contact with the dielectric layer. 7 . The memory structure of claim 1 , further comprising a first polycrystalline semiconductor layer between the first silicide layer and the oxide layer, and a second polycrystalline semiconductor layer between the second silicide layer and the oxide layer.

8. A memory device comprising: a bottom dielectric layer; A gate structure vertically extending from the bottom dielectric layer along a first direction; A stacking structure, comprising: a first silicide layer; a second silicide layer; an oxide layer extending along the first direction between the first silicide layer and the second silicide layer; a channel region extending along the first direction above the oxide layer and between the first silicide layer and the second silicide layer; and an isolation layer on the second silicide layer; and A dielectric layer extends along the first direction between the gate structure and the stack structure; wherein the first silicide layer and the second silicide layer include cobalt, titanium, tungsten or palladium. 9 . The memory device as claimed in claim 8 , wherein the isolation layer is formed of silicon nitride, and the bottom dielectric layer is formed of aluminum oxide or aluminum nitride. 10 . The memory device of claim 8 , wherein the stack structure does not have a metal nitride layer between the first silicide layer and the oxide layer and between the second silicide layer and the oxide layer.

11. The memory device of claim 8, further comprising a first polysilicon layer between the first silicide layer and the oxide layer, and a second polysilicon layer between the second silicide layer and the oxide layer. 12 . The memory device of claim 11 , wherein the first silicide layer and the second silicide layer are directly in contact with the dielectric layer.

13. A semiconductor device comprising: A channel column includes a plurality of thin film stacking structures, each of which includes: a first silicide layer; a second silicide layer on the first silicide layer; an oxide layer extending between the first silicide layer and the second silicide layer; and a channel feature extending between the first silicide layer and the second silicide layer; A grid fence, adjacent to the channel fence, the grid fence comprising: a first dielectric layer and a second dielectric layer; and A gate material is between the first dielectric layer and the second dielectric layer; and An isolation structure, adjacent to the channel fence, includes: a third dielectric layer and a fourth dielectric layer; and An isolation feature is sandwiched between the third dielectric layer and the fourth dielectric layer. The semiconductor device as claimed in claim 13 , wherein the channel rail is disposed between the gate rail and the isolation structure. 15 . The semiconductor device of claim 13 , wherein the first silicide layer and the second silicide layer comprise titanium silicide, cobalt silicide, tungsten silicide or palladium silicide.

16. The semiconductor device of claim 13, wherein the channel feature comprises polysilicon. 17 . The semiconductor device as claimed in claim 13 , wherein each of the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer comprises a semiconductor nitride layer sandwiched between two semiconductor oxide layers.

18. The semiconductor device of claim 13, wherein each of the thin film stack structures further comprises: a first polysilicon layer disposed between the first silicide layer and the oxide layer; as well as A second polysilicon layer is disposed between the second silicide layer and the oxide layer.

19. The semiconductor device of claim 13, wherein the isolation feature comprises silicon oxide, silicon oxycarbonitride, silicon carbonitride, or silicon oxycarbide.

20. The semiconductor device according to claim 13, wherein The thin film stack structure is stacked along a first direction, The gate material is sandwiched between the first dielectric layer and the second dielectric layer along a second direction perpendicular to the first direction. The isolation feature is sandwiched between the third dielectric layer and the fourth dielectric layer along the second direction.

21. A method for manufacturing a semiconductor device, comprising: A stack structure is formed on a bottom dielectric layer by performing a plurality of film stacking cycles, each film stacking cycle comprising: depositing a first silicide layer; depositing an oxide layer on the first silicide layer; depositing a second silicide layer on the oxide layer; and depositing an isolation layer on the second silicide layer; forming a plurality of first trenches through the stack structure to expose the oxide layer and the bottom dielectric layer; Etching the oxide layer exposed in the first trench to form a recess; depositing a semiconductor material in the first trench; recessing the semiconductor material to form a plurality of second trenches through the stacked structure, such that a portion of the semiconductor material remains deposited in the recesses; depositing a dielectric layer on the sidewalls in the second trench; and A conductive material is deposited on the dielectric layer in the second trench.

22. The method for manufacturing a semiconductor device according to claim 21, wherein the deposition of the dielectric layer comprises: The dielectric layer is deposited using a low pressure chemical vapor deposition process or a low pressure atomic layer deposition process.

23. The method for manufacturing a semiconductor device as claimed in claim 21, wherein the first silicide layer and the second silicide layer comprise titanium, cobalt, tungsten or palladium.

24. The method of manufacturing a semiconductor device according to claim 21, wherein each of the film stacking cycles further comprises: Before depositing the oxide layer, depositing a first polycrystalline semiconductor layer on the first silicide layer; as well as Before depositing the second silicide layer, a second polycrystalline semiconductor layer is deposited on the oxide layer.

25. The method for manufacturing a semiconductor device as claimed in claim 21, wherein the isolation layer and the bottom dielectric layer have different compositions.

26. The method for manufacturing a semiconductor device as claimed in claim 21, wherein the isolation layer comprises silicon nitride.

27. The method for manufacturing a semiconductor device according to claim 21, wherein the deposition of the dielectric layer comprises: Depositing a first silicon oxide layer on the sidewalls in the second trench; depositing a silicon nitride layer on the first silicon oxide layer; as well as A second silicon oxide layer is deposited on the silicon nitride layer.

28. The method of manufacturing a semiconductor device according to claim 21, further comprising: A plurality of vertical isolation features are formed to separate the conductive material into a plurality of segments.

29. A method of manufacturing a semiconductor device, comprising: Receiving a workpiece, including: a bottom dielectric layer; a first silicide layer above the bottom dielectric layer; an oxide layer over the first silicide layer; a second silicide layer over the oxide layer; and an isolation layer, above the second silicide layer; Forming a plurality of first trenches through the isolation layer, the second silicide layer, the oxide layer, and the first silicide layer to expose the bottom dielectric layer and the sidewalls of the isolation layer, the second silicide layer, the oxide layer, and the first silicide layer; Selectively etching the oxide layer exposed in the first trench to form a recess; depositing a semiconductor material in the first trench and the recess; forming a plurality of second trenches in the semiconductor material to expose the isolation layer, the second silicide layer, the semiconductor material in the recess, and the sidewalls of the first silicide layer; Depositing a dielectric layer on the sidewalls of the second trench; and A conductive material is deposited above the dielectric layer in the second trench.

30. The method of manufacturing a semiconductor device as claimed in claim 29, wherein the workpiece further comprises a first polysilicon layer disposed between the first silicide layer and the oxide layer and a second polysilicon layer disposed between the oxide layer and the second silicide layer, The first trench extends through the first polysilicon layer and the second polysilicon layer, and the sidewalls of the first polysilicon layer and the second polysilicon layer are exposed in the second trench.

31. The method for manufacturing a semiconductor device according to claim 29, wherein the deposition of the dielectric layer comprises: Depositing a first semiconductor oxide layer on the sidewall of the second trench; Depositing a semiconductor nitride layer on the first semiconductor oxide layer; as well as A second semiconductor oxide layer is deposited on the semiconductor nitride layer.

32. The method of manufacturing a semiconductor device as claimed in claim 31, wherein the deposition of the first semiconductor oxide layer and the second semiconductor oxide layer comprises using a low pressure chemical vapor deposition process or a low pressure atomic layer deposition process at a temperature between 50°C and 850°C.

33. The method of manufacturing a semiconductor device as claimed in claim 32, wherein the deposition of the semiconductor nitride layer comprises using a low pressure chemical vapor deposition process or a low pressure atomic layer deposition process at a temperature between 650°C and 700°C.

34. The method for manufacturing a semiconductor device as claimed in claim 32, wherein the first silicide layer and the second silicide layer comprise cobalt silicide, and during the deposition of the first semiconductor oxide layer and the second semiconductor oxide layer, the first silicide layer and the second silicide layer are transformed into a C54 phase.

35. The method of fabricating a semiconductor device as claimed in claim 29, wherein the depositing of the conductive material comprises depositing a polysilicon doped with a dopant.

36. The method of fabricating a semiconductor device as claimed in claim 29, wherein the depositing of the conductive material comprises depositing tungsten, cobalt, nickel, copper, titanium nitride, tantalum nitride or ruthenium.

37. A method of manufacturing a semiconductor device, comprising: Receiving a workpiece, including: a first silicide layer; an oxide layer over the first silicide layer; and a second silicide layer over the oxide layer; forming a plurality of first trenches passing through the second silicide layer, the oxide layer and the first silicide layer; Selectively etching the oxide layer exposed in the first trench to form a recess; depositing a semiconductor material in the first trench and the recess; forming a plurality of second trenches in the semiconductor material; depositing a dielectric layer on the sidewalls of the second trench; and A conductive material is deposited above the dielectric layer in the second trench. 38 . The method for manufacturing a semiconductor device as claimed in claim 37 , wherein forming the first trench comprises exposing sidewalls of the second silicide layer, the oxide layer, and the first silicide layer.

39. The method for manufacturing a semiconductor device as claimed in claim 37, wherein after the selective etching, a width of the first silicide layer or a width of the second silicide layer is greater than a width of the oxide layer.

40. The method for manufacturing a semiconductor device as claimed in claim 37, wherein the step of forming the second trench comprises exposing the second silicide layer, the semiconductor material in the recess, and a sidewall of the first silicide layer.

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