Semiconductor package with filled conductive cavity

Abstract

The present invention discloses a semiconductor package, comprising a frame having: an insulating body having a first main surface and a second main surface opposite to the first main surface; a first plurality of metal traces at the first main surface; and a first cavity in the insulating body. A thermally conductive and / or electrically conductive material fills the first cavity in the insulating body and has a composition different from that of the first plurality of metal traces. The thermally conductive and / or electrically conductive material provides a thermally conductive and / or electrically conductive path between the first main surface and the second main surface of the insulating body. A semiconductor die attached to the frame at the first main surface of the insulating body is electrically connected to the first plurality of metal traces and to the thermally conductive and / or electrically conductive material filling the first cavity in the insulating body. A corresponding manufacturing method is also described.

Description

Background Art

[0001] Conventional lead frame packages provide good heat dissipation due to the use of a thick copper base. However, the redistribution of electrical signals in conventional lead frame packages is limited by wire bonding constraints. Conventional RDL (redistribution layer) packages (e.g., laminate-based packages) provide better flexibility for electrical signal redistribution than conventional lead frame packages. However, conventional RDL packages typically have thinner copper traces manufactured by etching a thin Cu sheet or by Cu plating. In conventional RDL packages, the use of thin copper traces limits the heat dissipation and power (high current) capacity of such packages. This limitation is more severe for system-on-chip (SoC) products / chips, where higher pin counts and electrical signal redistribution are important considerations, while sufficient levels of power and thermal management must be provided.

[0002] Therefore, there is a need for an improved power semiconductor package with good electrical signal redistribution as well as good power and heat management. Summary of the invention

[0003] According to an embodiment of a semiconductor package, the semiconductor package includes: a frame, the frame including an insulating body having a first main surface and a second main surface opposite to the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulating body; a thermally conductive and / or electrically conductive material filling the first cavity in the insulating body and having a composition different from that of the first plurality of metal traces, the thermally conductive and / or electrically conductive material providing a thermally conductive and / or electrically conductive path between the first and second main surfaces of the insulating body; and a semiconductor die, the semiconductor die being attached to the frame at the first main surface of the insulating body and being electrically connected to the first plurality of metal traces and to the thermally conductive and / or electrically conductive material filling the first cavity in the insulating body.

[0004] The semiconductor die may be a power semiconductor die, and a high-power terminal of the power semiconductor die facing the first main surface of the insulating body may be electrically connected to the thermally and / or electrically conductive material filling the first cavity in the insulating body.

[0005] Either alone or in combination, the frame may also include a second plurality of metal traces at the second main surface of the insulating body, and a plurality of vias electrically connecting the first plurality of metal traces at the first main surface of the insulating body to the second plurality of metal traces at the second main surface of the insulating body, and the high-power terminals of the power semiconductor die may be electrically connected to the metal traces at the second main surface of the insulating body by filling the first cavity in the insulating body with thermally conductive and / or electrically conductive material.

[0006] Alone or in combination, the area of ​​the thermally and / or electrically conductive material filling the first cavity may be at least 10 times the average area of ​​a single via.

[0007] Either alone or in combination, the frame may further include a second cavity in the insulating body, the second cavity may be smaller than the first cavity and laterally spaced apart from the first cavity, the second cavity may be filled with a thermally conductive and / or electrically conductive material having a composition different from that of the first plurality of metal traces and providing a thermally conductive and / or electrically conductive path between the first and second main surfaces of the insulating body, and a second high-power terminal of the power semiconductor die facing the first main surface of the insulating body may be electrically connected to the thermally conductive and / or electrically conductive material filling the second cavity in the insulating body.

[0008] Either alone or in combination, the power semiconductor die may include a plurality of low-power terminals electrically connected to a second plurality of metal traces at the second major surface of the insulating body through the plurality of vias and the first plurality of metal traces.

[0009] Alone or in combination, the semiconductor package may further include a logic die attached to a side of the power semiconductor die facing away from the frame or attached to the frame at the first main surface of the insulating body, and the logic die may be configured to control the power semiconductor die.

[0010] Alone or in combination, the semiconductor package may further include an encapsulation body encapsulating the semiconductor die at the first main surface of the insulating body.

[0011] Either alone or in combination, the frame may be a printed circuit board and the encapsulation may be a molding compound.

[0012] Either alone or in combination, the thermally and / or electrically conductive material filling the first cavity may include a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste, and the first plurality of metal traces may include electroplated copper.

[0013] Alone or in combination, the thermally and / or electrically conductive material filling the first cavity may not be covered by the metal trace at the first main surface of the insulating body, and the semiconductor die may be attached to the thermally and / or electrically conductive material at the first main surface of the insulating body.

[0014] Alone or in combination, the first cavity may terminate at a metal trace at the second main surface of the insulating body, and the semiconductor die may be electrically connected to the metal trace terminating the first cavity at the second main surface of the insulating body by a thermally and / or electrically conductive material filling the first cavity.

[0015] Either alone or in combination, the first cavity may terminate at a metal trace at the first major surface of the insulating body, the semiconductor die may be attached to the metal trace terminating the first cavity at the first major surface of the insulating body, and the semiconductor die may be electrically connected to the thermally and / or electrically conductive material filling the first cavity through the metal trace terminating the first cavity at the first major surface of the insulating body.

[0016] Either alone or in combination, the thermally and / or electrically conductive material filling the first cavity may not be covered by the metal trace at the second major surface of the insulating body.

[0017] Alone or in combination, the semiconductor die can be encapsulated in a molding compound at the first major surface of the insulating body, and the metal trace terminating the first cavity at the first major surface of the insulating body can separate the molding compound from the thermally and / or electrically conductive material filling the first cavity.

[0018] Either alone or in combination, the frame may further include a second cavity in the insulating body, the second cavity may be smaller than the first cavity and laterally spaced apart from the first cavity, the second cavity may be filled with a thermally conductive and / or electrically conductive material having a different composition than the first plurality of metal traces and providing a thermally conductive and / or electrically conductive path between the first and second major surfaces of the insulating body, and the semiconductor die may be electrically connected to the thermally conductive and / or electrically conductive material filling the second cavity in the insulating body.

[0019] Either alone or in combination, the thermally and / or electrically conductive material filling the second cavity may have the same composition as the thermally and / or electrically conductive material filling the first cavity.

[0020] Either alone or in combination, the thermally conductive and / or electrically conductive material filling the first cavity may include a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste, the first plurality of metal traces may include electroplated copper, and the thermally conductive and / or electrically conductive material filling the second cavity may include a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste.

[0021] According to an embodiment of a method for manufacturing a semiconductor package, the method includes: forming a cavity in an insulating body of a frame, the insulating body having a first main surface and a second main surface opposite to the first main surface, and forming a first plurality of metal traces at the first main surface of the insulating body; filling the first cavity in the insulating body with a thermally conductive and / or electrically conductive material having a composition different from that of the first plurality of metal traces, the thermally conductive and / or electrically conductive material providing a thermally conductive and / or electrically conductive path between the first and second main surfaces of the insulating body; and attaching a semiconductor die to the frame at the first main surface of the insulating body so that the semiconductor die is electrically connected to the first plurality of metal traces and to the thermally conductive and / or electrically conductive material filling the first cavity in the insulating body.

[0022] Filling the first cavity in the insulating body with the thermally and / or electrically conductive material may include screen printing a conductive paste in the first cavity and on interconnect pads in the plurality of metal traces formed at the first main surface of the insulating body.

[0023] The conductive paste may be a sintered silver paste, a sintered copper paste or a sintered solder paste, alone or in combination, and the first plurality of metal traces may be formed by electrochemical deposition prior to screen printing of the conductive paste.

[0024] Either alone or in combination, attaching the semiconductor die to the frame at the first major surface of the insulating body may include flip-chip bonding high-power terminals of the semiconductor die to thermally and / or electrically conductive material filling a first cavity in the insulating body, and flip-chip bonding multiple low-power terminals of the semiconductor die to interconnect pads at the first major surface of the insulating body.

[0025] Alone or in combination, the method may further include encapsulating the semiconductor die and the first main surface of the insulating body in a molding compound after attaching the semiconductor die to the frame.

[0026] According to another embodiment of a semiconductor package, the semiconductor package includes: a frame including an insulating body, a first metal trace at a first main surface of the insulating body, a second metal trace at a second main surface of the insulating body opposite to the first main surface, vias electrically connecting some or all of the first metal traces at the first main surface to some or all of the second metal traces at the second main surface, and a cavity formed in an area of ​​the insulating body without conductive vias; a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste filling the cavity in the insulating body; and a semiconductor die attached to the frame at the first main surface of the insulating body and electrically connected to some or all of the first metal traces and electrically connected to the hardened silver paste, the hardened copper paste, the nano-carbon material, or the hardened solder paste filling the cavity in the insulating body.

[0027] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The elements of the drawings are not necessarily to scale with respect to each other. Similar reference numerals represent corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and described in detail in the subsequent description.

[0029] Figure 1 A partial cross-sectional view of an embodiment of a semiconductor package including a frame having a filled cavity without conductive vias is shown.

[0030] Figure 2 A partial cross-sectional view of another embodiment of a semiconductor package including a frame having a filled cavity without conductive vias is shown.

[0031] Figure 3 A partial cross-sectional view of another embodiment of a semiconductor package including a frame having a filled cavity without conductive vias is shown.

[0032] Figure 4 A partial cross-sectional view of another embodiment of a semiconductor package including a frame having a filled cavity without conductive vias is shown.

[0033] Figure 5 Shows the manufacturing Figures 1 to 4 A flow chart of an embodiment of a method of semiconductor packaging is shown.

[0034] FIG. 6A to FIG. 6D Shown in Figure 5 Corresponding partial cross-sectional views during different stages of the production method are shown.

[0035] 7A to 7C Shows Figures 1 to 4 The different layers of the frame included in the semiconductor package are shown. DETAILED DESCRIPTION

[0036] Embodiments described herein provide a semiconductor package and a corresponding method for manufacturing a semiconductor package, the semiconductor package comprising a frame to which one or more semiconductor dies are attached. The frame has a cavity that has no conductive vias and is filled with a hardened silver paste, a hardened copper paste, a nanocarbon material, a hardened solder paste, or a similar type of thermally conductive and / or electrically conductive material that is different from the electroplated metal portion of the frame. The thermally conductive and / or electrically conductive material filling the cavity in the frame provides a thermally conductive and / or electrically conductive path between the relative main surfaces of the frame. The frame can have a single cavity or more than one cavity filled with a thermally conductive and / or electrically conductive material for providing at least one thermally conductive and / or electrically conductive path between the relative main surfaces of the frame.

[0037] Figure 1A partial cross-sectional view of an embodiment of a semiconductor package 100 is shown. The semiconductor package 100 includes a frame 102, the frame 102 including an insulating body 104 having a first major surface 106 and a second major surface 108 opposite the first major surface 106, a first metal trace 110 at the first major surface 106, and a first cavity 112 formed in the insulating body 104. In one embodiment, the frame 102 is a circuit board, such as a printed circuit board (PCB). In the case of a PCB frame, the PCB can be single-sided (e.g., one copper layer), double-sided (e.g., two copper layers on both sides of the insulating body), or multi-layered (e.g., inner and outer layers of copper alternating with layers of insulating material). In another embodiment, the frame 102 is a plastic molded body. Other frames with cavities formed therein can be used.

[0038] The frame 102 may also include second metal traces 114 at the second main surface 108 of the insulating body 104, and vias 116, which electrically connect some or all of the first metal traces 110 at the first main surface 106 of the insulating body 104 to some or all of the second metal traces 114 at the second main surface 108 of the insulating body 104. The metal traces 110, 114 at each main surface 106, 108 of the insulating body 104 are separated from each other by an insulating material 118, which, in the case of a PCB frame, is, for example, a photoresist mask used during the electroplating of the traces 110, 114 and the vias 116. The cavity 112 is formed in an area of ​​the insulating body 104 that is free of conductive vias. As used herein, the term "via" refers to a small opening or hole in an insulating material that allows a conductive connection between different layers. That is, a via is a mechanical structure that allows electrical interconnection between dedicated layers of the frame 102.

[0039] The frame 102 may have Figure 1 The two layers of metal traces 110, 114 shown may be more than two layers of metal traces. In either case, the vias 116 electrically connect some or all of the first metal traces 110 at the first major surface 106 of the insulating body 104 to some or all of the second metal traces 114 at the second major surface 108 of the insulating body 104. In the case where the frame 102 has more than two layers of metal traces 110, 114, the vias 116 will be provided in more than one insulating layer 118 of the frame 102.

[0040] The via-free cavity 112 formed in the insulating body 104 of the frame 102 is filled with a thermally and / or electrically conductive material 120. The thermally and / or electrically conductive material 120 filling the cavity 112 has a different composition than the metal traces 110, 114 and the conductive vias 116. In other words, the thermally conductive and / or electrically conductive material 120 filling the cavity 112 may include a different material than the metal traces 110, 114 and the conductive vias 116 (e.g., hardened silver paste is used for the material 120 filling the cavity 112, and Cu is used for the metal traces 110, 114 and the vias 116), or the thermally conductive and / or electrically conductive material 120 filling the cavity 112 may include a material of the same type as the metal traces 110, 114 and the vias 116 but having one or more structural and / or chemical (e.g., purity level, concentration level of components, etc.) differences (e.g., hardened Cu paste having a Cu purity level of less than 99.99% is used for the material 120 filling the cavity 112, and at least 99.99% pure Cu is used for the metal traces 110, 114 and the vias 116). Because the thermally and / or electrically conductive material 120 filling the cavity 112 is formed at a different time and / or by a different process than the metal traces 110, 114 and the vias 116, the material 120 filling the cavity 112 does not have the same composition as the metal traces 110, 114 and the vias 116 - even if they contain the same type of material (e.g., Cu). In the case of a PCB, the metal traces 110, 114 may be patterned into one or more copper sheet layers laminated to and / or between layers of the insulating body 104. The conductive vias 116 may be plated through holes formed in the insulating body 104. In one embodiment, the metal traces 110, 114 and the conductive vias 116 include electroplated copper formed by electrochemical deposition (ECD).

[0041] The metal traces 110, 114 may be patterned as conductive tracks for signal redistribution at one or both main surfaces 106, 108 of the insulating body 104, and / or patterned as conductive pads for attaching one or more semiconductor dies 122 to the frame 102 of the semiconductor package 100 and / or attaching the semiconductor package 100 to another semiconductor package and / or a circuit board. For example, the one or more semiconductor dies 122 may be attached to the frame 102 at the first main surface 106 of the insulating body 104 and electrically connected to the first metal traces 110 and electrically connected to the thermally and / or electrically conductive material 120 filling the cavity 112 formed in the insulating body 104. The semiconductor package 100 may be attached to another semiconductor package or a circuit board (not shown) at the second main surface 108 of the insulating body 104.

[0042] Die interconnects 124, such as wire stud bumps, metal pillars, vertical bond wires, etc., may be used to attach die pads 126 on each semiconductor die 122 to corresponding pads 128 patterned into first metal traces 110. Die attach material 128 may be used to join die interconnects 124 to pads patterned into first metal traces 110. Die attach material 128 may have the same or different composition as thermally conductive and / or electrically conductive material 120 filling cavity 112 formed in insulating body 104 of frame 102. For example, die attach material 128 and thermally conductive and / or electrically conductive material 120 filling cavity 112 may be formed using a common deposition process, such as screen printing.

[0043] In one embodiment, the thermally conductive and / or electrically conductive material 120 filling the cavity 112 formed in the insulating body 104 includes a hardened silver paste. In another embodiment, the thermally conductive and / or electrically conductive material 120 filling the cavity 112 formed in the insulating body 104 includes a hardened copper paste. In another embodiment, the thermally conductive and / or electrically conductive material 120 filling the cavity 112 formed in the insulating body 104 includes a nano-carbon material. In another embodiment, the thermally conductive and / or electrically conductive material 120 filling the cavity 112 formed in the insulating body 104 includes a hardened solder paste such as SAC305, which is a lead-free alloy containing 96.5% tin, 3% silver and 0.5% copper. Other types of thermally conductive and / or electrically conductive materials may also fill the cavity 112 formed in the insulating body 104.

[0044] In each case, the cavity 112 is formed in an area of ​​the insulating body 104 that is free of conductive vias, and the thermally and / or electrically conductive material 120 that fills the cavity 112 has a different composition (e.g., hardened silver paste, hardened copper paste, nano-carbon material, or hardened solder paste) than the metal traces 110, 114 and the conductive vias 116 (e.g., electroplated copper) of the frame 102. In this way, the thermally and / or electrically conductive path provided by the thermally and / or electrically conductive material 120 that fills the cavity 112 in the insulating body 104 is not constrained by via design rules or via processing limitations and tolerances. For example, a typical PCB thermal via may have a diameter of approximately 0.5 mm. 2 The area of ​​the via and the minimum via-to-via spacing of about 40μm. Such dimensions limit the number of vias that can be placed below thermal hot spots of the semiconductor die or any area where the die temperature tends to be hotter, which affects the thermal performance of the package. For example, in the case of a power semiconductor die, severe electrical transients can generate thermal hot spots that can reach the point of uncontrolled turn-on. If the temperature continues to rise, permanent damage may occur.

[0045] By omitting thermal vias below one or more thermal hot spots of the semiconductor die in favor of filled cavities as described herein, the overall size of the frame 102 can be reduced compared to using vias, and / or the thermal resistance of the thermally and / or electrically conductive paths provided by the thermally and / or electrically conductive material 120 filling the cavities 112 in the insulating body 104 of the frame 102 can be reduced, thereby reducing overall packaging costs and / or improving thermal performance of the package 100. In one embodiment, the thermally and / or electrically conductive material 120 filling the cavities 112 in the insulating body 104 has an area that is at least 10 times, such as at least 100 times, such as at least 200 times, such as at least 300 times, such as at least 400 times, such as at least 500 times, greater than the average area of ​​the individual vias 116 outside the area of ​​the cavities 112.

[0046] The thermally and / or electrically conductive material 120 filling the cavity 112 in the insulating body 104 of the frame 102 may also have a thickness that is less than the minimum thickness that can be achieved by rolling / stamping a Cu block from a Cu sheet. Such a Cu block has a typical minimum thickness of about 125 μm, while the thermally and / or electrically conductive material 120 filling the cavity 112 in the insulating body 104 may have a thickness of less than 100 μm or even less than 80 μm, which further reduces the thermal resistance of the thermally and / or electrically conductive path provided by the thermally and / or electrically conductive material 120 filling the cavity 112 compared to using a Cu block.

[0047] In one embodiment, at least one semiconductor die 122 included in the semiconductor package 100 is a power semiconductor die, such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) die, an IGBT (Insulated Gate Bipolar Transistor) die, a HEMT (High Electron Mobility Transistor) die, a power diode die, etc. A high power terminal 127 (e.g., a drain, collector, or cathode terminal) of the power semiconductor die 122 facing the first main surface 106 of the insulating body 104 is electrically connected to the thermally conductive and / or electrically conductive material 120 filling the cavity 112 in the insulating body 104. According to this embodiment, the high power terminal 127 of the power semiconductor die 122 is electrically connected to the metal trace 114' at the second main surface 108 of the insulating body 104 through the thermally conductive and / or electrically conductive material 120 filling the cavity 112 in the insulating body 104 (rather than through a plurality of vias or Cu blocks). The semiconductor package 100 may include a single semiconductor die 122 or more than one die 122. For ease of illustration only, Figure 1 One semiconductor die 122 is shown in FIG.

[0048] At least one semiconductor die 122 attached to the frame 102 of the package 100 may have more than one thermal hot spot or more than one area where the die temperature tends to be hotter. In one embodiment, the frame 102 also includes at least one second cavity 130 formed in the insulating body 104. The second cavity 130 is laterally spaced apart from the first cavity 112, and the second cavity 130 may be smaller than the first cavity 112. The second cavity 130 is also filled with a thermally and / or electrically conductive material 132 having a different composition than the metal traces 110, 114 and vias 116 of the frame 102, and provides an additional thermally and / or electrically conductive path between the first and second main surfaces 106, 108 of the insulating body 104. In the case of a power semiconductor die 122, a second high power terminal 129 of the power semiconductor die 122 facing the first main surface 106 of the insulating body 104 may be electrically connected to the thermally and / or electrically conductive material 132 filling the second cavity 130 formed in the insulating body 104. According to this embodiment, the second high-power terminal 129 of the power semiconductor die 122 is electrically connected to the metal trace 114 at the second main surface 108 of the insulating body 104 through the thermally and / or electrically conductive material 132 filling the second cavity 130 in the insulating body 104 (rather than through a plurality of vias or Cu blocks).

[0049] The thermally conductive and / or electrically conductive material 132 filling the second cavity 130 formed in the insulating body 104 may or may not have the same composition as the thermally conductive and / or electrically conductive material 120 filling the first cavity 112 formed in the insulating body 104. In one embodiment, the thermally conductive and / or electrically conductive material 120 filling the first cavity 112 includes a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste, the thermally conductive and / or electrically conductive material 132 filling the second cavity 130 includes a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste, and the metal traces 110, 114 and the conductive vias 116 of the frame 102 include electroplated copper. For example, the thermally conductive and / or electrically conductive material 120 filling the first cavity 112 formed in the insulating body 104 and the thermally conductive and / or electrically conductive material 132 filling the second cavity 130 formed in the insulating body 104 may be formed using a common deposition process (e.g., screen printing), while the metal traces 110, 114 and the conductive vias 116 of the frame 102 may be formed by an electroplating process (e.g., ECD).

[0050] Continuing with the example of the power semiconductor die, the power semiconductor die 122 may also have low-power terminals (e.g., I / O (input / output) terminals), sensing terminals (e.g., voltage, current and / or temperature sensing terminals), etc., which are electrically connected to the metal traces 114 at the second main surface 108 of the insulating body 104 through vias 116 and through the metal traces 110 at the first main surface 106 of the insulating body 104.

[0051] The semiconductor package 100 may further include an encapsulation body 134 encapsulating each semiconductor die 122 at the first main surface 106 of the insulating body 104. In one embodiment, the frame 102 is a PCB and the encapsulation body 134 is a molding compound.

[0052] according to Figure 1 In the illustrated embodiment, the thermally and / or electrically conductive material 120, 132 filling each cavity 112, 130 formed in the insulating body 104 of the frame 102 is not covered by the metal traces at the first major surface 106 of the insulating body 104. Thus, in the absence of intermediate metal traces, Figure 1 The semiconductor die 122 is shown attached to the thermally and / or electrically conductive material 120, 132 filling each cavity 112, 130 at the first main surface 106 of the insulating body 104 via a die interconnect 124. Further in accordance with this embodiment, each cavity 112, 130 terminates at a metal trace 114', 114". The semiconductor die 122 is electrically connected to the metal trace 114 via the thermally and / or electrically conductive material 120, 132 filling the corresponding cavity 112, 130, and the metal trace 114 terminates the cavity 112, 130 at the second main surface 108 of the insulating body 104. The metal traces 114 at the second major surface 108 of the insulating body 104 may be patterned as pads for attachment to another semiconductor package or a circuit board (not shown) such as a PCB, and are relatively thin compared to the thermally and / or electrically conductive material 120, 132 filling each cavity 112, 130. In one embodiment, the metal traces 114 at the second major surface 108 of the insulating body 104 terminating each cavity 112, 130 have a thickness of approximately 15 μm to 20 μm.

[0053] Figure 2 A partial cross-sectional view of another embodiment of a semiconductor package 200 is shown. Figure 2 The semiconductor package 200 shown in FIG. Figure 1 The semiconductor package 100 shown in FIG. 1 is similar to the semiconductor package 100 shown in FIG. 1 . However, the difference is that in Figure 2In the embodiment, at least one first cavity 112 formed in the insulating body 104 of the package frame 102 terminates at a metal trace 110' at the first main surface 106 of the insulating body 104. A semiconductor die 122 is attached to the metal trace 110' terminating the first cavity 112 at the first main surface 106 of the insulating body 104, and is electrically connected to the thermally conductive and / or electrically conductive material 120 filling the first cavity 112 by terminating the first cavity 112 at the first main surface 106 of the insulating body 104. The thermally conductive and / or electrically conductive material 120, 132 filling each cavity 112, 130 formed in the insulating body 104 is not covered by the metal trace at the second main surface 108 of the insulating body 104.

[0054] The metal trace 110′ terminating the first cavity 112 at the first major surface 106 of the insulating body 104 separates the encapsulation 134 from the thermally and / or electrically conductive material 120 filling the first cavity 112. In the case of a mold compound type encapsulation 134, by terminating the first cavity 112 at the first major surface 106 of the insulating body 104 with the metal trace 110′, the possibility of delamination between the mold compound encapsulation 134 and the thermally and / or electrically conductive material 120 filling the first cavity 112 is eliminated. In the case where the cavity filling material is a hardened solder paste, terminating the first cavity 112 at the first major surface 106 of the insulating body 104 with the metal trace 110′ also mitigates against re-melted solder contacting the mold compound type encapsulation 134. Other cavities 130 formed in the insulating body 104 of the package frame 102 may also terminate at the metal trace at the first major surface 106 of the insulating body 104.

[0055] Figure 3 A partial cross-sectional view of another embodiment of a semiconductor package 300 is shown. Figure 3 The semiconductor package 300 is shown with Figure 1 The semiconductor package 100 shown is similar. However, the difference is that Figure 3 The semiconductor package 300 in the embodiment also includes a logic die 302, which is attached to a side of the first semiconductor die 122 facing away from the frame 102. In one embodiment, the first semiconductor die 122 is a power transistor die, such as a power MOSFET die, an IGBT die, a HEMT die, etc., and the logic die 302 includes a controller and / or driver circuit for controlling the power transistor die 122. The logic die 302 can be attached to the power transistor die 122 by a die attach material 304 (e.g., solder, glue, etc.). The logic die 302 can be electrically connected to some metal traces 110 at the first main surface 106 of the insulating body 104 by electrical conductors 306 (e.g., bonding wires).

[0056] Figure 4 A partial cross-sectional view of another embodiment of a semiconductor package 400 is shown. Figure 4 The semiconductor package 400 is shown with Figure 3 The semiconductor package 300 is similar to the semiconductor package 300 shown. However, the difference is that Figure 4 , the logic die 302 is attached to the frame 102 at the first surface 106 of the insulating body 104 instead of being attached to the power transistor die 122. The logic die 302 has a pad 402 that is attached to the frame 102 through the same or different interconnects 404 as the power transistor die 122.

[0057] Figure 5 An embodiment of a method of manufacturing the semiconductor packages 100 , 200 , 300 , 400 described herein is shown. FIG. 6A to FIG. 6D Corresponding partial cross-sectional views during different stages of the manufacturing process are shown.

[0058] The method includes providing a frame, such as a circuit board, a plastic molded body, etc. (block 500). One or more cavities are then formed in the frame (block 502). The one or more cavities may be formed in the frame as part of, for example, a typical PCB or plastic molding process. Metal traces and conductive vias are then formed. In the case of copper traces and vias, the traces and vias may be plated using an ECD surface plating process. Using ECD, Cu traces are formed on areas of the major surface of the insulating body of the frame that are not covered by a plating mask (e.g., a photoresist), and the sidewalls of through-holes formed in the insulating body are plated with Cu.

[0059] Fig. 6A The frame 102 is shown after forming one or more cavities 112 , 130 in the insulating body 104 and after forming the metal traces 110 , 114 and the conductive vias 116 .

[0060] Then, each cavity 112, 130 formed in the insulating body 104 of the frame 102 is filled with a thermally and / or electrically conductive material 120, 132 having a different composition than the metal traces 110, 114 and the conductive vias 116 of the frame 102 (block 506). In one embodiment, each cavity 112, 130 formed in the insulating body 104 of the frame 102 is filled by screen printing a conductive paste 600 in each cavity 112, 130 and on the interconnect pads in the metal traces 110 formed at the first major surface 106 of the insulating body 104. For example, the conductive paste 600 may be a sintered silver paste, a sintered copper paste, or a sintered solder paste, and the metal traces 110, 114 and the vias 116 may be electroplated copper formed by ECD. Each filled cavity 112, 130 provides a thermally and / or electrically conductive path between the first and second major surfaces 106, 108 of the insulating body 104.

[0061] Figure 6B The frame 102 is shown after each cavity 112 , 130 formed in the insulating body 104 has been filled with a conductive paste 600 .

[0062] Then, one or more semiconductor dies 122 are attached to the frame 102 at the first main surface 106 of the insulating body 104 (block 508). At least one semiconductor die 122 is electrically connected to the metal traces 110 at the first main surface 106 of the insulating body 104 and to the conductive paste 600 formed in each cavity 112, 130 in the insulating body 104. The conductive paste 600 screen-printed on the interconnect pads patterned into the metal traces 110 at the first main surface 106 of the insulating body 104 serves as a die attach material for bonding the die interconnects 124 to the pads of the frame 102. In one embodiment, at least one semiconductor die 122 is attached to the frame 102 at the first surface 106 of the insulating body 104 by flip-chip bonding the high-power terminals 127 of the semiconductor die 122 to the conductive paste 600 formed in the first cavity 112 in the insulating body 104, and flip-chip bonding the low-power terminals of the semiconductor die 122 to the interconnect pads in the metal traces 110 patterned at the first major surface 106 of the insulating body 104.

[0063] Figure 6C The frame 102 is shown after each die 122 is attached to the frame 102 at the first main surface 106 of the insulating body 104. Additional dies may be attached to the second main surface 106 of the insulating body 104 and / or to one or more of the dies 122 attached to the first main surface 106 of the insulating body 104, e.g. Figure 3 shown.

[0064] The semiconductor package is then subjected to a reflow process during which the conductive paste 600 screen-printed in each cavity 112, 130 and on the interconnect pads in the metal traces 110 formed at the first main surface 106 of the insulating body 104 is reflowed at an elevated temperature (and optionally, elevated pressure), and then the conductive paste 600 is cooled until hardened to form a die attach material 128 that secures the die interconnect 124 to the frame 102 and the thermally and / or electrically conductive material 120, 132 that fills each cavity 112 formed in the insulating body 104 of the frame 102. Each semiconductor die 122 attached to the frame 102 at the first main surface 106 of the insulating body 104 is then encapsulated in an encapsulation 134 such as a molding compound (block 510). Additional processes such as deburring, marking, singulation, etc. may be performed.

[0065] Fig.6D The frame 102 is shown after a reflow and encapsulation process.

[0066] 7A to 7C The various layers of the semiconductor package frame 102 described herein are shown. Fig. 7A A metal trace 110 is shown at the first major surface 106 of the insulating body 104, Figure 7C A metal trace 114 is shown at the second major surface 108 of the insulating body 104, and Figure 7B Metal vias 116 are shown that electrically connect metal traces 110, 114 at opposing major surfaces 106, 108 of the insulating body 104. As previously described herein, the metal traces 110, 114 may be patterned as conductive tracks 110a, 114a for signal redistribution at one or both major surfaces 106, 108 of the insulating body 104, and / or the metal traces 110, 114 may be patterned as conductive pads 110b, 114b for attaching one or more semiconductor dies to the frame 102 and / or attaching the frame 102 to another semiconductor package or circuit board (not shown).

[0067] At least one region of the insulating body 104 is free of conductive vias. 7A to 7C One such region is shown in the dashed box. Figure 7B, which shows a via layer of an insulating substrate 104, with conductive vias 116 omitted in at least one area of ​​the insulating substrate 104. Each of these via-free areas is reserved for forming a cavity 112 / 130 in the insulating body 104. As previously described herein, each cavity 112 / 130 in the insulating body 104 is subsequently filled with a thermally and / or electrically conductive material 120 / 132 having a different composition than the metal traces 110, 114 and vias 116 of the frame 102 to provide one or more separate thermally and / or electrically conductive paths between the first and second major surfaces 106, 108 of the insulating body 104. Figure 7C In the embodiment, the individual pads 114b at the second main surface 108 of the insulating body 104 and located within the via-free region reserved for the cavity may be joined together to form a single pad.

[0068] Terms such as "first", "second", etc. are used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the specification, like terms refer to like elements.

[0069] As used herein, the terms "having", "comprising", "including", etc. are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular.

[0070] It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0071] Although specific embodiments have been shown and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent embodiments may replace the specific embodiments shown and described without departing from the scope of the present invention. The present application is intended to cover any changes or modifications to the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: a frame comprising an insulating body having a first major surface and a second major surface opposite the first major surface, a first plurality of metal traces at the first major surface, and a first cavity in the insulating body; a thermally and / or electrically conductive material filling the first cavity in the insulating body and having a different composition than the first plurality of metal traces, the thermally and / or electrically conductive material providing a thermally and / or electrically conductive path between the first major surface and the second major surface of the insulating body; as well as a semiconductor die attached to the frame at the first major surface of the insulating body and electrically connected to the first plurality of metal traces and to the thermally and / or electrically conductive material filling the first cavity in the insulating body, Wherein, the semiconductor die is a power semiconductor die, Therein, a high-power terminal of the power semiconductor die facing the first main surface of the insulating body is electrically connected to the thermally and / or electrically conductive material filling the first cavity in the insulating body.

2. The semiconductor package according to claim 1, wherein The frame also includes: one or more second metal traces at the second main surface of the insulating body; and one or more vias, which electrically connect one or more of the first plurality of metal traces at the first main surface of the insulating body to the one or more second metal traces at the second main surface of the insulating body, and wherein the high-power terminals of the power semiconductor die are electrically connected to the metal traces at the second main surface of the insulating body by filling the thermally conductive and / or electrically conductive material of the first cavity in the insulating body.

3. The semiconductor package according to claim 2, wherein: The thermally and / or electrically conductive material filling the first cavity has an area at least 10 times the average area of ​​the individual vias.

4. The semiconductor package according to claim 1, wherein: The frame further comprises a second cavity in the insulating body, wherein the second cavity is smaller than the first cavity and is laterally spaced apart from the first cavity, wherein the second cavity is filled with a thermally and / or electrically conductive material having a different composition than the first plurality of metal traces and providing a thermally and / or electrically conductive path between the first main surface and the second main surface of the insulating body, and wherein a second high-power terminal of the power semiconductor die facing the first main surface of the insulating body is electrically connected to the thermally and / or electrically conductive material filling the second cavity in the insulating body.

5. The semiconductor package according to claim 1, wherein The power semiconductor die includes one or more low-power terminals electrically connected to one or more second metal traces at the second major surface of the insulating body through one or more vias and one or more metal traces of the first plurality of metal traces.

6. The semiconductor package according to claim 1 , further comprising a logic die attached to a side of the power semiconductor die facing away from the frame or to the frame at the first main surface of the insulating body, wherein The logic die is configured to control the power semiconductor die.

7. The semiconductor package according to claim 1, wherein: The thermally and / or electrically conductive material filling the first cavity comprises a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste, and wherein the first plurality of metal traces comprises electroplated copper.

8. A method for manufacturing a semiconductor package, the method comprising: forming a cavity in an insulating body of a frame, the insulating body having a first major surface and a second major surface opposite the first major surface, and forming a first plurality of metal traces at the first major surface of the insulating body, the frame further comprising a first cavity in the insulating body; filling the first cavity in the insulating body with a thermally and / or electrically conductive material having a different composition than the first plurality of metal traces, the electrically conductive material providing a thermally and / or electrically conductive path between the first major surface and the second major surface of the insulating body; as well as attaching a semiconductor die to the frame at the first major surface of the insulating body such that the semiconductor die is electrically connected to the first plurality of metal traces and to the thermally and / or electrically conductive material filling the first cavity in the insulating body, Wherein attaching the semiconductor die to the frame at the first main surface of the insulating body comprises: Flip-chip bonding high-power terminals of the semiconductor die to the thermally and / or electrically conductive material filling the first cavity in the insulating body at the first major surface of the insulating body, and flip-chip bonding multiple low-power terminals of the semiconductor die to interconnect pads formed in the multiple metal traces.

9. The method according to claim 8, wherein: Filling the first cavity in the insulating body with the thermally and / or electrically conductive material comprises: Conductive paste is screen printed in the first cavity and on the interconnect pad.

10. The method according to claim 9, wherein: The conductive paste is a silver paste, a copper paste or a solder paste, and wherein the first plurality of metal traces are formed by electrochemical deposition prior to the screen printing of the conductive paste.

11. A semiconductor package, comprising: a frame comprising an insulating body having a first major surface and a second major surface opposite the first major surface, a first plurality of metal traces at the first major surface, and a first cavity in the insulating body; a thermally and / or electrically conductive material filling the first cavity in the insulating body and having a different composition than the first plurality of metal traces, the thermally and / or electrically conductive material providing a thermally and / or electrically conductive path between the first major surface and the second major surface of the insulating body; as well as a semiconductor die attached to the frame at the first major surface of the insulating body and electrically connected to the first plurality of metal traces and to the thermally and / or electrically conductive material filling the first cavity in the insulating body, wherein the thermally and / or electrically conductive material filling the first cavity is not covered by metal traces at the first main surface of the insulating body, wherein the semiconductor die is attached to the thermally and / or electrically conductive material at the first main surface of the insulating body, wherein the first cavity terminates at a metal trace at the second major surface of the insulating body, Therein, the semiconductor die is electrically connected to the metal trace terminating the first cavity at the second main surface of the insulating body through the thermally and / or electrically conductive material filling the first cavity.

12. A semiconductor package, comprising: a frame comprising an insulating body having a first major surface and a second major surface opposite the first major surface, a first plurality of metal traces at the first major surface, and a first cavity in the insulating body; a thermally and / or electrically conductive material filling the first cavity in the insulating body and having a different composition than the first plurality of metal traces, the thermally and / or electrically conductive material providing a thermally and / or electrically conductive path between the first major surface and the second major surface of the insulating body; as well as a semiconductor die attached to the frame at the first major surface of the insulating body and electrically connected to the first plurality of metal traces and to the thermally and / or electrically conductive material filling the first cavity in the insulating body, wherein the first cavity terminates at a metal trace at the first major surface of the insulating body, wherein the semiconductor die is attached to the metal trace terminating the first cavity at the first major surface of the insulating body, Therein, the semiconductor die is electrically connected to the thermally and / or electrically conductive material filling the first cavity by the metal trace terminating the first cavity at the first major surface of the insulating body.

13. The semiconductor package according to claim 12, wherein: The thermally and / or electrically conductive material filling the first cavity is not covered by the metal traces at the second major surface of the insulating body.

14. The semiconductor package according to claim 12, wherein: The semiconductor die is encapsulated in a molding compound at the first main surface of the insulating body, and wherein the metal trace terminating the first cavity at the first main surface of the insulating body separates the molding compound from the thermally and / or electrically conductive material filling the first cavity.

15. A semiconductor package, comprising: a frame comprising an insulating body having a first major surface and a second major surface opposite the first major surface, a first plurality of metal traces at the first major surface, and a first cavity in the insulating body; a thermally and / or electrically conductive material filling the first cavity in the insulating body and having a different composition than the first plurality of metal traces, the thermally and / or electrically conductive material providing a thermally and / or electrically conductive path between the first major surface and the second major surface of the insulating body; as well as a semiconductor die attached to the frame at the first major surface of the insulating body and electrically connected to the first plurality of metal traces and to the thermally and / or electrically conductive material filling the first cavity in the insulating body, Wherein, the frame further comprises a second cavity in the insulating body, wherein the second cavity is smaller than the first cavity and is spaced apart from the first cavity in the lateral direction, wherein the second cavity is filled with a thermally and / or electrically conductive material having a different composition than the first plurality of metal traces and providing a thermally and / or electrically conductive path between the first major surface and the second major surface of the insulating body, Therein, the semiconductor die is electrically connected to the thermally and / or electrically conductive material filling the second cavity in the insulating body.

16. The semiconductor package according to claim 15, wherein: The thermally and / or electrically conductive material filling the second cavity has the same composition as the thermally and / or electrically conductive material filling the first cavity.

17. The semiconductor package according to claim 15, wherein: The thermally and / or electrically conductive material filling the first cavity comprises a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste, wherein the first plurality of metal traces comprises electroplated copper, and wherein the thermally and / or electrically conductive material filling the second cavity comprises a hardened silver paste, a hardened copper paste, a nano-carbon material, or a hardened solder paste.

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