Wafer processing method

Abstract

A wafer processing method is provided that can improve the bending strength of a device chip. The wafer processing method comprises the following steps: a protective member attaching step of attaching a protective tape to the front side of the wafer; a grinding step of holding the wafer on a chuck table with the protective tape interposed therebetween and grinding the back side of the wafer to thin it to a predetermined thickness; a lapping step of lapping the back side of the wafer ground in the grinding step using a lapping pad to remove a fracture layer formed in the lapping step; and a plasma processing step of supplying an inert gas in a plasma state to the back side of the wafer ground in the lapping step to remove a surface layer of processing strain on the back side of the wafer.

Description

Technical Field

[0001] The present invention relates to a method for processing a wafer. Background Art

[0002] Device chips are becoming increasingly thinner and smaller, but there is a growing demand for increased bending strength. When semiconductor device wafers are thinned, a broken layer formed by grinding tools reduces bending strength. Therefore, methods are being used to increase bending strength by removing this broken layer through grinding. However, removing this broken layer diminishes the chip's defect removal effect, potentially causing device failure in memory devices and other applications. Consequently, a so-called defect removal dry polishing method has been proposed (see, for example, Patent Document 1).

[0003] The method disclosed in Patent Document 1 is a method of dry polishing using a polishing pad containing abrasive grains, in which a small scratch is formed to a degree that can exhibit a defect removal effect while removing the crushed layer by polishing.

[0004] Patent Document 1: Japanese Patent No. 4871617

[0005] However, it is desired to further improve the bending strength of the device chip. Summary of the Invention

[0006] Therefore, an object of the present invention is to provide a wafer processing method capable of improving the bending strength of a device chip.

[0007] According to the present invention, a method for processing a wafer is provided, wherein the wafer has a plurality of predetermined dividing lines in a grid shape formed on the front side of a semiconductor substrate, and devices are formed in each area divided by the predetermined dividing lines, wherein the method for processing the wafer has the following steps: a protective component pasting step, in which the protective component is pasted on the front side of the wafer; a grinding step, in which the wafer is held on a chuck worktable through the protective component, and the back side of the wafer is ground to be thinned to a specified thickness; a polishing step, in which the back side of the wafer ground by the grinding step is polished with a polishing pad to remove a broken layer formed by the grinding step; and a plasma processing step, in which an inert gas in a plasma state is supplied to the back side of the wafer ground by the polishing step to remove the surface layer on the back side of the wafer.

[0008] In the polishing step, the back side of the wafer is preferably polished using the polishing pad containing abrasive grains to remove the crushed layer formed in the grinding step and to form fine processing strain as a gettering layer using the abrasive grains.

[0009] In this plasma processing step, it is preferable to form a preliminary gettering layer composed of an amorphous layer on the surface layer on the back side of the wafer.

[0010] Preferably, the chip processing method also has the following modified layer forming step: before implementing the grinding step, laser light of a wavelength that is transparent to the semiconductor substrate is irradiated along the predetermined dividing line to form a modified layer along the predetermined dividing line inside the chip, and the chip is divided with the modified layer as the starting point of fracture due to the grinding stress generated by the grinding step.

[0011] Preferably, the chip processing method also has the following cutting step: before implementing the grinding step, a cutting groove with a depth exceeding the finished thickness is formed from the front side of the chip along the predetermined dividing line using a cutting tool, and in the grinding step, the cutting groove is exposed on the back side of the chip to divide the chip.

[0012] The wafer processing method of the present invention has the effect of improving the bending strength of the device chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a perspective view showing an example of a wafer to be processed by the wafer processing method according to the first embodiment.

[0014] Figure 2 This is a flowchart showing the flow of the wafer processing method according to the first embodiment.

[0015] Figure 3 It shows Figure 2 A perspective view of a protective member attaching step in a wafer processing method is shown.

[0016] Figure 4 yes Figure 2 A perspective view of a wafer after the protective member attaching step in the wafer processing method shown.

[0017] Figure 5 It shows Figure 2 A side cross-sectional view of a wafer processing method showing a preliminary grinding step.

[0018] Figure 6 It shows Figure 2 A side cross-sectional view of a reforming layer forming step in a wafer processing method is shown.

[0019] Figure 7 It shows the implementation Figure 2 A perspective view of a structural example of a grinding and polishing apparatus in the grinding step and the polishing step of the wafer processing method shown.

[0020] Figure 8 It shows Figure 2 A side cross-sectional view of the wafer processing method is shown in the grinding step.

[0021] Figure 9 It shows Figure 2A side cross-sectional view of the polishing step of the wafer processing method is shown.

[0022] Figure 10 It will Figure 2 This is an enlarged cross-sectional view showing a main portion of a wafer after a grinding step in the wafer processing method shown.

[0023] Figure 11 It is shown in Figure 2 A cross-sectional view showing the structure of a plasma apparatus used in a plasma processing step of a wafer processing method is shown.

[0024] Figure 12 It will Figure 2 This is a cross-sectional view showing an enlarged view of a main portion of a wafer in a plasma processing step of the wafer processing method shown.

[0025] Figure 13 It will Figure 2 This is an enlarged cross-sectional view showing a main portion of a wafer after a plasma processing step in the wafer processing method shown.

[0026] Figure 14 This is a flowchart showing the flow of a wafer processing method according to the second embodiment.

[0027] Figure 15 It shows Figure 14 A side cross-sectional view of a wafer processing method is shown.

[0028] Description of labels

[0029] 1: Wafer; 2: Semiconductor substrate; 3: Front side; 4: Predetermined dividing line; 5: Device; 6: Device chip; 7: Back side; 8: Modified layer; 9: Cutting groove; 10: Defect removal layer; 11: Processing strain; 12: Preparatory defect removal layer; 12-1: Amorphous layer; 20: Protective tape (protective component); 44: Laser beam; 54-1: Polishing pad; 56: Chuck worktable; 100: Finished thickness; 400: Inert gas in plasma state; ST1: Protective component pasting step; ST3: Modified layer forming step; ST4: Grinding step; ST5: Polishing step; ST6: Plasma processing step; ST10: Cutting step. DETAILED DESCRIPTION

[0030] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. The present invention is not limited to the contents described in the following embodiments. Furthermore, the components described below include substantially the same components that can be easily imagined by those skilled in the art. In addition, the structures described below can be appropriately combined. Furthermore, various omissions, substitutions, or modifications of the structures can be made without departing from the scope of the present invention.

[0031] [First embodiment]

[0032] A wafer processing method according to a first embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a perspective view showing an example of a wafer to be processed by the wafer processing method according to the first embodiment. Figure 2 This is a flowchart showing the flow of the wafer processing method according to the first embodiment.

[0033] The wafer processing method of the first embodiment is Figure 1 The processing method of the wafer 1 shown in FIG. The wafer 1 is a disk-shaped semiconductor wafer or optical device wafer having a semiconductor substrate 2 made of silicon, sapphire, gallium arsenide, etc. In addition, in the first embodiment, the semiconductor substrate 2 of the wafer 1 is made of silicon. Figure 1 As shown, the wafer 1 has a grid of planned dividing lines 4 formed on a front surface 3 of a semiconductor substrate 2 , and devices 5 are formed in each region partitioned by the planned dividing lines 4 .

[0034] The device 5 is, for example, an integrated circuit such as an IC (Integrated Circuit) or an LSI (Large Scale Integration), or an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor).

[0035] The wafer processing method of the first embodiment is a method of dividing the wafer 1 into individual device chips 6 along the planned dividing lines 4 and thinning the device chips 6 to a final thickness of 100. The device chips 6 are composed of a portion of the semiconductor substrate 2 and the device 5 formed on the front surface 3 of the semiconductor substrate 2. Figure 2 As shown, the wafer processing method includes a protective member attaching step ST1, a preliminary grinding step ST2, a reforming layer forming step ST3, a grinding step ST4, a polishing step ST5, and a plasma processing step ST6.

[0036] (Protective part pasting steps)

[0037] Figure 3 It shows Figure 2 A perspective view of a protective member attaching step in a wafer processing method is shown. Figure 4 yes Figure 2 A perspective view of a wafer after the protective member attaching step of the wafer processing method shown. The protective member attaching step ST1 is a step of attaching a protective tape 20 as a protective member to the front surface 3 side of the wafer 1.

[0038] In the first embodiment, in the protective member pasting step ST1, as shown in FIG. Figure 3 and Figure 4 As shown in FIG. 1 , a protective tape 20 having the same diameter as the wafer 1 is attached to the front surface 3 of the wafer 1. In the first embodiment, the protective tape 20 is used as the protective member, but in the present invention, the protective member is not limited to the protective tape 20. Figure 4 As shown, when the protective tape 20 is attached to the front side 3 of the wafer 1, the wafer processing method enters the preliminary grinding step ST2.

[0039] (Preparatory grinding step)

[0040] Figure 5 It shows Figure 2 The preliminary grinding step ST2 is a step of grinding the back surface 7 of the semiconductor substrate 2 of the wafer 1 before the reforming layer forming step ST3, the grinding step ST4, and the lapping step ST5.

[0041] In the first embodiment, in the preliminary grinding step ST2, the grinding device 30 sucks and holds the front surface 3 side of the semiconductor substrate 2 of the wafer 1 on the holding surface 32 of the chuck table 31 via the protective tape 20. In the cutting step ST10, as shown in FIG. Figure 5 As shown, the grinding wheel 34 for preliminary grinding is rotated by the main shaft 33 and the chuck table 31 is rotated around the axis. While the grinding fluid 36 is supplied from the grinding fluid nozzle 35, the preliminary grinding tool 37 of the grinding wheel 34 is brought into contact with the back surface 7 of the semiconductor substrate 2 of the wafer 1 and approaches the chuck table 31 at a predetermined feed speed, and the back surface 7 of the wafer 1 is ground by the preliminary grinding tool 37.

[0042] In the preliminary grinding step ST2, the wafer 1 is ground to a predetermined thickness such that the laser beam 44, which will be described later, can be focused at a desired depth (height) inside the wafer 1 near the front surface 3 of the wafer 1, thereby forming the modified layer 8. In the first embodiment, when the wafer 1 is ground to the predetermined thickness, the wafer processing method proceeds to the modified layer forming step ST3.

[0043] (Reformed Layer Formation Step)

[0044] Figure 6 It shows Figure 2A side cross-sectional view of a modified layer forming step of a wafer processing method is shown. Modified layer forming step ST3 is a step in which, before performing grinding step ST4, laser light 44 having a wavelength (1300 nm to 1064 nm in the embodiment) that is transparent to semiconductor substrate 2 of wafer 1 is irradiated along planned dividing line 4 from back surface 7 of semiconductor substrate 2 of wafer 1, thereby forming modified layer 8 along planned dividing line 4 within semiconductor substrate 2 of wafer 1.

[0045] The modified layer 8 refers to a region whose density, refractive index, mechanical strength, and other physical properties are different from those of the surrounding regions, and examples thereof include a melt-processed region, a crack region, a dielectric breakdown region, a refractive index change region, and a region where these regions are mixed. Furthermore, the mechanical strength of the modified layer 8 is lower than that of other portions of the wafer 1.

[0046] In the first embodiment, in the modified layer forming step ST3, the laser processing device 40 sucks and holds the front surface 3 of the semiconductor substrate 2 of the wafer 1 on the holding surface 42 of the chuck table 41 via the protective tape 20. In the modified layer forming step ST3, the laser processing device 40 moves the chuck table 41 and the laser beam irradiation unit 43 relative to each other along the planned dividing line 4, as shown in FIG. Figure 6 As shown, a focusing point 44 - 1 of the laser beam irradiation unit 43 is set inside the semiconductor substrate 2 , and a pulsed laser beam 44 is irradiated along the planned dividing line 4 .

[0047] In the first embodiment, in the reforming layer forming step ST3, the laser processing device 40 moves the chuck table 41 so that the laser beam irradiation unit 43 moves from the wafer 1 held by the chuck table 41 to the wafer 1 held by the chuck table 41. Figure 6 The position indicated by the dotted line is toward Figure 6 The position shown by the solid line is irradiated with laser light 44. In the reforming layer forming step ST3, since the laser light 44 has a wavelength that is transparent to the wafer 1, Figure 6 As shown, a modified layer 8 is formed along the planned dividing line 4 within the semiconductor substrate 2. In the modified layer forming step ST3, the modified layer 8 is formed in the region within the wafer 1 that was removed in the grinding step ST4. Furthermore, in the present invention, prior to the modified layer forming step ST3 and prior to the protective member attaching step ST1, a laser beam may be used to ablate the functional layer on the front surface 3 of the semiconductor substrate 2 forming the device 5, thereby forming a laser-machined groove in which the functional layer along the planned dividing line 4 has been removed.

[0048] In the reformed layer forming step ST3, when the reformed layer 8 is formed inside the semiconductor substrate 2 along all the planned dividing lines 4, the irradiation of the laser beam 44 and the suction holding of the chuck table 41 are released and the process proceeds to the grinding step ST4. The grinding step ST4 is performed by Figure 7 The grinding and polishing device 50 shown is implemented.

[0049] (Grinding and polishing device)

[0050] Figure 7 It shows the implementation Figure 2 A perspective view of a structural example of a grinding and polishing apparatus for the grinding step and the polishing step of the wafer processing method shown in FIG. Figure 7 As shown, the grinding and polishing device 50 mainly includes: a device body 51, a first grinding unit 52, a second grinding unit 53, a grinding unit 54, four chuck worktables 56, for example, arranged on a rotary worktable 55, boxes 57, 58, a positioning unit 59, a load-in unit 60, a load-out unit 61, a cleaning unit 62, a load-in and load-out unit 63, and a control unit not shown.

[0051] The first grinding unit 52 is configured to rotate a grinding wheel 52-2 having a grinding tool 52-1 attached to the lower end of the main spindle while pressing the back surface 7 of the wafer 1 held on the chuck table 56 at the rough grinding position 302 in the Z-axis direction parallel to the vertical direction, thereby performing rough grinding on the back surface 7 of the wafer 1. Similarly, the second grinding unit 53 is configured to rotate a grinding wheel 53-2 having a grinding tool 53-1 attached to the lower end of the main spindle while pressing the back surface 7 of the rough-ground wafer 1 held on the chuck table 56 at the fine grinding position 303 in the Z-axis direction, thereby performing fine grinding on the back surface 7 of the wafer 1.

[0052] In the first embodiment, the rotation centers, i.e., the axes, of the grinding wheels 52-2 and 53-2 of the first grinding unit 52 and the second grinding unit 53 are substantially parallel to the rotation center, i.e., the axis of the chuck table 56, and are arranged horizontally spaced apart. In the first embodiment, the grinding units 52 and 53 supply grinding fluids 52-4 and 53-4 (such as pure water) to the wafer 1. Figure 8 As shown), the back side 7 of the wafer 1 is ground.

[0053] like Figure 7As shown, the grinding unit 54 is arranged so that the grinding pad 54-1 of the grinding tool 54-2 mounted on the lower end of the spindle faces the holding surface of the chuck table 56. The grinding unit 54 rotates the grinding tool 54-2 while pressing the back surface 7 of the wafer 1, which has been finish-ground and is held on the holding surface of the chuck table 56 at the grinding position 304, in the Z-axis direction. The grinding unit 54 grinds the back surface 7 of the wafer 1 by pressing the grinding pad 54-1 of the grinding tool 54-2 in the Z-axis direction.

[0054] The polishing pad 54-1 is constructed by dispersing abrasive grains in a flexible base material such as polishing cloth, rubber, or elastomer. In the first embodiment, the hardness of the abrasive grains in the polishing pad 54-1 is equal to or greater than that of the wafer 1. This refers to a hardness that is equal to or higher than that of the wafer 1 but not significantly different from that of the wafer 1, excluding grains with a hardness significantly higher than that of the wafer 1. The abrasive grains are also required to have a particle size of 5 μm or less and a blocky shape. This refers to a small particle size and a polyhedron shape such as a cuboctahedron without sharp corners, relatively close to a sphere. In addition, abrasive grains with sharp corners, as opposed to a blocky shape, are called angular contact shapes, and such angular contact shapes are inappropriate for the present invention.

[0055] Furthermore, in the first embodiment, the abrasive grains are so-called general abrasive grains. Specifically, when the semiconductor substrate 2 of the wafer 1 is silicon, a material having a Mohs hardness of 7 or higher is selected, such as polycrystalline or single-crystalline silicon oxide (SiO2). General abrasive grains such as GC (green corundum) or WA (white corundum) with a Mohs hardness of 9 can also be used, but diamond with a Mohs hardness of 10 is too hard and is not suitable.

[0056] Furthermore, in the first embodiment, the grinding unit 54 performs dry grinding, so-called dry polishing, on the back surface 7 of the wafer 1 without supplying a processing fluid such as a grinding liquid.

[0057] The rotary table 55 is a disc-shaped table provided on the upper surface of the apparatus body 51. It is configured to rotate within a horizontal plane and is driven to rotate according to a predetermined timing. Four chuck tables 56, for example, are provided on the rotary table 55 at equal intervals, for example, at a phase angle of 90 degrees. These four chuck tables 56 have a chuck table structure with a vacuum chuck on the holding surface. The wafer 1, which is placed on the holding surface on the front side 3 with the protective tape 20 interposed therebetween, is held by vacuum suction. During grinding and polishing, these chuck tables 56 are driven to rotate within a horizontal plane by a rotary drive mechanism, with an axis parallel to the vertical direction serving as the rotation axis. The chuck tables 56 are sequentially moved to the load-in / load-out position 301, the rough grinding position 302, the fine grinding position 303, the polishing position 304, and the load-in / load-out position 301 by the rotation of the rotary table 55.

[0058] Cassettes 57 and 58 are containers with multiple slots for storing wafers 1. Cassette 57 stores wafers 1 with protective tape 20 attached to their front surfaces 3 before grinding or polishing. Cassette 58 stores wafers 1 after grinding or polishing. Furthermore, alignment unit 59 is a table on which wafers 1 removed from cassette 57 are temporarily placed for center alignment.

[0059] The loading unit 60 has a suction pad and suction-holds the wafer 1 before grinding and polishing, which has been aligned by the alignment unit 59, and then loads it onto the chuck table 56 located at the loading / unloading position 301. The unloading unit 61 suction-holds the wafer 1 after grinding and polishing held on the chuck table 56 located at the loading / unloading position 301 and then unloads it to the cleaning unit 62.

[0060] The loading / unloading unit 63 is, for example, a robot picker having a circular robot arm 63-1. The circular robot arm 63-1 suction-holds the wafer 1 and transports the wafer 1. Specifically, the loading / unloading unit 63 unloads the wafer 1 before grinding and polishing from the cassette 57 to the alignment unit 59 and loads the wafer 1 after grinding and polishing from the cleaning unit 62 to the cassette 58. The cleaning unit 62 cleans the wafer 1 after grinding and polishing to remove contaminants such as grinding chips and polishing debris adhering to the processed surface after grinding and polishing.

[0061] The control unit controls each of the above-mentioned components constituting the grinding and polishing device 50. That is, the control unit causes the grinding and polishing device 50 to perform a grinding operation on the wafer 1. The control unit is a computer capable of executing computer programs. The control unit includes: an arithmetic processing device having a microprocessor such as a CPU (central processing unit); a storage device having a memory such as a ROM (read only memory) or a RAM (random access memory); and an input / output interface device. The arithmetic processing device of the control unit executes the computer program stored in the storage device and generates a control signal for controlling the grinding and polishing device 50. The arithmetic processing device of the control unit outputs the generated control signal to each component of the grinding and polishing device 50 via the input / output interface device.

[0062] (Grinding steps)

[0063] Figure 8 It shows Figure 2 FIG2 is a side cross-sectional view of the grinding step of the wafer processing method shown in FIG2. Grinding step ST4 involves thinning the wafer 1 to a predetermined thickness by grinding the back surface 7 of the wafer 1 while the wafer 1 is held by suction on the holding surface of the chuck table 56 via the protective tape 20. In the first embodiment, a cassette 57 containing wafers 1 with the protective tape 20 attached to their front surfaces 3 and a cassette 58 containing no wafers 1 are mounted on the main body 51 of the grinding and polishing apparatus 50. An operator registers processing details in the control unit, and when the operator inputs a start instruction for the processing operation, the grinding and polishing apparatus 50 executes grinding step ST4.

[0064] In the grinding step ST4, the grinding and polishing apparatus 50 causes the loading and unloading unit 63 to remove the wafer 1 from the cassette 57 and unload it to the alignment unit 59, which then causes the alignment unit 59 to perform center alignment on the wafer 1. In the grinding step ST4, the grinding and polishing apparatus 50 causes the loading unit 60 to load the center-aligned wafer 1 onto the chuck table 56 located at the loading and unloading position 301.

[0065] In the grinding step ST4, the grinding and polishing device 50 sucks and holds the front surface 3 side of the wafer 1 on the chuck table 56 via the protective tape 20, and exposes the back surface 7. The wafer 1 is sequentially transported to the rough grinding position 302 and the fine grinding position 303 by the rotary table 55. In the grinding step ST4, the grinding and polishing device 50 is as follows at the rough grinding position 302 and the fine grinding position 303. Figure 8As shown, while the grinding wheels 52-2 and 53-2 are rotated by the main shaft and the chuck table 56 is rotated about its axis, grinding fluids 52-4 and 53-4 are supplied from the grinding fluid nozzles 52-3 and 53-3, and the grinding tools 52-1 and 53-1 are brought into contact with the back surface 7 of the semiconductor substrate 2 of the wafer 1 and brought close to the chuck table 56 at a predetermined feed speed. Thus, the back surface 7 of the wafer 1 is subjected to rough grinding and finish grinding in sequence by the grinding tools 52-1 and 53-1. In the grinding step ST4, the wafer 1 is ground until it reaches a predetermined thickness.

[0066] Furthermore, in the first embodiment, during the grinding step ST4, the grinding stress applied by the grinding wheels 52-2 and 53-2 of the first grinding unit 52 at the rough grinding position 302 of the grinding step ST4 causes the wafer 1 to be divided into individual device chips 6 along the planned dividing lines 4, with the reformed layer 8 serving as the fracture starting point. In the first embodiment, when the wafer 1 is ground to a predetermined thickness, the wafer processing method proceeds to the lapping step ST5. Furthermore, after the grinding step ST4, the wafer 1 has a fracture layer (not shown) formed on the surface layer of the back surface 7. This fracture layer is caused by processing strain such as crystal defects and strain.

[0067] (Grinding step)

[0068] Figure 9 It shows Figure 2 A side cross-sectional view of the polishing step of the wafer processing method is shown. Figure 10 It will Figure 2 This is an enlarged cross-sectional view of the main portion of the wafer after the grinding step of the wafer processing method shown. The grinding step ST5 is a step in which the back surface 7 of the wafer 1 ground in the grinding step ST4 is ground using a grinding pad 54-1 to remove the crushed layer formed in the grinding step ST4. In the first embodiment, the grinding step ST5 is a step in which the back surface 7 of the wafer 1 ground in the grinding step ST4 is ground using a grinding pad 54-1 containing abrasive grains to remove the crushed layer formed in the grinding step ST4 and to form fine processing strain 11 as a gettering layer 10 using the abrasive grains.

[0069] In the first embodiment, the gettering layer 10 exhibits a so-called gettering capability by capturing impurities, primarily metal impurities such as copper (Cu) ions, attached to the wafer 1, thereby suppressing metal contamination caused by impurities in the device 5. The process strain 11 is fine crystal defects and strain formed in the surface layer of the back surface 7 of the semiconductor substrate 2 of the wafer 1. The crystal defects and strain of the process strain 11 are smaller than those of the crushing layer.

[0070] In the grinding step ST5, the grinding device 50 rotates the rotary table 55 to move the chuck table 56 holding the finely ground wafer 1 to the grinding position 304. At the grinding position 304, as shown in FIG. Figure 9 As shown, while the main shaft rotates the grinding tool 54-2 and the chuck table 56 about its axis, the grinding pad 54-1 is brought into contact with the back surface 7 of the semiconductor substrate 2 of the wafer 1 and brought closer to the chuck table 56 at a predetermined feed speed, thereby dry-grinding the back surface 7 of the wafer 1 using the grinding pad 54-1. In the grinding step ST5, when the grinding apparatus 50 performs dry grinding for a predetermined time, the grinding unit 54 ends the grinding, and the wafer 1 ground by the grinding unit 54 is positioned at the loading and unloading position 301 and loaded into the cleaning unit 62 by the unloading unit 61. The wafer 1 is cleaned by the cleaning unit 62, and the cleaned wafer 1 is loaded into the cassette 58 by the loading and unloading unit 63.

[0071] The wafer processing method enters the plasma processing step ST6. Figure 10 As shown, after the polishing step ST5 , the wafer 1 has formed on the surface layer of the back surface 7 a fine crystal defect and fine processing strain 11 such as strain, which serves as a gettering layer 10 .

[0072] Thus, in the grinding step ST4 and the polishing step ST5, the grinding and polishing apparatus 50 sequentially transports the wafer 1 to the rough grinding position 302, the fine grinding position 303, the polishing position 304, and the loading and unloading position 301 using the rotary table 55, sequentially performing rough grinding, fine grinding, and polishing to flatten the back surface 7 of the wafer 1 with high precision. Furthermore, each time the grinding and polishing apparatus 50 rotates the rotary table 55 90 degrees, the wafer 1 before grinding and polishing is loaded onto the chuck table 56 at the loading and unloading position 301. When all the wafers 1 in the cassette 57 have been ground and polished, the grinding and polishing apparatus 50 terminates the processing operation.

[0073] (Plasma processing steps)

[0074] Figure 11 It is shown in Figure 2 A cross-sectional view showing the structure of a plasma apparatus used in a plasma processing step of a wafer processing method is shown. Figure 12 It will Figure 2 This is a cross-sectional view showing an enlarged view of a main portion of a wafer in a plasma processing step of the wafer processing method shown. Figure 13 It will Figure 2 This is an enlarged cross-sectional view showing a main portion of a wafer after a plasma processing step in the wafer processing method shown.

[0075] The plasma processing step ST6 is the following step: Figure 11The plasma device 70 shown in FIG. 1 supplies an inert gas 400 ( 0.05 %) in a plasma state to the back surface 7 side of the wafer 1 after being ground in the grinding step ST5. Figure 12 (as shown), plasma processing is performed on wafer 1 to remove silicon 401 constituting the surface layer on the back side 7 of wafer 1, thereby forming a getter layer 10. In the first embodiment, plasma processing step ST6 is a step of plasma processing wafer 1 to remove silicon 401 constituting the surface layer of process strain 11 on the back side 7 of wafer 1. In plasma processing step ST6, plasma device 70 places front side 3 of wafer 1 on chuck table 74 (electrostatic chuck, ESC) constituting lower electrode 73 within enclosed space 72 within plasma etching chamber 71, with protective tape 20 interposed therebetween, and applies power to electrodes 75 and 76 to attract and hold wafer 1 on chuck table 74.

[0076] In the plasma processing step ST6, the plasma device 70 seals the enclosed space 72 in the plasma etching chamber 71, operates the gas exhaust unit 77 to vacuum exhaust the enclosed space 72, thereby maintaining the pressure of the enclosed space 72 at a specified pressure, and operates the refrigerant supply unit 78 to circulate helium as a refrigerant in the refrigerant inlet passage 79, the cooling passage 80 and the refrigerant exhaust passage 81 provided in the lower electrode 73, thereby suppressing abnormal temperature rise of the lower electrode 73.

[0077] In the plasma processing step ST6, the inert gas supply unit 82 is operated to eject inert gas from the plurality of ejection ports 85 of the upper electrode 84 toward the wafer 1 held on the chuck table 74 of the lower electrode 73. Then, in the plasma processing step ST6, the plasma device applies high-frequency power from the high-frequency power supply 83 to the upper electrode 84 to generate and maintain plasma, and applies high-frequency power from the high-frequency power supply 83 to the lower electrode 73 to attract ions. As a result, an inert gas 400 ( Figure 12 As shown in FIG. 4 , the inert gas 400 in the plasma state collides with the back surface 7 of the wafer 1. In the first embodiment, the plasma device 70 supplies argon as the inert gas. However, in the present invention, the inert gas is not limited to argon.

[0078] In the first embodiment, in the plasma processing step ST6, as shown in FIG. Figure 12As shown, the surface layer of the holding surface of the chuck table 74 is negatively charged 402, so that the wafer 1 is attracted and held on the holding surface of the chuck table 74. The inert gas 400 in the positively charged plasma state is attracted to the wafer 1 and collides with the back surface 7. As a result, in the plasma processing step ST6, the silicon 401 on the surface layer of the process strain 11 on the back surface 7 side of the wafer 1 is removed, and the surface layer of the process strain 11 is transformed into an amorphous layer 12-1 as a microscopic crystalline strain layer. A preliminary gettering layer 12 ( Figure 13 As shown in FIG. 1 , the amorphous layer 12-1 is a layer formed into an amorphous shape by imparting crystal defects and strain smaller than the process strain 11. This layer exhibits a so-called gettering capability, trapping metallic impurities, primarily copper (Cu) ions, contained in the wafer 1, thereby suppressing metallic contamination caused by impurities in the device 5. In this manner, the wafer 1 forms a gettering layer 10, including the process strain 11 and the preliminary gettering layer 12, on the back surface 7 of the semiconductor substrate 2.

[0079] When the inert gas 400 in the plasma state collides with the back surface 7 of the wafer 1 according to the prescribed time, the wafer processing method ends. Figure 13 As shown, the wafer 1 after the plasma processing step is thinned to a finished thickness 100 , and a gettering layer 10 including a preliminary gettering layer 12 and a processing strain 11 is formed on the surface of the back side 7 .

[0080] In the wafer processing method of the first embodiment, fine process strain 11 is formed as a gettering layer 10 in the dry polishing step ST5. Then, plasma processing using an inert gas is performed in the plasma processing step ST6. This removes the surface layer of the fine process strain 11 from the back surface 7 of the polished wafer 1. As a result, the wafer processing method of the first embodiment can improve the bending strength of the device chip 6 even while providing gettering capability.

[0081] Furthermore, in the wafer processing method of the first embodiment, the surface layer of the fine processing strain 11 is removed by plasma processing in the plasma processing step ST6, and a preliminary gettering layer 12 having smaller crystal defects and strain than the processing strain 11 is formed. Therefore, compared with a device chip having a gettering layer 10 composed only of the processing strain 11 formed by the grinding step ST5, the bending strength can be improved.

[0082] Furthermore, in the chip processing method, a gettering layer 10 including a preliminary gettering layer 12 is formed on the back side 7 of the semiconductor substrate 2 during plasma processing, thereby achieving the effect of reliably forming the gettering layer 10 on the entire surface of the back side 7, compared to a processing strain layer in which fine scratches are randomly formed.

[0083] In addition, the chip processing method also has the following effects: the same grinding and polishing device 50 is used to perform the grinding step ST4 and the polishing step ST5. There is a risk of metal contamination of the chip 1 during the transportation to the plasma device after the polishing step ST5, but the metal contamination of the device chip 6 is avoided by the processing strain 11 that has been formed in the polishing step ST5.

[0084] Furthermore, the wafer processing method implements plasma processing based on an inert gas in the plasma processing step ST6, so compared with the case of using a gas such as SF6, there is no need for harmless treatment of the exhaust gas, and it also has the effect of simplifying the equipment.

[0085] [Second embodiment]

[0086] A wafer processing method according to a second embodiment of the present invention will be described with reference to the accompanying drawings. Figure 14 This is a flowchart showing the flow of a wafer processing method according to the second embodiment. Figure 15 It shows Figure 14 A side sectional view of the cutting step of the wafer processing method shown. Figure 14 and Figure 15 The same components as those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0087] like Figure 14 As shown, the wafer processing method of the second embodiment is the same as that of the first embodiment, except that a cutting step ST10 is included instead of the modified layer forming step ST3. Cutting step ST10 is a step in which, before the grinding step ST4 is performed, a cutting tool 94 is used to form a cut groove 9 having a depth exceeding the finished thickness 100, along the planned dividing line 4 from the front surface 3 of the semiconductor substrate 2 of the wafer 1. In the second embodiment, the wafer processing method performs cutting step ST10 before the protective member attaching step ST1. However, in the present invention, cutting step ST10 may be performed after the preliminary grinding step ST2, as long as it is performed before the grinding step ST4.

[0088] In the second embodiment, in the cutting step ST10, the dicing tape 21 is attached to the back surface 7 of the wafer 1, and the cutting device 90 attracts and holds the back surface 7 of the wafer 1 on the holding surface 92 of the chuck table 91 via the dicing tape 21. In the cutting step ST10, as shown in FIG. Figure 15 As shown in the cutting step ST10, the cutting device 90 moves the chuck table 91 and the cutting tool 94 of the cutting unit 93 relatively along the predetermined dividing line 4, while Figure 15As shown, the cutting tool 94 is made to cut from the front surface 3 to a depth exceeding the finished thickness 100 to form the cut groove 9. In the present invention, in the cutting step ST10, the cutting process can also be performed without attaching the dicing tape 21 to the back surface 7.

[0089] In the second embodiment, in the cutting step ST10, the cutting device 90 moves the chuck table 91 so that the cutting tool 94 moves from the wafer 1 held by the chuck table 91 to the wafer 1 held by the chuck table 91. Figure 15 The position indicated by the double-dotted line is toward Figure 15 The wafer 1 is cut along the planned dividing line 4 at the position indicated by the solid line.

[0090] In the cutting step ST10, when the cut grooves 9 are formed in the semiconductor substrate 2 along all the planned dividing lines 4, the cutting process using the cutting tool 94 and the suction and holding of the chuck table 91 are released, and the process proceeds to the protective member applying step ST1. In the protective member applying step ST1 of the wafer processing method of the second embodiment, after the protective tape 20 is applied to the front side 3 of the wafer 1, the dicing tape 21 is peeled off from the back side 7. Furthermore, in the grinding step ST4 of the wafer processing method of the second embodiment, the cut grooves 9 are exposed on the back side 7, and the wafer 1 is divided into individual device chips 6. Furthermore, in the present invention, before the cutting step ST10 and before the protective member applying step ST1, the functional layer on the front side 3 of the semiconductor substrate 2 forming the devices 5 may be ablated using laser light to form laser-processed grooves along the planned dividing lines 4, where the functional layer has been removed. In this case, the width of the laser-processed grooves is wider than the cut grooves 9.

[0091] The wafer processing method of the second embodiment forms fine process strain 11 as a gettering layer 10 in the dry polishing step ST5. Then, plasma processing using an inert gas is performed in the plasma processing step ST6 to remove the surface layer of the fine process strain 11 from the back surface 7 of the polished wafer 1. As a result, similar to the first embodiment, the wafer processing method of the second embodiment can improve the bending strength of the device chip 6.

[0092] Next, the inventors of the present invention confirmed the effects of the wafer processing method according to the first embodiment. The results are shown in Table 1 below.

[0093]

Table 1

[0094] Bending strength Comparative Example 1 1350MPa Comparative Example 2 1670MPa Product 1 of the present invention 2107MPa Product 2 of the present invention 3631MPa

[0095] During the verification, the bending strength of the device chips 6 of Comparative Example 1, Comparative Example 2, Inventive Product 1, and Inventive Product 2 was measured. For Comparative Example 1, a polishing tool (product name: DPEG) manufactured by DISCO Co., Ltd. was used to perform the protective member attaching step ST1, preliminary grinding step ST2, modified layer forming step ST3, grinding step ST4, and polishing step ST5, resulting in a gettering layer 10 consisting solely of process strain 11. For Comparative Example 2, a polishing tool (product name: DP08) manufactured by DISCO Co., Ltd. was used to perform the protective member attaching step ST1, preliminary grinding step ST2, modified layer forming step ST3, grinding step ST4, and polishing step ST5, resulting in a gettering layer 10 consisting solely of process strain 11.

[0096] In the case of the product 1 of the present invention, a protective member attaching step ST1, a preliminary grinding step ST2, a modified layer forming step ST3, a grinding step ST4, a polishing step ST5, and a plasma processing step ST6 were performed using a polishing tool manufactured by DISCO Co., Ltd., thereby forming a getter layer 10 including a processing strain 11 and a preliminary getter layer 12. In the case of the product 2 of the present invention, a protective member attaching step ST1, a preliminary grinding step ST2, a modified layer forming step ST3, a grinding step ST4, a polishing step ST5, and a plasma processing step ST6 were performed using a polishing tool manufactured by DISCO Co., Ltd., thereby forming a getter layer 10 including a processing strain 11 and a preliminary getter layer 12.

[0097] In addition, in Comparative Example 1, Comparative Example 2, Product 1 of the Present Invention, and Product 2 of the Present Invention, a plurality of device chips 6 with a size of 10 mm × 10 mm and a thickness of 25 μm were respectively manufactured, and the bending strength of each device chip 6 was measured by three-point bending with a distance between support points of 1.4 mm. Table 1 shows the average value of the bending strength of the plurality of device chips 6.

[0098] According to Table 1, the flexural strength of Comparative Example 1 is 1350 MPa, while the flexural strength of Product 1 of the Invention is 2107 MPa, which is 1.5 times greater than the flexural strength of Comparative Example 1. According to Table 1, the flexural strength of Comparative Example 2 is 1670 MPa, while the flexural strength of Product 2 of the Invention is 3631 MPa, which is 2.1 times greater than the flexural strength of Comparative Example 2.

[0099] Therefore, it can be seen from Table 1 that the bending strength of the device chip 6 can be improved by performing the plasma processing step ST6 after the polishing step ST5 .

[0100] Furthermore, the present invention is not limited to the above-described embodiment. That is, various modifications can be made without departing from the scope of the present invention. For example, in the above-described embodiment, so-called dry grinding is performed in the grinding step ST5 to form fine processing strain 11 on the back surface 7. However, in the present invention, in the grinding step ST5, the back surface 7 can also be ground while providing a processing fluid such as a CMP (Chemical Mechanical Polishing) process, thereby removing the crushed layer formed in the grinding step ST4 without forming processing strain 11. Specifically, the grinding step ST5 can be a step of grinding the back surface 7 of the wafer 1 ground in the grinding step ST4 using a grinding pad to remove the crushed layer formed in the grinding step ST4, and the plasma processing step ST6 can be a step of providing an inert gas 400 in a plasma state to the back surface 7 of the wafer 1 ground in the grinding step ST5 to form a gettering layer 10 on the back surface 7 of the wafer 1. Furthermore, the grinding step ST5 of the present invention is not limited to CMP grinding, and dry grinding (dry polishing) can also be performed using a grinding pad containing abrasives such as silica in a grinding cloth or elastomer, or a grinding pad containing one or more abrasives selected from the group consisting of silica, alumina, forsterite, talc, mullite, cubic boron nitride, diamond, silicon nitride, silicon carbide, boron carbide, barium carbonate, calcium carbonate, iron oxide, magnesium oxide, zirconium oxide, cerium oxide, chromium oxide, tin oxide, and titanium oxide as described in Japanese Patent Gazette No. 2002-283243.

Claims

1. A method for processing a wafer having a plurality of predetermined dividing lines formed in a grid pattern on a front surface of a semiconductor substrate, wherein devices are formed in each region divided by the predetermined dividing lines, wherein: The wafer processing method has the following steps: a protective member pasting step of pasting the protective member on the front side of the wafer; a grinding step of holding the wafer on the chuck table via the protective member and grinding the back side of the wafer to thin it to a predetermined thickness; a grinding step of grinding the back side of the wafer ground in the grinding step using a grinding pad containing abrasive grains, removing the crushed layer formed in the grinding step and forming a processing strain as a gettering layer having crystal defects and strain smaller than those of the crushed layer using the abrasive grains; and A plasma processing step is performed to supply an inert gas in a plasma state to the back side of the wafer polished in the polishing step, thereby removing the surface layer of the process-strained surface on the back side of the wafer and transforming the surface layer of the process-strained surface into an amorphous layer having an amorphous shape and being endowed with crystal defects and strain smaller than the process strain, as a crystal strain layer, and forming a preliminary gettering layer composed of the amorphous layer on the surface layer of the process-strained surface on the back side.

2. The wafer processing method according to claim 1, wherein: The wafer processing method further comprises the following step of forming a modified layer: before performing the grinding step, irradiating the wafer with a laser beam having a wavelength that is transparent to the semiconductor substrate along the predetermined dividing line to form a modified layer along the predetermined dividing line inside the wafer; Due to the grinding stress generated by the grinding step, the wafer is divided with the reformed layer as a fracture starting point.

3. The wafer processing method according to claim 1, wherein: The wafer processing method comprises the following cutting step: before the grinding step, a cutting groove having a depth exceeding the finished thickness is formed along the predetermined dividing line from the front side of the wafer using a cutting tool; In this grinding step, the cut grooves are exposed on the back surface side of the wafer, thereby dividing the wafer.

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